Epitaxial method for reducing cracks and epitaxial wafer thereof

Abstract

The present invention proposes an epitaxial method and epitaxial wafer for reducing cracks. The epitaxial method comprises the following steps: providing a substrate; growing a pre-layer on the surface of the substrate; cooling to release the stress in the pre-layer; and continuing to form the epitaxial layer after heating. The present invention arranges a pre-layer between a buffer layer and an epitaxial layer, heat treats the pre-layer so that cracks are generated in the pre-layer during the cooling process, and then epitaxially grows an epitaxial layer on the pre-layer with cracks, and releases the stress on the substrate in advance through the pre-layer. The probability of epitaxial growth causing the epitaxial wafer to be scrapped due to cracks is reduced, the production yield is improved, and the production cost is reduced.

Description

Technical Field

[0001] The invention relates to the field of semiconductor technology, and in particular to an epitaxial method for reducing cracks and an epitaxial wafer thereof. Background Art

[0002] As a third-generation semiconductor material, GaN has the characteristics of high bandgap, high critical breakdown electric field, high carrier saturation migration velocity, high thermal conductivity and direct bandgap, and has great application prospects in the fields of high-temperature, high-frequency, high-power microelectronic devices and high-performance optoelectronic devices. SiC substrate is currently the most ideal substrate material for GaN heteroepitaxial growth due to its small lattice mismatch with GaN and high thermal conductivity. However, since the thermal expansion coefficient of SiC substrate is smaller than that of GaN, the thermal mismatch is 33.1%, which will cause large tensile stress in the GaN epitaxial layer, and then cause cracks in the epitaxial layer, which will have an adverse effect on the performance of semiconductor devices.

[0003] The existing technology improves the crystal quality and stress state of the film by optimizing the buffer layer technology. However, as the thickness of the GaN epitaxial layer increases, cracks in the epitaxial layer are still unavoidable, making it difficult to obtain a high-quality GaN epitaxial layer.

[0004] Therefore, how to obtain a high-quality GaN epitaxial layer has become a problem that needs to be solved in the existing technology. Summary of the invention

[0005] In order to solve the above problems, the present invention proposes an epitaxial method for reducing cracks and an epitaxial wafer thereof, which can obtain a high-quality GaN epitaxial layer.

[0006] In order to solve the above problems, the present invention proposes an epitaxial method, comprising the following steps: providing a substrate; growing a pre-layer on the surface of the substrate; cooling to release the stress in the pre-layer; and continuing to form an epitaxial layer after heating.

[0007] In order to solve the above problem, the present invention provides an epitaxial wafer, comprising a substrate and an epitaxial layer on the surface of the substrate, and further comprising a pre-layer having a thermal mismatch crack between the substrate and the epitaxial layer.

[0008] The above technical solution arranges a pre-layer between the buffer layer and the epitaxial layer, heat treats the pre-layer so that cracks are generated in the pre-layer during the cooling process, and then epitaxially grows the epitaxial layer on the pre-layer with cracks, and releases the stress on the substrate in advance through the pre-layer. The probability of epitaxial growth causing the epitaxial wafer to be scrapped due to cracks is reduced, the production yield is improved, and the production cost is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Attached Figure 1 Shown is a schematic diagram of the implementation steps of a specific implementation method of the epitaxial method of the present invention.

[0010] Attached Figure 2A to Figure 2F Shown is a process flow chart of a specific implementation of the epitaxial method of the present invention. DETAILED DESCRIPTION

[0011] The specific implementation methods of the epitaxial method for reducing cracks and the epitaxial wafer thereof provided by the present invention are described in detail below in conjunction with the accompanying drawings.

[0012] Attached Figure 1 The figure shows a schematic diagram of the implementation steps of a specific implementation mode of the epitaxial method of the present invention, which includes the following steps: step S11, providing a substrate; step S12, growing a buffer layer on the substrate; step S13, growing a pre-layer on the buffer layer; step S14, cooling to release the stress in the pre-layer; step S15, continuing to form the epitaxial layer after heating.

[0013] Attached Figure 2A ~Attached Figure 2F Shown is a process flow chart of a specific implementation of the epitaxial method of the present invention.

[0014] Attached Figure 2A As shown, and referring to step S11, a substrate 20 is provided. The material of the substrate 20 is any one of SiC, sapphire, and single crystal silicon. As a specific embodiment, SiC is selected as the substrate material, which has the smallest thermal mismatch and lattice mismatch with the epitaxial layer. In other specific embodiments, sapphire or single crystal silicon can also be selected as the substrate material.

[0015] Attached Figure 2B As shown, and referring to step S12, a buffer layer 29 is grown on the substrate 20. As a specific embodiment, in the step of growing the buffer layer 29 on the substrate 20, the following steps are further included: placing the substrate 20 in a MOCVD reaction chamber, subjecting the substrate 20 to a hydrogen heat treatment for 1 minute to 10 minutes, with a heat treatment temperature of 1000°C to 1200°C; alternately introducing an Al source and an In source, with a growth temperature of 750°C to 1050°C, introducing an Al source, maintaining for 5s to 15s, turning off the Al source, introducing an In source, maintaining for 2s to 5s, turning off the In source, introducing an Al source, and maintaining for 5s to 15s. The total thickness of the buffer layer 29 obtained in the above steps is 5 nanometers to 200 nanometers. In other specific embodiments, the heat treatment time can also be 15 minutes or 20 minutes, the heat treatment temperature can also be 1200℃-1600℃ or 1600℃-2000℃; the number of times of alternatingly introducing the Al source and the In source can also be 5 times or 7 times; the thickness of the buffer layer can also be 200 nanometers-500 nanometers, and the growth temperature can also be 1050℃-1150℃.

[0016] Attached Figure 2CAs shown, and referring to step S13, a prelayer 21 is grown on the buffer layer 29. The growth temperature of this step is T1. As a specific embodiment, the material of the prelayer 21 is a nitride, and is further selected from AlN, GaN, InN and one of the ternary or quaternary compounds of the above materials. As a specific embodiment, the prelayer 21 is a GaN layer with a thickness of 500 nanometers to 800 nanometers, and the growth temperature T1 ranges from 1050°C to 1150°C. In other specific embodiments, the prelayer 21 can also be AlN or InN, and the thickness can also be 800 nanometers to 1000 nanometers; the growth temperature can also be 1150°C to 1250°C.

[0017] Attached Figure 2D As shown, and referring to step S14, the temperature is lowered to release the stress in the pre-layer. This step is carried out in a hydrogen atmosphere, and the target temperature for cooling is T2. After cooling, cracks appear in the pre-layer 21 due to the stress generated during the cooling process. Cracks appear in the pre-layer 21 during the cooling process, and then the epitaxial layer continues to grow epitaxially on the pre-layer with cracks, and the stress on the substrate 20 can be released in advance through the pre-layer 21. In addition, conventional stress improvement generally adopts multi-layer buffer layer growth improvement. Although the multi-layer buffer layer can alleviate part of the stress of the epitaxial layer to a certain extent, the multi-layer buffer layer will increase the leakage channel of the epitaxial layer. The above-mentioned technical solution adopts the pre-layer, which can reduce the number of buffer layers, thereby improving the leakage channel of the epitaxial layer and improving the device performance.

[0018] The cooling can be performed in one step or in stages to release the stress in the front layer, and preferably in stages. As a specific implementation, the cooling step further includes the following stages: the temperature is first reduced from T1 to T4 (900°C-1050°C), the cooling rate is less than 1°C / s, and it is implemented in N2 atmosphere; then T4 is reduced to T3 (700°C-900°C), the cooling rate is 1°C / s-1.5°C / s, and it is implemented in N2 or H2 atmosphere; finally, T3 is reduced to T2 (400°C-700°C), the cooling rate is 1.5°C / s-2°C / s, and it is implemented in H2 atmosphere.

[0019] As a specific implementation, the cooling method can also be: the temperature is first reduced from T1 to T3 (1000-1050°C), the cooling rate is 1°C / s-1.5°C / s, and it is implemented in an N2 atmosphere, and then reduced from T3 to T2 (400-700°C), the cooling rate is 1.5°C / s-2°C / s, and it is implemented in an H2 atmosphere. Each cooling stage can be set to a different atmosphere. On the one hand, during the high-temperature cooling process, the relatively low thermal conductivity of N2 is used to reduce the temperature difference between the bottom of the substrate and the surface of the front layer, and improve the uniformity of the cooling crack. On the other hand, during the relatively low-temperature cooling process, the relatively high thermal conductivity of H2 is used to increase the temperature difference between the bottom of the substrate and the surface of the front layer, and improve the crack distribution.

[0020] During the cooling process, increasing the cooling rate can better form cracks in the front layer to release stress more evenly. Since the temperature of the front layer is high, a high cooling rate cannot be used at the beginning of cooling. If a high cooling rate is used at the beginning, large irregular cracks will be generated in the front layer at the beginning, and it will easily cause the substrate to crack, especially in the case of large-sized substrates.

[0021] The above technical solution adopts non-uniform cooling. By cooling from low speed to high speed, the substrate can be avoided from splitting, while the crack uniformity can be improved, and the stress release effect can be better achieved. It can ensure that during the growth of the epitaxial layer and the cooling process after the growth, the epitaxial layer on the substrate will not produce cracks due to the large stress. The crack length caused by cooling is 1 to 5000nm. According to the actual process requirements of the epitaxial production substrate size, when the substrate size is less than 2 inches, the crack length is preferably 1 to 100nm, when the substrate size is less than 2 to 4 inches, the crack length is preferably 100nm to 1000nm, and when the substrate size is less than 6 to 12 inches, the crack length is preferably 1000nm to 5000nm. Although there are cracks, it will not affect the formation of the epitaxial layer and can have the effect of releasing stress.

[0022] Attached Figure 2E As shown, and referring to step S15, the epitaxial layer 22 is continuously formed after the temperature is increased. The material of the epitaxial layer 22 is nitride, and the material of the epitaxial layer is selected from AlN, GaN, InN and one of the ternary or quaternary compounds of the above materials. As a specific embodiment, the temperature is increased and the Al source is introduced, and maintained for 30s-60s, and the heating temperature is 950℃-1200℃; the thickness of the epitaxial layer 22 is 1 micron-5 microns, and the growth temperature T1 ranges from 1050 to 1150℃. In other specific embodiments, the heating temperature can also be 1200℃-1400℃, the thickness of the epitaxial layer 22 can also be 5 microns-10 microns, and the growth temperature T1 ranges from 1150 to 1250℃. As Figure 2EAs shown, after the temperature is raised, the cracks in the pre-layer are filled by the generated epitaxial layer, the gap is reduced, and a flat epitaxial layer can be grown on the pre-layer.

[0023] Attached Figure 2F The structure shown is a flat epitaxial wafer obtained after the above specific implementation is completed and cooled. The epitaxial wafer includes: a substrate 20; an epitaxial layer 22 on the surface of the substrate 20; and a pre-layer 21 with thermal mismatch cracks between the substrate 20 and the epitaxial layer 22, and optionally includes a buffer layer 29.

[0024] As attached Figure 2F As shown, during the cooling process, the epitaxial layer releases the tensile stress on the substrate in advance through the pre-layer, ensuring that the epitaxial layer will not crack during the growth process and the cooling process after the growth due to the large tensile stress on the epitaxial layer on the substrate.

[0025] As a specific implementation, the material of the substrate 20 is any one of SiC, sapphire, and single crystal silicon. The material of the epitaxial layer 20 is nitride, and the material of the pre-layer 21 is nitride. The materials of the epitaxial layer 20 and the pre-layer 21 are independently selected from AlN, GaN, InN, and one of the ternary or quaternary compounds of the above materials.

[0026] The above technical solution sets a pre-layer between the buffer layer and the epitaxial layer, and generates cracks in the pre-layer during the cooling process by heat treating the pre-layer, and then epitaxially grows the epitaxial layer on the pre-layer with cracks, and releases the stress on the substrate in advance through the pre-layer. The probability of epitaxial growth causing the epitaxial wafer to be scrapped due to cracks is reduced, the production yield is improved, and the production cost is reduced.

[0027] In addition, compared with the technology of improving the growth of multi-layer buffer layers, although the multi-layer buffer layers can alleviate some stress of the epitaxial layer to a certain extent, the multi-layer buffer layers will increase the leakage channel of the epitaxial layer. The above-mentioned technical solution can reduce the number of buffer layers due to the use of a pre-layer, thereby improving the leakage channel of the epitaxial layer and improving device performance.

[0028] The above technical solution adopts non-uniform cooling, which can avoid substrate cracking by cooling from low speed to high speed, while improving crack uniformity and better achieving stress release effect. It can ensure that during the growth of the epitaxial layer and the cooling process after growth, cracks will not occur due to the large stress in the epitaxial layer on the substrate.

[0029] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. An epitaxial method for reducing cracks, characterized in that: The steps include: providing a substrate; Growing a front layer on the surface of the substrate, wherein the material of the front layer is gallium nitride; Cooling to release the stress in the front layer; wherein the front layer has uniform thermal mismatch cracks, and the cooling is carried out in stages, and the cooling rate is gradually increased during the cooling process, and the cooling is a two-stage step-by-step cooling: the first stage cooling rate is 1°C / s to 1.5°C / s, starting from a temperature range of 1050°C to 1150°C, with a target temperature range of 1000°C to 1050°C, and is implemented in an N2 atmosphere; the second stage cooling rate is 1.5°C / s to 2°C / s, starting from a temperature range of 1000°C to 1050°C, with a target temperature range of 400 to 700°C, and is implemented in an H2 atmosphere; and After the temperature is raised, the epitaxial layer continues to form.

2. The method according to claim 1, characterized in that: The substrate is made of any one of SiC, sapphire and single crystal silicon.

3. The method according to claim 1, characterized in that The material of the epitaxial layer is nitride, and the material of the epitaxial layer is selected from AlN, GaN, InN and one of ternary or quaternary compounds of the above materials.

4. The method according to claim 1, characterized in that Before the step of growing a nitride pre-layer on the substrate surface, the method further comprises the following steps: A buffer layer is grown on the substrate, and the pre-layer is grown on the surface of the buffer layer.

5. The method according to claim 1, characterized in that The cooling rate is less than 2°C / s.

6. The method according to claim 1, characterized in that The cooling process is divided into three stages: The first stage cooling rate is less than 1°C / s, the target temperature range is 900°C to 1050°C, and it is implemented in N2 atmosphere; The second stage cooling rate is 1℃ / s~1.5℃ / s, the target temperature range is 700℃~900℃, and it is implemented in N2 or H2 atmosphere. The third stage cooling rate is 1.5℃ / s~2℃ / s, the target temperature range is 400℃~700℃, and it is implemented in H2 atmosphere.

7. An epitaxial wafer comprising: substrate; Epitaxial layer on the substrate surface; It is characterized in that a pre-layer with uniform thermal mismatch cracks is also included between the substrate and the epitaxial layer, and the material of the pre-layer is gallium nitride; wherein the thermal mismatch cracks are formed by staged cooling, and the cooling rate gradually increases during the cooling process, and the cooling is a two-stage step-by-step cooling: the first stage cooling rate is 1°C / s to 1.5°C / s, starting from a temperature range of 1050°C to 1150°C, with a target temperature range of 1000°C to 1050°C, and is implemented in an N2 atmosphere; the second stage cooling rate is 1.5°C / s to 2°C / s, starting from a temperature range of 1000°C to 1050°C, with a target temperature range of 400 to 700°C, and is implemented in an H2 atmosphere.

8. The epitaxial wafer according to claim 7, characterized in that: The substrate is made of any one of SiC, sapphire and single crystal silicon.

9. The epitaxial wafer according to claim 7, characterized in that: The material of the epitaxial layer is nitride, and the material of the epitaxial layer is selected from AlN, GaN, InN and one of ternary or quaternary compounds of the above materials.

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