A GaN HEMT and GaO x Fabrication method of MOSFET heterogeneous inverter

Abstract

This invention discloses GaN HEMT and GaO. x A method for fabricating a MOSFET heterogeneous inverter includes: growing a GaN-Fe modulation buffer layer on a sapphire single-crystal substrate; homoepitaxially growing a 30-50 nm GaN layer at 900-1200 °C; growing a silicon-doped AlGaN barrier layer on the GaN layer; and growing a SiN passivation layer on the AlGaN barrier layer to form a HEMT structure; etching a portion of the SiN passivation layer down to the sapphire layer; etching the channel isolation region; and growing a first GaO layer on the etched sapphire surface. x The buffer layer makes the first GaO x The buffer layer forms a step with the sapphire surface, and in the first GaO x Growing a second GaO layer x Layer, and in the second GaO x After implanting Si ions to dope the SiN layer to form the drain and source doped regions of the MOSFET, a SiO2 gate layer is deposited. Metal films are deposited at both ends of the SiN passivation layer and the SiO2 dielectric layer, then peeled off and annealed to obtain the source and drain electrodes, respectively. A metal film is deposited in the middle of the SiN passivation layer and the SiO2 dielectric layer, then peeled off and annealed to obtain the gate electrode. This invention is applicable to high-temperature and high-pressure operating environments.

Description

Technical Field

[0001] This invention relates to the field of materials technology, and in particular to a GaN HEMT and a GaO x Method for fabricating MOSFET heterogeneous inverters. Background Technology

[0002] Gallium nitride (GaN), as a third-generation semiconductor, possesses a wide bandgap, high electron mobility, and high electron saturation velocity, enabling it to achieve higher breakdown voltage and on-resistance and operate at high temperatures. It is widely used in power devices and other fields. Gallium oxide (GaO) x With a wide bandgap of 4.8 eV, its theoretical breakdown strength surpasses that of gallium nitride and silicon carbide. Its optimized epitaxial layer with low defect density and high charge carrier density, which enhances electron mobility, can significantly improve the performance of GaO. x Performance of power transistors. In order to meet the performance and integration requirements of power devices, this paper introduces a monolithically integrated heterogeneous inverter of gallium nitride and gallium oxide. The main features of this inverter are: (1) two field-effect transistors are integrated on the same substrate; (2) compared with traditional silicon-based devices, it is more suitable for high temperature (400-900℃) and high pressure working scenarios; (3) monolithic integration can realize high frequency operation, which is conducive to miniaturization;

[0003] Traditional silicon-based devices have an upper operating temperature limit of 125-150℃, making it difficult to operate normally under high temperature and high pressure environments. Furthermore, the driving circuit module of traditional silicon-based inverters is separate, which increases the size and design complexity of integrated circuit systems. Summary of the Invention

[0004] This invention provides a GaN HEMT and a GaO x Methods for fabricating MOSFET heterogeneous inverters include:

[0005] A GaN-Fe modulation buffer layer is grown on a sapphire single crystal substrate, a GaN layer of 30-50 nm is homoepitaxially grown at 900-1200 °C, a silicon-doped AlGaN barrier layer is grown on the GaN layer, and a SiN passivation layer is grown on the AlGaN barrier layer to form a HEMT structure.

[0006] A portion of the SiN passivation layer is etched down to the sapphire layer, the channel isolation region is etched, and the first GaO layer is grown on the etched sapphire surface. x The buffer layer makes the first GaO x The buffer layer forms a step with the sapphire surface, and in the first GaO X Growing a second GaO layer x Layer, and in the second GaO xAfter implanting Si ions into the layer to perform N doping to form the drain and source doped regions of the MOSFET, a SiO2 gate layer is deposited.

[0007] Metal films are deposited at both ends of the SiN passivation layer and the SiO2 dielectric layer, and then peeled off and annealed to obtain the source and drain electrodes, respectively. A metal film is deposited in the middle of the SiN passivation layer and the SiO2 dielectric layer, and then peeled off and annealed to obtain the gate electrode, respectively.

[0008] Furthermore, the thickness of the GaN-Fe modulation buffer layer is 30–40 nm.

[0009] Furthermore, the Fe source flux is 200–400 sccm, and the Fe doping concentration is 1–3 × 10⁻⁶. 19 cm -3 The growth temperature is 450–600℃.

[0010] Furthermore, the thickness of the homoepitaxially grown GaN layer is 30–50 nm, and the growth temperature is 1000–1100 °C.

[0011] Furthermore, the thickness of the SiN passivation layer is 40-60 nm.

[0012] Furthermore, the AlGaN barrier layer has a thickness of 3–8 nm, in which the Al composition is 25%.

[0013] Furthermore, the first GaO x The thickness of the buffer layer is 40–60 nm, and the second GaO x The thickness of the layer is 10–30 nm.

[0014] Furthermore, the thickness of the SiO2 gate layer is 20–40 nm.

[0015] Furthermore, the drain and source metal films are made of Ti, Al, Ni, or Au, and are annealed at 825°C in an N2 environment.

[0016] Furthermore, the gate metal film uses Ni or Au.

[0017] This invention proposes a monolithically integrated GaN HEMT and GaO x MOSFET heterogeneous inverters, characterized by the use of GaN HEMT and GaO x The complementary structure of MOSFETs has the following advantages: it is suitable for high temperature, high pressure and high frequency operating scenarios; it reduces the static power consumption of the device and achieves higher power density; and it effectively reduces the size and weight required for integration compared to traditional silicon-based devices. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 A GaN HEMT and GaO provided for embodiments of the present invention x Methods for fabricating MOSFET heterogeneous inverters;

[0020] Figure 2 A GaN HEMT and GaO provided for embodiments of the present invention x Methods for fabricating MOSFET heterogeneous inverters;

[0021] Figure 3 GaN HEMT and GaO prepared for embodiments of the present invention x Schematic diagram of a MOSFET heterogeneous inverter;

[0022] Figure 4 GaN HEMT and GaO provided in the embodiments of the present invention x Circuit diagram of a MOSFET heterogeneous inverter. Detailed Implementation

[0023] To enable those skilled in the art to better understand the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings.

[0024] One embodiment of the present invention provides a GaO-based x The fabrication method of GaN CMOS inverter includes the following steps:

[0025] Step 1: Grow a GaN-Fe modulation buffer layer on a sapphire single crystal substrate, homoepitaxially grow a 30-50 nm GaN layer at 900-1200 °C, grow a silicon-doped AlGaN barrier layer on the GaN layer, and grow a SiN passivation layer on the AlGaN barrier layer to form a HEMT structure.

[0026] One embodiment of the present invention, such as Figure 1 As shown, a GaN-Fe modulation buffer layer with a thickness of 30–40 nm, preferably 35 nm, is grown on a sapphire substrate using metal-organic chemical vapor deposition (MOCVD). The Fe source flux is 200–400 sccm, preferably 300 sccm, and the Fe doping concentration is 1–3 × 10⁻⁶. 19 cm -3The growth temperature is preferably 450–600℃, and the doping concentration is 3 × 10⁻⁶. 19 cm -3 The growth temperature was controlled at 500℃.

[0027] The temperature conditions are changed to 1000–1100℃, preferably controlled at 1050℃, to homoepitaxially grow a 30–50 nm thick, preferably 40 nm thick, GaN layer on the GaN buffer layer using metal-organic chemical vapor deposition (MOCVD). A silicon-doped AlGaN barrier layer with a thickness of 3–8 nm, preferably 5 nm thick, is grown on the GaN layer using MOCVD, wherein the Al content is 20–30%, preferably 25%. An ion-enhanced chemical vapor deposition (PECVD) layer of 40–60 nm thick, preferably 50 nm thick, SiN is deposited on the AlGaN barrier layer as a passivation layer.

[0028] Step 2: Etch a portion of the SiN passivation layer down to the sapphire layer, etch the channel isolation area, and grow the first GaO layer on the etched sapphire surface. x The buffer layer makes the first GaO x The buffer layer forms a step with the sapphire surface, and in the first GaO x Growing a second GaO layer x Layer, and in the second GaO x After implanting Si ions into the layer to perform N doping to form the drain and source doped regions of the MOSFET, a SiO2 gate layer is deposited.

[0029] In embodiments of the present invention, such as Figure 2 As shown, a portion of the HEMT structure is etched down to the sapphire layer using plasma etching. Then, using SiO2 as a growth mask, a P-channel metal-oxide-semiconductor field-effect transistor structure is fabricated in the etched portion using selective MOCVD. Dry etching with Cl2 / BCl3 is performed on the existing structure to form steps on both sides. In the mesa isolation portion, a first GaO layer with a thickness of 40–60 nm, preferably 50 nm, is grown using MOCVD. x Buffer layer, changing temperature conditions, using MOCVD on GaO x A second GaO layer with a thickness of 10–30 nm, preferably 20 nm, is grown on the buffer layer. x Layer; then Si ion implantation is used in the second GaO layer. x N-type doping is performed on the layer to form the drain and source doped regions of the MOSFET; plasma chemical vapor deposition (PECVD) is used to deposit N-type doping on the second GaO layer. x A SiO2 gate dielectric layer of 20–40 nm, preferably 30 nm, is deposited on the layer.

[0030] Step 3: Deposit metal films at both ends of the SiN passivation layer and the SiO2 dielectric layer, peel off, and anneal to obtain the source and drain electrodes, respectively. Deposit metal films in the middle of the SiN passivation layer and the SiO2 dielectric layer, peel off, and anneal to obtain the gate electrode, respectively.

[0031] In fabricating the drain and source electrodes: metal films (such as Ti (25nm) / Al (75nm) / Ni (25nm) / Au (75nm)) are deposited using methods such as thermal evaporation, magnetron sputtering, or electron beam evaporation. After forming the electrodes using a lift-off process, they are annealed at 825℃ in an N2 environment. In fabricating the gate electrode: metal films (such as Ti (25nm) / Al (75nm) / Ni (25nm) / Au (75nm)) are deposited using methods such as thermal evaporation, magnetron sputtering, or electron beam evaporation on GaO. x and Mg-GaO x A metal film (such as Ni (25nm) / Au (25nm)) is deposited on the layer, and after forming electrodes using a stripping process, it is annealed at 870℃ in an N2 environment.

[0032] In this embodiment of the invention, a SiC substrate can be used to replace the sapphire substrate in the structure; the material of the gallium nitride buffer layer in the device structure can be changed, such as replacing low-temperature GaO with AlN. x Buffer layer; change the electrode material, such as changing the drain and source materials to Ti / Al / Au; the gate oxide material can also be changed, such as changing the gate oxide SiO2 to Al2O3, HFO2 or other materials.

[0033] like Figure 3 To prepare the GaN-based HEMT and GaO x A schematic diagram of a MOSFET heterogeneous inverter, where 1 is a sapphire single-crystal substrate, 2 is a GaN buffer layer, 3 is a GaN layer, 4 is an AlGaN barrier layer, 5 is a SiN layer, 6 is a channel isolation region, 7 and 14 are drains, 8 and 15 are gates, 9 and 16 are sources, and 10 is a GaO layer. x Buffer layer, 11 is GaO x Layer 12 is Mg ion-doped GaO x 13 is the SiO2 gate dielectric layer. For example... Figure 4 The image shows GaN HEMT and GaO prepared according to embodiments of the present invention. x A circuit diagram of a MOSFET heterogeneous inverter.

[0034] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

[0035] The above description is only a partial embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A GaN HEMT and GaO x A method of fabricating a MOSFET and GaO The application relates to a GaN HEMT structure, which comprises the following steps: GaN Fe modulation buffer layer is grown on a sapphire single crystal substrate, a 30-50nm GaN layer is homo-epitaxially grown at 900-1200 DEG C, a silicon-doped AlGaN barrier layer is grown on the GaN layer, and a SiN passivation layer is grown on the AlGaN barrier layer to form a HEMT structure; etching part of the region on the SiN passivation layer to the sapphire layer, etching the channel isolation region, and growing a first GaO x The buffer layer makes the first GaO x The buffer layer forms a step with the sapphire surface, and the first GaO x The buffer layer grows a second GaO x layer, and implants Si ions on the second GaO x layer to form the drain-source doping region of the MOSFET, and then deposits a SiO2 gate quality layer; Metal films are deposited at both ends of the SiN passivation layer and the SiO2 dielectric layer, stripping and annealing to obtain the source and the drain respectively, a metal film is deposited in the middle of the SiN passivation layer and the SiO2 dielectric layer, stripping and annealing to obtain the gate.

2. The production method according to claim 1, characterized by, The thickness of the GaN Fe modulation buffer layer is 30-40nm.

3. The method of claim 2, wherein, The Fe source flux is 200–400 sccm, and the Fe doping concentration is 1–3 × 10⁻⁶. 19 cm -3 The growth temperature is 450–600℃.

4. The method of claim 1, wherein, The thickness of the homo-epitaxially grown GaN layer is 30-50nm, and the growth temperature is 1000-1100 DEG C.

5. The preparation method according to claim 1, characterized in that, The thickness of the SiN passivation layer is 40-60nm.

6. The method of claim 1, wherein, The thickness of the AlGaN barrier layer is 3-8nm, and the Al component is 20-30%.

7. The preparation method according to claim 1, characterized in that, first GaO x The thickness of the buffer layer is 40-60 nm, the second GaO x The thickness of the second GaO layer is 10-30 nm.

8. The method of claim 1, wherein, The thickness of the SiO2 gate layer is 20-40nm.

9. The method of claim 1, wherein, The metal films of the drain and the source use Ti, Al, Ni or Au, and annealing is carried out at 825 DEG C in an N2 environment.

10. The method of claim 1, wherein, The metal film of the gate uses Ni or Au.

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