Memory device

Abstract

Embodiments provide a memory device whose chip size is not limited by the size of a peripheral circuit. A memory device of an embodiment has: a first chip; and a second chip disposed on the first chip and attached so as to be in contact with the first chip. The first chip includes: a first peripheral circuit disposed on a first semiconductor substrate; a first memory cell array disposed above the first peripheral circuit; and a first electrode disposed above the first memory cell array. The second chip includes: a second electrode in contact with the first electrode; a second memory cell array disposed above the second electrode; a second peripheral circuit disposed above the second memory cell array; a second semiconductor substrate disposed above the second peripheral circuit; and a pad disposed above the second peripheral circuit and capable of receiving a command and an address from a memory controller. The first peripheral circuit controls either one or both of the first memory cell array or the second memory cell array based on a command and an address input from the pad, and the second peripheral circuit controls the other one or both of the first memory cell array or the second memory cell array based on a command and an address input from the pad.

Description

[0001] [Related Application]

[0002] This application claims priority to Japanese Patent Application No. 2021-015875 (Filing Date: February 3, 2021). This application incorporates the entire contents of the base application by reference thereto. TECHNICAL FIELD

[0003] Embodiments relate to a memory device. BACKGROUND

[0004] As a memory device capable of non-volatile storage of data, a NAND (Not AND) flash memory is known. In a memory device such as a NAND flash memory, a three-dimensional memory structure is employed to achieve high integration and large capacity. Also, a peripheral circuit for controlling the three-dimensional memory structure is sometimes provided between a semiconductor substrate and the three-dimensional memory structure. The chip size of the memory device is limited by the larger one of the three-dimensional memory structure and the peripheral circuit. SUMMARY

[0005] Embodiments provide a memory device whose chip size is not limited by the size of a peripheral circuit.

[0006] A memory device of an embodiment includes: a first chip; and a second chip provided on the first chip and attached so as to be in contact with the first chip, the first chip including: a first semiconductor substrate; a first peripheral circuit provided on the first semiconductor substrate; a first memory cell array provided above the first peripheral circuit; and a first electrode provided above the first memory cell array, the second chip including: a second electrode in contact with the first electrode; a second memory cell array provided above the second electrode; a second peripheral circuit provided above the second memory cell array; a second semiconductor substrate provided above the second peripheral circuit; and a pad provided above the second peripheral circuit, capable of receiving an instruction and an address from a memory controller, the first peripheral circuit controlling either one or both of the first memory cell array or the second memory cell array based on the instruction and the address input from the pad, and the second peripheral circuit controlling the other one or both of the first memory cell array or the second memory cell array based on the instruction and the address input from the pad. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 is a block diagram showing the configuration of a memory system including the memory device of the first embodiment.

[0008] Figure 2is a circuit diagram showing an example of the structure of the memory cell array of the memory device of Embodiment 1.

[0009] Figure 3 is a diagram showing an example of the structure of the plurality of chips of the memory device of Embodiment 1.

[0010] Figure 4 is a diagram showing an example of the planar layout in one of the two peripheral circuit chips of the memory device of Embodiment 1.

[0011] Figure 5 is a diagram showing an example of the planar layout in the unit chip of the memory device of Embodiment 1.

[0012] Figure 6 is a diagram showing an example of the planar layout in the other of the two peripheral circuit chips of the memory device of Embodiment 1.

[0013] Figure 7 is a cross-sectional view showing an example of the structure of the memory device of Embodiment 1 and taken along the line VII-VII of Figures 4 to 6 .

[0014] Figure 8 is a cross-sectional view showing an example of the configuration of the memory pillar of the memory device of Embodiment 1.

[0015] Figure 9 is a cross-sectional view showing an example of the structure of the memory cell transistor of Embodiment 1 and taken along the line IX-IX of Figure 8 .

[0016] Figure 10 (A) and Figure 10 (B) are cross-sectional views for explaining the manufacturing steps of the memory device of Embodiment 1.

[0017] Figure 11 is a cross-sectional view for explaining the manufacturing steps of the memory device of Embodiment 1.

[0018] Figure 12 is a cross-sectional view for explaining the manufacturing steps of the memory device of Embodiment 1.

[0019] Figure 13 is a cross-sectional view for explaining the manufacturing steps of the memory device of Embodiment 1.

[0020] Figure 14 is a cross-sectional view for explaining the manufacturing steps of the memory device of Embodiment 1.

[0021] Figure 15is a view showing an example of a stacked structure of a plurality of chips in the memory device of the second embodiment.

[0022] Figure 16 is a view showing an example of a planar layout in one of the two peripheral circuit chips of the memory device of the second embodiment.

[0023] Figure 17 is a view showing an example of a planar layout in the other of the two peripheral circuit chips of the memory device of the second embodiment.

[0024] Figure 18 is a cross-sectional view showing an example of a structure of the memory device of the second embodiment.

[0025] Figure 19 is a view showing an example of a stacked structure of a plurality of chips in the memory device of the first example of the first variation.

[0026] Figure 20 is a cross-sectional view showing an example of a structure of the memory device of the first example of the first variation.

[0027] Figure 21 is a view showing an example of a stacked structure of a plurality of chips in the memory device of the second example of the first variation.

[0028] Figure 22 is a cross-sectional view showing an example of a structure of the memory device of the second example of the first variation.

[0029] Figure 23 is a view showing an example of a stacked structure of a plurality of chips in the memory device of the second variation. DETAILED DESCRIPTION

[0030] Hereinafter, the embodiments will be described with reference to the drawings. The dimensions and the ratios of the drawings are not necessarily the same as those of actual products.

[0031] Further, in the following description, the same reference numerals are attached to the constituent elements having substantially the same functions and configurations. In the case where the elements having the same configuration are particularly distinguished from each other, a character or a numeral which is different from each other is sometimes attached to the end of the same reference numeral.

[0032] 1. First Embodiment

[0033] 1.1 Configuration

[0034] 1.1.1 Memory System

[0035] Figure 1is a block diagram for explaining a configuration of a memory system of the first embodiment. The memory system 1 is a storage device configured to be connected to an external host machine (not illustrated). The memory system 1 is, for example, a memory card such as an SD™ (Secure Digital Touch Memory) card, a UFS (universal flash storage), an SSD (solid state drive). The memory system 1 includes a memory controller 2 and a memory device 3.

[0036] The memory controller 2 includes an integrated circuit such as an SoC (system-on-a-chip). The memory controller 2 controls the memory device 3 according to a request from the host machine. Specifically, for example, the memory controller 2 writes data requested to be written by the host machine to the memory device 3. In addition, the memory controller 2 reads out data requested to be read out by the host machine from the memory device 3 and transmits to the host machine.

[0037] The memory device 3 is a memory that stores data non-volatile. The memory device 3 is, for example, a NAND type flash memory. The memory device 3 includes a plurality of chips (not illustrated).

[0038] The memory controller 2 and the memory device 3 are connected through a bus BUS. The bus BUS is, for example, in accordance with an SDR (single data rate) interface, a Toggle DDR (double data rate) interface, or an ONFI (Open NAND flash interface).

[0039] Signals used in the bus BUS include, for example, an instruction latch enable signal CLE, an address latch enable signal ALE, a write enable signal WEn, a read enable signal REn, a ready / busy signal RBn, and an input / output signal I / O. In this specification, n at the end of the name of the signal means that the signal is activated at an "L (Low)" level. In the following description, the instruction latch enable signal CLE, the address latch enable signal ALE, the write enable signal WEn, the read enable signal REn, the ready / busy signal RBn, and the input / output signal I / O are also simply referred to as signals, respectively.

[0040] The signals CLE and ALE are signals that notify the memory device 3 that the signal I / O of the memory device 3 is an instruction and an address, respectively.

[0041] The signal WEn is a signal for storing the signal I / O in the memory device 3.

[0042] The signal REn is a signal for reading out the signal I / O from the memory device 3.

[0043] The signal RBn is a signal indicating whether the memory device 3 is in a ready state or a busy state. The ready state is a state in which the memory device 3 is able to receive a command from the memory controller 2. The busy state is a state in which the memory device 3 is unable to receive a command from the memory controller 2. The "L" level of the signal RBn indicates the busy state.

[0044] The signal I / O is a signal of, for example, 8 bits. The signal I / O is the entity of data that is transceived between the memory device 3 and the memory controller 2. The signal I / O includes the command CMD, the address information ADD, and the data DAT. The data DAT includes write data and read data.

[0045] 1.1.2 Internal configuration of the memory device

[0046] Next, the internal configuration of the memory device of the first embodiment will be described with reference to the block diagram shown in FIG. 1. Figure 1

[0047] The memory device 3 is provided with a pad group 5, a memory cell array 6, and a peripheral circuit 7.

[0048] The pad group 5 is a plurality of terminals (electrodes) provided on the surface of the memory device 3. The pad group 5 is configured to be connected to the bus BUS. Thus, the memory device 3 is able to communicate with the memory controller 2 via the bus BUS.

[0049] The memory cell array 6 includes a plurality of blocks BLK0 to BLKn (n is an integer of 1 or more). Each block BLK is a collection of a plurality of memory cells that are able to store data non-volatilely, and serves as, for example, an erasing unit of data. In addition, a plurality of bit lines and a plurality of word lines are provided in the memory cell array 6. Each memory cell is associated with, for example, one bit line and one word line. The detailed configuration of the memory cell array 6 will be described later.

[0050] The peripheral circuit 7 is a circuit for performing various actions on the memory cell array 6. The peripheral circuit 7 is provided with an input / output circuit 11, a logic control circuit 12, a command register 13, an address register 14, a sequencer 15, a driver module 16, a row decoder module 17, and a sense amplifier module 18.

[0051] ​The input / output circuit 11 transmits and receives a signal I / O with the memory controller 2. Upon receiving the signal I / O from the memory controller 2, the input / output circuit 11 divides the signal I / O into a command CMD, address information ADD, and data DAT based on information from the logic control circuit 12. The input / output circuit 11 transmits the command CMD to the command register 13 and transmits the address information ADD to the address register 14. In addition, the input / output circuit 11 transmits and receives the data DAT between the sense amplifier module 18.

[0052] The logic control circuit 12 receives the signals CLE, ALE, WEn, and REn from the memory controller 2. The logic control circuit 12 sends information for identifying the command CMD, the address information ADD, and the data DAT within the signal I / O to the input / output circuit 11. In addition, the logic control circuit 12 transmits the signal RBn to the memory controller 2 to inform the memory controller 2 of the state of the memory device 3.

[0053] The command register 13 stores the command CMD from the input / output circuit 11. The command CMD includes, for example, a command for causing the sequencer 15 to perform a read operation, a write operation, an erase operation, and the like.

[0054] The address register 14 stores the address information ADD from the input / output circuit 11. The address information ADD includes, for example, a block address BAd, a page address PAd, and a column address CAd. The block address BAd, the page address PAd, and the column address CAd are used for selection of the block BLK, the word line, and the bit line, respectively, for example.

[0055] The sequencer 15 controls the operations of the entire memory device 3. For example, the sequencer 15 controls the driver module 16, the row decoder module 17, the sense amplifier module 18, and the like based on the command CMD stored in the command register 13 to perform a read operation, a write operation, an erase operation, and the like.

[0056] The driver module 16 generates voltages used in a read operation, a write operation, an erase operation, and the like. Also, the driver module 16 applies the generated voltages to a signal line corresponding to a selected word line based on the page address PAd stored in the address register 14, for example.

[0057] The row decoder module 17 selects one block BLK within the corresponding memory cell array 6 based on the block address BAd stored in the address register 14. Also, the row decoder module 17 transmits the voltage applied to the signal line corresponding to the selected word line to the selected word line within the selected block BLK, for example.

[0058] The sense amplifier module 18 applies a required voltage to each bit line in accordance with the write data received from the memory controller 2 in a write operation. In addition, the sense amplifier module 18 determines the data stored in the memory cell based on the voltage of the bit line in a read operation, and transmits the determination result as read data to the memory controller 2. 1.1.3

[0060] Circuit configuration of memory cell array

[0061] Next, the configuration of the memory cell array included in the memory device of the first embodiment will be described. Figure 2 is an example of a circuit diagram showing the configuration of the memory cell array of the memory device of the first embodiment. Figure 2 In the drawing, one block BLK in the memory cell array 6 is extracted and shown. As shown in the drawing, the block BLK includes, for example, four string units SUO to SU3. Figure 2 As shown in the drawing, the block BLK includes, for example, four string units SUO to SU3.

[0062] Each string unit SU includes a plurality of NAND strings NS (m is an integer of two or more) each of which is associated with a bit line BL0 to BLm. The NAND string NS includes, for example, memory cell transistors MTO to MT7, and selection transistors ST1 and ST2.

[0063] The memory cell transistor MT includes a control gate and a charge storage film, and stores data nonvolatilely. The selection transistors ST1 and ST2 are used for selection of the string unit SU in each operation.

[0064] In each NAND string NS, the memory cell transistors MTO to MT7 are connected in series. The selection transistor ST1 is connected between one end of the series-connected memory cell transistors MTO to MT7 and the associated bit line BL. The selection transistor ST2 is connected between the other end of the series-connected memory cell transistors MTO to MT7 and the source line SL.

[0065] In the same block BLK, the gates of the plurality of selection transistors ST1 included in the string units SUO to SU3 are commonly connected to selection gate lines SGD0 to SGD3, respectively. The control gates of the plurality of memory cell transistors MTO to MT7 are commonly connected to word lines WL0 to WL7, respectively. The gates of the plurality of selection transistors ST2 are commonly connected to a selection gate line SGS. Voltages are applied to the selection gate lines SGD0 to SGD3 and SGS, and the word lines WL0 to WL7 via the row decoder module 17.

[0066] The bit lines BL0 to BLm are shared among the plurality of blocks BLK. The NAND strings NS corresponding to the same column address are connected to the same bit line BL. The word lines WL0 to WL7 are provided for each block BLK. The source line SL is shared among the plurality of blocks BLK, for example. Voltages are applied to the bit lines BL0 to BLm via the sense amplifier module 18.

[0067] A set of the plurality of memory cell transistors MT connected to the common word line WL within one string assembly SU is referred to as a cell assembly CU, for example, and serves as a write unit of data. The storage capacity of the cell assembly CU including the memory cell transistors MT each storing one bit of data is defined as "one page of data", for example. One page of data serves as a read unit of data, for example. The cell assembly CU can have a storage capacity of two or more pages of data depending on the number of bits of data stored by the memory cell transistors MT.

[0068] Further, the circuit configuration of the memory cell array 6 described above is only an example and is not limited thereto. The number of the string assemblies SU included in each block BLK can be designed to be any number, for example. The number of the memory cell transistors MT and the selection transistors ST1 and ST2 included in each NAND string NS can be designed to be any number, respectively.

[0069] 1.1.4 Mounting structure of memory device

[0070] Figure 3 is a view showing an example of a mounting structure of a plurality of chips in the memory device of the first embodiment. As shown in Figure 3 , the memory device 3 is mounted in a four-chip stacked manner.

[0071] Specifically, the memory device 3 includes the peripheral circuit chips 100 and 400, and the cell chips 200 and 300. The memory cell arrays 6a and 6b are formed in the cell chips 200 and 300, respectively. The peripheral circuit 7a corresponding to the memory cell array 6a is formed in the peripheral circuit chip 100. In the peripheral circuit chip 400, the peripheral circuit 7b corresponding to the memory cell array 6b is formed, in addition to the pad group 5. The peripheral circuits 7a and 7b can each include the input / output circuit 11, the logic control circuit 12, the command register 13, the address register 14, the sequencer 15, the driver module 16, the row decoder module 17, and the sense amplifier module 18.

[0072] The peripheral circuit chip 100, the cell chip 200, the cell chip 300, and the peripheral circuit chip 400 each have a first face and a second face facing each other.

[0073] The first surface of the peripheral circuit chip 100 is not connected to any chip. The second surface of the peripheral circuit chip 100 is connected to the first surface of the unit chip 200 by bonding. The second surface of the unit chip 200 is connected to the first surface of the unit chip 300 by bonding. The second surface of the unit chip 300 is connected to the first surface of the peripheral circuit chip 400 by bonding. The second surface of the peripheral circuit chip 400 is not connected to any chip.

[0074] Hereinafter, the peripheral circuit chip 100 and the unit chip 200 bonded together are appropriately referred to as a first chip. Hereinafter, the unit chip 300 and the peripheral circuit chip 400 bonded together are appropriately referred to as a second chip. The second chip includes the pad group 61. The pad group 61 is disposed above the peripheral circuit 7b and can receive a command and an address from the memory controller 2.

[0075] The peripheral circuit 7a controls either one or both of the memory cell array 6a or the memory cell array 6b based on the command and the address input from the pad group 61.

[0076] The peripheral circuit 7b controls the other one or both of the memory cell array 6a or the memory cell array 6b based on the command and the address input from the pad group 61.

[0077] Hereinafter, the peripheral circuit chip 100, the unit chip 200, the unit chip 300, and the peripheral circuit chip 400 are sometimes simply referred to as "chips" without particularly distinguishing each of them. In addition, the lamination surface (bonding surface or joining surface) of the peripheral circuit chip 100, the unit chip 200, the unit chip 300, and the peripheral circuit chip 400 is referred to as an "XY plane" or simply "plane". Two directions intersecting with each other in the XY plane are referred to as an "X direction" and a "Y direction". A lamination direction from the peripheral circuit chip 100 toward the peripheral circuit chip 400 is referred to as a "Z direction".

[0078] 1.1.5 Planar Layout of Memory Device

[0079] Figures 4 to 6 is a view showing an example of a planar layout of the memory device of the first embodiment. Figure 4 shows a planar layout in the peripheral circuit chip 100. Figure 5 shows a planar layout in the unit chips 200 and 300. Figure 6 shows a planar layout in the peripheral circuit chip 400.

[0080] First, the planar layout of the peripheral circuit chip 100 is described with reference to Figure 4

[0081] As shown in FIG. 2, the peripheral circuit chip 100 includes a peripheral circuit 7a, a peripheral circuit 7b, a memory cell array 6a, and a memory cell array 6b. The peripheral circuit 7a and the peripheral circuit 7b are disposed above the memory cell array 6a and the memory cell array 6b. The memory cell array 6a and the memory cell array 6b are disposed below the peripheral circuit 7a and the peripheral circuit 7b. Figure 4 ​As shown, the peripheral circuit chip 100 has, for example, a peripheral circuit region PERI and four wiring connection regions WJCT in the XY plane.

[0082] The Peripheral Circuit Region (PERI) is the region that forms the peripheral circuit 7. The Peripheral Circuit Region (PERI) is located in the center of the peripheral circuit chip 100.

[0083] The wiring connection area WJCT is formed for the chip ( Figure 4 In the example, the peripheral circuit chip 100 and the chip connected to it are... Figure 4 In the example, this refers to the area where the wiring for the unit chip 200 is electrically connected. Two of the four wiring connection areas WJCT are configured along the X direction, separated by the peripheral circuit area PERI. The remaining two of the four wiring connection areas WJCT are configured along the Y direction, separated by the peripheral circuit area PERI.

[0084] The peripheral circuit area PERI has, for example, two line decoder areas RD, two sense amplifier areas SA, and other areas OTH.

[0085] The Other Area (OTH) is where the input / output circuits 11, logic control circuits 12, instruction register 13, address register 14, sequencer 15, and driver module 16 are formed. The Other Area (OTH) is located in the central part of the Peripheral Circuits Area (PERI).

[0086] The sensing amplifier region SA is the region that forms the sensing amplifier module 18. The two sensing amplifier regions SA are arranged in a manner that separates them from the other regions OTH along the Y direction.

[0087] The line decoder region RD is the region that forms the line decoder module 17. The two line decoder regions RD are arranged along the X direction, separated from the other regions OTH and the two sense amplifier regions SA.

[0088] Next, refer to Figure 5 The planar layout of unit chips 200 and 300 is explained.

[0089] like Figure 5 As shown, the peripheral circuit chip 100 has, for example, a cell region CA, two bit line connection regions BLHU, two word line connection regions WLHU, and four wiring connection regions WJCT in the XY plane.

[0090] Cell region CA is the region that forms the memory cell array 6. Cell region CA is located in the center of each of cell chips 200 and 300.

[0091] The word line connection area (WLHU) is the area for bringing out word lines from memory cell array 6. The two word line connection areas (WLHU) are configured along the X direction, separated by cell area (CA) and two bit line connection areas (BLHU).

[0092] The bit line connection area (BLHU) is the area for bringing out bit lines from memory cell array 6. Two bit line connection areas (BLHU) are configured along the Y direction, separated by cell area (CA).

[0093] Two of the four wiring connection areas WJCT are configured with two word line connection areas WLHU separated by a distance along the X direction. The remaining two of the four wiring connection areas WJCT are configured with two bit line connection areas BLHU separated by a distance along the Y direction.

[0094] Next, refer to Figure 6 The planar layout of the peripheral circuit chip 400 is described.

[0095] like Figure 6 As shown, the peripheral circuit chip 400, for example, has a peripheral circuit region PERI, four wiring connection regions WJCT, and a pad region PD in the XY plane. The configuration of the peripheral circuit region PERI and the four wiring connection regions WJCT is the same as that of the peripheral circuit chip 100, therefore, description is omitted.

[0096] The pad area PD is the area that forms pad group 5. In the XY plane, the pad area PD is positioned on the outside relative to the surrounding circuit area PERI and the four wiring connection areas WJCT.

[0097] also, Figures 4 to 6 The planar layout shown is just one example, and the planar layout of memory device 3 is not limited to this. For example, the word line connection area WLHU, the bit line connection area BLHU, and the wiring connection area WJCT can also be located inside the cell area CA.

[0098] 1.1.6 Cross-sectional structure of memory devices

[0099] Figure 7 This is an example illustrating the structure of the memory device according to the first embodiment, and along... Figures 4 to 6 Sectional view of line VII-VII. Figure 7 In the example shown, the XZ cross section of the memory device 3 is shown, which includes the wiring connection area WJCT, the pad area PD, the peripheral circuit area PERI, the word line connection area WLHU, and the cell area CA.

[0100] First, the connection configuration between chips 100 and 400 will be explained.

[0101] like Figure 7As shown, the peripheral circuit chip 100 includes a semiconductor substrate 40a and an insulator layer 41a. The semiconductor substrate 40a and the insulator layer 41a have a first surface and a second surface facing each other along the Z direction, respectively. The first surface of the semiconductor substrate 40a corresponds to the first surface of the peripheral circuit chip 100. The second surface of the semiconductor substrate 40a and the first surface of the insulator layer 41a are in contact with each other. The second surface of the insulator layer 41a corresponds to the second surface of the peripheral circuit chip 100.

[0102] The peripheral circuit 7a is formed in a boundary region of the semiconductor substrate 40a and the insulator layer 41a. The electrodes 51a and 52a are provided on the second surface of the insulator layer 41a. For example, a row decoder module 17 in the peripheral circuit 7a is electrically connected to the electrode 51a via a wiring layer 53a. Also, for example, an input / output circuit 11 or a logic control circuit 12 in the peripheral circuit 7a is electrically connected to the electrode 52a via a wiring layer 54a.

[0103] The unit chip 200 includes an insulator layer 42a. A first surface and a second surface of the insulator layer 42a facing each other along the Z direction correspond to a first surface and a second surface of the unit chip 200, respectively. The memory cell array 6a is formed in the insulator layer 42a. The electrodes 55a and 56a are provided on the first surface of the insulator layer 42a. The electrode 57a is provided on the second surface of the insulator layer 42a. For example, the memory cell array 6a is electrically connected to the electrode 55a via a wiring layer 58a. Also, for example, the electrode 56a is electrically connected to the electrode 57a via a wiring layer 59a.

[0104] The unit chip 300 includes an insulator layer 42b. A first surface and a second surface of the insulator layer 42b facing each other along the Z direction correspond to a first surface and a second surface of the unit chip 300, respectively. The memory cell array 6b is formed in the insulator layer 42b. The electrode 57b is provided on the first surface of the insulator layer 42b. The electrodes 55b and 56b are provided on the second surface of the insulator layer 42b. For example, the memory cell array 6b is electrically connected to the electrode 55b via a wiring layer 58b. Also, for example, the electrode 57b is electrically connected to the electrode 56b via a wiring layer 59b.

[0105] The peripheral circuit chip 400 includes a semiconductor substrate 40b and an insulator layer 41b. The semiconductor substrate 40b has a thickness equivalent to that of the semiconductor substrate 40a along the Z direction. The semiconductor substrate 40b and the insulator layer 41b have a first surface and a second surface facing each other along the Z direction, respectively. The first surface of the insulator layer 41b corresponds to the first surface of the peripheral circuit chip 400. The second surface of the insulator layer 41b and the first surface of the semiconductor substrate 40b are in contact with each other. The second surface of the semiconductor substrate 40b corresponds to the second surface of the peripheral circuit chip 400.

[0106] A peripheral circuit 7b is formed in a boundary region of the semiconductor substrate 40b and the insulator layer 41b. Electrodes 51b and 52b are provided on the first face of the insulator layer 41b. For example, a row decoder module 17 in the peripheral circuit 7b is electrically connected to the electrode 51b via a wiring layer 53b. Also, for example, an input / output circuit 11 or a logic control circuit 12 in the peripheral circuit 7b is electrically connected to the electrode 52b via a wiring layer 54b.

[0107] An electrode 61 is provided on the second face of the semiconductor substrate 40b. For example, the electrode 61 is electrically connected to the wiring layer 54b via a contact 60 formed so as to penetrate the semiconductor substrate 40b. The contact 60 and the electrode 61 constitute one of the pad groups 5.

[0108] The electrodes 51a, 52a, 55a to 57a, 51b, 52b, and 55b to 57b, and the wiring layers 53a, 54a, 58a, 59a, 53b, 54b, 58b, and 59b contain, for example, copper or a copper alloy in which copper is the main component. The contact 60 contains, for example, copper or a copper alloy in which copper is the main component. The electrode 61 contains, for example, aluminum.

[0109] The second face of the insulator layer 41a and the first face of the insulator layer 42a are joined so that the corresponding electrodes are in contact with each other. Figure 7 In the example of Fig. 2, the second face of the insulator layer 41a and the first face of the insulator layer 42a are joined so that the electrode 51a and the electrode 55a are in contact and the electrode 52a and the electrode 56a are in contact.

[0110] The second face of the insulator layer 42a and the first face of the insulator layer 42b are joined so that the corresponding electrodes are in contact with each other. Figure 7 In the example of Fig. 3, the second face of the insulator layer 42a and the first face of the insulator layer 42b are joined so that the electrode 57a and the electrode 57b are in contact. The second face of the insulator layer 42a and the first face of the insulator layer 42b are in contact.

[0111] The second face of the insulator layer 42b and the first face of the insulator layer 41b are joined so that the corresponding electrodes are in contact with each other. Figure 7 In the example of Fig. 4, the second face of the insulator layer 42b and the first face of the insulator layer 41b are joined so that the electrode 55b and the electrode 51b are in contact and the electrode 56b and the electrode 52b are in contact.

[0112] By being configured as described above, the memory device 3 is able to transmit various signals received from the pad groups 5 to the peripheral circuits 7a and 7b. The peripheral circuits 7a and 7b are each able to supply the required voltage to the memory cell arrays 6a and 6b on the basis of the various signals received from the pad groups 5.

[0113] 1.1.7 Structure of Memory Cell Array

[0114] Next, the description will be continued with reference to Figure 7 The configuration of the memory cell array 6 will be described. Hereinafter, the configuration of the memory cell array 6b will be described. That is, the memory cell array 6b is formed by alternately stacking the insulator layer and the conductor layer in the Z direction. Figure 7 In the memory cell array 6b, the planar direction corresponds to the Z direction. Further, the memory cell array 6a is equivalent to the memory cell array obtained by forming the memory cell array 6b in the Z direction in the reverse direction, and thus the description will be omitted.

[0115] Inside the insulator layer 42b, the conductor layers 20 to 24 are provided, for example.

[0116] The conductor layer 20 is formed in a plate shape extending along the XY plane, for example, and serves as a source line SL. The conductor layer 20 contains silicon, for example.

[0117] Above the conductor layer 20, the conductor layer 21 is provided with the insulator layer interposed therebetween. The conductor layer 21 serves as a selection gate line SGS.

[0118] Above the conductor layer 21, a plurality of layers of the insulator layer and the conductor layer 22 are stacked in alternation. The conductor layers 22 serve as word lines WL0 to WL7, for example, in order from the side of the conductor layer 20.

[0119] Above the conductor layer 22 of the uppermost layer, the conductor layer 23 is provided with the insulator layer (not shown) interposed therebetween. The conductor layer 23 serves as a selection gate line SGD.

[0120] The conductor layers 21 to 23 are formed in a plate shape extending along the XY plane, for example, and contain tungsten (W), for example.

[0121] Above the conductor layer 23, a plurality of conductor layers 24 are provided with the insulator layer (not shown) interposed therebetween. The conductor layers 24 extend along the Y direction, for example. The plurality of conductor layers 24 are arranged along the X direction. The plurality of conductor layers 24 serve as bit lines BL, respectively. The conductor layers 24 contain copper (Cu), for example.

[0122] In the following description, the conductor layers 20 to 24 are also collectively referred to as "stacked wires".

[0123] The conductor layers 21 to 23 are electrically connected to the corresponding peripheral circuit 7 via the wire junction region WJCT after being led out by the contact extending in the Z direction, respectively. Figure 7In the present embodiment, as an example, a case where the conductive layer 21 is electrically connected to the electrode 55a via the contact 50a is shown. Thereby, the peripheral circuit 7a can apply a desired voltage to the selection gate line SGD, the plurality of word lines WL, and the selection gate line SGS in the memory cell array 6a, respectively. In addition, the peripheral circuit 7b can apply a desired voltage to the selection gate line SGD, the plurality of word lines WL, and the selection gate line SGS in the memory cell array 6b, respectively.

[0124] Further, although Figure 7 In the present embodiment, as an example, a case where the conductive layer 21 is electrically connected to the electrode 55a via the contact 50a is shown. Thereby, the peripheral circuit 7a can apply a desired voltage to the selection gate line SGD, the plurality of word lines WL, and the selection gate line SGS in the memory cell array 6a, respectively. In addition, the peripheral circuit 7b can apply a desired voltage to the selection gate line SGD, the plurality of word lines WL, and the selection gate line SGS in the memory cell array 6b, respectively.

[0125] In addition, in the cell region CA, the memory cell arrays 6a and 6b have a plurality of memory pillars MP. The plurality of memory pillars MP respectively penetrate the selection gate line SGD, the plurality of word lines WL, and the selection gate line SGS, and reach the source line SL. The plurality of memory pillars MP are respectively configured to electrically connect between the bit line BL and the source line SL corresponding to the plurality of memory pillars MP, respectively. The intersection portion of the memory pillar MP and the word line functions as one memory cell transistor.

[0126] 1.1.8 Memory Pillar and Laminated Wiring

[0127] Figure 8 is a cross-sectional view showing an example of the configuration of the memory pillar and the laminated wiring of the memory device of the first embodiment. Figure 8 In the present embodiment, as an example, a case where the conductive layer 21 is electrically connected to the electrode 55a via the contact 50a is shown. Thereby, the peripheral circuit 7a can apply a desired voltage to the selection gate line SGD, the plurality of word lines WL, and the selection gate line SGS in the memory cell array 6a, respectively. In addition, the peripheral circuit 7b can apply a desired voltage to the selection gate line SGD, the plurality of word lines WL, and the selection gate line SGS in the memory cell array 6b, respectively. Figure 7 of the memory cell array 6b. That is, Figure 8 In the present embodiment, as an example, a case where the conductive layer 21 is electrically connected to the electrode 55a via the contact 50a is shown. Thereby, the peripheral circuit 7a can apply a desired voltage to the selection gate line SGD, the plurality of word lines WL, and the selection gate line SGS in the memory cell array 6a, respectively. In addition, the peripheral circuit 7b can apply a desired voltage to the selection gate line SGD, the plurality of word lines WL, and the selection gate line SGS in the memory cell array 6b, respectively.

[0128] As shown in Figure 8 The memory pillar MP is provided so as to extend along the Z direction, penetrates the conductive layers 21 to 23, and has a bottom portion in contact with the conductive layer 20. The memory pillar MP includes, for example, a core film 30, a semiconductor film 31, a tunnel insulating film 32, a charge storage film 33, a barrier insulating film 34, and a semiconductor portion 35.

[0129] The core film 30 extends along the Z direction, and an upper end thereof is located, for example, above the uppermost conductive layer 23. A lower end of the core film 30 is located within the layer of the conductive layer 20. The core film 30 includes, for example, an insulator such as silicon oxide (SiO2).

[0130] The semiconductor film 31 covers the bottom surface and the side surface of the core film 30. The lower end of the semiconductor film 31 is in contact with the conductive layer 21, and the upper end thereof is positioned at a layer higher than the uppermost conductive layer 23. The semiconductor film 31 contains, for example, polysilicon.

[0131] The tunnel insulating film 32 covers the side surface of the semiconductor film 31. The tunnel insulating film 32 contains, for example, silicon oxide.

[0132] The charge storage film 33 covers the side surface of the tunnel insulating film 32. The charge storage film 33 contains, for example, silicon nitride (SiN).

[0133] The barrier insulating film 34 covers the side surface of the charge storage film 33. The barrier insulating film 34 contains, for example, silicon oxide.

[0134] The semiconductor portion 35 covers the upper surface of the core film 30 and is in contact with the inner wall of the portion of the semiconductor film 31 provided above the core film 30. The semiconductor portion 35 is provided, for example, in a cylindrical shape and reaches the upper end of the memory pillar MP.

[0135] The contact 36 is provided on the upper surface of the memory pillar MP. The upper surface of the contact 36 is in contact with the conductive layer 24. Thus, the memory pillar MP is configured to electrically connect between the conductive layer 20 and the conductive layer 24.

[0136] Figure 9 is Figure 8 a cross-sectional view of the memory pillar MP along the IX-IX line. Figure 9 indicates an example of the cross-sectional structure of the conductive layer 22 including the memory pillar MP and the periphery thereof.

[0137] As Figure 9 indicated, the core film 30 is provided at substantially the center of the memory pillar MP. Further, the semiconductor film 31, the tunnel insulating film 32, the charge storage film 33, and the barrier insulating film 34 are provided in a concentric circular shape around the core film 30. Also, the conductive layer 22 is provided in a manner to cover the periphery of the barrier insulating film 34.

[0138] In the structure described above, the portion where the memory pillar MP and the conductive layer 21 cross functions as the selection transistor ST2. The portion where the memory pillar MP and the conductive layer 22 cross functions as the memory cell transistor MT0 to MT7. The portion where the memory pillar MP and the conductive layer 23 cross functions as the selection transistor ST1.

[0139] That is, the semiconductor film 31 functions as each channel of the memory cell transistor MT and the selection transistors ST1 and ST2. Thus, the memory pillar MP functions as, for example, one NAND string NS, respectively.

[0140] Furthermore, the structure of the memory cell array 6 described above is only one example, and the memory cell array 6 can also have other structures. For example, the number of conductor layers 22 is designed based on the number of word lines WL. Multiple conductor layers 21 and 23 can also be configured as multiple layers for the select gate lines SGS and SGD, respectively. When the select gate line SGS is configured as multiple layers, a conductor of a different material than the conductor layer 21 can also be used. The memory pillar MP and the conductor layer 24 can be electrically connected via two or more contacts, or via other wiring.

[0141] 1.2 Manufacturing Method

[0142] Hereinafter, an example of a series of manufacturing steps of the memory device according to the first embodiment will be described. Figures 10 to 14 Each of the following examples illustrates a cross-sectional structure of a structure corresponding to a memory cell array during the manufacturing process of the memory device according to the first embodiment. Furthermore, the cross-sectional views of the manufacturing steps referenced below include structures corresponding to... Figure 7 The cross section corresponding to the cross section of the memory device 3 shown.

[0143] First, such as Figure 10 As shown in (A), a peripheral circuit chip 100 is formed. Specifically, a peripheral circuit 7a, including transistors, is formed on a semiconductor substrate 40a. The peripheral circuit 7a is covered by an insulating layer 41a. A plurality of electrodes, including electrodes 51a and 52a, are formed exposed on the insulating layer 41a. Furthermore, a plurality of wiring layers, including wiring layers 53a and 54a, are formed within the insulating layer 41a, and these wiring layers electrically connect the plurality of electrodes including electrodes 51a and 52a to the peripheral circuit 7a. Furthermore, although... Figure 10 (A) is not illustrated, but the peripheral circuit chip 400 can be formed in parallel with the formation of the peripheral circuit chip 100 by the same steps as the peripheral circuit chip 100.

[0144] In addition, in parallel with the manufacturing of the peripheral circuit chip 100, such as Figure 10(B) and form the unit chip 200. Specifically, an insulator layer 71 is formed on the substrate 70 as a buffer layer. The insulator layer 71 contains, for example, silicon oxide. Above the insulator layer 71, a memory cell array 6a is formed. The memory cell array 6a is covered with an insulator layer 42a. A plurality of electrodes including the electrodes 55a and 56a are formed in a manner so as to be exposed on the insulator layer 42a. Further, a plurality of wiring layers including a wiring layer 58a are formed in the insulator layer 42a, which electrically connect the plurality of electrodes including the electrodes 55a and the memory cell array 6a. In addition, a plurality of wiring layers including a wiring layer 59a are formed in the insulator layer 42a, which physically connect the plurality of electrodes including the electrodes 56a and the insulator layer 71. Further, although not illustrated in (B), a plurality of electrodes including the electrodes 51a and 52a are formed on the peripheral circuit chip 100 by steps equivalent to those of the unit chip 200 in parallel with the formation of the unit chip 200. Figure 10 (B) and form the unit chip 200. Specifically, an insulator layer 71 is formed on the substrate 70 as a buffer layer. The insulator layer 71 contains, for example, silicon oxide. Above the insulator layer 71, a memory cell array 6a is formed. The memory cell array 6a is covered with an insulator layer 42a. A plurality of electrodes including the electrodes 55a and 56a are formed in a manner so as to be exposed on the insulator layer 42a. Further, a plurality of wiring layers including a wiring layer 58a are formed in the insulator layer 42a, which electrically connect the plurality of electrodes including the electrodes 55a and the memory cell array 6a. In addition, a plurality of wiring layers including a wiring layer 59a are formed in the insulator layer 42a, which physically connect the plurality of electrodes including the electrodes 56a and the insulator layer 71. Further, although not illustrated in (B), a plurality of electrodes including the electrodes 51a and 52a are formed on the peripheral circuit chip 100 by steps equivalent to those of the unit chip 200 in parallel with the formation of the unit chip 200.

[0145] Next, as illustrated in (C), the peripheral circuit chip 100 is attached to the unit chip 200. Specifically, the plurality of electrodes including the electrodes 51a and 52a of the peripheral circuit chip 100 are joined to the plurality of electrodes including the electrodes 55a and 56a of the unit chip 200, respectively. As the joining method, for example, a joining method using mechanical pressure, a joining method by inert plasma treatment on a joining surface, or a joining method using an organic adhesive or the like can be applied. Figure 11

[0146] After the peripheral circuit chip 100 is attached to the unit chip 200, the substrate 70 is removed with a chemical liquid such as potassium hydroxide (KOH). By this, the insulator layers around the joined electrodes can also be joined to each other.

[0147] After the substrate 70 is removed, an insulator layer 72 is formed on the upper surface of the insulator layer 71. The insulator layer 72 is a layer that generates stress in a direction opposite to the warping generated in the unit chip 200 due to the removal of the substrate 70. The insulator layer 72 contains, for example, silicon nitride. By this, the influence of the warping generated in the unit chip 200 after the removal of the substrate 70 can be reduced.

[0148] Next, the predetermined regions of the insulator layers 71 and 72 for forming the plurality of electrodes including the electrodes 57a are removed, and the plurality of wiring layers including the wiring layer 59a are exposed. Then, as illustrated in (E), the plurality of electrodes including the electrodes 57a are formed in the regions after the removal of the insulator layers 71 and 72 in a manner so as to be electrically connected to the plurality of wiring layers including the wiring layer 59a, respectively. Figure 12

[0149] Further, although not illustrated in (E), a plurality of electrodes including the electrodes 53a and 54a are formed on the peripheral circuit chip 100 by steps equivalent to those of the unit chip 200 in parallel with the formation of the unit chip 200. Figure 11 Figure 12 ​​​The steps shown related to peripheral circuit chip 100 and unit chip 200 can also be applied to peripheral circuit chip 400 and unit chip 300.

[0150] In other words, through with Figure 11 The same steps are used to bond the peripheral circuit chip 400 to the unit chip 300. Specifically, the plurality of electrodes including electrodes 51b and 52b of the peripheral circuit chip 400 are respectively bonded to the plurality of electrodes including electrodes 55b and 56b of the unit chip 300.

[0151] After the peripheral circuit chip 400 is bonded to the unit chip 300, the substrate (not shown) of the unit chip 300 is removed using a solution such as potassium hydroxide (KOH). After removing the substrate of the unit chip 300, an insulating layer 74 is formed on the upper surface of the insulating layer 73 of the unit chip 300, which corresponds to the insulating layer 71. The insulating layer 73 contains, for example, silicon oxide. The insulating layer 74 is a layer that generates stress in the opposite direction to the warping generated in the unit chip 300 due to the removal of the substrate. The insulating layer 74 contains, for example, silicon nitride.

[0152] Next, the predetermined regions in insulating layers 73 and 74 for forming the plurality of electrodes including electrode 57b are removed, exposing the plurality of wiring layers including wiring layer 59b. Then, by... Figure 12 Similarly, in a manner that electrically connects to the multiple wiring layers including wiring layer 59b, multiple electrodes including electrode 57b are formed in the region after the insulation layers 73 and 74 are removed.

[0153] The steps related to peripheral circuit chip 400 and unit chip 300 can be performed in parallel with the steps related to peripheral circuit chip 100 and unit chip 200.

[0154] Then, as Figure 13 As shown, unit chip 200 and unit chip 300 are bonded together. Figure 13 The bonding steps and Figure 11 The bonding steps are the same.

[0155] Next, as Figure 14 As shown, a group of solder pads 5 is formed. Specifically, a predetermined area in the semiconductor substrate 40b and insulating layer 41b of the peripheral circuit chip 400 for forming the contact 60 is removed. This exposes a predetermined wiring layer 54b that is electrically connected to the electrode 61. The contact 60 is formed in the removed area of ​​the semiconductor substrate 40b and insulating layer 41b. Then, the electrode 61 is formed in connection with the upper surface of the contact 60.

[0156] The memory device 3 is formed by the steps described above.

[0157] 1.3Effects of the Embodiments

[0158] According to the first embodiment, the peripheral circuit chip 100 and the unit chip 200 include the semiconductor substrate 40a, the electrode 57a, and the memory cell array 6a provided between the semiconductor substrate 40a and the electrode 57a. The peripheral circuit chip 400 and the unit chip 300 include the semiconductor substrate 40b, the electrode 57b which is connected to the electrode 57a, and the memory cell array 6b provided between the semiconductor substrate 40b and the electrode 57b. Thus, the memory device 3 can have one peripheral circuit region PERI at each of both ends in the stacking direction of the chip. Therefore, compared with the case where the peripheral circuit region PERI is provided at only one side in the stacking direction of the chip, the peripheral circuit region PERI can be increased. Thus, a memory device whose chip size (area) is not limited by the size of the peripheral circuit can be provided.

[0159] If supplemented, by increasing the number of layers of the word line WL, the memory capacity per unit area of the chip in the XY plane can be increased. Thus, the chip size required for a memory device having a certain specified memory capacity can be reduced in correspondence with the increase in the number of layers of the word line WL. However, the chip size required for the peripheral circuit hardly changes depending on the number of layers of the word line WL. Therefore, if the number of layers of the word line WL is increased to some extent, the chip size required for the memory device is limited by the chip size required for the peripheral circuit, so that the effect of reduction accompanying the increase in the number of layers of the word line WL cannot be expected.

[0160] According to the first embodiment, the memory device 3 has the peripheral circuit chips 100 and 400 at both ends. Thus, compared with the case where there is only one peripheral circuit chip, the amount of the peripheral circuit that can be formed per unit area of the chip can be doubled. Thus, a memory device whose chip size is not limited by the size of the peripheral circuit can be provided.

[0161] In addition, the four chips 100 to 400 can be formed in parallel. That is, the peripheral circuit 7 and the memory cell array 6 can be formed in parallel. Thus, compared with the case where the memory cell array 6 is formed after the step of forming the peripheral circuit 7, the time required for manufacturing the memory device 3 can be shortened.

[0162] 2. Second Embodiment

[0163] The memory device of the second embodiment differs from the first embodiment in that the thicknesses of the semiconductor substrates of the two peripheral circuit chips are significantly different. Hereinafter, regarding the memory device of the second embodiment, the configuration different from the first embodiment will mainly be described, and the configuration common to the first embodiment will be omitted.

[0164] 2.1 Mounting structure of memory device

[0165] Figure 15 is a view showing an example of a mounting structure of a plurality of chips in the memory device of the second embodiment. Figure 15 corresponding to the Figure 3 .

[0166] Specifically, the memory device 3A includes the peripheral circuit chips 100A and 400A, and the cell chips 200 and 300.

[0167] The peripheral circuit 7a' is formed in the peripheral circuit chip 100A. The peripheral circuit 7a' can include the input / output circuit 11, the logic control circuit 12, the instruction register 13, the address register 14, the sequencer 15, the driver module 16, and the row decoder module 17. The driver module 16 formed in the peripheral circuit 7a' includes a portion that supplies a voltage to the row decoder module 17.

[0168] On the other hand, the pad group 5 and the peripheral circuit 7b' are formed in the peripheral circuit chip 400. The peripheral circuit 7b' can include the input / output circuit 11, the logic control circuit 12, the instruction register 13, the address register 14, the sequencer 15, the driver module 16, and the sense amplifier module 18. The driver module 16 formed in the peripheral circuit 7b' does not include a portion that supplies a voltage to the row decoder module 17.

[0169] As such, the peripheral circuit chip 100A includes a circuit group that applies a high voltage such as the voltage VPGM. On the other hand, the peripheral circuit chip 400A does not include a circuit group that applies a high voltage such as the voltage VPGM. The voltage VPGM is a voltage applied to the word line WL of the memory cell transistor MT that is a target of writing in a writing operation of data. The voltage VPGM can be, for example, 20 V or more.

[0170] 2.2 Planar layout of memory device

[0171] Figure 16 and Figure 17 is a view showing an example of a planar layout of the memory device of the second embodiment. Figure 16 shows the planar layout in the peripheral circuit chip 100A. Figure 17 shows the planar layout in the peripheral circuit chip 400A. Figure 16 and Figure 17 corresponding to the Figure 4 and Figure 6 .

[0172] First, the planar layout of the peripheral circuit chip 100A will be described with reference to Figure 16 .

[0173] As Figure 16 illustrated, the peripheral circuit chip 100A has, for example, a peripheral circuit region PERI and four wiring junction regions WJCT in the XY plane.

[0174] The peripheral circuit region PERI has, for example, two row decoder regions RD and other regions OTH, but does not have a sense amplifier region SA. The circuit provided in the other regions OTH of the peripheral circuit chip 100A includes a circuit that processes a high voltage such as the voltage VPGM.

[0175] Next, the planar layout of the peripheral circuit chip 400A will be described with reference to Figure 16 .

[0176] As Figure 16 illustrated, the peripheral circuit chip 400A has, for example, a peripheral circuit region PERI, four wiring junction regions WJCT, and a pad region PD in the XY plane. The four wiring junction regions WJCT and the pad region PD are arranged similarly to the peripheral circuit chip 400 in the peripheral circuit chip 400 of the first embodiment, and thus the description thereof is omitted. Figure 6

[0177] The peripheral circuit region PERI has, for example, two sense amplifier regions SA and other regions OTH, but does not have a row decoder region RD. The circuit provided in the other regions OTH of the peripheral circuit chip 400A does not include a circuit that processes a high voltage such as the voltage VPGM.

[0178] 2.3 Cross-sectional structure of memory device

[0179] Figure 18 is a cross-sectional view taken along the line XVIII-XVIII of the memory device of the second embodiment. Figure 16 and Figure 17 . Figure 18 Corresponds to the peripheral circuit chip 400 in the first embodiment. Figure 7 .

[0180] As Figure 18 illustrated, the peripheral circuit 7a' is formed in a boundary region of the semiconductor substrate 40a and the insulator layer 41a of the peripheral circuit chip 100. The electrodes 51a and 52a are provided on the second face of the insulator layer 41a. For example, the row decoder module 17 in the peripheral circuit 7a' is electrically connected to the electrode 51a via the wiring layer 53a, and is electrically connected to the electrode 62a via a wiring layer not shown.

[0181] ​The electrodes 55a, 56a, and 63a are provided on the first surface of the insulator layer 42a of the unit chip 200. The electrodes 57a and 65a are provided on the second surface of the insulator layer 42a. The electrode 63a is electrically connected to the electrode 65a via the wiring layer 64a, for example.

[0182] The electrodes 57b and 65b are provided on the first surface of the insulator layer 42b of the unit chip 300. The electrode 56b is provided on the second surface of the insulator layer 42b. The memory cell array 6b is electrically connected to the electrode 65b via the wiring layers 58b and 64b, for example.

[0183] The peripheral circuit chip 400 includes a semiconductor substrate 40b' and an insulator layer 41b. The semiconductor substrate 40b' is thinner than the semiconductor substrate 40a in the thickness along the Z direction. The peripheral circuit 7b' is formed in the boundary region of the semiconductor substrate 40b' and the insulator layer 41b. The electrode 52b is provided on the first surface of the insulator layer 41b. As described above, the row decoder module 17 is not provided in the peripheral circuit 7b'. Therefore, the wiring layer of the word line wiring region WLHU of the unit chip 300 is not electrically connected to the peripheral circuit 7b' at times.

[0184] The second surface of the insulator layer 41a and the first surface of the insulator layer 42a are attached to each other in a manner that the corresponding electrodes are in contact with each other. Figure 18 In the example of FIG. 6, the second surface of the insulator layer 41a and the first surface of the insulator layer 42a are attached in a manner that the electrode 51a is in contact with the electrode 55a, the electrode 52a is in contact with the electrode 56a, and the electrode 62a is in contact with the electrode 63a.

[0185] The second surface of the insulator layer 42a and the first surface of the insulator layer 42b are attached to each other in a manner that the corresponding electrodes are in contact with each other. Figure 18 In the example of FIG. 7, the second surface of the insulator layer 42a and the first surface of the insulator layer 42b are attached in a manner that the electrode 57a is in contact with the electrode 57b and the electrode 65a is in contact with the electrode 65b.

[0186] The second surface of the insulator layer 42b and the first surface of the insulator layer 41b are attached to each other in a manner that the corresponding electrodes are in contact with each other. Figure 18 In the example of FIG. 8, the second surface of the insulator layer 42b and the first surface of the insulator layer 41b are attached in a manner that the electrode 56b is in contact with the electrode 52b.

[0187] In either of the unit chips 200 and 300, each of the conductive layers 21 to 23 is electrically connected to the peripheral circuit 7a' via the wiring junction region WJCT after being led out by the contact extending along the Z direction. Figure 18In the present embodiment, as an example, a case is shown in which the conductor layer 21 of the unit chip 200 and the conductor layer 21 of the unit chip 300 are electrically connected to the electrodes 55a and 62a via the contacts 50a and 50b, respectively. Thereby, the peripheral circuit 7a' can apply a desired voltage to the selection gate line SGD, the plurality of word lines WL, and the selection gate line SGS in either of the memory cell arrays 6a and 6b, respectively. The peripheral circuit 7b' does not supply a desired voltage to the selection gate line SGD, the plurality of word lines WL, and the selection gate line SGS, respectively.

[0188] Further, although Figure 18 In the present embodiment, as an example, a case is shown in which the conductor layer 21 of the unit chip 200 and the conductor layer 21 of the unit chip 300 are electrically connected to the electrodes 55a and 62a via the contacts 50a and 50b, respectively. Thereby, the peripheral circuit 7a' can apply a desired voltage to the selection gate line SGD, the plurality of word lines WL, and the selection gate line SGS in either of the memory cell arrays 6a and 6b, respectively. The peripheral circuit 7b' does not supply a desired voltage to the selection gate line SGD, the plurality of word lines WL, and the selection gate line SGS, respectively.

[0189] 2.4 Effects of the Present Embodiment

[0190] According to the second embodiment, the driver module 16 and the row decoder module 17 that supply a voltage to either of the memory cell array 6a in the unit chip 200 and the memory cell array 6b in the unit chip 300 are formed in the peripheral circuit chip 100A. That is, the circuit that applies a high voltage such as the voltage VPGM is concentrated in the peripheral circuit chip 100A. Thereby, it is possible to avoid forming the circuit that applies a high voltage in the peripheral circuit chip 400A. Therefore, it is possible to avoid forming a deep depletion layer in the film thickness direction (Z direction) of the semiconductor substrate 40b. Therefore, it is possible to make the thickness of the semiconductor substrate 40b thinner than the semiconductor substrate 40a. By making the thickness of the semiconductor substrate 40b thinner, it is possible to reduce the load of the step of forming a hole that penetrates the semiconductor substrate 40b when forming the bump group 5 (particularly, the contacts 60).

[0191] 3. Variations and the Like

[0192] Further, the first and second embodiments can be variously changed.

[0193] 3.1 First Variation

[0194] For example, in the first and second embodiments, the case where the configuration obtained by bonding the peripheral circuit chip 100 and the unit chip 200 is further bonded to the configuration obtained by bonding the peripheral circuit chip 400 and the unit chip 300 is described, but the present application is not limited to this. For example, at least one of the configuration including the peripheral circuit 7a and the memory cell array 6a and the configuration including the peripheral circuit 7b and the memory cell array 6b can also be configured by a single chip. In the following description, the configuration different from the first embodiment is mainly described, and the configuration equivalent to the first embodiment is omitted.

[0195] 3.1.1 First Example

[0196] Figure 19 is a view showing an example of a bonding structure of a plurality of chips in the memory device of the first example of the first variation example. Figure 19 Corresponding to the Figure 3 .

[0197] As shown in Figure 19 , the memory device 3B-1 is bonded in a three-chip stacking manner. Specifically, the memory device 3B-1 includes the unit chip 300, the peripheral circuit chip 400, and the chip 500. The chip 500 includes a peripheral circuit layer in which the peripheral circuit 7a is formed, and a unit layer in which the memory cell array 6a' is formed.

[0198] The unit chip 300, the peripheral circuit chip 400, and the chip 500 each have a first surface and a second surface facing each other. The first surface of the chip 500 does not interface with any chip. The second surface of the chip 500 interfaces with the first surface of the unit chip 300 by bonding. The second surface of the unit chip 300 interfaces with the first surface of the peripheral circuit chip 400 by bonding. The second surface of the peripheral circuit chip 400 does not interface with any chip.

[0199] Figure 20 is a cross-sectional view showing an example of a configuration of the memory device of the first example of the first variation example. Figure 20 Corresponding to the Figure 7 .

[0200] As shown in Figure 20 , the chip 500 includes the semiconductor substrate 40a and the insulator layer 41a'. The first surface of the semiconductor substrate 40a corresponds to the first surface of the chip 500. The second surface of the semiconductor substrate 40a interfaces with the first surface of the insulator layer 41a'. The second surface of the insulator layer 41a' corresponds to the second surface of the chip 500. The electrode 57a is provided on the second surface of the insulator layer 41a'.

[0201] Peripheral circuitry 7a is formed at the boundary region between semiconductor substrate 40a and insulating layer 41a'. A memory cell array 6a' is formed within insulating layer 41a'. The memory cell array 6a' is formed by sequentially stacking conductive layers 20, 21, 22, 23, and 24 along the Z-direction. For example, conductive layer 21 of memory cell array 6a' is led out along the Z-direction to a position above the paper plane than conductive layer 24. Thus, conductive layer 21 of memory cell array 6a' is electrically connected via contact 50a to wiring layer 58a', which is located above the paper plane than conductive layer 24.

[0202] The line decoder module 17 within the peripheral circuit 7a is electrically connected to the conductive layer 21 of the memory cell array 6b' via wiring layers 53a and 58a'. Additionally, for example, the input / output circuit 11 or logic control circuit 12 within the peripheral circuit 7a is electrically connected to electrode 57a via wiring layers 54a and 59a.

[0203] As described above, in the first example of the first variation, the peripheral circuit 7a and the memory cell array 6a' are formed in the same chip 500. The peripheral circuit chip 400 forming the peripheral circuit 7b is bonded to the cell chip 300 forming the memory cell array 6b. Furthermore, the chip 500 and the cell chip 300 after being bonded to the peripheral circuit chip 400 are further bonded together. In this case, both the memory cell arrays 6a' and 6b are configured as conductive layers 20 to 24 sequentially stacked along the Z direction. In this configuration, similar to the first embodiment, the peripheral circuit can be divided and formed on two semiconductor substrates 40a and 40b. Therefore, compared to the case where the peripheral circuit is formed on one semiconductor substrate, the area required for the peripheral circuit can be reduced.

[0204] 3.1.2 Case 2

[0205] Figure 21 This is a diagram illustrating an example of the bonding structure of multiple chips in a memory device, which is the second example of the first variation. Figure 21 Corresponding to the first embodiment Figure 3 .

[0206] like Figure 21 As shown, the memory device 3B-2 is formed by bonding three chips together. Specifically, the memory device 3B-2 includes a peripheral circuit chip 100, a cell chip 200, and a chip 600. The chip 600 includes a peripheral circuit layer forming a pad group 5 and peripheral circuit 7b, and a cell layer forming a memory cell array 6b'.

[0207] Peripheral circuit chip 100, unit chip 200, and chip 600 each have a first surface and a second surface facing each other. The first surface of peripheral circuit chip 100 is not connected to any other chip. The second surface of peripheral circuit chip 100 is connected to the first surface of unit chip 200 by bonding. The second surface of unit chip 200 is connected to the first surface of chip 600 by bonding. The second surface of chip 600 is not connected to any other chip.

[0208] Figure 22 This is a cross-sectional view showing an example of the structure of the memory device in the second example of the first variation. Figure 22 Corresponding to the first embodiment Figure 7 .

[0209] like Figure 22 As shown, chip 600 includes a semiconductor substrate 40b and an insulating layer 41b'. The first surface of the insulating layer 41b' corresponds to the first surface of chip 600. The second surface of the insulating layer 41b' is in contact with the first surface of the semiconductor substrate 40a. The second surface of the semiconductor substrate 40b corresponds to the second surface of chip 600. An electrode 57b is disposed on the first surface of the insulating layer 41b'.

[0210] Peripheral circuitry 7b is formed at the boundary region between semiconductor substrate 40b and insulating layer 41b'. A memory cell array 6b' is formed within insulating layer 41b'. The memory cell array 6b' is formed by sequentially stacking conductive layers 24, 23, 22, 21, and 20 along the Z-direction. For example, conductive layer 21 of memory cell array 6b' is led out along the Z-direction to a position below the plane of the paper, more so than conductive layer 24. Thus, conductive layer 21 of memory cell array 6b' is electrically connected via contact 50b to wiring layer 58b', which is located below the plane of the paper, more so than conductive layer 24.

[0211] The line decoder module 17 within the peripheral circuit 7b is electrically connected to the conductive layer 21 of the memory cell array 6b' via wiring layers 53b and 58b'. Additionally, for example, the input / output circuit 11 or logic control circuit 12 within the peripheral circuit 7b is electrically connected to the electrode 57b via wiring layers 54b and 59b.

[0212] As described above, in the second example of the first variation, the peripheral circuit 7b and the memory cell array 6b' are formed in the same chip 600. The peripheral circuit chip 100 forming the peripheral circuit 7a is bonded to the cell chip 200 forming the memory cell array 6a. Furthermore, the chip 600 and the cell chip 200 after being bonded to the peripheral circuit chip 100 are further bonded together. In this case, both the memory cell arrays 6a and 6b' are configured as conductive layers 24 to 20 sequentially stacked along the Z direction. In this configuration, similar to the first embodiment, the peripheral circuit can be divided and formed on two semiconductor substrates 40a and 40b. Therefore, compared to the case where the peripheral circuit is formed on one semiconductor substrate, the area required for the peripheral circuit can be reduced.

[0213] 3.2 Second variation example

[0214] Furthermore, for example, in the first and second embodiments described, the case where unit chips 200 and 300 are provided between peripheral circuit chips 100 and 400 has been explained, but this is not a limitation. For example, more than three unit chips may be provided between peripheral circuit chips 100 and 400. In the following description, the configuration different from that of the first embodiment will be mainly described, and the configuration equivalent to that of the first embodiment will be omitted.

[0215] Figure 23 This is a diagram illustrating an example of the bonding structure of multiple chips in a memory device of the second variation. Figure 23 Corresponding to the first embodiment Figure 3 .

[0216] like Figure 23 As shown, the memory device 3C is formed by stacking two peripheral circuit chips and three unit chips. Specifically, it includes peripheral circuit chips 100 and 400, and unit chips 200, 300, and 700. Memory cell arrays 6a, 6b, and 6c are formed on unit chips 200, 300, and 700, respectively. Peripheral circuits 7a and 7c-1 corresponding to memory cell arrays 6a and 6c are formed on peripheral circuit chip 100. Pad group 5 and peripheral circuits 7b and 7c-2 corresponding to memory cell arrays 6b and 6c are formed on peripheral circuit chip 400.

[0217] The peripheral circuit chips 100 and 400, and the unit chips 200, 300, and 700 each have a first surface and a second surface facing each other. The first surface of the peripheral circuit chip 100 is not connected to any chip. The second surface of the peripheral circuit chip 100 is connected to the first surface of the unit chip 200 by bonding. The second surface of the unit chip 200 is connected to the first surface of the unit chip 700 by bonding. The second surface of the unit chip 700 is connected to the first surface of the unit chip 300 by bonding. The second surface of the unit chip 300 is connected to the first surface of the peripheral circuit chip 400 by bonding. The second surface of the peripheral circuit chip 400 is not connected to any chip.

[0218] As described above, in the second modification, three or more unit chips are provided between the two peripheral circuit chips. In this configuration, as with the first embodiment, the peripheral circuit can be divided and formed in the two semiconductor substrates 40a and 40b. Therefore, compared to the case where the peripheral circuit is formed in one semiconductor substrate, the area required for the peripheral circuit can be reduced. In addition, in the three or more unit chips, the memory cell arrays are formed by different manufacturing steps, respectively. Thus, the size of the memory can be increased without excessively increasing the number of layers of the word lines WL of the memory cell array formed in one unit chip. Therefore, an increase in manufacturing load accompanying an increase in the number of layers can be suppressed.

[0219] 3.3 Others

[0220] In the embodiments, the configuration in which three or more chips are bonded has been described, but is not limited thereto. For example, a chip in which the memory cell array 6a is formed above the semiconductor substrate 40a (for example, the chip 500) can be bonded to a chip in which the memory cell array 6b is formed above the semiconductor substrate 40b (for example, the chip 600).

[0221] The embodiments of the present application have been described, but these embodiments are presented as examples and are not intended to limit the scope of the application. These novel embodiments can be implemented in other various ways, and various omissions, substitutions, and changes can be made without departing from the scope of the application. These embodiments or changes are included in the scope or spirit of the application, and are included in the scope of the application and equivalents thereof recited in the claims.

[0222] [Explanation of Symbols]

[0223] 1 Memory system

[0224] 2 Memory controller

[0225] 3, 3A, 3B-1, 3B-2, 3C Memory device

[0226] 5 pad group

[0227] 6, 6a, 6b, 6a', 6b' memory cell array

[0228] 7, 7a, 7b, 7a', 7b' peripheral circuit

[0229] 11 input / output circuit

[0230] 12 logic control circuit

[0231] 13 instruction register

[0232] 14 address register

[0233] 15 sequencer

[0234] 16 driver module

[0235] 17 row decoder module

[0236] 18 sense amplifier module

[0237] 20-24 conductive body layer

[0238] 30 core film

[0239] 31 semiconductor film

[0240] 32 tunnel insulating film

[0241] 33 charge storage film

[0242] 34 barrier insulating film

[0243] 35 semiconductor portion

[0244] 36, 50a, 50b, 60 contact

[0245] 40a, 40b, 40b' semiconductor substrate

[0246] 41a, 41a', 41b, 41b', 42a, 42b insulator layer

[0247] 51a, 51b, 52a, 52b, 55a, 55b, 56a, 56b, 57a, 57b, 61, 62a, 63a, 65a, 65b electrode

[0248] 53a, 53b, 54a, 54b, 58a, 58a', 58b, 58b', 59a, 59b, 64a, 64b wiring layer

[0249] 100, 100A, 400, 400A peripheral circuit chip

[0250] 200, 300, 700 unit chip

[0251] 500, 600 chip

Claims

1. A memory device, comprising: Possessing: a first chip; and a second chip provided on the first chip and attached to the first chip, the first chip includes: a first semiconductor substrate; a first peripheral circuit provided on the first semiconductor substrate; a first memory cell array provided above the first peripheral circuit; and a first electrode provided above the first memory cell array; the second chip includes: a second electrode connected to the first electrode; a second memory cell array provided above the second electrode; a second peripheral circuit provided above the second memory cell array; a second semiconductor substrate provided above the second peripheral circuit; and a pad provided above the second peripheral circuit and capable of receiving a command and an address from a memory controller; the first peripheral circuit controls either one or both of the first memory cell array or the second memory cell array based on the command and the address input from the pad, and the second peripheral circuit controls the other one or both of the first memory cell array or the second memory cell array based on the command and the address input from the pad.

2. The memory device according to claim 1, wherein: the first memory cell array includes: a plurality of first conductive layers; a first semiconductor film penetrating the plurality of first conductive layers along a first direction; and a first charge storage film provided between the plurality of first conductive layers and the first semiconductor film; the second memory cell array includes: a plurality of second conductive layers; a second semiconductor film penetrating the plurality of second conductive layers along the first direction; and a second charge storage film provided between the plurality of second conductive layers and the second semiconductor film; and the second semiconductor substrate has a first surface and a second surface located on a side opposite to the first semiconductor substrate with respect to the first surface, and the first direction intersects at least one of the first surface and the second surface.

3. The memory device according to claim 2, wherein: the first peripheral circuit includes a first row decoder electrically connected to the plurality of first conductive layers, and the second peripheral circuit includes a second row decoder electrically connected to the plurality of second conductive layers.

4. The memory device according to claim 2, wherein: the first peripheral circuit includes a first row decoder electrically connected to the plurality of first conductive layers and a second row decoder electrically connected to the plurality of second conductive layers.

5. The memory device according to claim 4, wherein: a thickness of the first semiconductor substrate along the first direction is thicker than a thickness of the second semiconductor substrate along the first direction.

6. The memory device according to claim 1, wherein: the second semiconductor substrate has a first surface and a second surface located on a side opposite to the first semiconductor substrate with respect to the first surface, and the pad is provided on the second surface of the second semiconductor substrate.

7. The memory device of claim 1, wherein: the first chip comprises: a first peripheral circuit chip comprising the first substrate; and a first cell chip disposed on the first peripheral circuit chip and comprising the first memory cell array and the first electrode.

8. The memory device of claim 7, wherein: the second chip comprises: a second cell chip disposed on the first cell chip and comprising the second memory cell array and the second electrode; and a second peripheral circuit chip disposed on the second cell chip and comprising the second substrate.

9. The memory device of claim 1, wherein: the first chip comprises: a first peripheral circuit chip comprising the first substrate; a first cell chip disposed on the first peripheral circuit chip and comprising the first memory cell array; and a third cell chip disposed above the first cell chip and comprising a third memory cell array and the first electrode; the second chip comprises: a second cell chip disposed on the third cell chip and comprising the second memory cell array and the second electrode; and a second peripheral circuit chip disposed on the second cell chip and comprising the second substrate.

10. The memory device of claim 1, wherein: the first electrode and the second electrode comprise copper.

11. The memory device of claim 1, wherein: the pad comprises aluminum.

12. A memory device, comprising comprises: a first semiconductor substrate; a first peripheral circuit disposed on the first semiconductor substrate; a first memory cell array disposed above the first peripheral circuit; a first insulator layer covering the first memory cell array; a first electrode disposed on the first insulator layer; a second insulator layer in contact with the first insulator layer; a second electrode disposed on the second insulator layer and in contact with the first electrode; a second memory cell array covered by the second insulator layer and disposed above the second electrode; a second peripheral circuit disposed above the second memory cell array; a second semiconductor substrate disposed above the second peripheral circuit; and a pad disposed above the second peripheral circuit and capable of receiving commands and addresses from a memory controller; the first peripheral circuit controls either or both of the first memory cell array or the second memory cell array based on the commands and addresses input from the pad, and the second peripheral circuit controls the other of the first memory cell array or the second memory cell array based on the commands and addresses input from the pad. ​

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