A high-efficiency vertical cavity surface EML chip with an oxide isolation layer and a preparation method thereof

Abstract

The present invention discloses a high-efficiency vertical cavity surface EML chip with an oxidation isolation layer and a preparation method, wherein the high-efficiency vertical cavity surface EML chip includes a VCSEL unit, an oxidation isolation layer and an EOM unit, and the oxidation isolation layer is arranged between the VCSEL unit and the EOM unit to prevent the potential at the contact point of the two units from affecting the working current in each unit. The present invention has a breakthrough in that an oxidation isolation layer with an electrical insulation effect is arranged between the VCSEL unit and the EOM unit to isolate the high-frequency modulation signal applied to the EOM unit, so that the VCSEL unit and the EOM unit are relatively independent, preventing the high-frequency modulation signal from affecting the current in the VCSEL unit, thereby ensuring the stable output of the VCSEL unit. At the same time, the present invention innovatively creates a differential oxidation method. By precisely designing the aluminum content deviation of the oxidation isolation prefabricated layer and the oxidation restriction prefabricated layer, the oxidation isolation layer and the oxidation restriction layer can be formed in the same oxidation process, which greatly simplifies the chip process and reduces production costs.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor optoelectronic technology, and in particular to a high-efficiency vertical cavity surface (EML) chip with an oxidation isolation layer and a preparation method thereof. Background Art

[0002] With the rapid development of data communications, Vertical Cavity Surface Emitting Laser (VCSEL) chips are widely used in optical communications due to their excellent characteristics, such as small chip size, circular output spot, low operating threshold, high coupling efficiency, and easy integration. These include optical interconnect, optical sensing, and optical storage. Applications include short-distance communication in data centers, 5G base stations, and HDMI ultra-high-definition video transmission. VCSEL chips offer excellent economical, practical, and reliable performance, greatly facilitating information exchange across various industries.

[0003] The ever-increasing volume of data is driving higher demands on data transmission speed and quality. Currently, most VCSEL chips utilize direct modulation for signal transmission, employing high-speed RF signals for direct modulation. As the modulation rate increases, direct modulation VCSEL chips are prone to generating chirping during operation, which limits the laser chip's transmission rate. As the transmission distance increases, this can also lead to crosstalk and optical power attenuation, reducing signal transmission quality. Achieving higher modulation rates without changing the modulation method requires exponentially increasing the current density, which in turn increases chip power consumption and shortens the chip's lifespan.

[0004] Similar to edge-emitting laser chips, which monolithically integrate a light-emitting unit (DFB) and a modulation unit, existing vertical-cavity surface-mount laser (VCSEL) chips monolithically integrate a light-emitting unit (VCSEL) and a modulation unit (EOM). These chips typically employ a "NDBR-active region-oxide confinement layer-PDBR-absorption region-NDBR" structure. The VCSEL and EOM share a common PDBR to achieve optical resonance and enhance light absorption in the VCSEL and EOM, respectively. However, due to the lack of electrical isolation between the VCSEL and EOM, applying a high-frequency modulation signal to the EOM affects the current in the VCSEL, thereby affecting the VCSEL's stable output.

[0005] Based on this, we provide a high-efficiency vertical cavity surface EML chip with an oxide isolation layer and a preparation method thereof. Summary of the Invention

[0006] The present invention provides a high-efficiency vertical cavity surface EML chip with an oxidation isolation layer and a preparation method thereof, the main purpose of which is to solve the problems existing in the prior art.

[0007] The present invention adopts the following technical solutions:

[0008] A high-efficiency vertical cavity surface EML chip with an oxide isolation layer includes a VCSEL unit, an oxide isolation layer and an EOM unit, wherein:

[0009] The VCSEL unit includes, from bottom to top, a substrate, a buffer layer, a first DBR, a resonant cavity, and a second DBR, and the resonant cavity includes, from bottom to top, a first confinement layer, a first waveguide layer, a quantum well layer, a second waveguide layer, a second confinement layer, and an oxidized confinement layer;

[0010] The EOM unit includes a third DBR, an absorption region and a fourth DBR from bottom to top;

[0011] The oxidation isolation layer is arranged between the VCSEL unit and the EOM unit, and is used to prevent the potential at the contact point between the two units from affecting the operating current in each unit.

[0012] This invention innovatively places an electrically insulating oxide isolation layer between the VCSEL unit and the EOM unit to isolate the high-frequency modulation signal applied to the EOM unit. This makes the VCSEL unit and the EOM unit relatively independent, preventing the high-frequency modulation signal from affecting the current in the VCSEL unit, thereby ensuring stable output from the VCSEL unit. Compared to the prior art method of direct contact between the VCSEL unit and the EOM unit, electrical isolation reduces RC delay during high-frequency signal transmission, helping to improve transmission performance and achieve better modulation effects.

[0013] The high-efficiency vertical cavity surface EML chip further includes a first electrode, a second annular electrode, a third annular electrode and a fourth annular electrode, wherein:

[0014] The first electrode may be a first planar electrode disposed on the lower surface of the substrate or a first annular electrode disposed on the upper surface of the first DBR;

[0015] The second annular electrode is arranged on the upper surface of the second DBR;

[0016] The third annular electrode is arranged on the upper surface of the third DBR;

[0017] The fourth annular electrode is disposed on the upper surface of the fourth DBR.

[0018] Because an oxide isolation layer with electrical isolation is placed between the VCSEL unit and the EOM unit, they cannot share electrodes, requiring a four-electrode structure. In practical applications, the first electrode can be configured as a first planar electrode or a first annular electrode as needed to meet different application scenarios, such as top-top contact type and top-bottom contact type applications.

[0019] The substrate is made of GaAs, and the thickness of the oxide isolation layer and the oxide restriction layer is 5-5000nm. The GaAs material system has higher reliability. When the resonant cavity of the VCSEL unit and the absorption region of the EOM unit are both made of the GaAs material system, the material properties of the two units are similar, which can greatly improve the stability of chip epitaxial deposition and reduce the difficulty of mass production.

[0020] Based on the GaAs material system, the material of the oxidation isolation layer is Al2O3, which has good electrical insulation effect and is an ideal material for the oxidation isolation layer. The oxidation isolation layer is formed by oxidizing the oxidation isolation prefabricated layer through a wet oxidation process, and the material of the oxidation isolation prefabricated layer is doped or undoped Al x Ga 1-x The oxidation restriction layer is formed by wet oxidation of the oxidation restriction prefabricated layer. The oxidation region forms Al2O3 with optical and electrical restriction functions. The pore size of the unoxidized region is in the range of 2-100 μm. The oxidation restriction prefabricated layer is doped or undoped Al y Ga 1-y As can be seen, the prefabricated layer materials of the oxidation restriction layer and the oxidation isolation layer are both AlGaAs materials, which match the lattice of the GaAs substrate system, can achieve one-time epitaxial growth, reduce the difficulty of epitaxial production, facilitate mass production, and also ensure the epitaxial crystal quality of the VCSEL unit and EOM unit, improving the reliability of the device.

[0021] In the preparation process, since the oxidation restriction prefabricated layer needs to be partially oxidized to form the photoelectrically restricted aperture, and the oxidation isolation prefabricated layer needs to be fully oxidized to form the oxidation isolation layer, if the oxidation restriction layer and the oxidation isolation layer are to be prepared simultaneously in the same oxidation process, it is necessary to control the Al content of the oxidation restriction prefabricated layer. y Ga 1-y The aluminum content y of As is less than that of the oxide isolation prefabricated layer Al x Ga 1-x The aluminum content of As is x. The present invention innovatively creates a differential oxidation method. By precisely designing the aluminum content deviation of the oxidation isolation pre-layer and the oxidation restriction pre-layer, the oxidation isolation layer and the oxidation restriction layer can be formed in the same oxidation process, greatly simplifying the chip manufacturing process and reducing production costs.

[0022] The first DBR, the second DBR, the third DBR and the fourth DBR are made of Al i Ga 1-i As / Al j Ga 1-j As material composed of periodic structure. As the oxidation isolation prefabricated layer uses Al with high aluminum content x Ga 1-x As material, on the one hand, in order to prevent the first to fourth DBRs from being over-oxidized, on the other hand, the higher the aluminum content, the greater the device resistance. Therefore, it is necessary to ensure that the material Al2O3 of the first to fourth DBRs is i Ga 1-i As / Al j Ga 1-j The aluminum content i and j of As is less than that of the oxide isolation prefabricated layer Al x Ga 1-x The aluminum content of As is x. In addition, care should be taken to avoid using aluminum arsenide materials in applications.

[0023] As one embodiment, the Al x Ga 1-x The Al content of As is in the range of x≥0.97; i Ga 1-i As / Al j Ga 1-j The range of the aluminum content i and j of As is i≤0.92, j≤0.92; y Ga 1-y The Al content of As ranges from 0.92<y<0.97.

[0024] In one embodiment, the first DBR is a first N-type doped DBR; the second DBR is a first P-type doped DBR; the third DBR is a second N-type doped DBR; and the fourth DBR is a second P-type doped DBR. Thus, the epitaxial structure provided by the present invention is an NP-O-NP structure. However, in practical applications, the epitaxial structure can be adjusted to an NP-O-PN, PN-O-NP, or PN-O-PN structure as needed, where N refers to the N-type doped DBR, P refers to the P-type doped DBR, and O refers to the oxide isolation layer.

[0025] The resonant cavity comprises a sandwich structure consisting of a lower waveguide, an active region, and an upper waveguide, and employs an oxidized confinement layer for optical and electrical confinement. The cavity length is an integer multiple of half the lasing wavelength. The quantum well gain structure of the resonant cavity can be a single quantum well, multiple quantum wells, a tunnel junction cascade quantum well, or a quantum dot. Specifically, one of InGaAs / GaAs, InGaAs / AlGaAs, InGaAs / GaAsP, GaAs / AlGaAs, AlInGaAs / AlGaAs, InGaAsP / AlGaAs, and AlGaInP / GaAs can be selected.

[0026] For the quantum well of the same resonant cavity, the quantum well material of the absorption region can also be selected from InGaAs / GaAs, InGaAs / AlGaAs, InGaAs / GaAsP, GaAs / AlGaAs, AlInGaAs / AlGaAs, InGaAsP / AlGaAs and AlGaInP / GaAs, but in order to achieve modulation, the quantum well wavelength of the absorption region should be controlled to be 5-99nm shorter than the quantum well wavelength of the resonant cavity.

[0027] The absorption region is a single quantum well or multi-quantum well structure. When the absorption region is a single quantum well structure, a third waveguide layer is provided between the absorption region and the second N-type doped DBR, and a fourth waveguide layer is provided between the absorption region and the second P-type doped DBR. This is because the single quantum well structure requires the formation of an FP resonant cavity similar to a VCSEL unit, but the FP resonant cavity in the absorption region is a passive FP to enhance absorption, rather than an active FP as in a VCSEL unit.

[0028] When the absorption region utilizes a pair of quantum well structures, the EOM unit modulates the light intensity of the VCSEL unit based on the quantum confined Stark effect (QCSE). By modulating the bias voltage of the EOM unit, the absorption sideband of the absorption region is directly shifted, indirectly achieving high-speed modulation of the VCSEL output light intensity. Compared to traditional direct modulation methods, the efficient modulation of the EOM modulation unit can reduce the design constraints of the VCSEL unit, thereby improving the photoelectric conversion efficiency and optimizing the structural design of the VCSEL unit.

[0029] When the absorption region uses a multi-pair quantum well structure, the EOM unit modulates the light intensity of the VCSEL unit based on the reflectivity deviation between the top and bottom reflectors. By modulating the bias voltage of the EOM unit, the absorption state of the absorption region is directly affected, thereby controlling the overall reflectivity of the top reflector, thereby indirectly achieving high-speed modulation of the VCSEL output light intensity.

[0030] A method for preparing a high-efficiency vertical cavity surface EML chip with an oxide isolation layer, characterized by:

[0031] (1) growing a buffer layer, a first DBR, a resonant cavity, a second DBR, an oxidized isolation prefabricated layer, a third DBR, an absorption region, and a fourth DBR on a substrate in sequence; the resonant cavity includes a first confinement layer, a first waveguide layer, a quantum well layer, a second waveguide layer, a second confinement layer, and an oxidized confinement prefabricated layer;

[0032] (2) preparing a first planar electrode on the lower surface of the buffer layer or preparing a first annular electrode on the upper surface of the first DBR;

[0033] (3) fabricating a second annular electrode on the upper surface of the second DBR;

[0034] (4) The oxidation isolation prefabricated layer and the oxidation restriction prefabricated layer are oxidized by a wet oxidation process to form an oxidation isolation layer and an oxidation restriction layer.

[0035] (5) A third annular electrode is fabricated on the upper surface of the third DBR, and a fourth annular electrode is fabricated on the upper surface of the fourth DBR.

[0036] Furthermore, in step (1), the growth process of the epitaxial wafer adopts a metal organic vapor phase deposition method.

[0037] Furthermore, in step (1), when the quantum well of the absorption region is a single quantum well structure, it should be noted that a third waveguide layer must be deposited between the absorption region and the third DBR, and a fourth waveguide layer must be deposited between the absorption region and the fourth DBR.

[0038] Furthermore, in step (2), the first electrode in the present invention is preferably a first planar electrode, which is manufactured by etching the substrate with ICP to expose the buffer layer, and preparing the first planar electrode on the buffer layer away from the first DBR surface.

[0039] Furthermore, in step (3), a contact layer selection mask SiNx is first formed on the upper surface of the second DBR by using a plasma enhanced chemical vapor deposition method (PECVD), photolithography and reactive ion etching (RIE) process, and then selective edge etching is performed by ICP etching to etch the epitaxial structure above the top of the second DBR to the upper surface of the second DBR, and then the contact layer selection mask SiNx is removed by BOE; finally, a second annular electrode is formed on the upper surface of the second DBR by using a photolithography process, an electron beam evaporation metal layer process and a lift-off process.

[0040] Furthermore, in step (4), the reason for selecting the oxidation process of the oxidation isolation prefabricated layer and the oxidation restriction prefabricated layer to be performed after the first electrode and the second annular electrode are as follows: first, the oxidation process can fully utilize the advantage of more accurate alignment of the metal layer (the first electrode and the second annular electrode) to ensure that the oxidation process is precise and controllable; second, the etching process of the electrode will reduce the oxidation area of ​​the oxidation process, which can greatly save the oxidation time and also help to improve the uniformity of the oxidation; third, the oxidation isolation prefabricated layer and the oxidation restriction prefabricated layer will generate stress after oxidation, which will have a certain impact on the etching step of the metal electrode part, so the metal electrode part needs to be manufactured first.

[0041] Furthermore, in step (5), the preparation method of the third annular electrode is the same as that of the second annular electrode, and will not be described in detail here. However, it should be noted that when performing ICP etching, selective edge etching must be performed on the epitaxial structure more than 200nm away from the bottom of the third DBR to prevent the etching depth from exceeding the oxide isolation layer, resulting in failure of the oxide isolation layer. The preparation of the fourth annular electrode adopts conventional processes and will not be described in detail here. The reason for choosing to prepare the third and fourth annular electrodes after the oxidation process is that during the oxidation process, it is necessary to observe under an infrared microscope whether the oxide isolation prefabricated layer is fully oxidized to form an oxide isolation layer. If oxidation is performed after the metal layer above is made, it is not conducive to observing the morphology of the oxide isolation layer.

[0042] Compared with the prior art, the present invention has the following beneficial effects:

[0043] 1. This invention innovatively incorporates an electrically insulating oxide isolation layer between the VCSEL unit and the EOM unit to isolate the high-frequency modulation signal applied to the EOM unit. This makes the VCSEL unit and the EOM unit relatively independent, preventing the high-frequency modulation signal from affecting the current in the VCSEL unit, thereby ensuring stable output from the VCSEL unit. Compared to the prior art method of direct contact between the VCSEL unit and the EOM unit, electrical isolation reduces RC delay during high-frequency signal transmission, helping to improve transmission performance and achieve better modulation effects.

[0044] The present invention innovatively creates a differential oxidation method. By precisely designing the aluminum content deviation of the oxidation isolation prelayer and the oxidation restriction prelayer, the oxidation isolation layer and the oxidation restriction layer can be formed in the same oxidation process, which greatly simplifies the chip process and reduces production costs.

[0045] The prefabricated materials for both the oxide confinement layer and the oxide isolation layer are AlGaAs, which matches the lattice of the GaAs substrate system. This allows for one-step epitaxial growth, reduces the difficulty of epitaxial production, and facilitates mass production. This also ensures the quality of the epitaxial crystals for the VCSEL and EOM units, improving device reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 This is a schematic diagram of the cross-sectional structure of the chip provided in Example 1 of the present invention.

[0047] Figure 2 This is a schematic diagram of the resonant cavity structure of the VCSEL unit provided in Example 1 of the present invention.

[0048] Figure 3 This is a schematic diagram of the modulation principle provided in Example 1 of the present invention.

[0049] Figure 4 This is a schematic diagram of the modulation principle provided in the second embodiment of the present invention.

[0050] In the picture:

[0051] 10. Substrate 11. Buffer layer

[0052] 12. First N-type doped DBR 13. Resonant cavity

[0053] 14. First P-type doped DBR 15. Oxide isolation layer

[0054] 16. Second N-type doped DBR 17. Third waveguide layer

[0055] 18. Absorption region 19. Fourth waveguide layer

[0056] 110. Second P-type doped DBR 111. First planar electrode

[0057] 111 ', first annular electrode 112, second annular electrode

[0058] 113. Third annular electrode 114. Fourth annular electrode

[0059] 21. First confinement layer 22. First waveguide layer

[0060] 23. Quantum well layer 24. Second waveguide layer

[0061] 25. Second restriction layer 26. Oxidation restriction layer

[0062] 20. Top reflector 30. Bottom reflector. DETAILED DESCRIPTION

[0063] The specific embodiments of the present invention are described below with reference to the accompanying drawings. In order to fully understand the present invention, many details are described below, but for those skilled in the art, the present invention can be implemented without these details.

[0064] Example 1:

[0065] like Figure 1 As shown, this embodiment provides a high-efficiency vertical cavity surface EML chip with an oxide isolation layer, including a VCSEL unit, an oxide isolation layer 15 and an EOM unit. The oxide isolation layer 15 is arranged between the VCSEL unit and the EOM unit to prevent the potential at the contact point between the two units from affecting the operating current in each unit.

[0066] like Figure 1 As shown, the VCSEL unit includes, from bottom to top, a substrate 10, a buffer layer 11, a first N-type doped DBR 12, a resonant cavity 13, and a first P-type doped DBR 14. The EOM unit includes, from bottom to top, a second N-type doped DBR 16, a third waveguide layer 17, an absorption region 18, a fourth waveguide layer 19, and a second P-type doped DBR 110.

[0067] like Figure 1 As shown, the chip further includes a first electrode, a second annular electrode 112, a third annular electrode 113, and a fourth annular electrode 114. Specifically, in this embodiment, the first electrode is a first planar electrode 111 disposed on the lower surface of the substrate 10. In other embodiments, the first electrode may also be a first annular electrode 111' disposed on the upper surface of the first N-type doped DBR 12; the second annular electrode 112 is disposed on the upper surface of the first P-type doped DBR 14; the third annular electrode 113 is disposed on the upper surface of the second N-type doped DBR 16; and the fourth annular electrode 114 is disposed on the upper surface of the second P-type doped DBR 110.

[0068] Preferably, the substrate 10 is a Si-doped GaAs substrate with a doping concentration of 1.5e 18 cm -3 .

[0069] Preferably, the buffer layer 11 is a Si-doped GaAs layer with a doping concentration of 2e 18 cm -3 , with a thickness of 200nm.

[0070] Preferably, the first N-type doped DBR 12 and the second N-type doped DBR 16 are of high refractive index / low refractive index / high refractive index / low refractive index ... / high refractive index structure, and the high refractive index material is Si-doped Al 0.12 Ga 0.88 As layer, the low refractive index material is Si-doped Al 0.9 Ga 0.1As layer. Si-doped Al 0.12 Ga 0.88 The thickness of the As layer is 60 nm and the doping concentration is 2e 18 cm -3 , Si-doped Al 0.9 Ga 0.1 The thickness of the As layer is 69.4 nm and the doping concentration is 2e 18 cm -3 .

[0071] like Figure 2 As shown, the optical thickness of the resonant cavity 13 is one wavelength, and the resonant cavity 13 includes, from bottom to top, a first confinement layer 21 , a first waveguide layer 22 , a quantum well layer 23 , a second waveguide layer 24 , a second confinement layer 25 , and an oxidized confinement layer 26 .

[0072] Preferably, the first confinement layer 21 is Si-doped Al 0.6 Ga 0.4 As, thickness is 22nm, and doping concentration is 2e 17 cm -3 .

[0073] Preferably, the first waveguide layer 22 is Al 0.45 Ga 0.55 As, thickness 18 nm;

[0074] Preferably, the quantum well layer 23 is made of a barrier layer Al with a thickness of 10 nm. 0.35 Ga 0.65 As and a well layer GaAs with a thickness of 8nm, which consists of a well / barrier / well / barrier / well structure, and the lasing wavelength is 850nm.

[0075] Preferably, the second waveguide layer 24 is Al 0.45 Ga 0.55 As, thickness is 30nm.

[0076] Preferably, the second confinement layer 25 is Si-doped Al 0.6 Ga 0.4 As, thickness is 62.5nm, and doping concentration is 2e 18 cm -3 .

[0077] Preferably, the oxidation restriction layer 26 is made of undoped Al with a thickness of 30 nm. 0.93 Ga 0.07 The As oxidation restriction pre-layer is formed by a wet oxidation process. The pore size of the unoxidized area is retained at 8 μm, and the oxidized area forms Al2O3 with optical and electrical restriction functions.

[0078] Preferably, the oxide isolation layer 15 is made of undoped Al with a thickness of 30 nm.0.98 Ga 0.02 The As oxide isolation prefabricated layer is subjected to a wet oxidation process to form an Al2O3 isolation layer with an electrical insulation effect, thereby effectively preventing the potential at the contact point between the VCSEL unit and the EOM unit from affecting the current in the VCSEL unit, further improving the performance of the VCSEL.

[0079] Preferably, the third waveguide layer 17 is Si-doped Al 0.45 Ga 0.55 As, thickness 77nm, doping concentration 2e 17 cm -3 .

[0080] Preferably, the absorption region 18 is a pair of Al 0.35 Ga 0.65 As is the barrier and GaAs is the well quantum well, Al 0.35 Ga 0.65 The thickness of the As barrier layer is 5 nm, the thickness of the GaAs well layer is 6 nm, the thickness of the absorption region 18 is 450 nm, and the quantum well wavelength of the absorption region 18 is 830 nm.

[0081] Preferably, the fourth waveguide layer 19 is C-doped Al 0.45 Ga 0.55 As, thickness 77nm, doping concentration 2e 17 cm -3 The third waveguide layer 17 and the fourth waveguide layer 19 are doped with N-type and P-type respectively to form a PN junction, and the absorption region 18 is formed between the PN junctions.

[0082] Preferably, the first P-type doped DBR 14 and the second P-type doped DBR 110 are periodically superimposed high refractive index / low refractive index / high refractive index / low refractive index ... / high refractive index structures, and the high refractive index material is C-doped Al 0.12 Ga 0.88 As layer, the low refractive index material is C-doped Al 0.9 Ga 0.1 As layer. C-doped Al 0.12 Ga 0.88 The thickness of the As layer is 60 nm and the doping concentration is 2e 18 cm -3 ; C-doped Al 0.9 Ga 0.1 The thickness of the As layer is 69.4 nm and the doping concentration is 2e 18 cm -3 .

[0083] like Figure 3As shown, the modulation principle of this embodiment is: when no bias is applied or a low bias is applied between the third annular electrode 113 and the fourth annular electrode 114, the absorption curve of the EOM unit is in the blue-shift direction compared to the emission wavelength of the VCSEL unit. At this time, the light beam emitted by the VCSEL unit will not suffer absorption loss after passing through the EOM unit. When a higher bias is applied to the EOM unit, due to the quantum confined Stark effect (QCSE), its absorption spectrum sideband will quickly drift to a long wavelength, covering the emission wavelength of the VCSEL unit. Therefore, the high-speed electrical modulation signal applied to the EOM unit directly affects the movement of its absorption sideband, thereby realizing high-speed modulation of the light intensity of the VCSEL. In this embodiment, the EOM unit and the VCSEL unit are isolated by the oxide isolation layer 15, and the two are relatively independent, which helps to achieve a better modulation effect.

[0084] The preparation method of this embodiment comprises the following steps:

[0085] 1. A buffer layer 11, a first N-type doped DBR 12, a resonant cavity 13, a first P-type doped DBR 14, an oxidized isolation prefabricated layer, a second N-type doped DBR 16, a third waveguide layer 17, an absorption region 18, a fourth waveguide layer 19, and a second P-doped DBR 110 are sequentially grown on a substrate 10 using an MOCVD method. The resonant cavity 13 includes a first confinement layer 21, a first waveguide layer 22, a quantum well layer 23, a second waveguide layer 24, a second confinement layer 25, and an oxidized confinement prefabricated layer.

[0086] , using ICP to etch the substrate 10 to expose the buffer layer 11 , and preparing a first planar electrode on the buffer layer 11 away from the first N-type doped DBR surface 12 .

[0087] First, a contact layer selection mask SiNx is formed on the upper surface of the first P-type doped DBR14 through enhanced plasma chemical vapor deposition (PECVD), photolithography and reactive ion etching (RIE) processes, and then selective edge etching is performed through ICP etching to etch the epitaxial structure above the top of the first P-type doped DBR14 to the upper surface of the first P-type doped DBR14. Then, the contact layer selection mask SiNx is removed through BOE; finally, a second annular electrode 112 is formed on the upper surface of the first P-type doped DBR14 through photolithography, electron beam evaporation of metal layer process and stripping process.

[0088] , using wet oxidation process to 0.98 Ga 0.02 As oxide isolation prefabricated layer and Al 0.93 Ga 0.07 The As oxidation limiting pre-layer is oxidized to form an Al2O3 oxidation isolation layer 15 and an oxidation limiting layer 26;

[0089] 5. Fabricate the third annular electrode 113 on the upper surface of the second N-type doped DBR 16 using the same method as in step 4. However, note that during ICP etching, selective edge etching must be performed on the epitaxial structure at least 200 nm from the bottom of the second N-type doped DBR 16 to prevent penetration of the oxide isolation layer 15, which could cause failure of the oxide isolation layer 15. Then, fabricate the fourth annular electrode 114 on the upper surface of the second P-type doped DBR 110 using conventional techniques.

[0090] Example 2:

[0091] like Figure 1 and 2 As shown, the structural design of this embodiment is basically the same as that of the first embodiment, except that the third waveguide layer 17 and the fourth waveguide layer 19 are not provided in this embodiment, and the absorption region 18 is composed of multiple pairs of Al 0.35 Ga 0.65 As is the barrier and GaAs is the well quantum well, Al 0.35 Ga 0.65 The thickness of the As barrier layer is 5 nm, the thickness of the GaAs well layer is 6 nm, and the thickness of the absorption region is 450 nm. Increasing the period number of the quantum well of the absorption region 18 can reduce the period number of the second P-type doped DBR 110 on the top.

[0092] like Figure 1 As shown, the bottom reflector 30 covers the entire portion below the resonant cavity 13, while the top reflector 20 covers the entire portion above the resonant cavity 13. For the lasing wavelength of 850 nm for the resonant cavity 13, the overall reflectivity of the bottom reflector 30 can be designed to be 99.995%, while the overall reflectivity of the top reflector 20 can be designed to be 99.89%. The absorption region 18 of the EOM unit is placed at the point of maximum light intensity on the top reflector 20.

[0093] like Figure 4As described above, the modulation principle of this embodiment is as follows: when no bias or a low bias is applied between the third annular electrode 113 and the fourth annular electrode 114, the absorption region 18 in the EOM unit is in a non-absorbing state. At this time, the reflectivity of the bottom reflector 30 is 99.995%, and the reflectivity of the top reflector 20 is 99.89%. The photons emitted by the quantum well 23 can form a continuous and stable back-and-forth oscillation in the resonant cavity 13. After the gain reaches a certain value, they can pass through the top reflector 20 to form light output; when a higher bias is applied between the third annular electrode 113 and the fourth annular electrode 114, the absorption effect of the absorption region 18 in the EOM unit is enhanced, and the reflectivity of the top reflector 20 drops to 99.68%. At this time, the photons emitted by the quantum well 23 cannot form a continuous and stable oscillation in the resonant cavity 13, or the gain is insufficient, the light intensity cannot penetrate the top reflector 20 to stabilize the light output, or the output laser power is reduced. Therefore, by modulating the bias level of the EOM unit and changing the working state of the absorption region 18, the reflectivity of the top DBR can be affected, thereby achieving high-speed modulation of the light intensity of the VCSEL unit.

[0094] The above is only a specific implementation of the present invention, but the design concept of the present invention is not limited to this. Any non-substantial changes to the present invention using this concept shall be deemed as an infringement of the protection scope of the present invention.

Claims

1. A high-efficiency vertical cavity surface EML chip with an oxide isolation layer, characterized by: It includes a VCSEL unit, an oxide isolation layer and an EOM unit, wherein: The VCSEL unit includes, from bottom to top, a substrate, a buffer layer, a first DBR, a resonant cavity, and a second DBR, and the resonant cavity includes, from bottom to top, a first confinement layer, a first waveguide layer, a quantum well layer, a second waveguide layer, a second confinement layer, and an oxidized confinement layer; The EOM unit includes a third DBR, an absorption region and a fourth DBR from bottom to top; The oxide isolation layer is provided between the VCSEL unit and the EOM unit to prevent the potential at the contact point between the two units from affecting the operating current in each unit; The method for preparing the high-efficiency vertical cavity surface EML chip comprises the following steps: (1) growing a buffer layer, a first DBR, a resonant cavity, a second DBR, an oxidized isolation prefabricated layer, a third DBR, an absorption region, and a fourth DBR on a substrate in sequence; the resonant cavity includes a first confinement layer, a first waveguide layer, a quantum well layer, a second waveguide layer, a second confinement layer, and an oxidized confinement prefabricated layer; (2) preparing a first planar electrode on the lower surface of the buffer layer or preparing a first annular electrode on the upper surface of the first DBR; (3) fabricating a second annular electrode on the upper surface of the second DBR; (4) The oxidation isolation prefabricated layer and the oxidation restriction prefabricated layer are oxidized by a wet oxidation process to form an oxidation isolation layer and an oxidation restriction layer; the materials of the oxidation isolation layer and the oxidation restriction layer are both Al2O3, wherein the oxidation isolation layer is made of Al x Ga 1-x The As oxide isolation prefabricated layer is formed by wet oxidation process, and the oxide restriction layer is made of Al y Ga 1-y The As oxidation restriction prefabricated layer is formed by a wet oxidation process. Since the oxidation restriction prefabricated layer needs to be partially oxidized to form a photoelectrically restricted aperture, and the oxidation isolation prefabricated layer needs to be fully oxidized to form an oxidation isolation layer, if the oxidation restriction layer and the oxidation isolation layer are to be prepared simultaneously in the same oxidation process, it is necessary to control the oxidation restriction prefabricated layer Al y Ga 1-y The aluminum content y of As is less than that of the oxide isolation prefabricated layer Al x Ga 1-x Aluminum content of As x; (5) A third annular electrode is fabricated on the upper surface of the third DBR, and a fourth annular electrode is fabricated on the upper surface of the fourth DBR.

2. The high-efficiency vertical cavity surface EML chip with an oxide isolation layer according to claim 1, characterized in that: The first DBR, the second DBR, the third DBR and the fourth DBR are made of Al i Ga 1-i As / Al j Ga 1-j As material constitutes a periodic structure, and Al i Ga 1-i As / Al j Ga 1-j The aluminum content i and j of As are both less than Al x Ga 1-x The aluminum content of As is x.

3. The high-efficiency vertical cavity surface EML chip with an oxide isolation layer according to claim 2, characterized in that: The Al x Ga 1-x The Al content of As is in the range of x≥0.97; i Ga 1-i As / Al j Ga 1-j The range of the aluminum content i and j of As is i≤0.92, j≤0.92; y Ga 1-y The Al content of As ranges from 0.92<y<0.

97.

4. The high-efficiency vertical cavity surface EML chip with an oxide isolation layer according to claim 1, characterized in that: Also included are a first electrode, a second annular electrode, a third annular electrode, and a fourth annular electrode, wherein: The first electrode is a first planar electrode provided on the lower surface of the substrate or a first annular electrode provided on the upper surface of the first DBR; The second annular electrode is arranged on the upper surface of the second DBR; The third annular electrode is arranged on the upper surface of the third DBR; The fourth annular electrode is disposed on the upper surface of the fourth DBR.

5. The high-efficiency vertical cavity surface EML chip with an oxide isolation layer according to claim 1, characterized in that: The first DBR is a first N-type doped DBR; the second DBR is a first P-type doped DBR; the third DBR is a second N-type doped DBR; and the fourth DBR is a second P-type doped DBR.

6. The high-efficiency vertical cavity surface EML chip with an oxide isolation layer according to claim 1, characterized in that: The pore size of the unoxidized region of the oxidation restriction layer ranges from 2 to 100 μm.

7. The high-efficiency vertical cavity surface EML chip with an oxide isolation layer according to claim 1, characterized in that: The quantum well wavelength of the absorption region is 5-99 nm shorter than the quantum well wavelength of the resonant cavity.

8. The high-efficiency vertical cavity surface EML chip with an oxide isolation layer according to claim 1, characterized in that: The absorption region is a single quantum well or multi-quantum well structure; when the absorption region is a single quantum well structure, a third waveguide layer is provided between the absorption region and the third DBR, and a fourth waveguide layer is provided between the absorption region and the fourth DBR.

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