Variable capacitance circuit, circuit device, and oscillator

Abstract

Provided are a variable capacitance circuit, a circuit device, and an oscillator that can improve the linearity of a capacitance value change. The variable capacitance circuit includes a capacitor array having a first capacitor in which a plurality of MIM capacitors are connected in parallel and a second capacitor in which a plurality of MIM capacitors are connected in series, and a switch array having a first switch and a second switch. At least one of a shape pattern of a first electrode of the first capacitor, a first ground shield, a second electrode of the second capacitor, and a second ground shield is set in a manner such that a first capacitance difference in each 1 LSB of a first capacitance value with respect to the first capacitor when the first switch is on and off is close to a second capacitance difference in each 1 LSB of a second capacitance value with respect to the second capacitor when the second switch is on and off.

Description

TECHNICAL FIELD

[0001] The present application relates to a variable capacitance circuit, a circuit device, and an oscillator, etc. BACKGROUND

[0002] Conventionally, a variable capacitance circuit using a MIM (Metal-Insulator-Metal) capacitor is known. For example, a capacitor array using a MIM capacitor is disclosed in Patent Document 1.

[0003] Patent Document 1: Japanese Patent Application Publication No. 2006-032374

[0004] In the case where a variable capacitance circuit is realized by a capacitor array using a MIM capacitor like that of Patent Document 1, it is ascertained that there is a problem that linearity of a change in a capacitance value in the variable capacitance circuit deteriorates due to a parasitic capacitance between a capacitor, an electrode, and a ground. SUMMARY

[0005] One embodiment of the present application relates to a variable capacitance circuit whose capacitance value is variably controlled in accordance with control data, including: a capacitor array including a plurality of capacitors; and a switch array having a plurality of switches turned on or off in accordance with the control data, the switch array being provided in series with the capacitor array between a first node and a ground node, the capacitor array including: a first capacitor connected in parallel by a plurality of MIM (Metal-Insulator-Metal) capacitors; and a second capacitor connected in series by a plurality of MIM capacitors, the switch array including: a first switch connected in series with the first capacitor between the first node and the ground node; and a second switch connected in series with the second capacitor between the first node and the ground node, when a capacitance value between the first node and the ground node formed by the first capacitor and a parasitic capacitance of the first capacitor is a first capacitance value, and a capacitance value between the first node and the ground node formed by the second capacitor and a parasitic capacitance of the second capacitor is a second capacitance value, a shape pattern of at least one of a first electrode which is an electrode of the first capacitor, a first ground shield member surrounding the first capacitor, a second electrode which is an electrode of the second capacitor, and a second ground shield member surrounding the second capacitor is set so that a first capacitance difference in each 1 LSB of the control data between the first capacitance value when the first switch is turned on and the first capacitance value when the first switch is turned off and a second capacitance difference in each 1 LSB of the control data between the second capacitance value when the second switch is turned on and the second capacitance value when the second switch is turned off are close.

[0006] Further, one embodiment of the present application relates to a variable capacitance circuit which variably controls a capacitance value in accordance with control data, wherein the variable capacitance circuit includes: a capacitor array including a plurality of capacitors; and a switch array having a plurality of switches which are turned on or off in accordance with the control data, the switch array being provided in series with the capacitor array between a first node and a ground node, the capacitor array including: a first capacitor connected in parallel by a plurality of MIM capacitors; and a second capacitor connected in series by a plurality of MIM capacitors, the switch array including: a first switch connected in series with the first capacitor between the first node and the ground node; and a second switch connected in series with the second capacitor between the first node and the ground node, when a distance in a first direction between a first electrode of the first capacitor and a first ground shield surrounding the first capacitor is LA1 and a distance in the first direction between a second electrode of the second capacitor and a second ground shield surrounding the second capacitor is LA2 in a plan view, LA2 > LA1.

[0007] Further, one embodiment of the present application relates to a circuit device including: the above-described variable capacitance circuit; and an oscillation circuit whose oscillation frequency is controlled by the capacitance value of the variable capacitance circuit, the first node being an oscillation node of the oscillation circuit.

[0008] Further, one embodiment of the present application relates to an oscillator including: the above-described circuit device; and a vibrator which oscillates by being driven by the oscillation circuit. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 is a structural example of the variable capacitance circuit of this embodiment.

[0010] Figure 2 is an example of MIM capacitors connected in parallel.

[0011] Figure 3 is an example of MIM capacitors connected in series.

[0012] Figure 4 is an explanatory view of a ground shield.

[0013] Figure 5 is another example of MIM capacitors connected in series.

[0014] Figure 6 is an explanatory view of a method of increasing stray capacitance of MIM capacitors connected in parallel.

[0015] Figure 7is a diagram illustrating a method of reducing parasitic capacitance of series-connected MIM capacitors.

[0016] Figure 8 is a detailed configuration example of the variable capacitance circuit of the present embodiment.

[0017] Figure 9 is a specific configuration example of the capacitor and switch.

[0018] Figure 10 is a layout configuration example of the capacitor and switch.

[0019] Figure 11 is a diagram illustrating deterioration of linearity with respect to a change in capacitance value.

[0020] Figure 12 is an equivalent circuit diagram at the time of switch-on and at the time of switch-off of a switch of parallel-connected MIM capacitors.

[0021] Figure 13 is an equivalent circuit diagram at the time of switch-on and at the time of switch-off of a switch of series-connected MIM capacitors.

[0022] Figure 14 is an equivalent circuit diagram at the time of switch-on and at the time of switch-off of a switch of series-connected MIM capacitors.

[0023] Figure 15 is an example of capacitance value, capacitance difference of parallel-connected MIM capacitors and series-connected MIM capacitors.

[0024] Figure 16 is a diagram illustrating a method of increasing parasitic capacitance of parallel-connected MIM capacitors.

[0025] Figure 17 is a diagram illustrating a method of increasing parasitic capacitance of parallel-connected MIM capacitors.

[0026] Figure 18 is a diagram illustrating a method of increasing parasitic capacitance of parallel-connected MIM capacitors.

[0027] Figure 19 is a diagram illustrating a method of increasing parasitic capacitance of series-connected MIM capacitors.

[0028] Figure 20 is a diagram illustrating a method of increasing parasitic capacitance of series-connected MIM capacitors.

[0029] Figure 21 is a diagram illustrating a method of increasing parasitic capacitance of series-connected MIM capacitors.

[0030] Figure 22 is a whole layout configuration example of the variable capacitance circuit.

[0031] Figure 23 is a structural example of the circuit device of the present embodiment.

[0032] Figure 24 is a structural example of the oscillator.

[0033] Explanation of Reference Numerals

[0034] 4: Oscillator; 10: Vibrator; 15: Package; 16: Base; 17: Cover; 18, 19: External terminal; 20: Circuit device; 30: Variable capacitance circuit; 32: Capacitor array; 34: Switch array; 40: Oscillation circuit; 50: Output buffer circuit; 60: Power supply circuit; ALB, ALC, ALD: Metal layer; BMP: Bump; Cj: 1st capacitor; Ci: 2nd capacitor; C1-C18, C5A, C5B, Cn: Capacitor; CKQ: Clock signal; CM1-CM4: MIM capacitor; CP1-CP4, CPG1-CPG4, CPj, CPi: Parasitic capacitance; DCN: Control data; DR1: 1st direction; DR2: 2nd direction; EBj, ECj, EDj: 1st electrode; EBi, ECi, EDi, EBXi, EBYi, EDXi, EDYi: 2nd electrode; GS: Ground shield; GSj: 1st ground shield; GSi: 2nd ground shield; LA1, LA2, LB1, LB2: Distance; N1: 1st node; NG: Ground node; Ni, Nj: Node; OSC: Oscillation signal; P1: 1st part; P2: 2nd part; P3: 3rd part; P4: 4th part; PCK: Clock land; PGND: Ground land; PVDD: Power supply land; PX1, PX2: Land; SW1-SW16, SWn: Switch; SWj: 1st switch; SWi: 2nd switch; TCK: External terminal; TGND: External terminal; TP1, TP2, TP3, TP4: Electrode; TR: Transistor; TVDD: External terminal; VBC: Via contact; VCD: Via contact. DETAILED DESCRIPTION

[0035] Hereinafter, the present embodiment will be described. Note that the present embodiment described hereinafter does not unduly limit the recited content of the claims. Also, the structures described in the present embodiment are not necessarily all essential structural elements.

[0036] 1. Variable capacitance circuit

[0037] Figure 1An example of the structure of the variable capacitor circuit 30 of this embodiment is shown. The variable capacitor circuit 30, which variably controls the capacitance value according to control data DCN, includes a capacitor array 32 and a switch array 34. Specifically, the variable capacitor circuit 30 has: a capacitor array 32 comprising a plurality of capacitors Cn to C1; and a switch array 34 having a plurality of switches SWn to SW1 that are turned on or off according to control data DCN. The switch array 34 is connected in series with the capacitor array 32 between the first node N1 and the ground node NG. For example, capacitor Cn and switch SWn, first capacitor Cj and first switch SWj, second capacitor Ci and second switch SW1, and capacitor C1 and switch SW1 are connected in series between the first node N1 and the ground node NG. Here, i and j are different integers greater than or equal to 1 and less than or equal to n.

[0038] Furthermore, the capacitor array 32 includes a first capacitor Cj consisting of multiple MIM capacitors connected in parallel and a second capacitor Ci consisting of multiple MIM capacitors connected in series. MIM capacitors are Metal-Insulator-Metal (MIM) capacitors. For example, in the first capacitor Cj, MIM capacitors CM1 and CM2 are connected in parallel as multiple MIM capacitors. In the second capacitor Ci, MIM capacitors CM3 and CM4 are connected in series as multiple MIM capacitors. Additionally, in... Figure 1 In this configuration, the first capacitor Cj is formed by connecting two MIM capacitors CM1 and CM2 in parallel, but the number of MIM capacitors connected in parallel can also be three or more. Similarly, the second capacitor Ci is formed by connecting two MIM capacitors CM3 and CM4 in series, but the number of MIM capacitors connected in series can also be three or more.

[0039] Furthermore, the switch array 34 includes: a first switch SWj, which is connected in series with a first capacitor Cj between the first node N1 and the ground node NG; and a second switch SWi, which is connected in series with a second capacitor Ci between the first node N1 and the ground node NG. Additionally, in Figure 1 In this configuration, switches SWn to SW1 are provided on the grounding node NG side, and capacitors Cn to C1 are provided on the first node N1 side. However, it can also be configured such that capacitors Cn to C1 are provided on the grounding node NG side, and switches SWn to SW1 are provided on the first node N1 side.

[0040] exist Figure 2 The diagram illustrates a structural example of the first capacitor Cj. The first capacitor Cj comprises MIM capacitors CM1 and CM2, stacked and connected in parallel in the top view direction. MIM capacitor CM1 is the first MIM capacitor, and MIM capacitor CM2 is the second MIM capacitor. The top view direction is the same as described later. Figure 23The direction perpendicular to the substrate of the semiconductor chip in the circuit device 20. For example... Figure 2 As shown, the first capacitor Cj is configured as MIM capacitors CM1 and CM2 connected in parallel and stacked longitudinally in the top view direction. The first capacitor Cj has first electrodes EDj, ECj, and EBj. The first electrodes EDj, ECj, and EBj are formed by metal layers ALD, ALC, and ALB, respectively. ALD is the upper metal layer, ALB is the lower metal layer, and ALC is the metal layer between ALD and ALB. The metal layers ALD, ALC, and ALB are, for example, metal layers of aluminum or aluminum alloy. Furthermore, in Figure 2 The following is omitted. Figure 6 The diagram shows electrodes TP1 and TP2. Furthermore, the first electrode ECj of the first capacitor Cj is connected to the first node N1, and the first electrodes EDj and EBj are connected to the other end of the first switch SWj, one end of which is connected to the ground node NG. That is, the first electrodes EDj and EBj are connected to node Nj, which is the other end of the first switch SWj.

[0041] A first grounding shield GSj, set to ground voltage, is disposed around the first capacitor Cj. Specifically, as follows: Figure 4 As shown, the first grounding shield GSj is arranged to surround the first capacitor Cj. The first grounding shield GSj is formed by metal layers ALD, ALC, ALB, a path contact VCD connecting metal layers ALC and ALD, and a path contact VBC connecting metal layers ALB and ALC. Furthermore, in Figure 4 In this embodiment, the first grounding shield GSj surrounds the entire circumference of the first capacitor Cj, but this embodiment is not limited to this, and there may also be a region in the entire circumference where the first grounding shield GSj does not exist.

[0042] Furthermore, in Figure 2 In this design, the distance between the first grounding shield GSj on the first direction DR1 and the first electrodes EDj, ECj, and EBj, which serve as electrodes of the first capacitor Cj, is defined as LA1. Furthermore, the distance between the first grounding shield GSj on the second direction DR2, which is perpendicular to the first direction DR1, and the first electrodes EDj, ECj, and EBj is defined as LB1. For example, the first direction is the X direction, and the second direction is the Y direction. In this case, the direction viewed from above is the Z direction. Additionally, the number of MIM capacitors connected in parallel in the first capacitor Cj is not limited to two; it can be three or more.

[0043] exist Figure 3The diagram shows a structural example of the second capacitor Ci. The second capacitor Ci comprises MIM capacitors CM3 and CM4 stacked and connected in series in a top-view orientation. MIM capacitor CM3 is the third MIM capacitor, and MIM capacitor CM4 is the fourth MIM capacitor. Figure 3 As shown, the second capacitor Ci is configured as a series-connected MIM capacitor CM3 and CM4 stacked longitudinally in a top view. The second capacitor Ci has second electrodes EDi, ECi, and EBi. The second electrodes EDi, ECi, and EBi are formed from metal layers ALD, ALC, and ALB, respectively. Furthermore, in Figure 3 The following is omitted. Figure 7 The diagram shows electrodes TP3 and TP4. Furthermore, the second electrode EDi of the second capacitor Ci is connected to the first node N1, and the second electrode EBi is connected to the other end of the second switch SWi, which is connected at one end to the ground node NG. That is, the second electrode EBi is connected to node Ni, which is the other end of the second switch SWi.

[0044] A second grounding shield GSi, set to ground voltage, is disposed around the second capacitor Ci. Specifically, as follows: Figure 4 As shown, the second grounding shield GSi is arranged to surround the second capacitor Ci. The second grounding shield GSi is formed by metal layers ALD, ALC, ALB, a path contact VCD connecting metal layers ALC and ALD, and a path contact VBC connecting metal layers ALB and ALC. Furthermore, in Figure 4 In this embodiment, the second grounding shield GSi surrounds the entire circumference of the second capacitor Ci, but this embodiment is not limited to this, and there may be a region in the entire circumference where the second grounding shield GSi is not present.

[0045] Moreover, in Figure 3 In this design, the distance between the second grounding shield GSi on the first direction DR1 and the second electrodes EDi, ECi, and EBi, which serve as electrodes of the second capacitor Ci, is defined as LA2. Furthermore, the distance between the second grounding shield GSi on the second direction DR2, which is perpendicular to the first direction DR1, and the second electrodes EDi, ECi, and EBi is defined as LB2.

[0046] Furthermore, the number of MIM capacitors connected in series in the second capacitor Ci is not limited to two; it can also be three or more. For example, in Figure 5 The diagram shows the structure of a second capacitor Ci connected in series with four MIM capacitors CM3, CM4, CM5, and CM6. Figure 5In the present embodiment, the second electrode EDXi of the second capacitor Ci is formed of the metal layer ALD, and is connected to the first node Nl. The second electrode EBXi of the second capacitor Ci is formed of the metal layer ALB, and is connected to the second electrode EDYi formed of the metal layer ALD. The second electrode EBYi of the second capacitor Ci is formed of the metal layer ALB, and is connected to the node Ni of the other end of the second switch SWi.

[0047] In addition, as shown in FIG. 1, in the first capacitor Cj and the second capacitor Ci, parasitic capacitances CPj, CPi are generated between the first node Nl and the ground node NG. As explained in detail in Figure 1 Figures 12-14 the first capacitor Cj and the parasitic capacitance CPj of the first capacitor Cj, and the second capacitor value corresponds to a value obtained by adding the capacitance value of the second capacitor Ci to the capacitance value of the parasitic capacitance CPI thereof.

[0048] In addition, let the capacitance difference in each 1 LSB of the control data DCN between the first capacitor value when the first switch SWj is on and the first capacitor value when the first switch SWj is off be a first capacitor difference. That is, let the capacitance difference of the amount of 1 LSB between when the first switch SWj is on and when the first switch SWj is off with respect to the first capacitor value between the first node Nl and the ground node NG formed of the first capacitor Cj and the parasitic capacitance CPj be the first capacitor difference. Furthermore, let the capacitance difference in each 1 LSB of the control data DCN between the second capacitor value when the second switch SWi is on and the second capacitor value when the second switch SWi is off be a second capacitor difference. That is, let the capacitance difference of the amount of 1 LSB between when the second switch SWi is on and when the second switch SWi is off with respect to the second capacitor value between the first node Nl and the ground node NG formed of the second capacitor Ci and the parasitic capacitance CPI be the second capacitor difference. Details of these first capacitor difference and second capacitor difference are explained specifically in Figure 15

[0049] At this time, in the present embodiment, the first electrode EDj, ECj, EBj of the first capacitor Cj, the first ground shield GSj, the second ground shield GS2, and the third ground shield GS3 of the first capacitor Cj, and the first electrode EDXi, ECXi, EBYi of the second capacitor Ci, the first ground shield GSXi, the second ground shield GS2i, and the third ground shield GS3i of the second capacitor Ci are arranged in the manner that the first capacitor difference and the second capacitor difference are close to each other as described above, and in plan view, the first electrode EDj, ECj, EBj of the first capacitor Cj, the first ground shield GSj, the second ground shield GS2, and the third ground shield GS3 of the first capacitor Cj, and the first electrode EDXi, ECXi, EBYi of the second capacitor Ci, the first ground shield GSXi, the second ground shield GS2i, and the third ground shield GS3i of the second capacitor Ci are arranged in the manner shown in FIG. 2. Figure 2 Figure 3 ​​​The shape pattern of at least one of the second electrodes EDi, ECi, EBi of the second capacitor Ci shown, and the second grounding shield GSi surrounding the second electrodes EDi, ECi, EBi. That is, the shape pattern of at least one of the first electrodes EDj, ECj, EBj, the first grounding shield GSj, the second electrodes EDi, ECi, EBi, and the second grounding shield GSi is set in a manner that approximates the first capacitance difference and the second capacitance difference. For example, the shape pattern is set in a manner that approximates the first capacitance difference and the second capacitance difference. Figure 2 The first configuration relationship between the first electrodes EDj, ECj, EBj and the first grounding shield GSj is shown. Figure 3 The second configuration relationship is at least one of the following: the second electrode EDi, ECi, EBi and the second grounding shield GSi. The first configuration relationship includes the distance relationship between the first electrode EDj, ECj, EBj and the first grounding shield GSj, and the relationship between the opposing areas of the sides of the first electrode EDj, ECj, EBj and the opposing side of the first grounding shield GSj. The second configuration relationship includes the distance relationship between the second electrode EDi, ECi, EBi and the second grounding shield GSi, and the relationship between the opposing areas of the sides of the second electrode EDi, ECi, EBi and the opposing side of the second grounding shield GSi.

[0050] Specifically, regarding the first capacitor Cj connected in parallel to the MIM, the shape pattern of at least one of the first electrodes EDj, ECj, EBj and the first ground shield GSj is set such that its parasitic capacitance CPj increases, or a first configuration relationship is set between the first electrodes EDj, ECj, EBj and the first ground shield GSj. On the other hand, regarding the second capacitor Ci connected in series to the MIM, the shape pattern of at least one of the second electrodes EDi, ECi, EBi and the second ground shield GSi is set such that its parasitic capacitance CPi decreases, or a second configuration relationship is set between the second electrodes EDi, ECi, EBi and the second ground shield GSi. In addition, in this embodiment, a capacitor formed by connecting multiple MIM capacitors in parallel is appropriately described as a capacitor connected in parallel to the MIM, and a capacitor formed by connecting multiple MIM capacitors in series is appropriately described as a capacitor connected in series to the MIM.

[0051] For example, such as Figure 2 As shown, let LA1 be the distance along the first direction DR1 between the first electrodes EDj, ECj, EBj and the first grounding shield GSj. Additionally, as... Figure 3 As shown, let LA2 be the distance along the first direction DR1 between the second electrodes EDi, ECi, EBi and the second grounding shield GSi. At this time, as... Figure 6 , Figure 7As shown in the cross-sectional views of the first capacitor Cj and the second capacitor Ci, the relationship LA2 > LA1 holds true.

[0052] That is, such as Figure 6 As shown, regarding the first capacitor Cj connected in parallel to the MIM, the parasitic capacitance CPj increases by reducing the distance LA1 in the first direction DR1 between the first electrodes EDj, ECj, EBj and the first grounding shield GSj. On the other hand, as... Figure 7 As shown, regarding the second capacitor Ci connected in series with the MIM, the parasitic capacitance CPi is reduced by increasing the distance LA2 in the first direction DR1 between the second electrodes EDi, ECi, EBi and the second ground shield GSi. Thus, by setting LA2 > LA1, the parasitic capacitance CPj of the first capacitor Cj connected in parallel with the MIM increases, while the parasitic capacitance CPi of the second capacitor Ci connected in series with the MIM decreases. In this way, the first capacitance difference per 1 LSB for the first capacitor Cj connected in parallel with the MIM, when the first switch SWj is on and off, is close to the second capacitance difference per 1 LSB for the second capacitor Ci connected in series with the MIM, when the second switch SWi is on and off. Therefore, the capacitance value of the variable capacitor circuit 30 can change linearly with respect to the change in control data DCN.

[0053] In addition, such as Figure 2 As shown, let LB1 be the distance along the second direction DR2 between the first electrodes EDj, ECj, EBj and the first grounding shield GSj. Additionally, as... Figure 3 As shown, let LB2 be the distance along the second direction DR2 between the second electrodes EDi, ECi, EBi and the second grounding shield GSi. In this case, the relationship LB2 > LB1 holds.

[0054] That is, such as Figure 6 As shown, regarding the first capacitor Cj connected in parallel to the MIM, the parasitic capacitance CPj increases by reducing the distance LB1 in the second direction DR2 between the first electrodes EDj, ECj, EBj and the first grounding shield GSj. On the other hand, as... Figure 7 As shown, regarding the second capacitor Ci connected in series with the MIM, the parasitic capacitance CPi is reduced by increasing the distance LB2 in the second direction DR2 between the second electrodes EDi, ECi, EBi and the second ground shield GSi. Thus, the first capacitance difference per 1 LSB for the first capacitor Cj connected in parallel with the MIM when the first switch SWj is on and off is close to the second capacitance difference per 1 LSB for the second capacitor Ci connected in series with the MIM when the second switch SWi is on and off. Therefore, the capacitance value of the variable capacitor circuit 30 can change linearly with respect to changes in the control data DCN.

[0055] 2. Detailed structural example

[0056] Figure 8 A detailed structural example of the variable capacitor circuit 30 of this embodiment is shown. For example... Figure 8 As shown, the variable capacitor circuit 30, which variably controls the capacitance value according to control data DCN, includes a capacitor array 32 and a switch array 34. The capacitor array 32 includes multiple capacitors C18 to C1. The switch array 34 has multiple switches SW18 to SW1 that are turned on or off according to the control data DCN, and this switch array 34 is connected in series with the capacitor array 32 between the first node N1 and the ground node NG.

[0057] Furthermore, the capacitors C18 to C8 on the high-order bit side have the same capacitance value, and the switching on and off of these switches SW18 to SW8 is controlled by the control data DCN of the calorimeter-type code. On the other hand, the capacitance values ​​of the capacitors C7 to C1 on the low-order bit side are binary-weighted, and the switching on and off of their switches SW7 to SW1 is controlled by the control data DCN of the binary code.

[0058] Capacitors C18 to C4 are parallel-connected MIM capacitors, forming a parallel connection of multiple MIM capacitors. Figure 1 , Figure 2 The first capacitor Cj corresponds to this. With the capacitance value of capacitor C4 set to 1C, the capacitance values ​​of capacitors C7, C6, and C5 are 8C, 4C, and 2C, respectively, weighted in binary. Specifically, capacitor C7 corresponds to a capacitor formed by connecting eight capacitors C4 in parallel, capacitor C6 corresponds to a capacitor formed by connecting four capacitors C4 in parallel, and capacitor C5 corresponds to a capacitor formed by connecting two capacitors C4 in parallel. Furthermore, capacitors C18 to C8 each correspond to a capacitor formed by connecting sixteen capacitors C4 in parallel. Additionally, the switch SW4 for capacitor C4 is constructed by connecting eight transistors in parallel. The switches SW18 to SW5 for capacitors C18 to C5 are similarly configured.

[0059] On the other hand, capacitors C3, C2, and C1 are series-connected MIM capacitors formed by connecting multiple MIM capacitors in series. Figure 1 , Figure 3 The second capacitor Ci corresponds to this. With the capacitance of capacitor C4 set to 1C, the capacitances of capacitors C3, C2, and C1 are (1 / 2)×C, (1 / 4)×C, and (1 / 8)×C, respectively, and are weighted in binary. Specifically, capacitor C3 is constructed by connecting two MIM capacitors connected in series in parallel. For example... Figure 3As shown, capacitor C2 is constructed by connecting two MIM capacitors in series. Figure 5 As shown, capacitor C1 is constructed by connecting four MIM capacitors in series. Additionally, switches SW3 and SW2 are constructed by connecting four and two transistors in parallel, respectively, while switch SW1 is constructed by connecting one transistor.

[0060] For example, in Figure 9 The diagram shows a specific structural example of capacitor C5 and switch SW5. For example... Figure 9 As shown, capacitor C5 is constructed by connecting two capacitors C5A and C5B in parallel. Capacitors C5A and C5B are each constructed by connecting two MIM capacitors in parallel. Furthermore, switch SW5 consists of eight transistors TR connected in parallel between capacitor C5A and ground node NG, and eight transistors TR connected in parallel between capacitor C5B and ground node NG. Transistors TR correspond to unit switches.

[0061] For example Figure 8 The capacitance values ​​of capacitors C7 to C1 are weighted using binary weighting. Therefore, for example, the number of transistors constituting each switch is set to correspond to the capacitance value of the respective capacitor, such that switch SW1 for capacitor C1 consists of one transistor, switch SW2 for capacitor C2 consists of two transistors, and switch SW2 for capacitor C3 consists of four transistors. This prevents the linearity of the capacitance change in the variable capacitor circuit 30 from deteriorating due to parasitic capacitances such as transistor drain capacitance.

[0062] Figure 10 Show Figure 9 Example of the layout configuration of capacitors C5 and SW5. In Figure 10 In the diagram, capacitor C5A, connected in parallel to the MIM, is arranged on the left side, and capacitor C5B, also connected in parallel to the MIM, is arranged on the right side. Furthermore, eight transistors TR connected to capacitor C5A are arranged above and below capacitor C5A. Similarly, eight transistors TR connected to capacitor C5B are arranged above and below capacitor C5B. A grounding shield GS is provided to surround capacitors C5A and C5B and the multiple transistors TR constituting switch SW5.

[0063] In this embodiment, such as Figure 1 , Figure 8As shown, the capacitor array 32 is configured by combining the capacitor connected in parallel with the MIM and the capacitor connected in series with the MIM. These capacitors are capacitors in which a plurality of MIM capacitors are stacked, for example, in the longitudinal direction. By connecting a plurality of MIM capacitors in series, a capacitor with a smaller capacitance value can be realized. Therefore, for example, by using a capacitor connected in series with the MIM, which can further reduce the capacitance value, as a capacitor on the low bit side, the resolution of the capacitance value of the variable capacitance circuit 30 can be improved.

[0064] However, as explained later in Figures 12-14 , the capacitor connected in series with the MIM has a larger parasitic capacitance with respect to the ground than the capacitor connected in parallel with the MIM. Therefore, a problem arises in which the linearity of the change in the capacitance value of the variable capacitance circuit 30 with respect to the control data value as the value of the control data DCN deteriorates. For example, as shown in A1 of Figure 11 , in the variable capacitance circuit 30, the capacitance value is configured to change linearly with respect to the control data value. However, as shown in A3 of the partial enlargement of A2 shown in Figure 11 , for example, in the ranges shown in A4 and A5, the linearity of the capacitance value with respect to the control data value is destroyed. For example, Figure 11 , the range of A4 is a range from a state in which the capacitor C4 is not selected and the capacitors C3, C2, and Cl are selected to a state in which the capacitor C4 is selected and the capacitors C3, C2, and Cl are not selected. That is, the low 4 bits of the control data DCN are a range from 0111 to 1000. Figure 11 , the range of A5 is a range from a state in which the capacitor C5 is not selected and the capacitors C4, C3, C2, and Cl are selected to a state in which the capacitor C5 is selected and the capacitors C4, C3, C2, and Cl are not selected. That is, the low 5 bits of the control data DCN are a range from 01111 to 10000. When the linearity of the change in the capacitance value deteriorates like this, for example, in the case in which the variable capacitance circuit 30 is used in the circuit device 20 of the oscillator 4 as shown in Figure 23 , a problem arises in which the precision of the oscillation frequency deteriorates or the like.

[0065] Furthermore, it was ascertained that the reason for the deterioration in the linearity of the change in the capacitance value lies in the fact that the parasitic capacitance with respect to the ground or the like changes at the time of the switch-on and the switch-off. For example, Figure 12 shows that Figure 8Fig. 2 shows an equivalent circuit diagram of the parallelly connected MIM capacitor C18-C4 including a parasitic capacitance CP1 at the time of switch-on and an equivalent circuit diagram including parasitic capacitances CP1, CPG1, CSW at the time of switch-off. CP1 is a parasitic capacitance generated between 2 electrodes of the capacitor, CPG1 is a parasitic capacitance generated between an electrode of the capacitor and the ground, and CSW is a parasitic capacitance generated at the drain of the switch or the like. Further, Figure 13 Fig. 3 shows an equivalent circuit diagram of the parallelly connected MIM capacitor C3, C2 including a parasitic capacitance CP1, CP2, CPG2 at the time of switch-on and an equivalent circuit diagram including parasitic capacitances CP1, CP2, CPG1, CPG2, CSW at the time of switch-off. CP1, CP2 are parasitic capacitances generated between 2 electrodes of the capacitor, and CPG1, CPG2 are parasitic capacitances generated between an electrode of the capacitor and the ground. Further, C indicates one MIM capacitor. Figure 8 Fig. 4 shows an equivalent circuit diagram of the parallelly connected MIM capacitor C1 including parasitic capacitances CP1- CP4, CPG2- CPG4 at the time of switch-on and an equivalent circuit diagram including parasitic capacitances CP1- CP4, CPG1- CPG4, CSW at the time of switch-off. CP1- CP4 are parasitic capacitances generated between 2 electrodes of the capacitor, and CPG1- CPG4 are parasitic capacitances generated between an electrode of the capacitor and the ground. In this way, the positions and the additional modes of the parasitic capacitances at the time of switch-on and at the time of switch-off are different between the parallelly connected MIM capacitor and the seriesly connected MIM capacitor. Figure 14 Figure 8 Here, let the capacitance value between the first node N1 and the ground node NG with respect to the parallelly connected MIM capacitor as the first capacitor Cj be a first capacitance value. As shown in Fig. 2, the first capacitance value between the first node N1 and the ground node NG with respect to the parallelly connected MIM capacitor C18-C4 at the time of switch-on is a capacitance value formed by the capacitor C18-C4 which is connected in parallel by 2 MIM capacitors (C) and the parasitic capacitance CP1 of the capacitor C18-C4. Further, the first capacitance value of the parallelly connected MIM capacitor C18-C4 at the time of switch-off is a capacitance value formed by the capacitor C18-C4 and the parasitic capacitances CP1, CPG1, CSW of the capacitor C18-C4.

[0066] Here, let the capacitance value between the first node N1 and the ground node NG with respect to the parallelly connected MIM capacitor as the first capacitor Cj be a first capacitance value. As shown in Fig. 2, the first capacitance value between the first node N1 and the ground node NG with respect to the parallelly connected MIM capacitor C18-C4 at the time of switch-on is a capacitance value formed by the capacitor C18-C4 which is connected in parallel by 2 MIM capacitors (C) and the parasitic capacitance CP1 of the capacitor C18-C4. Further, the first capacitance value of the parallelly connected MIM capacitor C18-C4 at the time of switch-off is a capacitance value formed by the capacitor C18-C4 and the parasitic capacitances CP1, CPG1, CSW of the capacitor C18-C4. Figure 12 Further, let the capacitance value between the first node N1 and the ground node NG with respect to the seriesly connected MIM capacitor as the second capacitor Ci be a second capacitance value. As shown in Fig. 4, the second capacitance value between the first node N1 and the ground node NG with respect to the seriesly connected MIM capacitor C1 at the time of switch-on is a capacitance value formed by the capacitor C1 which is connected in series by 2 MIM capacitors (C) and the parasitic capacitances CP1- CP4 of the capacitor C1. Further, the second capacitance value of the seriesly connected MIM capacitor C1 at the time of switch-off is a capacitance value formed by the capacitor C1 and the parasitic capacitances CP1- CP4, CPG1- CPG4, CSW of the capacitor C1.

[0067] Figure 13 ​​As shown, the second capacitance value between the first node N1 of the series-connected MIM capacitor C3, C2 and the ground node NG at the time of switch-on is a capacitance value formed by the series connection of the capacitor C3, C2 and the parasitic capacitances CP1, CP2, CPG2 of the capacitor C3, C2. Further, the second capacitance value of the series-connected MIM capacitor C3, C2 at the time of switch-off is a capacitance value formed by the capacitor C3, C2 and the parasitic capacitances CP1, CP2, CPG1, CPG2, CSW of the capacitor C3, C2. Further, as shown, the first capacitance value between the first node N1 of the series-connected MIM capacitor C1 and the ground node NG at the time of switch-on is a capacitance value formed by the series connection of the capacitor C1 and the parasitic capacitances CP1 to CP4, CPG2 to CPG4 of the capacitor C1. Further, the second capacitance value of the series-connected MIM capacitor C1 at the time of switch-off is a capacitance value formed by the capacitor C1 and the parasitic capacitances CP1 to CP4, CPG1 to CPG4, CSW of the capacitor C1. Figure 14 As shown, the second capacitance value between the first node N1 of the series-connected MIM capacitor C3, C2 and the ground node NG at the time of switch-on is a capacitance value formed by the series connection of the capacitor C3, C2 and the parasitic capacitances CP1, CP2, CPG2 of the capacitor C3, C2. Further, the second capacitance value of the series-connected MIM capacitor C3, C2 at the time of switch-off is a capacitance value formed by the capacitor C3, C2 and the parasitic capacitances CP1, CP2, CPG1, CPG2, CSW of the capacitor C3, C2. Further, as shown, the first capacitance value between the first node N1 of the series-connected MIM capacitor C1 and the ground node NG at the time of switch-on is a capacitance value formed by the series connection of the capacitor C1 and the parasitic capacitances CP1 to CP4, CPG2 to CPG4 of the capacitor C1. Further, the second capacitance value of the series-connected MIM capacitor C1 at the time of switch-off is a capacitance value formed by the capacitor C1 and the parasitic capacitances CP1 to CP4, CPG1 to CPG4, CSW of the capacitor C1.

[0068] Figure 15 is an example of the capacitance value of the parallel-connected MIM capacitor C18 to C4 as the first capacitor Cj and the series-connected MIM capacitor C3 to C1 as the second capacitor Ci. In Figure 15 the first row, the first capacitance value between the first node N1 of the parallel-connected MIM capacitor C18 to C4 and the ground node NG at the time of switch-on and the second capacitance value between the first node N1 of the series-connected MIM capacitor C3 to C1 and the ground node NG at the time of switch-on are shown. Here, the switch-on and switch-off of the parallel-connected MIM capacitor C18 to C4 means the switch-on and switch-off of the switches SW18 to SW4 as the first switches SWj. Further, the switch-on and switch-off of the series-connected MIM capacitor C3 to C1 means the switch-on and switch-off of the switches SW3 to SW1 as the second switches SWi.

[0069] Further, in Figure 15 the second row, the first capacitance value between the first node N1 of the parallel-connected MIM capacitor C18 to C4 and the ground node NG at the time of switch-off and the second capacitance value between the first node N1 of the series-connected MIM capacitor C3 to C1 and the ground node NG at the time of switch-off are shown.

[0070] Further, in Figure 15 the third row, the first capacitance difference in each 1 LSB of the control data DCN between the first capacitance value at the time of switch-on and the first capacitance value at the time of switch-off of the parallel-connected MIM capacitor C18 to C4 is shown.

[0071] Taking capacitor C4 as an example, its first capacitance value is 117.62 fF when switch SW4 is on, and 16.08 fF when the switch is off. Furthermore, the capacitance C of capacitor C4 is 8 times the capacitance value (1 / 8) × C of capacitor C1 corresponding to the LSB. Therefore, the difference in the first capacitance value of capacitor C4 between the on and off states in each LSB is (117.62 - 16.08) / 8 = 12.69 fF. Similarly, taking capacitor C5 as an example, its first capacitance value is 234.42 fF when switch SW5 is on, and 30.58 fF when the switch is off. Furthermore, the capacitance value of capacitor C5 is 2 C, which is 16 times the capacitance value (1 / 8) × C of capacitor C1 corresponding to the LSB. Therefore, the difference in the first capacitance value of capacitor C5 when the switch is on and when the switch is off, per 1 LSB, is (234.42 - 30.58) / 16 = 12.74 fF. The difference in the first capacitance value per 1 LSB for capacitors C6, C7, and C18 to C8 is similarly calculated as 12.77 fF, 12.76 fF, and 12.76 fF, respectively.

[0072] In addition, Figure 15 In line 3, the difference in second capacitance value per LSB of control data DCN is shown for capacitors C3 to C1 connected in series with the MIM, when the switch is on and when the switch is off. Taking capacitor C3 as an example, the second capacitance value when switch SW3 is on is 52.50 fF, and the second capacitance value when the switch is off is 16.93 fF. Furthermore, the capacitance value of capacitor C3 is (1 / 2) × C, which is 4 times the capacitance value of capacitor C1. Therefore, the difference in second capacitance value per LSB for capacitor C3 when the switch is on and when the switch is off is (52.50 - 16.93) / 4 = 8.89 fF. Furthermore, taking capacitor C2 as an example, the second capacitance value when switch SW2 is on is 26.28 fF, and the second capacitance value when the switch is off is 9.33 fF. Furthermore, the capacitance of capacitor C2 is (1 / 4) × C, which is twice the capacitance of capacitor C1. Therefore, the difference in the second capacitance value of capacitor C2 per LSB between the second capacitance value when the switch is on and the second capacitance value when the switch is off is (26.28 - 9.33) / 2 = 8.48 fF. Additionally, the difference in the second capacitance value of capacitor C1 per LSB between the second capacitance value when the switch is on and the second capacitance value when the switch is off is 16.02 - 11.40 = 4.62 fF.

[0073] Thus, the first capacitance difference between the parallel-connected capacitors C18-C4 when the switch is on and off is significantly different from the second capacitance difference between the series-connected capacitors C3-C1 when the switch is on and off. Therefore, as... Figure 11 As shown in A4 and A5, the linearity of capacitance change deteriorates. For example, when changing from a state where switch SW4 of capacitor C4 is open and switches SW3-SW1 of capacitors C3-C1 are closed, to a state where switch SW4 is closed and switches SW3-SW1 are open, a deterioration in the linearity of capacitance change occurs, corresponding to the difference between the first capacitance difference and the second capacitance difference. For example, the larger the difference between the first capacitance difference and the second capacitance difference, the greater the degree of linearity deterioration. The reason why the first capacitance difference and the second capacitance difference are so different is that, as... Figures 12-14 As shown, the location and addition method of parasitic capacitance differ between capacitors with MIM connected in parallel and capacitors with MIM connected in series, with more parasitic capacitance generated in capacitors with MIM connected in series.

[0074] Therefore, in this embodiment, the method of using Figure 15 The method shown involves making the first capacitance difference of the capacitors connected in parallel with the second capacitance difference of the capacitors connected in series with the MIM approach each other. For example, by decreasing the first capacitance difference or increasing the second capacitance difference, the first capacitance difference and the second capacitance difference become close, thereby improving the linearity of capacitance value change. Specifically, for the capacitors connected in parallel with the MIM, the value of the parasitic capacitance relative to ground is increased. As a result, for example, the capacitance value increases when the switch is open, thereby decreasing the first capacitance difference, making the first capacitance difference and the second capacitance difference approach each other, thus improving the linearity of capacitance value change. Furthermore, for the capacitors connected in series with the MIM, the value of the parasitic capacitance relative to ground is decreased. As a result, for example, the capacitance value decreases when the switch is open, thereby increasing the second capacitance difference, making the first capacitance difference and the second capacitance difference approach each other, thus improving the linearity of capacitance value change.

[0075] Thus, in the present embodiment, let the capacitance value between the first node N1 and the ground node NG formed by the parallelly connected MIM capacitor as the first capacitor and the parasitic capacitance of the parallelly connected MIM capacitor be a first capacitance value. Also, let the capacitance value between the first node N1 and the ground node NG formed by the seriesly connected MIM capacitor as the second capacitor and the parasitic capacitance of the seriesly connected MIM capacitor be a second capacitance value. Also, let the capacitance difference in each 1 LSB of the control data DCN between the first capacitance value when the first switch as the switch of the parallelly connected MIM capacitor is on and the first capacitance value when the first switch is off be a first capacitance difference. Also, let the capacitance difference in each 1 LSB of the control data DCN between the second capacitance value when the second switch as the switch of the seriesly connected MIM capacitor is on and the second capacitance value when the second switch is off be a second capacitance difference. At this time, in the present embodiment, a method of making the first capacitance difference and the second capacitance difference close is adopted.

[0076] Specifically, in the present embodiment, as the method of making the first capacitance difference of the parallelly connected MIM capacitor and the second capacitance difference of the seriesly connected MIM capacitor close, the method described in Figures 2-7 is adopted. For example, in plan view, the shape pattern of at least one of the first electrodes EDj, ECj, EBj of the first capacitor Cj connected in parallel with MIM, the first ground shield GSj surrounding the first capacitor Cj, the second electrodes EDi, ECi, EBi of the second capacitor Ci connected in series with MIM, and the second ground shield GSi surrounding the second capacitor Ci is set. Here, in Figure 8 , Figure 15 , the capacitors C18 to C4 are the first capacitor Cj connected in parallel with MIM. In addition, the capacitors C3 to C1 are the second capacitor Ci connected in series with MIM.

[0077] Thus, by setting the shape pattern of the first electrodes EDj, ECj, EBj, the first ground shield GSj, the second electrodes EDi, ECi, EBi, or the second ground shield GSi to a prescribed shape pattern, the first capacitance difference and the second capacitance difference can be made close. For example, by setting these electrodes and ground shields to a shape pattern that increases the value of the parasitic capacitance of the first capacitor Cj or reduces the value of the parasitic capacitance of the second capacitor Ci, the first capacitance difference and the second capacitance difference can be made close. Also, by making the first capacitance difference and the second capacitance difference close, the deterioration of the linearity indicated by A4, A5 of Figure 11 can be suppressed, and a variable capacitance circuit 30 that can improve the linearity of the capacitance value change can be realized.

[0078] More specifically, in the present embodiment, at least one of the first arrangement relationship between the first electrodes EDj, ECj, EBj and the first ground shield GSj, and the second arrangement relationship between the second electrodes EDi, ECi, EBi and the second ground shield GSi is set in such a manner that the first capacitance difference and the second capacitance difference are close to each other. For example, as the first arrangement relationship, a distance relationship between the first electrodes EDj, ECj, EBj and the first ground shield GSj, a relationship of the opposing area of the side surface, and the like are set. Also, as the second arrangement relationship, a distance relationship between the second electrodes EDi, ECi, EBi and the second ground shield GSi, a relationship of the opposing area of the side surface, and the like are set. In this way, by setting the first arrangement relationship between the first electrodes EDj, ECj, EBj and the first ground shield GSj, and the second arrangement relationship between the second electrodes EDi, ECi, EBi and the second ground shield GSi to a prescribed arrangement relationship, the first capacitance difference and the second capacitance difference can be made close to each other. For example, by setting the first arrangement relationship and the second arrangement relationship to an arrangement relationship in which the value of the parasitic capacitance of the first capacitor Cj is increased, or the value of the parasitic capacitance of the second capacitor Ci is decreased, the first capacitance difference and the second capacitance difference can be made close to each other. Also, by making the first capacitance difference and the second capacitance difference close to each other, the deterioration of the linearity shown by A4, A5 of the variable capacitance circuit 30 can be suppressed, and a variable capacitance circuit 30 capable of improving the linearity of the change in the capacitance value can be implemented. Figure 11

[0079] Next, using Figures 16-21 the specific method of making the first capacitance difference close to the second capacitance difference will be described. First, using Figures 16-18 , a method of making the first capacitance difference close to the second capacitance difference by increasing the parasitic capacitance of the first capacitor Cj connected in parallel to the MIM will be described.

[0080] For example, Figure 16 is an example of the shape pattern or arrangement relationship of the first capacitor Cj in the case where the method of the present embodiment is not employed. In Figure 16 , the distance LA1 in the first direction DR1 and the distance LB1 in the second direction DR2 between the first electrode EDj and the first ground shield GSj are long.

[0081] On the other hand, Figure 17 is an example of the shape pattern or arrangement relationship of the first capacitor Cj in the case where the method of the present embodiment is employed. In Figure 17 , the distance LA1 in the first direction DR1 and the distance LB1 in the second direction DR2 between the first electrode EDj and the first ground shield GSj are shorter than Figure 16 . By thus shortening the distances LA1, LB1, the value of the parasitic capacitance with respect to the ground is increased. For example, Figure 12 ​The value of the parasitic capacitance CPG1 increases. Furthermore, by increasing the value of the parasitic capacitance, in Figure 15 In the parallel-connected MIM, the first capacitance value of the first capacitor Cj increases when the switch is off, thereby reducing the first capacitance difference, which is the difference between the first capacitance value when the switch is on and the first capacitance value when the switch is off. Since the first capacitance difference of the first capacitor Cj in the parallel-connected MIM is greater than the second capacitance difference of the second capacitor Ci in the series-connected MIM, by reducing the first capacitance difference in this way, the first capacitance difference is brought closer to the second capacitance difference. Therefore, it is possible to suppress... Figure 11 The deterioration of linearity shown in A4 and A5 can improve the linearity of the capacitance value change of the variable capacitor circuit 30.

[0082] In addition, Figure 18 In this design, the opposing area of ​​adjacent sides is increased by setting the first electrode EDj and the first grounding shield GSj to a comb-like shape with their sides facing each other when viewed from above. Specifically, the first electrode EDj has a first portion P1 and a second portion P2 that are convex when viewed from above. The first grounding shield GSj has a third portion P3 with its side facing the side of the first portion P1 of the first electrode EDj and having a concave shape when viewed from above, and a fourth portion P4 with its side facing the side of the second portion P2 of the first electrode EDj and having a concave shape when viewed from above. For example, the side of the convex first portion P1 of the first electrode EDj and the side of the concave third portion P3 of the first grounding shield GSj are facing each other in, for example, three directions. That is, the concave third portion P3 is formed in a manner that surrounds the convex first portion P1 in three directions. Furthermore, the convex second portion P2 of the first electrode EDj faces the concave fourth portion P4 of the first grounding shield GSj in, for example, three directions. That is, the concave fourth portion P4 is formed such that it surrounds the convex second portion P2 in three directions. This increases the area of ​​the opposing side of the first grounding shield GSj that faces the side of the first electrode EDj. Thus, by increasing the area of ​​the opposing side of the first electrode EDj and the first grounding shield GSj, the value of the parasitic capacitance relative to ground increases. For example, Figure 12 The value of the parasitic capacitance CPG1 increases. Furthermore, by increasing the value of the parasitic capacitance, the first capacitance value of the first capacitor Cj connected in parallel to the MIM when the switch is off increases, thereby reducing the first capacitance difference, which is the capacitance difference between the first capacitance value when the switch is on and the first capacitance value when the switch is off. The first capacitance difference of the first capacitor Cj connected in parallel to the MIM is larger than the second capacitance difference of the second capacitor Ci connected in series to the MIM. Therefore, by reducing the first capacitance difference and bringing it closer to the second capacitance difference, the linearity of the capacitance change in the variable capacitor circuit 30 can be improved.

[0083] Next, using Figures 19-21 The method of making the first capacitance close to the second capacitance by reducing the parasitic capacitance of the second capacitor Ci connected in series with the MIM will be described.

[0084] For example, Figure 19 is an example of the shape pattern and the arrangement relationship of the second capacitor Ci in the case where the method of the present embodiment is not employed. In Figure 19 , the distance LA2 in the first direction DR1 and the distance LB2 in the second direction DR2 between the second electrodes EBi, ECi, EDi and the second ground shield GSi are short.

[0085] On the other hand, Figure 20 , Figure 21 is an example of the shape pattern and the arrangement relationship of the second capacitor Ci in the case where the method of the present embodiment is employed. In Figure 20 , the distance LA2 in the first direction DR1 between the second electrodes EBi, ECi, EDi and the second ground shield GSi is longer than Figure 19 . In Figure 21 , the distance LB2 in the second direction DR2 between the second electrodes EBi, ECi, EDi and the second ground shield GSi is longer than Figure 19 . In this way, by making the distances LA2, LB2 longer, the value of the parasitic capacitance to the ground is reduced. For example Figure 13 , the values of the parasitic capacitances CPG1, CPG2 are reduced. Also, by the reduction in the value of the parasitic capacitance, in Figure 15 , the second capacitance value at the time when the switch of the second capacitor Ci connected in series with the MIM is off is reduced, and thus the second capacitance difference, which is the capacitance difference between the second capacitance value at the time when the switch is on and the second capacitance value at the time when the switch is off, is increased. The second capacitance difference of the second capacitor Ci connected in series with the MIM is smaller than the first capacitance difference of the first capacitor Cj connected in parallel with the MIM, and thus by thus making the second capacitance difference larger, the first capacitance difference and the second capacitance difference are made close to each other. Thereby, it is possible to suppress the deterioration of the linearity indicated by A4, A5 in Figure 11 , and it is possible to improve the linearity of the change in the capacitance value of the variable capacitance circuit 30.

[0086] In this way, in the present embodiment, in the first capacitor Cj connected in parallel with the MIM, as indicated by Figure 17 , the distance LA1 in the first direction DR1 between the first electrode EDj and the first ground shield GSi is shortened. On the other hand, in the second capacitor Ci connected in series with the MIM, as indicated by Figure 20As shown, the distance LA2 in the first direction DR1 between the second electrode EBi, ECi, EDi and the second ground shield GSi is made longer. That is, with respect to the distances LA1, LA2, the relationship LA2 > LA1 is satisfied. In this way, if the relationship LA2 > LA1 is satisfied, in the first capacitor Cj connected in parallel with the MIM, as shown in Figure 17 LA1 is made shorter, and thus the value of the parasitic capacitance with respect to the ground increases, and the first capacitance value at the time when the switch of the first capacitor Cj connected in parallel with the MIM is turned off increases. Thus, the first capacitance difference as the capacitance difference between the first capacitance value at the time when the switch is turned on and the first capacitance value at the time when the switch is turned off decreases, the first capacitance difference of the first capacitor Cj connected in parallel with the MIM and the second capacitance difference of the second capacitor Ci connected in series with the MIM approach, and the linearity of the change in the capacitance value of the variable capacitance circuit 30 can be improved. Further, if the relationship LA2 > LA1 is satisfied, in the second capacitor Ci connected in series with the MIM, as shown in Figure 20 LA2 is made longer, and thus the value of the parasitic capacitance with respect to the ground decreases, and the second capacitance value at the time when the switch of the second capacitor Ci connected in series with the MIM is turned off decreases. Thus, the second capacitance difference as the capacitance difference between the second capacitance value at the time when the switch is turned on and the second capacitance value at the time when the switch is turned off increases, the first capacitance difference of the first capacitor Cj connected in parallel with the MIM and the second capacitance difference of the second capacitor Ci connected in series with the MIM approach, and the linearity of the change in the capacitance value of the variable capacitance circuit 30 can be improved.

[0087] Further, in the present embodiment, in the first capacitor Cj connected in parallel with the MIM, as shown in Figure 17 LA1 is made shorter. On the other hand, in the second capacitor Ci connected in series with the MIM, as shown in Figure 21 LB2 is made longer. That is, with respect to the distances LB1, LB2, the relationship LB2 > LB1 is satisfied. In this way, if the relationship LB2 > LB1 is satisfied, in the first capacitor Cj connected in parallel with the MIM, as shown in Figure 17 LB1 is made shorter, and thus the value of the parasitic capacitance with respect to the ground increases, and the first capacitance value at the time when the switch of the first capacitor Cj connected in parallel with the MIM is turned off increases. Thus, the first capacitance difference as the capacitance difference between the first capacitance value at the time when the switch is turned on and the first capacitance value at the time when the switch is turned off decreases, the first capacitance difference and the second capacitance difference approach, and the linearity of the change in the capacitance value of the variable capacitance circuit 30 can be improved. Further, if the relationship LB2 > LB1 is satisfied, in the second capacitor Ci connected in series with the MIM, as shown in Figure 21As shown, the distance LB2 increases, thereby reducing the value of the parasitic capacitance relative to ground, and reducing the value of the second capacitor Ci connected in series with MIM when the switch is off. Consequently, the difference between the second capacitance value when the switch is on and when the switch is off increases, and the first capacitance difference becomes closer to the second capacitance difference, improving the linearity of the capacitance change in the variable capacitor circuit 30.

[0088] In addition, such as Figure 17 , Figure 18 As shown, the first electrode EDj of the first capacitor Cj connected in parallel to the MIM is, for example, an electrode connected to the other end of the first switch SWj, one end of which is connected to the ground node NG. By setting the shape pattern of the first electrode EDj or setting the first configuration relationship between the first electrode EDj and the first ground shield GSj, the value of the parasitic capacitance relative to ground can be increased, for example. Figure 17 As shown, reducing the distances LA1 and LB1 between the first electrode EDj and the first grounding shield GSj increases the value of the parasitic capacitance relative to ground, or as shown... Figure 18 By arranging the first electrode EDj and the first grounding shield GSj in a comb-like shape as shown, the value of the parasitic capacitance relative to ground can be increased. Furthermore, by increasing the value of the parasitic capacitance of the first capacitor Cj in this way, the first capacitance difference of the first capacitor Cj is reduced, and the first capacitance difference of the first capacitor Cj can be brought closer to the second capacitance difference of the second capacitor Ci, thereby improving the linearity of the capacitance change in the variable capacitor circuit 30. Alternatively, the first electrode of the first capacitor Cj connected in parallel to the MIM can be, for example, a first electrode EBj formed of a metal layer ALB. By setting the shape pattern of the first electrode EBj in this way, or by setting the first configuration relationship between the first electrode EBj and the first grounding shield GSj, the value of the parasitic capacitance relative to ground can be increased, and the first capacitance difference can be brought closer to the second capacitance difference.

[0089] In addition, such as Figure 20 , Figure 21 As shown, the second electrode EBi of the second capacitor Ci connected in series with the MIM is, for example, an electrode connected to the other end of the second switch SWi, one end of which is connected to the ground node NG. By setting the shape pattern of the second electrode EBi in this way, or by setting a second configuration relationship between the second electrode EBi and the second ground shield GSi, the value of parasitic capacitance relative to ground can be reduced, for example. Figure 20 , Figure 21As shown, by increasing the distances LA2, LB2, etc. between the second electrode EBi and the second grounding shield GSi, the value of the parasitic capacitance relative to ground can be reduced. Furthermore, by reducing the value of the parasitic capacitance of the second capacitor Ci in this way, the second capacitance difference of the second capacitor Ci is increased, and the first capacitance difference of the first capacitor Cj and the second capacitance difference of the second capacitor Ci can be brought closer together, thereby improving the linearity of the capacitance value change of the variable capacitor circuit 30.

[0090] In addition, such as Figure 3 As shown, the second electrode of the second capacitor Ci connected in series with the MIM can also be a second electrode ECi connected to the intermediate connection node of the multiple MIM capacitors CM3 and CM4 connected in series. That is, the second electrode can also be a second electrode ECi formed by the metal layer ALC. By setting the shape pattern of the second electrode ECi in this way, or setting a second configuration relationship between the second electrode ECi and the second ground shield GSi, for example, the value of parasitic capacitance relative to ground can be reduced. For example, as Figure 20 , Figure 21 As shown, by increasing the distances LA2, LB2, etc., between the second electrode ECi and the second grounding shield GSi, the value of parasitic capacitance relative to ground can be reduced, making the first capacitance difference closer to the second capacitance difference, thereby improving the linearity of the capacitance change in the variable capacitor circuit 30. Furthermore, the second electrode of the second capacitor Ci connected in series with the MIM can, for example, be a second electrode EDi formed from a metal layer ALD. By setting the shape and pattern of the second electrode EDi, or by setting a second configuration relationship between the second electrode EDi and the second grounding shield GSi, the value of parasitic capacitance relative to ground can be reduced, making the first capacitance difference closer to the second capacitance difference.

[0091] In addition, such as Figure 2 , Figure 17 , Figure 18 As shown, the first capacitor Cj of the MIM connected in parallel includes MIM capacitors CM1 and CM2 stacked and connected in parallel in the top view direction. CM1 is the first MIM capacitor, and CM2 is the second MIM capacitor. Furthermore, as... Figure 3 , Figure 20 , Figure 21As shown, the 2nd capacitor Ci connected in series with the MIMs includes the MIM capacitors CM3, CM4 stacked in the direction of the plan view and connected in series. CM3 is a 3rd MIM capacitor, and CM4 is a 4th MIM capacitor. In this way, if the 1st capacitor Cj connected in parallel with the MIMs is constituted by the MIM capacitors CM1, CM2 stacked in the direction of the plan view as the longitudinal direction, and the 2nd capacitor Ci connected in series with the MIMs is constituted by the MIM capacitors CM3, CM4 stacked in the direction of the plan view, the 1st capacitor Cj and the 2nd capacitor Ci can be implemented with a smaller layout area. That is, by stacking the MIM capacitors in the direction of the plan view as the longitudinal direction, the increase in the area in the lateral direction can be suppressed, and the 1st capacitor Cj connected in parallel with the MIMs and the 2nd capacitor Ci connected in series with the MIMs can be implemented. Thus, the layout area of the variable capacitance circuit 30 can be reduced, and miniaturization of the circuit device 20 including the variable capacitance circuit 30 can be achieved, for example. Figure 23

[0092] Further, as shown in FIG. 2, the 1st ground shield GSj surrounds the MIM capacitor CM1 and the MIM capacitor CM2 in the plan view, and the 2nd ground shield GSi surrounds the MIM capacitor CM3 and the MIM capacitor CM4 in the plan view. In this way, the MIM capacitors CM1, CM2 constituting the 1st capacitor Cj are surrounded by the 1st ground shield GSj, and the formation of useless parasitic capacitance between the MIM capacitors CM1, CM2 and components outside the 1st ground shield GSj can be prevented. Further, the MIM capacitors CM3, CM4 constituting the 2nd capacitor Ci are surrounded by the 2nd ground shield GSi, and the formation of useless parasitic capacitance between the MIM capacitors CM3, CM4 and components outside the 2nd ground shield GSi can be prevented. Figure 2 Figure 4 Further, in the present embodiment, the capacitance values of the plurality of capacitors of the capacitor array 32 of the variable capacitance circuit 30 are binary-weighted. For example, the capacitance values of the capacitors C7, C6, C5, C4, C3, C2, C1 are binary-weighted in the manner of 8C, 4C, 2C, 1C, (1 / 2) x C, (1 / 4) x C, (1 / 8) x C. In this way, by controlling the binary code of the data DCN, the capacitance value of the variable capacitance circuit 30 can be digitally adjusted. In addition, the capacitor array 32 of the variable capacitance circuit 30 may, for example, include capacitors whose capacitance values are not binary-weighted, like the capacitors C18 to C8 of FIG. 6.

[0093] Further, in the present embodiment, the capacitance values of the plurality of capacitors of the capacitor array 32 of the variable capacitance circuit 30 are binary-weighted. For example, the capacitance values of the capacitors C7, C6, C5, C4, C3, C2, C1 are binary-weighted in the manner of 8C, 4C, 2C, 1C, (1 / 2) x C, (1 / 4) x C, (1 / 8) x C. In this way, by controlling the binary code of the data DCN, the capacitance value of the variable capacitance circuit 30 can be digitally adjusted. In addition, the capacitor array 32 of the variable capacitance circuit 30 may, for example, include capacitors whose capacitance values are not binary-weighted, like the capacitors C18 to C8 of FIG. 6. Figure 8 Figure 8

[0094] Figure 22 A layout configuration example of the variable capacitance circuit 30 of the present embodiment is shown. For example, in the present embodiment, the variable capacitance circuit 30 is implemented by the capacitor array 32 including the plurality of capacitors C1 to C18, and the data DCN inputting the binary code to the capacitor array 32. Figure 22 ​​​​The MIM-connected capacitors C18 to C8 are arranged in the second direction DR2 with the first direction DR1 as the longitudinal direction, for example, in the lower right direction in the paper surface of the MIM-connected capacitors C18 to C8. Further, the MIM-connected capacitors C7 to C4 are arranged with the first direction DR1 as the longitudinal direction, for example, in the lower left direction in the paper surface of the MIM-connected capacitors C18 to C8. Further, the MIM-connected capacitors C3 to C1 are arranged with the first direction DR1 as the longitudinal direction, for example, in the upper left direction in the paper surface of the MIM-connected capacitors C18 to C8. In the MIM-connected capacitors C18 to C4, for example, as shown in FIG. 3, the layout is performed in such a manner that the distances LA1 and LB1 are small. On the other hand, in the MIM-connected capacitors C1 to C3, for example, as shown in FIG. 4, the layout is performed in such a manner that the distances LA2 and LB2 are large. That is, the layout is performed in such a manner that LA2 > LA1 and LB2 > LB1 are satisfied. Figure 17 Figure 20 Figure 21

[0095] 3. Circuit device

[0096] Figure 23 A structure example of the circuit device 20 of the present embodiment is shown. The circuit device 20 of the present embodiment includes the oscillation circuit 40. Further, the circuit device 20 can include the output buffer circuit 50, the power supply circuit 60, the power supply land PVDD, the ground land PGND, the clock land PCK, and the lands PX1 and PX2 for connection of the vibrator 10. Further, the oscillator 4 of the present embodiment includes the vibrator 10 and the circuit device 20. The vibrator 10 is electrically connected to the circuit device 20. For example, the vibrator 10 is electrically connected to the circuit device 20 using internal wiring, bonding wires, or metal bumps of a package in which the vibrator 10 and the circuit device 20 are housed.

[0097] ​​​The vibrator 10 is an element that generates mechanical vibration by an electric signal. The vibrator 10 can be implemented by, for example, a vibrating piece such as a quartz vibrating piece. For example, the vibrator 10 can be implemented by a quartz vibrating piece that performs thickness shear vibration in AT cut or SC cut, a tuning fork type quartz vibrating piece, or a double tuning fork type quartz vibrating piece, or the like. For example, the vibrator 10 can be a vibrator built in a temperature-compensated quartz oscillator (TCXO) that does not have a thermostat, or a vibrator built in a thermostat type quartz oscillator (OCXO) that has a thermostat. Alternatively, the vibrator 10 can be a vibrator built in an SPXO (Simple Packaged Crystal Oscillator). In addition, the vibrator 10 of the present embodiment can be implemented by various vibrating pieces other than the thickness shear vibration type, the tuning fork type, or the double tuning fork type, a piezoelectric vibrating piece formed of a material other than quartz, or the like. For example, as the vibrator 10, a SAW (Surface Acoustic Wave) resonator, a MEMS (Micro Electro Mechanical Systems) vibrator formed using a silicon substrate as a silicon vibrator, or the like can be used.

[0098] The circuit device 20 is, for example, an IC (Integrated Circuit) manufactured by a semiconductor process, and is a semiconductor chip in which circuit elements are formed on a semiconductor substrate. In the present embodiment, the circuit device 20 includes an oscillation circuit 40, an output buffer circuit 50, and a power supply circuit 60. Figure 23

[0099] The oscillation circuit 40 is a circuit that oscillates the vibrator 10. The oscillation circuit 40 is electrically connected to the connection pads PX1 and PX2, for example, and generates an oscillation signal OSC by oscillating the vibrator 10. The connection pad PX1 is a first connection pad, and the connection pad PX2 is a second connection pad. The oscillation circuit 40 can be implemented by, for example, a drive circuit for oscillation and active elements such as a capacitor, a resistor, or the like provided between the connection pad PX1 and the connection pad PX2. The drive circuit can be implemented by, for example, an inverter circuit of CMOS or a bipolar transistor. The drive circuit is a core circuit of the oscillation circuit 40, and the drive circuit performs voltage driving or current driving on the vibrator 10, thereby oscillating the vibrator 10. As the oscillation circuit 40, various types of oscillation circuits such as an inverter type, a Pierce type, a Colpitts type, or a Hartley type can be used.

[0100] ​The output buffer circuit 50 outputs a clock signal CKQ based on the oscillation signal OSC. For example, the output buffer circuit 50 buffers the oscillation signal OSC and outputs it as the clock signal CKQ to the clock land PCK. Also, this clock signal CKQ is output to the outside via the external terminal TCK of the oscillator 4. For example, the output buffer circuit 50 outputs the clock signal CKQ in the form of a signal of a single-ended CMOS. In addition, the output buffer circuit 50 can also output the clock signal CKQ in a signal form other than CMOS. For example, the output buffer circuit 50 can also output a differential clock signal to the outside in the form of a signal of LVDS (Low Voltage Differential Signaling), PECL (Positive Emitter Coupled Logic), HCSL (High Speed Current Steering Logic), or a differential CMOS (Complementary MOS).

[0101] The power supply circuit 60 is supplied with the power supply voltage VDD from the power supply land PVDD and the ground voltage from the ground land PGND, and supplies various power supply voltages for the internal circuit of the circuit device 20 to the internal circuit. For example, the power supply circuit 60 supplies a regulated power supply voltage based on the power supply voltage VDD to the oscillation circuit 40 and the like. For example, the power supply circuit 60 includes a regulator that generates the regulated power supply voltage. In addition, the power supply circuit 60 can include a reference voltage generation circuit that generates a reference voltage used for generating a bias current, a bias voltage, or a regulated power supply voltage, and the like.

[0102] Furthermore, the circuit device 20 includes a power connection pad PVDD, a ground connection pad PGND, a clock connection pad PCK, and connection pads PX1 and PX2 for connecting the oscillator. These connection pads are, for example, terminals of the circuit device 20, which are semiconductor chips. For example, in the connection pad area, a metal layer is exposed from a passivation film that serves as an insulating layer, and this exposed metal layer constitutes the connection pad of the circuit device 20. The power connection pad PVDD is the connection pad to which the input power supply voltage VDD is received. For example, the power supply voltage VDD from an external power supply device is supplied to the power connection pad PVDD. The ground connection pad PGND is the terminal to which the ground voltage GND is supplied. GND can also be called VSS, and the ground voltage is, for example, the ground potential. The clock connection pad PCK is the connection pad to which the clock signal CKQ is output. For example, the clock signal CKQ based on the oscillation signal OSC in the oscillation circuit 40 is output to the outside from the clock connection pad PCK. The power connection pad PVDD, the ground connection pad PGND, and the clock connection pad PCK are electrically connected to the external terminals TVDD, TGND, and TCK for external connection of the oscillator 4, respectively. For example, electrical connections can be made using internal wiring, bonding wires, or metal bumps within the package. Furthermore, the external terminals TVDD, TGND, and TCK of the oscillator 4 are electrically connected to external devices. Additionally, connection pads PX1 and PX2 are used for connecting the oscillator 10. For example, connection pad PX1 is electrically connected to one end of the oscillator 10, and connection pad PX2 is electrically connected to the other end of the oscillator 10. For example, the connection pads PX1 and PX2 of the package housing the oscillator 10 and the circuit device 20 can be electrically connected using internal wiring, bonding wires, or metal bumps within the package.

[0103] Furthermore, the oscillation circuit 40 includes a variable capacitor circuit 30, and the oscillation frequency can be adjusted by adjusting the capacitance of this variable capacitor circuit 30. For example... Figure 1 , Figure 8 As explained, the variable capacitor circuit 30 is implemented using a capacitor array 32 and a switch array 34 connected in series with the capacitor array 32. That is, the variable capacitor circuit 30 consists of a capacitor array 32 and a switch array 34. The capacitor array 32 has multiple capacitors with their capacitance values ​​weighted in binary, and the switch array 34 has multiple switches. Each of these switches connects or disconnects the connection between each capacitor in the capacitor array and the ground node NG. Furthermore, the connection in this embodiment is an electrical connection. An electrical connection is a connection capable of transmitting electrical signals, and thus a connection capable of transmitting information based on electrical signals. An electrical connection can also be a connection via passive components, etc.

[0104] As described above, the circuit device 20 of this embodiment includes an oscillation circuit 30 having a variable capacitor circuit 30, the oscillation circuit 30 controlling the oscillation frequency according to the capacitance value of the variable capacitor circuit 30. Furthermore, in Figure 1 ,Figure 8 The first node N1 explained in the above is an oscillation node of the oscillation circuit 40. For example, the first node N1 is a node connected to the land PX1 or the land PX2, and is a node electrically connected to one end or the other end of the vibrator 10. Thus, by setting the first node N1 as the oscillation node of the oscillation circuit 40, the capacitance value of the variable capacitance circuit 30 is controlled in accordance with the control data DCN, whereby the oscillation frequency of the oscillation circuit 40 can be controlled. Thus, for example, temperature compensation processing of the oscillation frequency, fine adjustment processing of the oscillation frequency, and the like can be implemented. Further, as the variable capacitance circuit 30, a first variable capacitance circuit connected to the land PX1 and a second variable capacitance circuit connected to the land PX2 can be provided.

[0105] 4. Oscillator

[0106] Figure 24 A configuration example of the oscillator 4 of the present embodiment is shown. The oscillator 4 of the present embodiment includes the circuit device 20 and the vibrator 10 that oscillates by being driven by the oscillation circuit 40 of the circuit device 20. Specifically, the oscillator 4 has the vibrator 10, the circuit device 20, and the package 15 that houses the vibrator 10 and the circuit device 20. The package 15 is formed of, for example, ceramic or the like, has a housing space in the inside thereof, and has the vibrator 10 and the circuit device 20 housed in the housing space. The housing space is hermetically sealed, and preferably becomes a reduced-pressure state that is a state close to a vacuum. By the package 15, the vibrator 10 and the circuit device 20 can be appropriately protected from impacts, dust, heat, moisture, and the like.

[0107] The package 15 has a base 16 and a lid 17. Specifically, the package 15 is composed of the base 16 that supports the vibrator 10 and the circuit device 20, and the lid 17 that is joined to the upper surface of the base 16 in a manner that forms a receiving space between the base 16. Also, the vibrator 10 is supported on a step portion provided on the inner side of the base 16 via a terminal electrode. In addition, the circuit device 20 is disposed on the inner side bottom surface of the base 16. Specifically, the circuit device 20 is disposed in a manner that the active surface faces the inner side bottom surface of the base 16. The active surface is a surface of the circuit device 20 on which circuit elements are formed. Further, bumps BMP are formed on lands that are terminals of the circuit device 20. Also, the circuit device 20 is supported on the inner side bottom surface of the base 16 via the conductive bumps BMP. The conductive bumps BMP are, for example, metal bumps, and the vibrator 10 and the circuit device 20 are electrically connected via the bumps BMP, internal wiring of the package 15, and a terminal electrode. Further, the circuit device 20 is electrically connected to external terminals 18, 19 that are external connection terminals of the oscillator 4 via the bumps BMP and the internal wiring of the package 15. The external terminals 18, 19 are formed on the outer side bottom surface of the package 15. The external terminals 18, 19 are connected to external devices via external wiring. The external wiring is, for example, wiring formed on a circuit board on which the external devices are mounted. Thus, it is possible to output a clock signal or the like to the external devices.

[0108] Further, in the Figure 24 circuit device 20 is mounted in a manner that the active surface faces downward, but the present embodiment is not limited to such mounting. For example, the circuit device 20 can be mounted in a manner that the active surface faces upward. That is, the circuit device 20 can be mounted in a manner that the active surface faces the vibrator 10. Alternatively, the oscillator 4 can be a wafer level package (WLP) oscillator. In this case, the oscillator 4 includes a base having a semiconductor substrate and a through electrode that penetrates between a first surface and a second surface of the semiconductor substrate, a vibrator 10 fixed on the first surface of the semiconductor substrate via a conductive joining member such as a metal bump, and external terminals provided on the second surface side of the semiconductor substrate via an insulating layer such as a redistribution layer. Also, an integrated circuit that is the circuit device 20 is formed on the first surface or the second surface of the semiconductor substrate. In this case, by sticking a first semiconductor wafer on which a plurality of bases in which the vibrator 10 and the integrated circuit are disposed are formed and a second semiconductor wafer on which a plurality of lids are formed, joining the plurality of bases and the plurality of lids, and then performing singulation of the oscillator 4 using a dicing saw or the like, it is possible to realize a wafer level package oscillator 4, and to manufacture the oscillator 4 at a high production rate and at a low cost.

[0109] As explained above, the variable capacitance circuit of the present embodiment variably controls a capacitance value in accordance with control data, wherein the variable capacitance circuit includes: a capacitor array including a plurality of capacitors; and a switch array having a plurality of switches turned on or off in accordance with the control data, the switch array being provided in series with the capacitor array between a first node and a ground node. Also, the capacitor array includes: a first capacitor connected in parallel by a plurality of MIM capacitors; and a second capacitor connected in series by a plurality of MIM capacitors. Further, the switch array includes: a first switch connected in series with the first capacitor between the first node and the ground node; and a second switch connected in series with the second capacitor between the first node and the ground node. Also, let a capacitance value between the first node and the ground node formed by the first capacitor and a parasitic capacitance of the first capacitor be a first capacitance value, and let a capacitance value between the first node and the ground node formed by the second capacitor and a parasitic capacitance of the second capacitor be a second capacitance value. In addition, let a difference in the first capacitance value when the first switch is on and the first capacitance value when the first switch is off in each 1 LSB of the control data be a first capacitance difference, and let a difference in the second capacitance value when the second switch is on and the second capacitance value when the second switch is off in each 1 LSB of the control data be a second capacitance difference. At this time, the shape pattern of at least one of a first electrode that is an electrode of the first capacitor, a first ground shield that surrounds the first capacitor, a second electrode that is an electrode of the second capacitor, and a second ground shield that surrounds the second capacitor is set in such a way that the first capacitance difference and the second capacitance difference are close.

[0110] Thus, the variable capacitance circuit of the present embodiment includes: a capacitor array having a first capacitor connected in parallel by a plurality of MIM capacitors and a second capacitor connected in series by a plurality of MIM capacitors; and a switch array having a first switch and a second switch. Also, the shape pattern of at least one of a first electrode of the first capacitor, a first ground shield, a second electrode of the second capacitor, and a second ground shield is set in such a way that a first capacitance difference in the first capacitance value of the first capacitor when the first switch is on and off in each 1 LSB and a second capacitance difference in the second capacitance value of the second capacitor when the second switch is on and off in each 1 LSB are close. Thus, by setting the shape pattern of the first electrode, the first ground shield, the second electrode, or the second ground shield to a prescribed shape pattern, the first capacitance difference and the second capacitance difference can be made close, and by making the first capacitance difference and the second capacitance difference close, deterioration in linearity of the capacitance value variation can be suppressed. Therefore, a variable capacitance circuit or the like capable of improving linearity of the capacitance value variation can be provided.

[0111] Further, in the present embodiment, at least one of the first positional relationship between the first electrode and the first ground shield and the second positional relationship between the second electrode and the second ground shield can be set in such a manner that the first capacitance difference and the second capacitance difference are close to each other.

[0112] Thus, by setting the first positional relationship between the first electrode and the first ground shield and the second positional relationship between the second electrode and the second ground shield to the prescribed positional relationship, the first capacitance difference and the second capacitance difference can be made close to each other, and by making the first capacitance difference and the second capacitance difference close to each other, the linearity of the change in the capacitance value of the variable capacitance circuit can be improved.

[0113] Further, in the present embodiment, when the distance in the first direction between the first electrode and the first ground shield when viewed from above is LA1 and the distance in the first direction between the second electrode and the second ground shield when viewed from above is LA2, LA2 > LA1.

[0114] Thus, in the first capacitor, the distance LA1 in the first direction between the first electrode and the first ground shield is short, and thus the value of the parasitic capacitance with respect to the ground increases, and in the second capacitor, the distance LA2 in the first direction between the second electrode and the second ground shield is long, and thus the value of the parasitic capacitance with respect to the ground decreases. Thus, the first capacitance difference of the first capacitor is close to the second capacitance difference of the second capacitor, and the linearity of the change in the capacitance value of the variable capacitance circuit can be improved.

[0115] Further, in the present embodiment, when the distance in the first direction between the first electrode and the first ground shield when viewed from above is LA1 and the distance in the first direction between the second electrode and the second ground shield when viewed from above is LA2, LA2 > LA1.

[0116] Thus, the variable capacitance circuit of the present embodiment includes a capacitor array having a first capacitor in which a plurality of MIM capacitors are connected in parallel and a second capacitor in which a plurality of MIM capacitors are connected in series, and a switch array having a first switch and a second switch. Also, a relationship LA2 > LA1 is established with respect to a distance LA1 in a first direction between a first electrode of the first capacitor and a first ground shield and a distance LA2 in the first direction between a second electrode of the second capacitor and a second ground shield. Thus, in the first capacitor, the distance LA1 in the first direction between the first electrode and the first ground shield is short, and thus the value of the parasitic capacitance with respect to the ground increases, and in the second capacitor, the distance LA2 in the first direction between the second electrode and the second ground shield is long, and thus the value of the parasitic capacitance with respect to the ground decreases. Thus, the first capacitance difference of the first capacitor approaches the second capacitance difference of the second capacitor, and the linearity of the change in the capacitance value of the variable capacitance circuit can be improved.

[0117] Also, in the present embodiment, when a direction perpendicular to the first direction is a second direction, a distance in the second direction between the first electrode and the first ground shield when viewed from above is LB1, and a distance in the second direction between the second electrode and the second ground shield when viewed from above is LB2, LB2 > LB1 can be established.

[0118] Thus, in the first capacitor, the distance LB1 in the second direction between the first electrode and the first ground shield is short, and thus the value of the parasitic capacitance with respect to the ground increases, and in the second capacitor, the distance LB2 in the second direction between the second electrode and the second ground shield is long, and thus the value of the parasitic capacitance with respect to the ground decreases. Thus, the first capacitance difference of the first capacitor approaches the second capacitance difference of the second capacitor, and the linearity of the change in the capacitance value of the variable capacitance circuit can be improved.

[0119] Also, in the present embodiment, the first electrode can have a first portion whose shape when viewed from above is convex, and a second portion whose shape when viewed from above is convex, and the first ground shield can have a third portion whose side surface opposes the side surface of the first portion and whose shape when viewed from above is concave, and a fourth portion whose side surface opposes the side surface of the second portion and whose shape when viewed from above is concave.

[0120] Thus, in the first capacitor, by increasing the opposing area of the side surface of the first ground shield that opposes the side surface of the first electrode, the value of the parasitic capacitance with respect to the ground can be increased, and the first capacitance difference of the first capacitor can be made to approach the second capacitance difference of the second capacitor.

[0121] Also, the first electrode can be an electrode connected to the other end of the first switch connected to the ground node at one end.

[0122] By thus setting the shape pattern of the first electrode of the first capacitor or setting the first arrangement relationship between the first electrode and the first ground shield, it is possible to increase the value of the parasitic capacitance with respect to the ground, and to make the first capacitance difference of the first capacitor close to the second capacitance difference of the second capacitor.

[0123] In addition, in the present embodiment, the second electrode can be an electrode connected to an intermediate connection node of a plurality of MIM capacitors connected in series.

[0124] By thus setting the shape pattern of the second electrode of the second capacitor or setting the second arrangement relationship between the second electrode and the second ground shield, it is possible to reduce the value of the parasitic capacitance with respect to the ground, and to make the first capacitance difference of the first capacitor close to the second capacitance difference of the second capacitor.

[0125] In addition, in the present embodiment, the second electrode can be an electrode connected to an intermediate connection node of a plurality of MIM capacitors connected in series.

[0126] By thus setting the shape pattern of the second electrode of the second capacitor or setting the second arrangement relationship between the second electrode and the second ground shield, it is possible to reduce the value of the parasitic capacitance with respect to the ground, and to make the first capacitance difference of the first capacitor close to the second capacitance difference of the second capacitor.

[0127] In addition, in the present embodiment, the first capacitor can include a first MIM capacitor and a second MIM capacitor stacked in a plan view direction and connected in parallel, and the second capacitor can include a third MIM capacitor and a fourth MIM capacitor stacked in the plan view direction and connected in series.

[0128] In this way, if the first capacitor is constituted by the first MIM capacitor and the second MIM capacitor stacked in the plan view direction, and the second capacitor is constituted by the third MIM capacitor and the fourth MIM capacitor stacked in the plan view direction, it is possible to realize the first capacitor and the second capacitor with a smaller layout area.

[0129] In addition, in the present embodiment, the first ground shield can surround the first MIM capacitor and the second MIM capacitor in a plan view, and the second ground shield can surround the third MIM capacitor and the fourth MIM capacitor in the plan view.

[0130] In this way, the first MIM capacitor and the second MIM capacitor constituting the first capacitor are surrounded by the first ground shield, and the third MIM capacitor and the fourth MIM capacitor constituting the second capacitor are surrounded by the second ground shield, and it is possible to prevent the formation of useless parasitic capacitance between components outside the first ground shield and the second ground shield.

[0131] Further, in the present embodiment, it can also be that the capacitance values of the plurality of capacitors of the capacitor array are binary-weighted.

[0132] In this way, by controlling the code of the binary of the data, the capacitance value of the variable capacitance circuit can be adjusted numerically.

[0133] Further, in the present embodiment, it can also be that the oscillation circuit including the variable capacitance circuit described above controls the oscillation frequency in accordance with the capacitance value of the variable capacitance circuit, and the first node is an oscillation node of the oscillation circuit.

[0134] Further, the present embodiment relates to a circuit device including the variable capacitance circuit described above and an oscillation circuit that controls the oscillation frequency in accordance with the capacitance value of the variable capacitance circuit, and the first node is an oscillation node of the oscillation circuit.

[0135] In this way, by providing the variable capacitance circuit whose first node is an oscillation node of the oscillation circuit, the capacitance value of the variable capacitance circuit is controlled in accordance with the control data, whereby the oscillation frequency of the oscillation circuit can be controlled.

[0136] Further, the present embodiment relates to an oscillator including: the circuit device described above; and an oscillator element that oscillates by being driven by the oscillation circuit.

[0137] Further, the present embodiment has been described in detail as described above, but a person skilled in the art can easily understand that various modifications can be made without departing substantially from the present application, and that new matters and effects can be obtained. Therefore, such modified examples are all included in the scope of the present application. For example, in the specification or the drawings, a term that is recorded at least once together with a different term that is more general or synonymous can be replaced with the different term at any place in the specification or the drawings. In addition, all combinations of the present embodiment and the modified examples are also included in the scope of the present application. Further, the structure and operation of the variable capacitance circuit, the circuit device, the oscillator, and the like are not limited to those described in the present embodiment, and various modifications can be made.

Claims

1. A variable capacitor circuit, characterized in that, The capacitance value of the variable capacitor circuit is variably controlled according to control data, and the variable capacitor circuit includes: A capacitor array, which contains multiple capacitors; as well as A switch array having multiple switches that are turned on or off according to the control data, the switch array being connected in series with the capacitor array between the first node and the ground node. The capacitor array comprises: The first capacitor is composed of multiple MIM capacitors, i.e., metal-insulator-metal capacitors connected in parallel; and The second capacitor is composed of multiple MIM capacitors connected in series. The switch array includes: A first switch, which is connected in series with the first capacitor between the first node and the ground node; and The second switch is connected in series with the second capacitor between the first node and the ground node. Let the capacitance between the first node and the ground node, formed by the first capacitor and its parasitic capacitance, be the first capacitance value, and the capacitance between the first node and the ground node, formed by the second capacitor and its parasitic capacitance, be the second capacitance value. In a manner that makes the first capacitance value when the first switch is turned on and the first capacitance value when the first switch is turned off, in each LSB of the control data, the first capacitance difference and the second capacitance value when the second switch is turned on and the second capacitance value when the second switch is turned off, in each LSB of the control data, approximately equal to the first capacitance difference in the control data. The shape pattern of at least one of the following when viewed from above: a first electrode that serves as an electrode of the first capacitor, a first grounding shield surrounding the first capacitor, a second electrode that serves as an electrode of the second capacitor, and a second grounding shield surrounding the second capacitor.

2. The variable capacitor circuit according to claim 1, characterized in that, At least one of a first configuration relationship between the first electrode and the first grounding shield and a second configuration relationship between the second electrode and the second grounding shield is set in such a way that the first capacitance difference is close to the second capacitance difference.

3. The variable capacitor circuit according to claim 1, characterized in that, When the distance in the first direction between the first electrode and the first grounding shield when viewed from above is LA1, and the distance in the first direction between the second electrode and the second grounding shield is LA2, LA2 > LA1.

4. A variable capacitor circuit, characterized in that, The capacitance value of the variable capacitor circuit is variably controlled according to control data, and the variable capacitor circuit includes: A capacitor array, which contains multiple capacitors; as well as A switch array having multiple switches that are turned on or off according to the control data, the switch array being connected in series with the capacitor array between the first node and the ground node. The capacitor array comprises: The first capacitor is composed of multiple MIM capacitors connected in parallel; and The second capacitor is composed of multiple MIM capacitors connected in series. The switch array includes: A first switch, which is connected in series with the first capacitor between the first node and the ground node; and The second switch is connected in series with the second capacitor between the first node and the ground node. When the distance in the first direction between the first electrode of the first capacitor and the first grounding shield surrounding the first capacitor when viewed from above is LA1, and the distance in the first direction between the second electrode of the second capacitor and the second grounding shield surrounding the second capacitor is LA2, then LA2 > LA1.

5. The variable capacitor circuit according to claim 3 or 4, characterized in that, When the direction perpendicular to the first direction is defined as the second direction, the distance between the first electrode and the first grounding shield in the second direction when viewed from above is LB1, and the distance between the second electrode and the second grounding shield in the second direction is LB2, then LB2 > LB1.

6. The variable capacitor circuit according to any one of claims 1 to 4, characterized in that, The first electrode has: Part 1, which has a convex shape when viewed from above; and Part 2, in its top-view shape, is convex. The first grounding shield has: Part 3, whose side faces the side of Part 1, has a concave shape when viewed from above; and Part 4, whose side faces the side of Part 2, has a concave shape when viewed from above.

7. The variable capacitor circuit according to any one of claims 1 to 4, characterized in that, The first electrode is an electrode connected to the other end of the first switch, which is connected at one end to the grounding node.

8. The variable capacitor circuit according to claim 7, characterized in that, The second electrode is an electrode connected to the other end of the second switch, which is connected at one end to the grounding node.

9. The variable capacitor circuit according to claim 7, characterized in that, The second electrode is an electrode connected to the intermediate connection node of the plurality of MIM capacitors connected in series.

10. The variable capacitor circuit according to any one of claims 1 to 4, characterized in that, The first capacitor comprises a first MIM capacitor and a second MIM capacitor that are stacked and connected in parallel in the top view direction. The second capacitor comprises a third MIM capacitor and a fourth MIM capacitor that are stacked and connected in series in the top view direction.

11. The variable capacitor circuit according to claim 10, characterized in that, The first grounding shield surrounds the first MIM capacitor and the second MIM capacitor when viewed from above. The second grounding shield surrounds the third MIM capacitor and the fourth MIM capacitor when viewed from above.

12. The variable capacitor circuit according to any one of claims 1 to 4, characterized in that, The capacitance values ​​of the multiple capacitors in the capacitor array are weighted in binary.

13. A circuit device, characterized in that, The circuit device includes an oscillation circuit having a variable capacitor circuit as described in any one of claims 1 to 12. The oscillation frequency of the oscillation circuit is controlled by the capacitance value of the variable capacitor circuit. The first node is the oscillation node of the oscillation circuit.

14. An oscillator, characterized in that, The oscillator contains: The circuit device according to claim 13; and An oscillator that oscillates by being driven by the oscillation circuit.

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