A DC offset cancellation circuit and method

Abstract

A DC offset cancellation circuit and method are disclosed, comprising an offset cancellation module, an amplifier group, and an inverter structure. Several inverter structures are connected between two amplifier groups, with one end of each amplifier group connected to the signal input and the other end connected to the signal output. An offset cancellation module is provided between the input and output terminals of each amplifier group. This invention differs from existing offset cancellation circuit structures, as it can correct both common-mode voltage and differential-mode offset, improving the reliability of the circuit operation. The use of single-ended bias stabilizes the output DC point at the optimal bias point, ensuring optimal linearity for the inverter-structured amplifier and thus meeting the overall circuit linearity requirements. The Class AB output stage significantly reduces static power consumption, avoids wasted current in the transconductor, and has a much stronger driving capability than a standalone transconductor.

Description

Technical Field

[0001] This invention belongs to the field of optical communication chip design technology, specifically relating to a DC offset cancellation circuit and method. Background Technology

[0002] With the continuous improvement of data transmission rates, optical carriers, due to their enormous capacity, play a crucial role in the field of communication. In optical communication systems, optical receivers convert current signals into voltage signals, amplify the current into a voltage signal through a transimpedance amplifier, and then output it after further amplification. The offset calibration circuit, as part of the optical receiver, plays an indispensable role. Especially for inverter-structured amplifier circuits, if the circuit has a large differential-mode offset, due to the large gain from the front stage to the output, it may eventually lead to output saturation, thus affecting the circuit's performance.

[0003] To address this issue, existing methods employ a cascaded structure of two single-ended inverters to form negative feedback with the main path to eliminate differential-mode offset. However, this structure has drawbacks: the amplifier gain of the inverter structure is relatively low, leading to lower calibration accuracy; secondly, since the inverter structure lacks a reference voltage, the output common-mode point correction may not be at the optimal bias point; and thirdly, due to the narrow linear region of the inverter, the existing structure has limitations for circuits requiring high linearity. Furthermore, the transconductor is typically large, and existing offset cancellation structures do not consider low power consumption, resulting in a relatively high quiescent current. Summary of the Invention

[0004] The purpose of this invention is to provide a DC offset cancellation circuit and method, which not only realizes the calibration of differential mode offset, but also the correction of common mode voltage, and also solves the problem that existing offset cancellation structures do not take into account low power consumption, resulting in a large quiescent current.

[0005] To achieve the above objectives, the present invention adopts the following technical solution:

[0006] A DC offset cancellation circuit includes an offset cancellation module, an amplifier group, and an inverter structure; several inverter structures are connected between two amplifier groups, one end of each amplifier group is connected to a signal input terminal, and the other end is connected to a signal output terminal; an offset cancellation module is provided between the input and output terminals of each amplifier group.

[0007] The offset cancellation module includes an RC low-pass filter circuit, a voltage bias circuit, a high-gain amplifier, and a Class AB output stage. One end of the RC low-pass filter circuit is connected to the output of the amplifier group, and the other end is connected to the input of the high-gain amplifier. The other input of the high-gain amplifier is connected to the voltage bias circuit. The output of the high-gain amplifier is connected to the input of the Class AB output stage, and the output of the Class AB output stage is connected to the amplifier group.

[0008] Furthermore, the amplifier group includes amplifier VGA1, amplifier VGA2, amplifier VGA3 and amplifier VGA4; amplifier VGA1, amplifier VGA2, amplifier VGA3 and amplifier VGA4 are connected in series, the input terminal of amplifier VGA1 is connected to the signal input terminal, and the output terminal of amplifier VGA4 is connected to the signal input terminal.

[0009] Furthermore, the output of the Class AB output stage is connected to the output of amplifier VGA1 in the same amplifier group.

[0010] Furthermore, the inverter structure is connected between the output terminals of the two amplifiers VGA1, between the output terminals of the two amplifiers VGA2, and between the output terminals of the two amplifiers VGA3.

[0011] Furthermore, the inverter structure consists of two inverters connected end-to-end.

[0012] Furthermore, the RC low-pass filter circuit consists of a resistor and a capacitor connected in series, with one end connected to the output of the amplifier group and the other end connected to the input of the high-gain amplifier.

[0013] Furthermore, the high-gain amplifier is a folded cascode amplifier circuit with differential input and single-ended output.

[0014] Furthermore, the voltage bias circuit includes a resistor string and a voltage regulator capacitor, both of which are connected to another input terminal of the high-gain amplifier. The voltage bias circuit can clamp the output DC point to correct the common-mode voltage.

[0015] Furthermore, the Class AB output stage includes a circuit with a PMOS and an NMOS connected in parallel and an output circuit with a PMOS and an NMOS connected in series.

[0016] Furthermore, a method for eliminating DC offset using a DC offset cancellation circuit includes the following steps:

[0017] The offset cancellation circuit detects the DC component output from both ends of the variable gain amplifier group based on the inverter structure. The detected DC component is converted into current by comparing with the bias voltage and fed back to the output of the first stage of the amplifier group VGA, thereby compensating for the output offset. The offset is eliminated through continuous feedback correction, so that the operating point of VGA is stabilized at the optimal bias point. At the same time, the differential mode of the circuit is corrected through the phase-locked module between the two branches.

[0018] The DC component is detected by a folded cascode amplifier. A fixed voltage of VDD / 2 is given at one end of the amplifier by a resistor string. The two ends are compared and the amplifier outputs a voltage value, which is then passed to the output stage.

[0019] When there is no mismatch, the output stage has very low static power consumption. When a mismatch occurs in the circuit, the folded cascode amplifier transmits the voltage change to the output stage. The current generated by the output stage is fed back to the input of VGA to eliminate the mismatch. Through continuous adjustment, the final output is stabilized at VDD / 2, at which point the inverter has the best linearity.

[0020] Monte Carlo simulation can be used to determine the maximum VGA offset, thereby determining the size of the transconduct in the output stage of the offset cancellation circuit.

[0021] Compared with the prior art, the present invention has the following technical effects:

[0022] This invention discloses an offset cancellation circuit structure, which differs from existing offset cancellation circuit structures. It can correct both common-mode voltage and differential-mode offset, improving the reliability of circuit operation. The single-ended bias method stabilizes the output DC point at the optimal bias point, ensuring optimal linearity for the inverter-structured amplifier and thus meeting the overall circuit linearity requirements. The Class AB output stage significantly reduces quiescent power consumption, avoids wasted current in the transconductor, and offers much stronger driving capability than a standalone transconductor.

[0023] Furthermore, by utilizing a single-ended offset elimination loop, the operating point is clamped at the optimal bias point by the bias circuit, ensuring that the linearity of the inverter is improved without affecting the DC operating points of the preceding and following stages of the circuit.

[0024] Furthermore, two inverters connected end-to-end can convert two single-ended output signals into differential signals, increasing the output swing.

[0025] Furthermore, the advantage of using a folded cascode amplifier in a high-gain amplifier is that it can generate high gain with only one stage of amplification and introduces fewer poles.

[0026] Furthermore, the voltage bias circuit allows the offset correction loop to eventually correct the DC point to its set bias voltage, providing flexibility in the correction process.

[0027] Furthermore, the transconductor size of the Class AB output stage is related to the maximum mismatch generated by the circuit. The transconductor size can be reasonably selected according to the circuit mismatch, and an appropriate size can reduce the static power consumption of the output stage.

[0028] This invention discloses a method for eliminating DC offset in a circuit. An RC low-pass filter samples the output of VGA4 to obtain the common-mode point, which is then compared with a bias voltage VDD / 2. The input error is amplified by a folded cascode amplifier and connected to the input of the Class AB output stage. The bias voltage of the output stage transistors is then adjusted to control the current. The advantages of this method are that it can correct both differential-mode offset and flexibly adjust the output common-mode voltage according to circuit requirements, and the static power consumption is very low after the circuit stabilizes.

[0029] In summary, this invention can correct both differential-mode offset and common-mode voltage, while biasing at VDD / 2 ensures the linearity of the inverter. The Class AB output stage significantly reduces power consumption compared to a separate transconductor. Attached Figure Description

[0030] Figure 1 A schematic diagram of an existing imbalance elimination structure;

[0031] Figure 2 This is a schematic diagram of the imbalance elimination structure proposed in this invention;

[0032] Figure 3 This is a Monte Carlo simulation diagram proposed in this invention; Detailed Implementation

[0033] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0034] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0035] It should be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0036] It should also be further understood that the term "and / or" as used in this specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0037] The accompanying drawings illustrate various structural schematic diagrams according to embodiments disclosed in this invention. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0038] Please see Figure 2 This invention discloses an offset cancellation circuit, comprising an RC low-pass filter circuit, a voltage bias circuit, a high-gain amplifier, and a Class AB output stage. The low-pass filter circuit is used to sample the DC output point of the VGA. The DC offset cancellation circuit mainly eliminates offset and includes a low-pass filter circuit, a folded common-source common-gate amplifier, and a Class AB output stage. The voltage bias circuit is implemented by a series of resistors, and the DC bias point of the circuit can be freely set.

[0039] The offset cancellation circuit can eliminate differential offset while correcting common-mode voltage and ensure the best linearity of the inverter. The Class AB output stage also reduces power consumption.

[0040] Specifically, a low-frequency RC low-pass filter samples the VGA output, and through large filtering, an output waveform with almost no ripple is obtained. At this point, it can be considered that the common-mode value of the output waveform has been successfully sampled.

[0041] Specifically, the offset cancellation loop requires compensation for the path that generates the offset. The amplifier on the feedback path is a folded cascode amplifier with differential input and single-ended output. The offset cancellation loop amplifies the small deviation in the output and feeds it back to the input of VGA. VGA1 to VGAn amplify the deviation and output it. At the same time, it changes the DC point of the signal. After DC compensation by the offset unit, the common-mode value of the circuit output is finally changed.

[0042] Furthermore, the voltage bias circuit sets the bias point at VDD / 2, and the offset elimination loop continuously corrects the DC point of the offset path through negative feedback, ultimately stabilizing the output DC point at the position of VDD / 2.

[0043] Specifically, the RC low-pass filter and the folded cascode amplifier amplify the tiny voltage changes of the VGA, and then output the changed voltage value to the Class AB output stage. The output stage then converts the voltage change into current and feeds it back to the offset path, thereby completing the offset correction.

[0044] The issues that need to be considered in implementing this invention, namely the design method of the offset correction circuit, include the following steps:

[0045] S1. The output of VGA4 needs to be sampled through an RC low-pass filter to obtain an output common-mode point with very small ripple.

[0046] S2. The DC point of the Class AB output stage circuit is adjusted to operate in the subthreshold region to obtain the minimum static power consumption.

[0047] S3. The maximum offset of the VGA cascaded amplifier was determined by Monte Carlo simulation. The larger the size of the cross-conduit in the output stage of the offset cancellation circuit, the stronger its offset correction capability.

[0048] Specific connection relationships:

[0049] The input signals VIP and VIN are amplified to the outputs VON and VOP by an amplifier consisting of VGA1, VGA2, VGA3, and VGA4 connected in series. Then, they are converted into differential signals by three inverters connected end to end to the two single-ended outputs of VGA1, VGA2, and VGA3 respectively.

[0050] The RC low-pass filter circuit includes a resistor and a capacitor, one end of which is connected to the outputs VOP and VON, and the other end is connected to the input of a high-gain amplifier. The high-gain amplifier includes a differential input, single-ended output, folded cascode amplifier circuit. The other input of the high-gain amplifier is connected to a voltage bias circuit, which includes a resistor series and a voltage-regulating capacitor. The output of the high-gain amplifier is connected to the input of the Class AB output stage. The Class AB output stage includes a PMOS and NMOS transistor in parallel circuit and a PMOS and NMOS transistor in series output circuit. The output of the Class AB output stage is connected to the output of VGA1.

[0051] The specific working process of the offset cancellation circuit of the present invention is as follows:

[0052] Variable gain amplifiers with multi-stage inverter structures exhibit significant gain variations. At maximum gain, the multi-stage amplifier amplifies the offset introduced by each stage, eventually leading to offset problems and degrading circuit performance. Offset cancellation loops are used to eliminate this offset. A low-pass filter samples the output, and an amplifier amplifies the voltage difference, transmitting it to the output stage. The output stage converts the voltage change into current, feeding it back to the first stage output of the VGA. A voltage biasing circuit stabilizes the final DC point at VDD / 2, ensuring optimal linearity of the inverter.

[0053] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0054] Compared to existing offset cancellation circuit structures, the offset cancellation structure proposed in this invention is as follows: Figure 2 As shown in the comparison, it can be seen that the offset cancellation circuit can eliminate differential-mode offset while correcting the common-mode voltage, and ensure the best linearity of the inverter. The Class AB output stage also reduces power consumption.

[0055] Figure 3 The Monte Carlo simulation of the circuit is shown. The simulation results show that the output offset can be controlled within 10mV with 3σ after adopting the offset cancellation circuit proposed in this paper.

[0056] During operation, the VGA output is sampled using a low-pass filter circuit. The low-pass filter circuit consists of a large resistor and a small capacitor, which is a very low-frequency RC low-pass filter circuit. The output waveform is filtered to obtain the DC value.

[0057] To ensure the accuracy of the offset cancellation loop and achieve a high-gain loop, the amplifier has a high output impedance. Furthermore, to ensure loop stability, the high-gain amplifier is implemented using a single-stage folded cascode amplifier. Since the linear region of the inverter is very narrow, to ensure good linearity of the variable-gain amplifier with an inverter structure, a separate bias circuit is used to clamp the DC point of the inverter at VDD / 2. The offset cancellation circuit structure of this invention differs from existing offset cancellation circuit structures. Because existing structures cannot guarantee that the DC point of the VGA output is at VDD / 2, a single-ended bias method can be used to correct both common-mode voltage and differential-mode offset.

[0058] Since the power consumption of the offset cancellation loop mainly comes from the power consumption of the transconductor, in order to reduce the power consumption of the offset cancellation loop, the existing transconductor was replaced with a Class AB output stage. This not only reduces the static power consumption, but also increases the driving capability.

[0059] In summary, this invention provides an offset cancellation circuit structure that differs from existing offset cancellation circuit structures. It can correct both common-mode and differential-mode offsets, improving the reliability of the circuit operation. The single-ended bias method stabilizes the output DC point at the optimal bias point, ensuring the best linearity for the inverter and thus meeting the overall circuit linearity requirements. The Class AB output stage significantly reduces static power consumption, avoids current waste in the transconductor, and offers much stronger driving capability than a standalone transconductor.

[0060] The above content is only for illustrating the technical concept of the present invention and should not be construed as limiting the scope of protection of the present invention. Any modifications made to the technical solution based on the technical concept proposed in this invention shall fall within the scope of protection of the claims of this invention.

Claims

1. A DC offset cancellation circuit, characterized in that, It includes an offset cancellation module, an amplifier group, and an inverter structure; several inverter structures are connected between two amplifier groups, with one end of each amplifier group connected to the signal input terminal and the other end connected to the signal output terminal; an offset cancellation module is provided between the input and output terminals of each amplifier group; The offset cancellation module includes an RC low-pass filter circuit, a voltage bias circuit, a high-gain amplifier, and a Class AB output stage. One end of the RC low-pass filter circuit is connected to the output of the amplifier group, and the other end is connected to the input of the high-gain amplifier. The other input of the high-gain amplifier is connected to the voltage bias circuit. The output of the high-gain amplifier is connected to the input of the Class AB output stage, and the output of the Class AB output stage is connected to the amplifier group. A single-ended bias method is used to stabilize the output DC point at the optimal bias point, thereby achieving both common-mode voltage correction and differential-mode offset correction. The amplifier group includes amplifier VGA1, amplifier VGA2, amplifier VGA3 and amplifier VGA4; amplifier VGA1, amplifier VGA2, amplifier VGA3 and amplifier VGA4 are connected in series, the input terminal of amplifier VGA1 is connected to the signal input terminal, and the output terminal of amplifier VGA4 is connected to the signal input terminal. The inverter structure is connected between the output terminals of the two amplifiers VGA1, between the output terminals of the two amplifiers VGA2, and between the output terminals of the two amplifiers VGA3.

2. The DC offset cancellation circuit according to claim 1, characterized in that, The output of the Class AB output stage is connected to the output of amplifier VGA1 in the amplifier group.

3. The DC offset cancellation circuit according to claim 1, characterized in that, An inverter consists of two inverters connected end-to-end.

4. The DC offset cancellation circuit according to claim 1, characterized in that, The RC low-pass filter circuit consists of a resistor and a capacitor connected in series. One end is connected to the output of the amplifier group, and the other end is connected to the input of the high-gain amplifier.

5. The DC offset cancellation circuit according to claim 1, characterized in that, The high-gain amplifier is a folded cascode amplifier circuit with a differential input and single-ended output.

6. The DC offset cancellation circuit according to claim 1, characterized in that, The voltage bias circuit includes a resistor string and a voltage regulator capacitor, both of which are connected to the other input terminal of the high-gain amplifier. The voltage bias circuit clamps the output DC point to correct the common-mode voltage.

7. The DC offset cancellation circuit according to claim 1, characterized in that, The Class AB output stage consists of a circuit with a PMOS and an NMOS connected in parallel and an output circuit with a PMOS and an NMOS connected in series.

8. A method for eliminating DC offset using a DC offset elimination circuit, characterized in that, The DC offset cancellation circuit according to any one of claims 1 to 7 includes the following steps: The offset cancellation circuit detects the DC component output from both ends of the variable gain amplifier group based on the inverter structure. The detected DC component is converted into current by comparing with the bias voltage and fed back to the output of the first stage of the amplifier group VGA, thereby compensating for the output offset. The offset is eliminated through continuous feedback correction, so that the operating point of VGA is stabilized at the optimal bias point. At the same time, the differential mode of the circuit is corrected through the phase-locked module between the two branches. The DC component is detected by a folded cascode amplifier. A fixed voltage of VDD / 2 is given at one end of the amplifier by a resistor series. The two ends are compared and the amplifier outputs a voltage value and transmits it to the output stage. When there is no mismatch, the output stage has very low static power consumption. When a mismatch occurs in the circuit, the folded cascode amplifier transmits the voltage change to the output stage. The current generated by the output stage is fed back to the input of VGA to eliminate the mismatch. Through continuous adjustment, the final output is stabilized at VDD / 2, at which point the inverter has the best linearity. The maximum VGA offset was determined using Monte Carlo simulation, which in turn determined the size of the transconduct in the output stage of the offset cancellation circuit.

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