Self-aligned control circuit for offset cancellation calibration circuit for input buffer

Abstract

This invention discloses a self-alignment control circuit for an offset cancellation calibration circuit of an input buffer. By generating multiple timing control signals based on a start signal through a delay chain and outputting them to the offset cancellation calibration circuit, self-alignment of the timing control signals can be achieved without using a clock to synchronize the signals. This saves the area of ​​the clock circuit and avoids increased power consumption due to clock switching. Furthermore, self-alignment ensures that there are no timing margin issues.

Description

TECHNICAL FIELD

[0001] The present application relates to an input buffer of a semiconductor device, and more particularly to a self-aligned control circuit for an offset cancellation calibration circuit of an input buffer. BACKGROUND

[0002] In a semiconductor device having a dynamic random access memory (DRAM) or the like, an input buffer is used to compare a level of an input signal with a reference level to determine whether the level of the input signal is higher or lower than the reference level. However, device mismatches can affect the comparison result of the input buffer. For this reason, an offset cancellation calibration technique is proposed. The offset cancellation calibration technique is used to compensate for mismatches of devices on a differential pair.

[0003] Reference is made to Figure 1 and Figure 2 to explain the principle of the offset cancellation calibration of the input buffer. As shown in Figure 1 and Figure 2 , the input buffer includes switching elements P22, P27 and a plurality of compensation switching elements P23-P25, P28-P30 which receive a reference voltage signal VREFDQ and an input signal DQ_IN, respectively, and a clock signal CKb is input to a clock input terminal of the input buffer, and an output signal OUT is output from the input buffer.

[0004] As shown in Figure 1 , if the threshold voltage on the right side is higher than that on the left side, the compensation switching elements P28-P30 on the right side are turned on by using control codes CNT<2:0> (CNT<2> - CNT<0>) to obtain more current for the compensation switching element P27. Otherwise, as shown in Figure 2 , the compensation switching elements P23-P25 on the left side are turned on by using control codes CNT<5:3> (CNT<5> - CNT<3>) to obtain more current for the compensation switching element P22.

[0005] Figure 1 In the above, the threshold of the switching element P22 is lower than that of the switching element P27, and the current of the switching element P22 is greater than that of the switching element P27. If the threshold offset is greater than the maximum compensation, the control codes CNT<000> are locked at the initial time, and the output signal OUT is at a high level. If the threshold offset is less than the maximum compensation, the control codes CNT<2:0> are counted up by using a counter until the output signal OUT changes from the high level to the low level, and the control codes CNT<2:0> are locked in a register.

[0006] Figure 2In this case, the threshold value of the switching element P27 is lower than that of the switching element P22, and the current of the switching element P27 is greater than that of the switching element P22, so that the output signal OUT is initially at a low level. The control code CNT<5:3> is decreased from <111> to <000> to obtain more current, until the output signal OUT becomes at a high level, and the control code CNT<5:3> is locked in the register. If the threshold value offset is greater than the maximum compensation, the control code CNT<5:3> is locked at <000>.

[0007] Figure 3 The circuit structure of an example of the offset cancellation control circuit of the input buffer is shown in the figure. The clock input terminal of the input buffer 1 inputs the clock signal DQS_CKb, and during the offset cancellation calibration, the non-inverting input terminal and the inverting input terminal both input the reference level VREFDQ, and the output terminal outputs the signal DFS.

[0008] The offset cancellation calibration circuit 10 includes a counter 11, a D flip-flop 12, a D flip-flop 13, an XOR gate 14, an inverter 15, and a D flip-flop 16.

[0009] The counter 11 inputs a count signal CNT, and outputs a control code CNT<5:0> for controlling the above-mentioned plurality of compensation switching elements P23-P25, P28-P30 to the input buffer 1.

[0010] The data input terminal of the D flip-flop 12 inputs the output signal DFS of the input buffer 1, and the clock input terminal inputs a trigger signal DFS_trig.

[0011] The data input terminal of the D flip-flop 13 inputs the output signal DFS_0 of the D flip-flop 12, and the clock input terminal inputs the trigger signal DFS_trig.

[0012] The XOR gate 14 inputs the output signal DFS_1 of the D flip-flop 13 and the output signal DFS_0 of the D flip-flop 12. The inverter 15 inputs the output signal of the XOR gate 14.

[0013] The data input terminal of the D flip-flop 15 inputs the output signal c_flag of the inverter 15, the clock input terminal inputs a trigger signal f_trig, and the D flip-flop 15 outputs an output signal fix_flag. The output signal fix_flag becomes a completion signal when the calibration is completed.

[0014] In addition, the reset terminals RST of the counter 11, the D flip-flop 12, the D flip-flop 13, and the D flip-flop 16 input the same reset signal RSTb.

[0015] Figure 3In the offset cancellation calibration circuit 10 of the input buffer shown, the counter 11 counts up the control code CNT<5:0> until the compensation is completed. Initially, the control code CNT<5:0> is set to 111000b. If the output signal of the input buffer is high, it indicates that the maximum compensation is not enough for the switching element P27, and the control code CNT<5:0> stops at 111000b. Otherwise, the control code CNT<5:0> counts up until the output signal of the input buffer changes from low to high. Then, the control code is locked, and the compensation is completed. SUMMARY

[0016] Technical problem to be solved by the invention

[0017] However, in the above-mentioned offset cancellation calibration circuit of the input buffer, a clock is needed to synchronize the signals, and accordingly, the area of the clock circuit needs to be set. In addition, the clock switching causes dynamic current consumption, resulting in increased power consumption. Moreover, since multiple timing control signals are needed, there is a timing margin problem.

[0018] The present application is completed to solve the above-mentioned problems, and aims to provide a self-alignment control circuit for an offset cancellation calibration circuit of an input buffer, which does not need to use a clock to synchronize signals, and can realize self-alignment of timing control signals.

[0019] Technical solution to solve the technical problem

[0020] The present application provides a self-alignment control circuit for an offset cancellation calibration circuit of an input buffer for comparing the level of an input signal with a reference level, the offset cancellation calibration circuit for compensating for the mismatch of the input buffer on a differential pair, which is provided with multiple timing control signals, and outputs a completion signal when the calibration is completed, wherein the self-alignment control circuit inputs a start signal, generates the multiple timing control signals based on the start signal through a delay chain, and outputs to the offset cancellation calibration circuit, and terminates the operation by using the completion signal output by the offset cancellation calibration circuit.

[0021] Preferably, the input buffer is provided with multiple compensation switching elements, and the clock input end inputs a clock signal, and during the offset cancellation calibration, the same-phase input end and the inverse-phase input end both input the reference level,

[0022] Preferably, the offset cancellation calibration circuit comprises a counter which inputs a count signal and outputs a control code for controlling the plurality of compensation switching elements to the input buffer, a first D flip-flop which inputs the output signal of the input buffer to a data input terminal and inputs a first trigger signal to a clock input terminal, a second D flip-flop which inputs the output signal of the first D flip-flop to a data input terminal and inputs the first trigger signal to a clock input terminal, an XOR gate which inputs the output signal of the second D flip-flop and the output signal of the first D flip-flop, a first inverter which inputs the output signal of the XOR gate, and a third D flip-flop which inputs the output signal of the first inverter to a data input terminal, inputs a second trigger signal to a clock input terminal, and outputs the output signal as the completion signal, and the reset terminals of the counter, the first D flip-flop, the second D flip-flop, and the third D flip-flop input the same reset signal.

[0023] Preferably, the self-alignment control circuit comprises a second inverter which inputs the start signal, a third inverter which inputs the output signal of the second inverter, a first delay chain which inputs the output signal of the third inverter, a NAND gate which inputs the output signal of the third inverter and the output signal of the first delay chain, and outputs the output signal as the reset signal to the offset cancellation calibration circuit, a fourth inverter which inputs the output signal of the NAND gate, a first NOR gate which inputs the output signal of the fourth inverter to one input terminal, a fifth inverter which inputs the output signal of the first NOR gate, a second delay chain which inputs the output signal of the fifth inverter, a sixth inverter which inputs the output signal of the second delay chain, a second NOR gate which inputs the output signal of the sixth inverter and the completion signal, and outputs the output signal as the count signal to the counter of the offset cancellation calibration circuit, a third delay chain which inputs the output signal of the second NOR gate, and outputs the output signal as the clock signal to the input buffer, a fourth delay chain which inputs the output signal of the third delay chain, and outputs the output signal as the first trigger signal to the first D flip-flop and the second D flip-flop of the offset cancellation calibration circuit, and a fifth delay chain which inputs the output signal of the fourth delay chain, and inputs the output signal to the other input terminal of the first NOR gate, and outputs the output signal as the second trigger signal to the third D flip-flop of the offset cancellation calibration circuit.

[0024] Preferably, the first to fifth delay chains are each composed of a plurality of inverters.

[0025] Preferably, a third NOR gate and a seventh inverter are further connected in series before the second inverter, the seventh inverter is inputted with the start signal, and the third NOR gate is inputted with an output signal of the seventh inverter and the completion signal.

[0026] Preferably, the self-alignment control circuit is repeatedly used in a plurality of cycles during operation of the offset cancellation calibration circuit.

[0027] Technical effects

[0028] The self-alignment control circuit for the offset cancellation calibration circuit for an input buffer according to the present application generates a plurality of timing control signals based on a start signal through a delay chain and outputs them to the offset cancellation calibration circuit, thereby achieving self-alignment of the timing control signals without using a clock to synchronize the signals. Thus, the area of a clock circuit can be saved, and an increase in power consumption due to clock switching can be avoided. In addition, self-alignment can ensure that there is no timing margin problem. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figure 1 is a schematic diagram illustrating the principle of offset cancellation calibration of an input buffer.

[0030] Figure 2 is a schematic diagram illustrating the principle of offset cancellation calibration of an input buffer.

[0031] Figure 3 is a circuit configuration diagram showing an example of an offset cancellation control circuit for an input buffer.

[0032] Figure 4 is a circuit configuration diagram showing an example of a self-alignment control circuit for an offset cancellation calibration circuit for an input buffer according to an embodiment of the present application.

[0033] Figure 5 is a timing chart showing timing of self-alignment control generated by the self-alignment control circuit shown in Figure 4

[0034] Figure 6 is a circuit configuration diagram showing a modified example of a self-alignment control circuit for an offset cancellation calibration circuit for an input buffer according to an embodiment of the present application. DETAILED DESCRIPTION

[0035] ​The application is described more fully below with reference to the accompanying drawings, in which embodiments of the application are shown. The application may, however, be embodied in different ways, and should not be limited to the embodiments set forth herein. Unless otherwise defined, the terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terms should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0036] The application provides a self-alignment control circuit for an offset cancellation calibration circuit of an input buffer. The input buffer is used to compare the level of an input signal with a reference level. The offset cancellation calibration circuit is used to compensate for the mismatch of the input buffer on a differential pair, which is provided with a plurality of timing control signals, and outputs a completion signal when the calibration is completed. The offset cancellation calibration circuit may, for example, adopt the circuit structure shown in Figure 3

[0037] The self-alignment control circuit is configured to input a start signal, generate a plurality of timing control signals based on the start signal through a delay chain, and output to the above-mentioned offset cancellation calibration circuit, and terminate the operation by using the completion signal output by the offset cancellation calibration circuit.

[0038] <Embodiment>

[0039] Hereinafter, the circuit structure of an example of the self-alignment control circuit for the offset cancellation calibration circuit of the input buffer involved in the embodiment of the application will be described with reference to Figure 4 Figure 4 The offset cancellation calibration circuit in Figure 3 is configured to have the same circuit structure as shown in

[0040] As shown in Figure 4 , the self-alignment control circuit 20 is configured to include an inverter 201, an inverter 202, a delay chain 203, an NAND gate 204, an inverter 205, an NOR gate 206, an inverter 207, a delay chain 208, an inverter 209, an NOR gate 210, a delay chain 211, a delay chain 212, and a delay chain 213.

[0041] The inverter 201 is input with a start signal ZQ_ON. The inverter 202 is input with the output signal of the inverter 201.

[0042] ​​Delay chain 203 receives the output signal of inverter 202 as input. NAND gate 204 receives the output signal of inverter 202 and the output signal of delay chain 203 as input, and its output signal is output as a reset signal RSTb to the offset cancellation calibration circuit. Inverter 205 receives the output signal of NAND gate 204 as input.

[0043] One input of NOR gate 206 receives the output signal of inverter 205, and the other input receives the output signal of delay chain 213. Inverter 207 receives the output signal of NOR gate 206. Delay chain 208 receives the output signal of inverter 207. Inverter 209 receives the output signal of delay chain 208.

[0044] The input to NOR gate 210 is the output signal of inverter 209 and the completion signal fix_flag output by the offset cancellation calibration circuit, and its output signal is output as the counting signal CNT to the counter of the offset cancellation calibration circuit. The input to delay chain 211 is the output signal of NOR gate 210, and its output signal is output as the clock signal DQS_CKb to the input buffer.

[0045] Delay chain 212 receives the output signal of delay chain 211 as input, and its output signal is output as a trigger signal DFS_trig to D flip-flops 12 and 13 of the offset cancellation calibration circuit. Delay chain 213 receives the output signal of delay chain 212 as input, and its output signal is input to another input of NOR gate 206, and is output as a trigger signal f_trig to D flip-flop 16 of the offset cancellation calibration circuit.

[0046] Furthermore, the specific structure of delay chains 203, 208, 211 to 213 can be, for example, composed of multiple inverters, but is not limited to this; any circuit structure capable of implementing the delay function can be adopted.

[0047] Furthermore, the offset elimination calibration circuit can operate in multiple cycles, and the self-alignment control circuit 20 is reused in these cycles. Therefore, chip area can be saved through circuit reuse.

[0048] Figure 5 Demonstrates the use of Figure 4 The timing diagram shows the self-alignment control generated by the self-alignment control circuit. For example... Figure 5 As shown, multiple timing control signals are generated sequentially, and all signals are synchronized with the start signal to perform all actions in sequence. There is no timing margin problem in this design.

[0049] The self-alignment control circuit for the offset cancellation calibration circuit of the input buffer according to the present invention generates multiple timing control signals based on a start signal through a delay chain and outputs them to the offset cancellation calibration circuit, thereby achieving self-alignment of the timing control signals without the need for a clock to synchronize the signals. This saves the area of ​​the clock circuit and avoids increased power consumption due to clock switching. Furthermore, self-alignment ensures that there are no timing margin issues.

[0050] In addition, there is actually only one control signal in the entire circuit, namely the start signal. The timing requirements are met by a delay chain. The continuous actions during operation can be triggered and stopped using only this control signal.

[0051] Furthermore, since the operation is terminated by the completion signal output of the offset elimination calibration circuit, the circuit will automatically stop operating when calibration is complete.

[0052] The above description illustrates an example of a self-alignment control circuit for an offset elimination calibration circuit of an input buffer according to an embodiment of the present invention. However, the present invention is not limited thereto, and the circuit structure can be modified in various ways. For example, as Figure 6 As shown in the modified example, an NOR gate 214 and an inverter 215 are connected in sequence before the inverter 201. The inverter 215 receives a start signal ZQ_ON as input, and the NOR gate 214 receives the output signal of the inverter 215 and the completion signal fix_flag as input.

[0053] certainly, Figure 6 The modified example is merely one example, and other modifications to the circuit structure are possible within the scope of this invention.

[0054] This invention has been described in detail, but the above embodiments are merely examples of all embodiments, and this invention is not limited thereto. Within the scope of this invention, embodiments can be freely combined, any constituent elements of each embodiment can be modified, or any constituent elements of each embodiment can be omitted.

Claims

1. A self-alignment control circuit for an offset cancellation calibration circuit of an input buffer, the input buffer being used to compare a level of an input signal with a reference level, the offset cancellation calibration circuit being used to compensate for a mismatch of the input buffer on a differential pair, being provided with a plurality of timing control signals, and outputting a completion signal when calibration is completed, the self-alignment control circuit being characterized in that the self-alignment control circuit is inputted with a start signal, the plurality of timing control signals are generated based on the start signal through a delay chain, and outputted to the offset cancellation calibration circuit, a plurality of compensation switching elements are provided in the input buffer, and are inputted with a clock signal at a clock input end, and both a non-inverted input end and an inverted input end are inputted with the reference level during offset cancellation calibration, and the completion signal outputted by the offset cancellation calibration circuit is used to terminate operation.

2. The self-alignment control circuit for an offset cancellation calibration circuit of an input buffer according to claim 1, characterized in that the offset cancellation calibration circuit comprises: a counter, which is inputted with a count signal, and outputs a control code for controlling the plurality of compensation switching elements to the input buffer; a first D flip-flop, which is inputted with an output signal of the input buffer at a data input end, and is inputted with a first trigger signal at a clock input end; a second D flip-flop, which is inputted with an output signal of the first D flip-flop at a data input end, and is inputted with the first trigger signal at a clock input end; an exclusive OR gate, which is inputted with an output signal of the second D flip-flop and an output signal of the first D flip-flop; a first inverter, which is inputted with an output signal of the exclusive OR gate; and a third D flip-flop, which is inputted with an output signal of the first inverter at a data input end, and is inputted with a second trigger signal at a clock input end, and outputs an output signal of the third D flip-flop as the completion signal, the counter, the first D flip-flop, the second D flip-flop and the third D flip-flop are inputted with a same reset signal at a reset end.

3. The self-alignment control circuit for an offset cancellation calibration circuit of an input buffer according to claim 2, characterized in that the self-alignment control circuit comprises: a second inverter, which is inputted with the start signal; a third inverter, which is inputted with an output signal of the second inverter; a first delay chain, which is inputted with an output signal of the third inverter; a NAND gate, which is inputted with the output signal of the third inverter and an output signal of the first delay chain, and outputs an output signal of the NAND gate as the reset signal to the offset cancellation calibration circuit; a fourth inverter, which is inputted with the output signal of the NAND gate; a first NOR gate, which is inputted with an output signal of the fourth inverter at one input end; a fifth inverter, which is inputted with an output signal of the first NOR gate; a second delay chain, which is inputted with an output signal of the fifth inverter; and a sixth inverter, which is inputted with an output signal of the second delay chain. a sixth inverter, an output signal of the second delay chain being input to the sixth inverter; a second NOR gate, an output signal of the sixth inverter and the completion signal being input to the second NOR gate, and an output signal of the second NOR gate being output as the count signal to the counter of the offset cancellation calibration circuit; a third delay chain, an output signal of the second NOR gate being input to the third delay chain, and an output signal of the third delay chain being output as the clock signal to the input buffer; a fourth delay chain, an output signal of the third delay chain being input to the fourth delay chain, and an output signal of the fourth delay chain being output as the first trigger signal to the first D flip-flop and the second D flip-flop of the offset cancellation calibration circuit; and a fifth delay chain, an output signal of the fourth delay chain being input to the fifth delay chain, and an output signal of the fifth delay chain being input to another input terminal of the first NOR gate and being output as the second trigger signal to the third D flip-flop of the offset cancellation calibration circuit.

4. The self-alignment control circuit of the offset cancellation calibration circuit for an input buffer according to claim 3, wherein the first delay chain to the fifth delay chain are respectively composed of a plurality of inverters.

5. The self-alignment control circuit of the offset cancellation calibration circuit for an input buffer according to claim 3, wherein a third NOR gate and a seventh inverter are further connected in sequence before the second inverter, the seventh inverter inputs the start signal, the third NOR gate inputs an output signal of the seventh inverter and the completion signal.

6. The self-alignment control circuit of the offset cancellation calibration circuit for an input buffer according to claim 1, wherein there are a plurality of loops during operation of the offset cancellation calibration circuit, the self-alignment control circuit is repeatedly used in the plurality of loops.

Images