Timing optimization methods, devices, and computer-readable storage media for clock tree synthesis

Abstract

This invention discloses a timing optimization method, device, and computer-readable storage medium for clock tree synthesis, belonging to the field of chip design. Considering that analyzing each receive register individually can avoid register omissions, and that timing optimization based on the violation severity evaluation value of the receive registers can avoid omitting violation paths with high violation severity, this invention can determine the sum of the time margins of all violation paths containing the receive register for any receive register in the target chip, which is used as the violation severity evaluation value of the receive register. Then, the receive registers with violation paths are sorted in descending order of the absolute value of the violation severity evaluation value, and the violation paths of the receive registers are time-optimized according to the sorting. By sorting according to the violation severity evaluation value and optimizing one by one from the most severe to the least severe, the comprehensiveness of the optimization can be improved, thereby improving the timing optimization efficiency.

Description

Technical Field

[0001] This invention relates to the field of chip design, and in particular to a timing optimization method, apparatus, and computer-readable storage medium for clock tree synthesis. Background Technology

[0002] Clock tree synthesis is a core step in the chip physical design phase. Its goal is to build a low-skew, low-power clock network covering the entire chip, starting from the clock source and by inserting buffers, adjusting routing paths, and topology. After clock tree synthesis, some data transmission paths in the chip may have timing violations, so timing optimization is needed to fix them. However, there is a lack of mature timing optimization methods for clock tree synthesis. During timing optimization, some registers are easily overlooked, and it is impossible to optimize them perfectly in one go. Therefore, it may be necessary to perform repeated optimizations, which reduces work efficiency.

[0003] Therefore, how to provide a solution to the above-mentioned technical problems is a problem that needs to be solved by those skilled in the art. Summary of the Invention

[0004] The purpose of this invention is to provide a timing optimization method, device, and computer-readable storage medium for clock tree synthesis. In this invention, for any receive register in the target chip, the sum of the time margins of all violation paths containing the receive register can be determined as the violation severity evaluation value of the receive register. Then, the receive registers with violation paths are sorted in descending order of the absolute value of the violation severity evaluation value, and the violation paths of the receive registers are optimized according to the sorting. The violation severity evaluation value can be sorted and optimized one by one from severe to mild, which can improve the comprehensiveness of the optimization and thus improve the timing optimization efficiency.

[0005] To address the aforementioned technical problems, this invention provides a timing optimization method for clock tree synthesis, comprising:

[0006] After clock tree synthesis, for any receive register in the target chip, the sum of the time margins of each violation path containing the receive register is determined as the violation severity evaluation value of the receive register.

[0007] Sort the receive registers with violation paths in descending order of the absolute value of the violation severity assessment value;

[0008] Timing optimization is performed on the violation paths of each receive register that have violation paths, according to the order of the receive registers.

[0009] On the other hand, after clock tree synthesis, for any receive register in the target chip, the sum of the time margins of all violation paths containing the receive register is determined as the violation severity evaluation value of the receive register, including:

[0010] After clock tree synthesis, for any receive register in the target chip, each violation path containing the receive register is determined;

[0011] For any violation path in the receive register, the time margin of the timing constraints containing timing violations in the violation path is added together to obtain the path margin of the violation path; the timing constraints include setup time and hold time.

[0012] The path margins of each of the receive registers are summed to obtain the violation assessment value for the receive register.

[0013] On the other hand, after summing the time margins of timing constraints containing timing violations in any violation path of the receive register to obtain the path margin of the violation path, and before summing the path margins of each of the receive registers as the violation severity evaluation value of the receive register, the timing optimization method of clock tree synthesis further includes:

[0014] Sort the path margins of each violation path in descending order of absolute value;

[0015] Path margins that are greater than a preset first threshold will be removed.

[0016] On the other hand, after clock tree synthesis, for any receive register in the target chip, after determining each violation path containing the receive register, the timing optimization method of clock tree synthesis further includes:

[0017] Determine if there are any receive registers with excessive violation paths; excessive violation paths are defined as: the number of violation paths containing the receive register is greater than a preset third threshold.

[0018] If present, the information regarding the exceeded receive register for the violation path will be pushed to the user.

[0019] On the other hand, the timing optimization of the violation paths of each receive register with a violation path according to the order of the receive registers includes:

[0020] The receiving register that is not timing optimized and is the first in the sorted receiving registers is taken as the target register.

[0021] For any violation path of the target register, determine whether there are two timing constraints for the timing violation in the violation path; the timing constraints include setup time and hold time.

[0022] If there are not two types, then according to the type of timing constraint of the timing violation in the violation path, a virtual delay is added to the violation path so that timing optimization is performed on the violation path during the next clock tree synthesis.

[0023] If there are two types, timing optimization is performed by replacing the standard cells in the clock tree of the violation path;

[0024] Determine if there are any un-timing-optimized receive registers in the order of the receive registers;

[0025] If it does not exist, then the process ends;

[0026] If it exists, then perform the following steps: select the receive register that has not undergone timing optimization and is ranked first in the receive registers as the target register.

[0027] On the other hand, the timing optimization by replacing the standard cells in the clock tree of the violation path includes:

[0028] Determine whether the distance between the transmit register and the receive register in the violation path is greater than a preset second threshold;

[0029] If the distance is greater than the second threshold, the distance between the transmit register and the receive register in the violation path will be reduced to within the second threshold by the placement and routing instructions, and timing optimization will be performed by replacing the standard cell in the clock tree of the violation path.

[0030] If the delay is not greater than the second threshold, a positive virtual delay is added to the clock pin of the receive register of the violation path, and timing optimization is performed by replacing the standard cell in the clock tree of the violation path.

[0031] On the other hand, determining whether the distance between the transmit register and the receive register in the violation path is greater than a preset second threshold includes:

[0032] Determine the clock frequency of the violation path;

[0033] Based on the preset first correspondence, a second threshold corresponding to the clock frequency is determined;

[0034] Determine whether the distance between the transmit register and the receive register in the violation path is greater than a second threshold.

[0035] On the other hand, adding a virtual delay to the violation path based on the type of timing constraint of the timing violation present in the violation path includes:

[0036] If the timing constraint of the timing violation in the violation path is a setup time constraint, then a positive virtual delay is added to the clock pin of the issue register in the violation path.

[0037] If the timing constraint of a timing violation in the violation path is a hold-time constraint, a positive virtual delay is added to the clock pin of the receive register in the violation path.

[0038] To address the aforementioned technical problems, the present invention also provides a timing optimization device for clock tree synthesis, comprising:

[0039] Memory, used to store computer programs;

[0040] A processor, used to implement the timing optimization method of clock tree synthesis as described above when executing the computer program.

[0041] To address the aforementioned technical problems, the present invention also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the timing optimization method for clock tree synthesis as described above.

[0042] Beneficial Effects: This invention provides a timing optimization method based on clock tree synthesis. Considering that analyzing each receive register individually avoids register omissions, and that timing optimization based on the violation severity evaluation value of the receive registers avoids omitting violation paths with high violation severity, this invention can determine the sum of time margins of all violation paths containing the receive register for any receive register in the target chip, using this as the violation severity evaluation value of the receive register. Then, the receive registers with violation paths are sorted in descending order of the absolute value of the violation severity evaluation value, and timing optimization is performed on the violation paths of the receive registers according to the sorting. By sorting according to the violation severity evaluation value and optimizing one by one from the most severe to the least severe, the comprehensiveness of the optimization can be improved, thereby improving the timing optimization efficiency.

[0043] The present invention also provides a timing optimization device for clock tree synthesis and a computer-readable storage medium, which have the same beneficial effects as the timing optimization method for clock tree synthesis described above. Attached Figure Description

[0044] To more clearly illustrate the technical solutions in the embodiments of the present invention, the relevant technologies and the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0045] Figure 1 A flowchart illustrating a timing optimization method for clock tree synthesis provided by this invention;

[0046] Figure 2 A flowchart illustrating another timing optimization method for clock tree synthesis provided by the present invention;

[0047] Figure 3 A schematic diagram of the timing optimization device for clock tree synthesis provided by the present invention;

[0048] Figure 4 This is a schematic diagram of the structure of a computer-readable storage medium provided by the present invention. Detailed Implementation

[0049] The core of this invention is to provide a timing optimization method, device, and computer-readable storage medium for clock tree synthesis. In this invention, for any receive register in the target chip, the sum of the time margins of all violation paths containing the receive register can be determined as the violation severity evaluation value of the receive register. Then, the receive registers with violation paths are sorted in descending order of the absolute value of the violation severity evaluation value, and the violation paths of the receive registers are optimized according to the sorting. The violation severity evaluation value can be sorted and optimized one by one from severe to mild, which can improve the comprehensiveness of the optimization and thus improve the timing optimization efficiency.

[0050] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0051] Please refer to Figure 1 , Figure 1 This is a flowchart illustrating a timing optimization method for clock tree synthesis provided by the present invention. The timing optimization method for clock tree synthesis includes:

[0052] S101: After clock tree synthesis, for any receive register in the target chip, determine the sum of the time margins of each violation path containing the receive register, and use it as the violation severity evaluation value of the receive register.

[0053] Specifically, considering the technical problems mentioned above, and taking into account that analyzing each receive register individually can avoid register omissions, and that timing optimization based on the violation severity evaluation value of the receive registers can avoid omitting violation paths with severe violations, this embodiment of the invention aims to start with each receive register in the target chip, evaluate the violation severity evaluation value of each receive register, sort the receive registers, and then perform timing optimization on the violation paths according to the sorting. This allows for timing repair of each violation program from severe to mild, avoiding omissions and improving the timing optimization effect and efficiency.

[0054] In this embodiment of the invention, considering that the sum of the time margins of each violation path containing the receive register can accurately reflect the violation degree of a single receive register, the sum of the time margins of each violation path containing the receive register can be determined for any receive register in the target chip and used as the violation degree evaluation value of the receive register.

[0055] Additionally, it is worth mentioning that timing optimization can also be considered by traversing the transmit register, which is included within the concept of this invention.

[0056] S102: Sort the receive registers of the paths with violations in descending order of the absolute value of the violation severity assessment value;

[0057] Specifically, considering that the time margin of the violation path is negative, this step sorts the violation severity assessment values ​​after taking the absolute value.

[0058] S103: Perform timing optimization on the violation paths of each receive register that has a violation path according to the order of the receive registers.

[0059] Specifically, after sorting, this step can perform timing optimization on the violation paths of each receive register that have violation paths, according to the sorting of the receive registers.

[0060] This invention provides a timing optimization method based on clock tree synthesis. Considering that analyzing each receive register individually avoids register omissions, and that timing optimization based on the violation severity evaluation value of the receive registers avoids omitting violation paths with high violation severity, this invention determines the sum of time margins of all violation paths containing the receive register for any receive register in the target chip, using this as the violation severity evaluation value of the receive register. Then, the receive registers with violation paths are sorted in descending order of the absolute value of the violation severity evaluation value, and timing optimization is performed on the violation paths of the receive registers according to the sorting. By sorting according to the violation severity evaluation value and optimizing one by one from the most severe to the least severe, the comprehensiveness of the optimization can be improved, thereby improving the timing optimization efficiency.

[0061] Based on the above embodiments:

[0062] As an optional implementation, after clock tree synthesis, for any receive register in the target chip, the sum of the time margins of all violation paths containing the receive register is determined, and the violation severity evaluation value of the receive register includes:

[0063] After clock tree synthesis, for any receive register in the target chip, each violation path containing the receive register is determined;

[0064] For any violation path in the receive register, the time margin of the timing constraints containing timing violations in the violation path is added together to obtain the path margin of the violation path; the timing constraints include setup time and hold time.

[0065] The path margins of the receive registers are summed to obtain the violation assessment value for the receive register.

[0066] Specifically, considering the need to clarify the specific calculation rules for the violation severity assessment value to avoid distortion of the assessment value due to inconsistent calculation standards, which would affect the optimization priority judgment; and considering that timing constraints include two types: setup time and hold time, it is necessary to obtain the time margin under the corresponding timing constraints to ensure calculation accuracy. Based on this, this embodiment of the invention sets up a scheme to first determine each violation path of the receive register, then calculate the sum of the time margins of the timing constraints containing timing violations in each path as the path margin, and finally summarize all path margins to obtain the violation severity assessment value. This embodiment of the invention clarifies the calculation process and standards for the violation severity assessment value, ensuring that the assessment value can truly reflect the severity of violations in the receive register, providing a reliable basis for subsequent ranking optimization, and avoiding optimization priority confusion due to calculation deviations.

[0067] In one specific example, during the timing analysis of a high-end System-on-Chip (SoC) after clock tree synthesis, a receive register of the floating-point arithmetic module within the SoC was selected as the analysis object. The first step involved using timing analysis tools to identify six violation paths containing this receive register. The second step involved analyzing each violation path individually: if the path only had setup time violations, the setup time margin (Setup Slack) was taken as the path margin (e.g., if the setup Slack for a path was -0.8ns, the path margin was -0.8ns); if the path only had hold time violations, the hold time margin (Hold Slack) was taken as the path margin (e.g., if the hold Slack for a path was -0.6ns, the path margin was -0.6ns); if the path had both types of violations, the setup Slack and hold Slack were added together as the path margin (e.g., if the setup Slack for a path was -0.5ns and the hold Slack was -0.6ns). The Slack is -0.3ns, and the path margin is -0.8ns. In the third step, the path margins of the six paths (e.g., -0.8ns, -0.6ns, -0.8ns, -0.4ns, -0.3ns, and -0.2ns respectively) are added together to get -3.1ns, which is the violation assessment value of the receive register.

[0068] Of course, in addition to this specific form, "after clock tree synthesis, for any receive register in the target chip, determine the sum of the time margins of each violation path containing the receive register as the violation severity evaluation value of the receive register" can also be in other forms, and this embodiment of the invention does not limit it here.

[0069] As an optional embodiment, for any violation path of the receive register, after summing the time margins of the timing constraints containing timing violations in the violation path to obtain the path margin of the violation path, and before summing the path margins of the receive register as the violation severity evaluation value of the receive register, the timing optimization method of clock tree synthesis further includes:

[0070] Sort the path margins of each violation path in descending order of absolute value;

[0071] Path margins that are greater than a preset first threshold will be removed.

[0072] Specifically, considering that some violation paths have small absolute values ​​of path margin, belonging to minor violations, including them in the violation severity assessment might lead to interference with the assessment value, failing to accurately reflect the core violation situation of the receive register. Furthermore, retaining minor violations increases the optimization workload and reduces overall optimization efficiency. Therefore, this embodiment of the invention sorts the path margins of each violation path from largest to smallest absolute value, eliminating path margins with a sorted value greater than a preset first threshold. This eliminates the interference of minor violations on the assessment value, allowing the assessment value to focus more on serious violation paths; simultaneously, it reduces ineffective optimization work, concentrating resources on core violation repair, and improving optimization efficiency and accuracy.

[0073] As an optional embodiment, after clock tree synthesis, and for any receive register in the target chip, after determining all violation paths containing the receive register, the timing optimization method of clock tree synthesis further includes:

[0074] Determine if there are any receive registers with excessive violation paths; excessive violation paths are defined as: the number of violation paths containing receive registers is greater than a preset third threshold.

[0075] If present, the information regarding the exceeded receive register for the violation path will be pushed to the user.

[0076] Specifically, considering that an excessive number of violation paths associated with certain receive registers may reflect systemic problems in the logical link (such as associated transmit registers, wiring paths, etc.) where the receive register resides (e.g., unreasonable physical layout, insufficient driving capability, etc.). If these problems are not detected and addressed in a timely manner, they can easily lead to repeated optimizations. Therefore, this embodiment of the invention includes a scheme to determine whether there are receive registers with excessive violation paths (the number of violation paths exceeds a preset third threshold). If such a register exists, information about that receive register is pushed to the system. This allows for early identification of potential systemic problems, enabling designers to prioritize investigating the root cause of the problem through information pushes, preventing the problem from spreading and causing more violations, and reducing the workload and iterations required for subsequent optimizations.

[0077] As an optional embodiment, timing optimization of the violation paths of each receive register with a violation path according to the order of the receive registers includes:

[0078] The receiving register that is not timing optimized and is the first in the sorted receiving registers is taken as the target register.

[0079] S201: For any violation path of the target register, determine whether there are two timing constraints for timing violations in the violation path; timing constraints include setup time and hold time.

[0080] S202: If there are not two types, then according to the type of timing constraint of the timing violation in the violation path, add virtual delay in the violation path so that timing optimization can be performed on the violation path during the next clock tree synthesis.

[0081] If there are two types, timing optimization is performed by replacing the standard cells in the clock tree of the violation path;

[0082] Determine if there are any un-timing-optimized receive registers in the order of the receive registers;

[0083] If it does not exist, then the process ends;

[0084] If it exists, then perform the following steps: select the receive register that has not undergone timing optimization and is ranked first in the receive registers as the target register.

[0085] Specifically, for a better explanation of the embodiments of the present invention, please refer to... Figure 2 , Figure 2 This is a flowchart illustrating another timing optimization method for clock tree synthesis provided by the present invention.

[0086] Specifically, considering that timing violation constraints in violation paths may be of a single type (only setup time violation or only hold time violation) or two types (both setup time and hold time violations exist simultaneously), different types require different optimization strategies (a single type can be optimized by adding a virtual delay, while two types require replacing the standard cell); simultaneously, it is necessary to ensure that all receive registers with violation paths are optimized to avoid omissions. Based on this, this embodiment of the invention sets up a scheme to select target registers in order, determine the number of violation constraint types, select the corresponding optimization strategy, and iterate until all receive registers are optimized; this embodiment of the invention can improve the violation repair effect by accurately matching the optimization strategy with the violation type; the iterative advancement mechanism ensures that no receive register is missed, improves the comprehensiveness of optimization, and avoids introducing new timing problems due to inappropriate strategies.

[0087] One specific example is: in the timing optimization after clock tree synthesis of a certain artificial intelligence chip, the absolute values ​​of the violation evaluation values ​​are first sorted from largest to smallest, and the unoptimized and first-ranked receive register (belonging to the neural network calculation module, with an evaluation value of -3.5ns) is selected as the target register.

[0088] Analysis of each violation path for the target register: The first path only has setup time violations (no hold time violations), that is, the violation constraint type is 1. A positive virtual delay of 0.6ns is added to the clock pin of the launch register of this path so that the path can be optimized in the next clock tree synthesis; The second path has both setup time and hold time violations, that is, the violation constraint type is 2. The standard cell in the clock tree of this path is replaced with an ultra-low threshold voltage cell (ULVTCell) to reduce the path delay.

[0089] After optimizing the target register, determine if there are any unoptimized receive registers (if so, such as the receive register of the next-ranked storage interface module). If so, select the receive register as the new target register and repeat the above operation of "determining the violation constraint type - selecting the optimization strategy" until all receive registers with violation paths have been optimized.

[0090] Of course, in addition to this specific form, "performing timing optimization of the violation paths of each receive register with a violation path according to the order of the receive registers" can also be in other forms, and this embodiment of the invention does not limit it here.

[0091] As an optional embodiment, timing optimization by replacing standard cells in the clock tree of the violation path includes:

[0092] S203: Determine whether the distance between the transmit register and the receive register in the violation path is greater than a preset second threshold;

[0093] S204: If the distance is greater than the second threshold, the distance between the transmit register and the receive register in the violation path will be reduced to within the second threshold by the placement and routing instructions, and timing optimization will be performed by replacing the standard cell in the clock tree of the violation path.

[0094] S205: If it is not greater than the second threshold, add a positive virtual delay to the clock pin of the receive register of the violation path and perform timing optimization by replacing the standard cell in the clock tree of the violation path.

[0095] Specifically, considering that when both setup time and hold time violations exist simultaneously in a violation path, the distance between the transmit register and the receive register directly affects the path delay. If the distance is too large, simply replacing the standard unit is insufficient to effectively repair the violation; the distance must first be reduced. If the distance is small, virtual delay can be added to assist in optimization. Based on this, this embodiment of the invention sets a scheme to determine whether the distance between the transmit register and the receive register is greater than a preset second threshold. If it is greater, the distance is reduced and the standard unit is replaced; otherwise, virtual delay is added and the standard unit is replaced. This embodiment of the invention can adapt to different distance scenarios, improving the repair effect when both types of violations exist simultaneously. Furthermore, the combination of reducing the distance and replacing the standard unit can reduce the number of buffer insertions and lower the chip's dynamic power consumption.

[0096] Of course, in addition to this specific form, "time optimization by replacing standard cells in the clock tree of the violation path" can also take other forms, and this embodiment of the invention does not limit them here.

[0097] As an optional embodiment, determining whether the distance between the transmit register and the receive register in the violation path is greater than a preset second threshold includes:

[0098] Determine the clock frequency of the violation path;

[0099] Based on the preset first correspondence, a second threshold corresponding to the clock frequency is determined;

[0100] Determine whether the distance between the transmit register and the receive register in the violation path is greater than the second threshold.

[0101] Specifically, considering that different clock frequencies have different requirements for path delay (the higher the clock frequency, the smaller the allowed path delay, and the smaller the corresponding register distance threshold should be), using a fixed second threshold would lead to a mismatch between the threshold and actual needs, affecting the violation repair effect. Therefore, this embodiment of the invention sets up a scheme that first determines the clock frequency of the violation path, finds the corresponding second threshold according to a preset first correspondence, and then determines whether the register distance is greater than the threshold. In this embodiment, the second threshold is precisely matched with the clock frequency, ensuring the rationality of the distance judgment, thereby making the optimization strategy for the simultaneous existence of two violations more adaptable to the actual scenario and improving the effectiveness and stability of violation repair.

[0102] Of course, in addition to this specific form, "determining whether the distance between the transmit register and the receive register in the violation path is greater than a preset second threshold" can also be in other forms, and this embodiment of the invention does not limit it here.

[0103] As an optional implementation, adding a virtual delay to the violation path, based on the type of timing constraint of the timing violation present in the violation path, includes:

[0104] If the timing constraint of a timing violation in the violation path is a setup time constraint, then a positive virtual delay is added to the clock pin of the issue register in the violation path.

[0105] If the timing constraint of a timing violation in the violation path is a hold-time constraint, then a positive virtual delay is added to the clock pin of the receive register in the violation path.

[0106] Specifically, considering that the core influencing factor for setup time violations is the transmitter delay (T_launch, LaunchDelay), and the core influencing factor for hold time violations is the receiver delay (T_capture, CaptureDelay), if the virtual delay is added at the wrong location (e.g., adding a setup time violation to the receiver), the corresponding timing margin cannot be effectively improved. Based on this, this embodiment of the invention designs a scheme to add a virtual delay to the transmitter register clock pin for setup time violations and to add a virtual delay to the receiver register clock pin for hold time violations. This ensures that the virtual delay addition location precisely matches the violation type, quickly reducing the corresponding delay (T_launch or T_capture), effectively improving setup time margin or hold time margin, while avoiding automatic buffer insertion by tools, reducing chip power consumption and area footprint.

[0107] One specific example is: in the timing optimization after clock tree synthesis of a consumer electronics chip (such as a smartphone SoC), path analysis is performed for paths with a single violation type:

[0108] The first path only had a setup time violation. Timing tools calculated its setup time margin (SetupSlack) to be -0.5ns, the core reason being excessive transmitter latency (T_launch). Based on the violation type, a positive virtual delay of 0.5ns was added to the transmitter register clock pin of this path, reducing T_launch and thus increasing Setup Slack to above 0ns, fixing the setup time violation.

[0109] The second path only has a hold-time violation, with a hold-slack of -0.3ns. The core reason is excessive receiver latency (T_capture). Based on the violation type, a positive virtual delay of 0.3ns is added to the receive register clock pin of this path to reduce T_capture, thereby increasing the hold-slack to above 0ns and correcting the hold-time violation.

[0110] Additionally, as an optional implementation, the timing optimization method for clock tree synthesis also includes:

[0111] From each receive register with a violation path, the receive registers that meet the preset conditions are used to form the target register set. The preset conditions are: they belong to the same functional logic module of the target chip, belong to the same clock source, and each violation path has a single violation timing constraint.

[0112] For the functional logic module to which the target register set belongs and the clock source, all registers except the target register set are uniformly given a virtual delay (the same virtual delay as the target register set) to prevent other registers under the same functional logic module and the same clock source from having the same type of timing violation in batches after clock tree synthesis.

[0113] Specifically, considering that registers under the same functional logic module and the same clock source have similar timing characteristics (such as delay characteristics and layout environment), if some registers exhibit a single type of violation, other registers may exhibit the same type of violation in batches after the next clock tree synthesis, leading to repeated optimizations. Based on this, this embodiment of the invention sets up a target set by selecting receive registers that meet preset conditions, and uniformly adding the same virtual delay to other registers under the same clock source within the same module. This can prevent batch violations of other registers under the same clock source within the same module in advance, reduce the optimization workload after the next clock tree synthesis, avoid repeated iterations, and shorten the chip design cycle.

[0114] Specifically, in one embodiment, during timing optimization after clock tree synthesis of a server chip, the following applies to the chip's PCIe (Peripheral Component Interconnect Express) controller module (functional logic module):

[0115] The first step is to select receive registers that meet preset conditions from the receive registers with violation paths (belonging to the PCIe controller module, belonging to the same clock source (250MHz), and all violation paths being a single hold-time violation) to form a target register set; the receive registers in this set all have a positive virtual delay of 0.2ns added to the clock pin to fix the violation.

[0116] The second step involves adding a positive virtual delay of 0.2ns to the clock pins of the 35 registers (excluding the target register set, which did not exhibit violations but had similar timing characteristics) under the PCIe controller module and the 250MHz clock source, to prevent these registers from exhibiting hold-time violations in batches after the next clock tree synthesis.

[0117] Please refer to Figure 3 , Figure 3This is a schematic diagram of a timing optimization device for clock tree synthesis provided by the present invention. The timing optimization device for clock tree synthesis includes:

[0118] Memory 31 is used to store computer programs;

[0119] The processor 32 is used to implement the timing optimization method of clock tree synthesis as described in the foregoing embodiments when executing a computer program.

[0120] For a description of the timing optimization device for clock tree synthesis provided in this embodiment of the invention, please refer to the aforementioned embodiment of the timing optimization method for clock tree synthesis. This embodiment of the invention will not be repeated here.

[0121] Please refer to Figure 4 , Figure 4 This is a schematic diagram of a computer-readable storage medium provided by the present invention. The computer-readable storage medium 41 stores a computer program 42. When the computer program 42 is executed by the processor, it implements the steps of the timing optimization method of clock tree synthesis as described in the previous embodiment.

[0122] For a description of the computer-readable storage medium provided in the embodiments of the present invention, please refer to the aforementioned embodiments of the timing optimization method for clock tree synthesis. The embodiments of the present invention will not be repeated here.

[0123] The present invention also provides a computer program product, including a computer program / instruction that, when executed by a processor, implements the timing optimization method of clock tree synthesis as described in the foregoing embodiments.

[0124] For a description of the computer program product provided in the embodiments of the present invention, please refer to the aforementioned embodiments of the timing optimization method for clock tree synthesis. The embodiments of the present invention will not be repeated here.

[0125] The various embodiments described in this specification are presented in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. It should also be noted that in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0126] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for timing optimization of clock tree synthesis, the method comprising: The method comprises the following steps: After clock tree synthesis, for any receiving register in a target chip, the sum of time margins of each violation path containing the receiving register is determined as a violation degree evaluation value of the receiving register; According to the order of violation degree evaluation value from large to small, each receiving register with a violation path is sorted; The receiving register which is not subjected to timing optimization and is at the top of the sorted receiving registers is taken as a target register; For any violation path of the target register, it is judged whether the timing constraints with timing violations in the violation path are two kinds or not; the timing constraints include setup time and hold time; If not, according to the type of the timing constraints with timing violations in the violation path, a virtual delay is added in the violation path so as to perform timing optimization on the violation path in the next clock tree synthesis; If yes, it is judged whether the distance between the transmitting register and the receiving register in the violation path is greater than a preset second threshold value or not; If yes, the distance between the transmitting register and the receiving register in the violation path is shortened to within the second threshold value through layout and routing instructions, and timing optimization is performed by replacing standard cells in the clock tree of the violation path; If not, a positive virtual delay is added at the clock pin of the receiving register of the violation path, and timing optimization is performed by replacing standard cells in the clock tree of the violation path; It is judged whether there is a receiving register which is not subjected to timing optimization in the sorted receiving registers or not; If not, the process is ended; If yes, the receiving register which is not subjected to timing optimization and is at the top of the sorted receiving registers is taken as a target register; The adding of the virtual delay in the violation path according to the type of the timing constraints with timing violations in the violation path comprises the following steps: If the timing constraints with timing violations in the violation path are setup time constraints, a positive virtual delay is added at the clock pin of the transmitting register in the violation path; If the timing constraints with timing violations in the violation path are hold time constraints, a positive virtual delay is added at the clock pin of the receiving register in the violation path.

2. The clock tree synthesis timing optimization method of claim 1, wherein, The determining of the sum of time margins of each violation path containing the receiving register as the violation degree evaluation value of the receiving register after the clock tree synthesis comprises the following steps: After clock tree synthesis, for any receiving register in a target chip, each violation path containing the receiving register is determined; For any violation path of the receiving register, the time margins of the timing constraints with timing violations in the violation path are added to obtain a path margin of the violation path; the timing constraints include setup time and hold time; The sum of each path margin of the receiving register is added as the violation degree evaluation value of the receiving register.

3. The clock tree synthesis timing optimization method of claim 2, wherein, Before the step of adding up the path slack of each of the receiving registers as the violation degree evaluation value of the receiving register, the clock tree synthesis timing optimization method further comprises: sorting the path slacks of the violation paths in descending order of absolute value; eliminating the path slacks greater than the first threshold value.

4. The clock tree synthesis timing optimization method of claim 2, wherein, Before the step of determining each violation path containing the receiving register in the target chip after the clock tree synthesis, the clock tree synthesis timing optimization method further comprises: determining whether there is a receiving register with a violation path exceeding a threshold value; the violation path exceeding the threshold value is that the number of violation paths containing the receiving register is greater than a third threshold value; if there is, pushing the information of the receiving register with the violation path exceeding the threshold value to a user.

5. The method of claim 1, wherein, The step of determining whether the distance between the transmitting register and the receiving register in the violation path is greater than the second threshold value comprises: determining the clock frequency of the violation path; determining the second threshold value corresponding to the clock frequency according to a first correspondence relationship; determining whether the distance between the transmitting register and the receiving register in the violation path is greater than the second threshold value.

6. A clock tree synthesis timing optimization apparatus, comprising: comprises: a memory for storing a computer program; a processor for executing the computer program to implement the steps of the clock tree synthesis timing optimization method according to any one of claims 1 to 5.

7. A computer-readable storage medium, characterized in that, The computer program is stored on the computer readable storage medium and is executed by the processor to implement the steps of the clock tree synthesis timing optimization method according to any one of claims 1 to 5.

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