Parallel digital bus adaptive clock phase calibration system and method
By using a parallel digital bus adaptive clock phase calibration system, the quality of the parallel bus signal is automatically identified and the common safety window is calculated, which solves the problem of manual adaptation of TDDI chips in mass production and achieves low-cost, high-precision hardware adaptation and improved stability.
Patent Information
- Application Number
- CN202511981945.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-25
- Publication Date
- 2026-03-20
AI Technical Summary
Existing technologies cannot automatically adapt to different customers and motherboards of different materials in TDDI chips, resulting in chaotic mass production version management, high error rate, and time-consuming, labor-intensive, and costly traditional manual adjustments.
A parallel digital bus adaptive clock phase calibration system is adopted, including a calibration control module, a test mode generation module, a high-speed oversampling module, a timing analysis engine, and a clock phase adjustment module. It achieves full hardware adaptive adaptation by automatically identifying the quality of parallel bus signals and calculating the common safety window of parallel channels.
It achieves full hardware adaptive adaptation at the chip level, reducing mass production testing costs and supply chain management difficulties, improving circuit stability and signal integrity in different environments, and reducing bit error rate.
Smart Images
Figure CN121705233A_ABST
Abstract
Description
Technical Field
[0001] This invention discloses a parallel digital bus adaptive clock phase calibration system and method, which relates to the field of integrated circuit interface technology. Background Technology
[0002] As display resolution and refresh rates continue to increase, system clock frequencies also rise, drastically shrinking the "data validity window" for parallel data transmission. In practical applications, especially for Touch and Display Driver Integration (TDDI) chips, this presents severe timing challenges. On one hand, it's difficult to achieve strictly equal trace lengths on printed circuit boards (PCBs) or flexible printed circuit boards (FPCs), leading to significant signal offsets between multiple data lines. On the other hand, impedance discontinuities introduced by long-distance transmission, vias, and connectors can cause signal overshoot, ringing, and inter-symbol interference, further deteriorating signal integrity. Furthermore, dynamic changes in process technology, voltage, and temperature can also cause drift in internal chip delays.
[0003] Existing solutions typically rely on strict PCB length matching or fixed delay compensation, which not only increases manufacturing costs but also fails to adapt to dynamic environmental changes. More seriously, in the mass production application of TDDI chips, due to the need to adapt to different customers, motherboards of different materials and lengths, engineers often need to manually adjust the clock phase register for each combination. This manual trial-and-error approach is not only time-consuming and labor-intensive but also makes it difficult to guarantee finding the optimal sampling point under all operating conditions, leading to chaotic mass production version management and a high risk of bit error rate.
[0004] Therefore, the industry urgently needs an adaptive calibration scheme that can automatically analyze signal quality (such as eye diagram features) and calculate the common safety window of all parallel channels without human intervention, in order to solve the above-mentioned technical bottlenecks. Summary of the Invention
[0005] In view of this, one of the objectives of the present invention is to provide a parallel digital bus adaptive clock phase calibration system to solve the problems mentioned in the background art.
[0006] The second objective of this invention is to provide a method for calibration using the aforementioned parallel digital bus adaptive clock phase calibration system.
[0007] To achieve the aforementioned first objective, the present invention provides a parallel digital bus adaptive clock phase calibration system, comprising: a calibration control module for coordinating the initiation and state switching of the calibration process; a test mode generation and request module configured to provide a predetermined test data sequence to the parallel digital bus; a high-speed oversampling module connected to the parallel digital bus, configured to asynchronously oversample each data line in the parallel bus using a sampling clock with a frequency N times the data transmission clock frequency to obtain sampled data streams within multiple unit intervals, where N is an integer greater than or equal to 32; a timing analysis engine connected to the high-speed oversampling module, configured to perform bit alignment on the sampled data streams and reconstruct the digital eye diagram of each data line by superimposing an average; the timing analysis engine is further configured to identify the stable region of each data line based on the digital eye diagram and calculate the intersection of the stable regions of all data lines to obtain a common safety window; and a clock phase adjustment module configured to receive the center position parameter of the common safety window calculated by the timing analysis engine and convert it into a control code to adjust the phase of the data transmission clock.
[0008] Based on the above solution, we can see that the parallel digital bus adaptive clock phase calibration system provided by this invention solves the technical problems of poor hardware compatibility and the need for manual adaptation of different motherboards in the mass production of existing display driver chips, and achieves the following technical effects:
[0009] 1. Achieved chip-level full hardware adaptive adaptation: By integrating a "calibration control module" and a "test mode generation module," the system possesses self-testing capabilities that do not rely on external test equipment (such as oscilloscopes or logic analyzers). This enables the TDDI / DDIC chip to automatically identify and adapt to FPC cables of different customers, lengths, and impedance characteristics, eliminating the tedious process of manually adjusting registers and significantly reducing mass production testing costs and supply chain management difficulties.
[0010] 2. Low-cost, high-precision hardware architecture: The system adopts an architecture combining a "high-speed oversampling module" with "digital logic analysis," replacing the traditional complex analog phase-locked loop (PLL) or clock data recovery (CDR) circuits to achieve phase alignment. This fully digital implementation not only reduces the design difficulty and chip area of analog circuits but also avoids the susceptibility of analog circuits to PVT (process, voltage, temperature) effects, improving the stability of the circuit under different operating environments.
[0011] To achieve the second objective mentioned above, the present invention provides a parallel digital bus adaptive clock phase calibration method, comprising the following steps:
[0012] Step S1: Enter calibration mode and send a predefined test mode sequence to the parallel digital bus;
[0013] Step S2: Oversample all data lines of the parallel bus using a high-speed clock with a frequency N times the data rate to capture a data snapshot;
[0014] Step S3: Align the data snapshots based on the test pattern sequence, and reconstruct the digital eye diagram of each data line by statistically superimposing multiple periods of data;
[0015] Step S4: Analyze the digital eye diagram of each data line to identify its respective effective stable range;
[0016] Step S5: Calculate the intersection of the effective stable intervals of all data lines to determine the common safety window;
[0017] Step S6: Calculate the center point of the public safety window and adjust the phase of the data sampling clock to the center point position.
[0018] Based on the above scheme, we can see that the parallel digital bus adaptive clock phase calibration method provided by this invention solves the problems of traditional DDR-type scanning algorithms being unable to identify signal quality and having a high bit error rate under poor channel conditions, and achieves the following technical effects:
[0019] 1. Signal Quality Perspective Based on Digital Eye Diagram: Steps S3-S4 of this method reconstruct the digital eye diagram through statistical superposition, enabling the system to "see" the waveform quality of the signal (such as overshoot, ringing, and noise). Compared with the traditional scanning method that only detects "on / off" states, this method can actively eliminate sampling regions that are correct in level but unstable at the edge. Thus, in channels with severe inter-symbol interference (ISI) or reflections, it can find truly robust sampling points, greatly reducing the bit error rate in long-term operation.
[0020] 2. Maximizing Globally Optimal Timing Margin: By executing the algorithm of "intersection of stable intervals of all data lines" in steps S5-S6, this method can accurately calculate the common safety window covering all parallel channels. Locking the sampling phase at the geometric center of this window mathematically ensures that each data line in the parallel bus can obtain the maximum setup and hold time margin under the current physical conditions, effectively overcoming the clock skew problem caused by unequal PCB trace lengths. Attached Figure Description
[0021] Figure 1 This is a schematic diagram of the module composition and data flow of the parallel digital bus adaptive clock phase calibration system according to an embodiment of the present invention;
[0022] Figure 2 This is a flowchart illustrating the parallel digital bus adaptive clock phase calibration method according to an embodiment of the present invention.
[0023] Figure 3 This is a schematic diagram of the digital eye diagram reconstruction and public safety window calculation principle described in the embodiment of the present invention, wherein (a) represents the oversampling point distribution of a single data line, (b) represents the reconstructed digital eye diagram and stable region, and (c) represents the intersection of the stable regions of multiple data lines and the calculation of the optimal phase center point;
[0024] Figure 4 This is a schematic diagram comparing the clock and data phase waveforms before and after calibration in a practical application of an embodiment of the present invention.
[0025] The correspondence between the labels and component names in the attached figures is as follows:
[0026] 1. Calibration control module; 2. Test mode generation and request module; 3. High-speed oversampling module; 4. Timing analysis engine; 5. Clock phase adjustment module; 6. Configuration and status register module. Detailed Implementation
[0027] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0028] I. Parallel Digital Bus Adaptive Clock Phase Calibration System
[0029] like Figure 1 As shown, in one embodiment of the parallel digital bus adaptive clock phase calibration system provided by this invention, the system is integrated into the physical layer interface circuit of the receiving chip (e.g., the display driver chip DDIC or the touch and display integrated chip TDDI). The system mainly consists of the following six core modules, forming a closed-loop automatic calibration architecture:
[0030] 1. Calibration Control Module 1
[0031] This module serves as the "command center" of the entire system and is typically implemented using a finite state machine (FSM). It is responsible for initiating the calibration process in response to external commands (such as power-on reset, software register triggers, or timer triggers). It coordinates the timing of various submodules; for example, when starting calibration, it notifies the test mode generation module to send a specific pattern while simultaneously enabling the high-speed oversampling module. Furthermore, it monitors the calibration status and executes pre-defined exception handling logic (such as degraded operation or triggering an interrupt) when a "calibration failure" or "timeout" signal is detected.
[0032] 2. Test Mode Generation and Request Module 2
[0033] For accurate channel analysis, the receiver needs a known data sequence. This module is configured to generate or request a pre-defined test data sequence from the sender (Host).
[0034] In this embodiment, the supported test modes include: a checkerboard sequence of alternating 0s and 1s (used to test the attenuation of the highest frequency signal), a pseudo-random binary sequence (PRBS) (used to simulate a wide-spectrum real data stream to stimulate inter-symbol interference), and a sequence of all 0s or all 1s.
[0035] This module ensures that all data lines on the parallel bus transmit a defined signal during calibration, providing a reference for subsequent bit alignment.
[0036] 3. High-speed oversampling module
[0037] This is the sensing front end of the system. It is connected to each data line of the parallel digital bus (e.g., D0-D23 of the RGB interface).
[0038] Sampling Mechanism: This module utilizes an internal high-speed sampling clock with a frequency much higher than the data transmission clock frequency for asynchronous sampling. According to a preferred embodiment of the invention, the sampling rate N is set to 32 or 64 (i.e., ...). For example, if the data rate is 100 Mbps, the sampling clock can be configured to 3.2 GHz or 6.4 GHz.
[0039] Function: Within a data unit interval (UI), this module captures N sampling points, thereby discretizing a continuous analog signal waveform into a high-precision digital sequence stream. These raw sampled data are temporarily stored in a FIFO buffer with a depth sufficient to cover multiple UIs.
[0040] 4. Time Series Analysis Engine 4
[0041] This is the core computing unit of the system, responsible for processing sampled data and making decisions. Its internal logic comprises three processing stages:
[0042] Bit alignment and digital eye diagram reconstruction: The engine first searches for a predefined test pattern header in the sampling stream to achieve coarse bit-level alignment. Then, it constructs the digital eye diagram using a "superimposed averaging" algorithm (see [link to principle]). Figure 3(b) Specifically, it overlaps the data segments of multiple aligned UIs on the time axis and counts the probability of the signal being "high" or "low" at each sampling phase point from 0 to N-1. For example, if the 5th sampling point is "1" 99 times and "0" 1 time out of 100 counts, the signal quality at that point is considered excellent; if it is "1" 50 times and "0" 50 times, then that point is in the jitter zone of signal transition.
[0043] Stable Region Identification: Based on the statistical view described above, the engine identifies the stable region of the signal for each data line i. The stable region is defined as a continuous sampling interval where the bit error rate is below a specific threshold (e.g., 0), denoted as [ , ].
[0044] Public safety window calculation: The engine performs logical operations to find the timing intersection of all parallel data lines (see principle). Figure 3 (c)). The calculation formula is as follows:
[0045] ;
[0046]
[0047] Where k is the total number of data lines. The intersection interval [ , This is a public window that is safe for all data cables.
[0048] 5. Clock phase adjustment module 5
[0049] This module performs physical-level adjustments based on the output of the timing analysis engine 4.
[0050] Center point calculation: First, calculate the center position of the common window. .
[0051] Hardware Execution: This module incorporates a programmable delay line, selected from either a digitally controlled delay line (DCDL) or a voltage-controlled delay line (VCDL). The control logic will calculate... The control word is mapped to a delay line, thereby precisely shifting the phase of the data sampling clock at the receiving end to that optimal moment.
[0052] 6. Configuration and Status Register Module 6
[0053] It provides an interface between the system and an external MCU or master controller for storing configurations such as oversampling factor N and test mode type, and provides calibration completion flags and result status.
[0054] II. Adaptive Calibration Method Flow
[0055] Based on the above embodiments, the present invention also provides an adaptive calibration method flow, combined with Figure 2 This embodiment will describe in detail the specific steps of calibration using the above system:
[0056] Step S1: System Initialization and Startup
[0057] When the system powers on or detects an environmental change (such as a drastic temperature fluctuation), calibration control module 1 is activated. At this time, the system suspends normal data reception and enters calibration mode.
[0058] Step S2: Test mode injection
[0059] The transmitting end begins sending a preset test sequence (such as a checkerboard pattern of 0x55AA) on the parallel bus. The receiving end waits for the signal to stabilize.
[0060] Step S3: Asynchronous oversampling across all channels
[0061] High-speed oversampling module 3 is activated, blindly sampling all parallel data lines at a frequency of 64 times (or N times) the data rate. The system captures data snapshots for several consecutive cycles. Clock recovery is not performed at this time; only data acquisition is conducted. See also Figure 3 (a) shows the discrete oversampling points of a single data line on the time axis.
[0062] Step S4: Digital Eye Reconstruction
[0063] The time series analysis engine 4 reads snapshot data.
[0064] Alignment: Based on the known pattern features, find the boundary of each cycle.
[0065] Superposition: Superimpose data from different periods by normalizing them according to their phase points.
[0066] Statistics: such as Figure 3 As shown in (b), the system constructs a digital eye diagram for each data line. The diagram clearly shows which phase points are stable "eye-open" regions (stable regions A / B) and which are "eye-closed" regions (jump edges) where overshoot, ringing, or jitter occurs.
[0067] Step S5: Extracting the effective window of a single channel
[0068] For each data line (e.g., D0, D1, ... D23), the system sets a threshold (e.g., 5 consecutive sampling points with constant levels consistent with the expected value). The interval that meets the condition is the effective window of that channel. , ].
[0069] Note: Due to the different PCB trace lengths, the window for D0 may be [5ns, 8ns], while the window for D1 may be [6ns, 9ns].
[0070] Step S6: Calculation and Judgment of Public Security Window
[0071] The system calculates the intersection of all channel windows. Based on the formula: .like Figure 3 As shown in (c), the dark area represents the common safety window for all passageways.
[0072] Error handling: The system will perform verification during the calculation process. If the calculation result displays... If the intersection does not exist or the length is negative, it indicates that the signal is too tilted or jittery, making it impossible to find a unified sampling point. In this case, the system determines that the calibration has failed and writes an error code to the register, triggering degraded operation (such as reducing the bus frequency) or an error alarm, instead of blindly applying incorrect phase parameters.
[0073] Step S7: Phase Implementation and Verification
[0074] If calibration is successful, the system calculates the midpoint of the common window ( Figure 3 (c) The circle is converted into DCDL configuration parameters. Clock phase adjustment module 5 updates the phase of the sampling clock. Subsequently, the system can selectively perform a quick verification to confirm that the bit error rate is 0. Figure 4 shows a comparison of the effects before and after calibration:
[0075] Before calibration ( Figure 4 Below): The rising edge of the original CLK is located near the transition edge of the data DATA ("dangerous" area), which is very prone to generating bit errors.
[0076] After calibration ( Figure 4 Above): After calibration by the present invention, the rising edge of CLK is precisely adjusted to the center position of the DATA valid window ("safe" area), ensuring sufficient setup time and hold time margin.
[0077] Step S8: Exit and Resume
[0078] Once calibration is complete, bus control is released, and the system returns to normal image or data transmission mode.
[0079] III. Applications in TDDI Chips
[0080] This invention is particularly applicable to Touch and Display Driver Integration (TDDI) chips. In practical applications, TDDI chips need to be adapted to different glass panels and flexible printed circuit boards (FPCs) from multiple customers. The length and impedance control capabilities of FPCs vary significantly between different customers. Previously, engineers had to manually adjust the phase register for each module, which was time-consuming, labor-intensive, and prone to errors. With this invention, the TDDI chip automatically executes the S1-S8 process described above during the power-on initialization phase. Regardless of the FPC cable length, the chip can see the actual signal quality reaching the chip pins through "oversampling-eye diagram reconstruction" and automatically calculate the optimal sampling point that simultaneously meets the setup / hold time requirements of all data lines (RGB or SPI interface). This allows the same firmware version to be compatible with modules of different quality, greatly reducing mass production testing costs and supply chain management difficulties.
[0081] The above description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.
Claims
1. A parallel digital bus adaptive clock phase calibration system, characterized in that, include: The calibration control module is used to coordinate the initiation and state switching of the calibration process; The test mode generation and request module is configured to provide a predetermined sequence of test data to the parallel digital bus; A high-speed oversampling module is connected to the parallel digital bus and is configured to use a sampling clock with a frequency N times that of the data transmission clock frequency to asynchronously oversample each data line in the parallel bus to obtain sampled data streams within multiple unit intervals. The timing analysis engine, connected to the high-speed oversampling module, is configured to perform bit alignment on the sampled data stream and reconstruct the digital eye diagram of each data line by superimposing an average. The timing analysis engine is further configured to identify the stable region of each data line based on the digital eye diagram and calculate the intersection of the stable regions of all data lines to obtain a common safety window. The clock phase adjustment module is configured to receive the center position parameter of the common safety window calculated by the timing analysis engine and convert it into a control code to adjust the phase of the data transmission clock.
2. The parallel digital bus adaptive clock phase calibration system according to claim 1, characterized in that, The specific method by which the time series analysis engine reconstructs the digital eye diagram is as follows: Using the test data sequence as a reference, the sampled data stream is divided into multiple data segments corresponding to a single unit interval (UI); The multiple data segments are superimposed on the time axis; By statistically analyzing the probability distribution of high and low levels at each sampling time point, a digital statistical view reflecting the characteristics of signal amplitude and time jitter is constructed.
3. The parallel digital bus adaptive clock phase calibration system according to claim 1, characterized in that, The logic by which the time-series analysis engine calculates the public safety window includes: For the i-th data line, determine the starting point for the signal level to remain stable based on its digital eye diagram. and end time ; Calculate the maximum value at the start time of all parallel data lines. ; Calculate the minimum value at the end time of all parallel data lines. ; The public safety window is defined as an interval [ , ].
4. The parallel digital bus adaptive clock phase calibration system according to claim 3, characterized in that, The time series analysis engine is also equipped with anomaly detection functionality: When the calculation yields If the calibration fails, an error signal is sent to the calibration control module. In response to the error signal, the calibration control module executes a retry mechanism or a degraded operation strategy.
5. The parallel digital bus adaptive clock phase calibration system according to claim 1, characterized in that, The clock phase adjustment module includes: A programmable delay line is disposed on the transmission path of the data sampling clock; the programmable delay line is selected from either a digitally controlled delay line (DCDL) or a voltage-controlled delay line (VCDL); A control logic unit is used to map the center position parameter to the delay level configuration word of the programmable delay line.
6. The parallel digital bus adaptive clock phase calibration system according to claim 1, characterized in that, The test data sequence generated by the test mode generation and request module is selected from at least one of the following groups: a checkerboard sequence of alternating 0s and 1s; a pseudo-random binary sequence (PRBS); or a sequence of all 0s or all 1s.
7. A method for calibration using the parallel digital bus adaptive clock phase calibration system according to any one of the preceding claims, characterized in that, Includes the following steps: Step S1: Enter calibration mode and send a predefined test mode sequence to the parallel digital bus; Step S2: Oversample all data lines of the parallel bus using a high-speed clock with a frequency N times the data rate to capture a data snapshot; Step S3: Align the data snapshots based on the test pattern sequence, and reconstruct the digital eye diagram of each data line by statistically superimposing multiple periods of data; Step S4: Analyze the digital eye diagram of each data line to identify its respective effective stable range; Step S5: Calculate the intersection of the effective stable intervals of all data lines to determine the common safety window; Step S6: Calculate the center point of the public safety window and adjust the phase of the data sampling clock to the center point position.
8. The method according to claim 7, characterized in that, The specific algorithm for calculating the intersection in step S5 is as follows: ； ； like If so, then a public safety window exists; like If no public safety window is found, the exception handling process will be triggered.