Memory training method, and memory controller, processor and electronic device

Abstract

The present application belongs to the field of electronic circuits, and relates to a memory training method, and a memory controller, a processor and an electronic device. The memory training method is applied to a memory controller, and the method comprises: acquiring an initial transmission delay range, wherein the initial transmission delay range is a transmission delay range for theoretically correctly transmitting DQ data; and on the basis of the initial transmission delay range, adjusting a transmission delay of a DQS timing signal or a DQ data signal, and determining, from the initial transmission delay range, a target transmission delay range for actually correctly transmitting the DQ data, wherein the DQS timing signal and the DQ data signal are interaction signals between a memory controller and a memory chip, the target transmission delay range is smaller than or equal to the initial transmission delay range, and the target transmission delay range is the relative timing slack of the DQ data signal with respect to the DQS timing signal. In the present application, by means of performing memory training, the accuracy of data transmission between a memory controller and a memory chip can be improved, and the efficiency of memory training can also be improved.

Description

A memory training method, a memory controller, a processor, and an electronic device.

[0001] Related applications

[0002] This application claims priority to Chinese invention patent filed on October 17, 2024, application number 202411455954.1, entitled "A Memory Training Method, Memory Controller, Processor and Electronic Device", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application belongs to the field of electronic circuits, specifically relating to a memory training method, a memory controller, a processor, and an electronic device. Background Technology

[0004] Most electronic devices integrate processors and memory chips. The processor and memory chips require a memory controller to drive them, and the memory controller is connected to the memory chips via a memory bus. The data signal line DQ transmits data signals; DQ is short for the data signal defined in the Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) protocol. The timing signal line DQS can transmit data strobe signals; DQS is short for the data strobe signal defined in the DDR protocol.

[0005] During the process of accessing data from the memory chip, the memory controller transmits data via DQ and DQS. When the memory controller writes data to the memory chip, it can send DQ and DQS to the chip. DQ carries the data the controller wants to write, and DQS triggers the memory chip to recognize the voltage level of DQ, allowing it to write the data. Conversely, when the memory controller reads data from the memory chip, the chip sends data from DQ to the controller, which then collects the DQ data based on DQS.

[0006] As can be seen from the working principles of DQ and DQS, the accuracy of data transmission between the memory controller and the memory chip depends on the relative timing alignment between DQ and DQS. That is, only when DQ has sufficient timing margin relative to DQS can the receiving end of DQ have a low bit error rate, thus ensuring data transmission accuracy. Voltage, temperature, and frequency can all cause phase changes in DQ and DQS. Therefore, how to ensure that DQ has sufficient timing margin relative to DQS to improve data transmission accuracy has become a focus of the industry.

[0007] This application content

[0008] Therefore, the purpose of this application is to provide a memory training method, a memory controller, a processor, and an electronic device to improve the accuracy of data transmission between the memory controller and the memory chip.

[0009] The embodiments of this application are implemented as follows:

[0010] In a first aspect, embodiments of this application provide a memory training method applied to a memory controller. The method includes: obtaining an initial transmission delay range; wherein the initial transmission delay range is the theoretically correct transmission delay range for DQ data; adjusting the transmission delay of a DQS timing signal or a DQ data signal based on the initial transmission delay range; determining a target transmission delay range for actual correct transmission of DQ data from the initial transmission delay range; wherein the DQS timing signal and the DQ data signal are interaction signals between the memory controller and the memory chip; the target transmission delay range is less than or equal to the initial transmission delay range, and the target transmission delay range is the relative timing margin between the DQ data signal and the DQS timing signal.

[0011] In the above embodiments, memory training ensures that the DQ data signal and the DQS timing signal have sufficient relative timing margin to improve the accuracy of data transmission between the memory controller and the memory chip. At the same time, since the maximum adjustable transmission delay range (i.e., the initial transmission delay range) is given in advance, the transmission delay of the DQS timing signal or the DQ data signal is adjusted only within the initial transmission delay range during adjustment, without exceeding the initial transmission delay range. This reduces unnecessary adjustment processes and allows the target transmission delay range for correctly transmitting DQ data to be quickly determined from the initial transmission delay range, which is beneficial to improving the efficiency of memory training.

[0012] In one possible implementation of the first aspect embodiment, determining the target transmission delay range for actually correctly transmitting DQ data from the initial transmission delay range includes: using a binary search method to determine the target transmission delay range for actually correctly transmitting DQ data from the initial transmission delay range.

[0013] In the above embodiment, the target transmission delay range for correctly transmitting DQ data is determined from the initial transmission delay range using a binary search method. This allows for the rapid determination of the target transmission delay range for correctly transmitting DQ data without traversing every value within the initial transmission delay range, which is beneficial for improving the efficiency of memory training.

[0014] In one possible implementation of the first aspect embodiment, the target transmission delay range for correctly transmitting DQ data is determined from the initial transmission delay range using a bisection method, comprising: dividing the initial transmission delay range into a first interval and a second interval from its middle position, wherein neither the first interval nor the second interval contains the middle value of the initial transmission delay range; determining whether the first interval includes a first transmission delay range for correctly transmitting DQ data; if the first interval does not include a first transmission delay range for correctly transmitting DQ data, determining the target transmission delay range for correctly transmitting DQ data from the second interval.

[0015] In the above embodiment, the initial transmission delay range is first divided into a first interval and a second interval. Then, it is determined whether the first interval includes the first transmission delay range for correctly transmitting DQ data. If not, the target transmission delay range for correctly transmitting DQ data is determined from the second interval. This allows for the rapid determination of the actual target transmission delay range for correctly transmitting DQ data.

[0016] In one possible implementation of the first aspect embodiment, if the first interval includes a first transmission delay range for correctly transmitting DQ data, the method further includes: determining whether the median value of the initial transmission delay range can correctly transmit DQ data; if the median value of the initial transmission delay range cannot correctly transmit DQ data, determining the first transmission delay range as the target transmission delay range.

[0017] In the above embodiment, when the first interval contains the first transmission delay range for correctly transmitting DQ data, if the middle value of the initial transmission delay range cannot correctly transmit DQ data, it indicates that the effective interval is to the left or right of the middle value. At the same time, the first transmission delay range for correctly transmitting DQ data can be determined from the first interval. Therefore, it can be determined that the second interval cannot correctly transmit DQ data, and thus the first transmission delay range can be determined as the required target transmission delay range. Since the traversal of the second interval is reduced, the efficiency of memory training can be improved.

[0018] In one possible implementation of the first aspect embodiment, if the median value of the initial transmission delay range can correctly transmit DQ data, the method further includes: determining a second transmission delay range for correctly transmitting DQ data from the second interval; and determining the target transmission delay range based on the first transmission delay range, the median value of the initial transmission delay range, and the second transmission delay range.

[0019] In the above embodiment, when the DQ data can be correctly transmitted at the midpoint of the initial transmission delay range, it indicates that the effective interval is to the left and right of the midpoint. Therefore, it is also necessary to determine the second transmission delay range for correctly transmitting DQ data from the second interval. Then, based on the first transmission delay range, the midpoint of the initial transmission delay range, and the second transmission delay range, the target transmission delay range is determined. This can ensure the accuracy and completeness of the target transmission delay range, thereby ensuring that the DQ data signal and the DQS timing signal have sufficient relative timing margin.

[0020] In one possible implementation of the first aspect embodiment, the target transmission delay range for correctly transmitting DQ data is determined from the initial transmission delay range using a bisection method, comprising: dividing the initial transmission delay range in half from its middle position into a first interval and a second interval, wherein neither the first interval nor the second interval contains the midpoint of the initial transmission delay range; determining whether the midpoint of the initial transmission delay range can correctly transmit DQ data; if the midpoint of the initial transmission delay range can correctly transmit DQ data, determining a first transmission delay range and a second transmission delay range for correctly transmitting DQ data from the first interval and the second interval, respectively; and determining the target transmission delay range based on the first transmission delay range, the midpoint of the initial transmission delay range, and the second transmission delay range.

[0021] In the above embodiment, it is first determined whether the median value of the initial transmission delay range can correctly transmit DQ data. This determines whether the effective interval is to the left or right of the median value. When the median value of the initial transmission delay range can correctly transmit DQ data, it indicates that the effective interval is to the left or right of the median value. Therefore, it is necessary to determine the first transmission delay range and the second transmission delay range for correctly transmitting DQ data from the first interval and the second interval, respectively. Then, based on the first transmission delay range, the median value of the initial transmission delay range, and the second transmission delay range, the target transmission delay range is determined. This ensures the accuracy and completeness of the target transmission delay range, thereby ensuring that the DQ data signal and the DQS timing signal have sufficient relative timing margin.

[0022] In one possible implementation of the first aspect embodiment, if the median value of the initial transmission delay range cannot correctly transmit DQ data, the method further includes: if the first interval includes a first transmission delay range for correctly transmitting DQ data, determining the first transmission delay range as the target transmission delay range; if the first interval does not include a first transmission delay range for correctly transmitting DQ data, determining a target transmission delay range for correctly transmitting DQ data from the second interval.

[0023] In the above embodiment, if the median value of the initial transmission delay range cannot correctly transmit DQ data, it indicates that the effective interval is to the left or right of the median value. Then, it is determined whether the first interval includes the first transmission delay range for correctly transmitting DQ data. If the first interval includes the first transmission delay range for correctly transmitting DQ data, the first transmission delay range is directly determined as the target transmission delay range. If the first interval does not include the first transmission delay range for correctly transmitting DQ data, the target transmission delay range for correctly transmitting DQ data is determined from the second interval. In this way, the required target transmission delay range can be quickly determined.

[0024] In one possible implementation of the first aspect embodiment, determining the first transmission delay range and the second transmission delay range for correctly transmitting DQ data from the first interval and the second interval respectively includes: determining the first transmission delay range and the second transmission delay range for correctly transmitting DQ data from the first interval and the second interval respectively using a bisection method.

[0025] In the above embodiments, the first transmission delay range and the second transmission delay range for correctly transmitting DQ data are determined from the first interval and the second interval, respectively, by using the binary search method. This is beneficial to further improve the efficiency of memory training.

[0026] Secondly, embodiments of this application also provide a memory controller, including: a delay adjustment module and a control module; the delay adjustment module is used to adjust the transmission delay of a DQS timing signal or a DQ data signal, wherein the DQS timing signal and the DQ data signal are interaction signals between the memory controller and the memory chip; the control module is used to obtain an initial transmission delay range; wherein the initial transmission delay range is the theoretically correct transmission delay range for DQ data; and control the delay adjustment module to adjust the transmission delay of the DQS timing signal or the DQ data signal based on the initial transmission delay range, and determine a target transmission delay range for actual correct transmission of DQ data from the initial transmission delay range, wherein the target transmission delay range is less than or equal to the initial transmission delay range, and the target transmission delay range is the relative timing margin between the DQ data signal and the DQS timing signal.

[0027] In one possible implementation of the second aspect embodiment, the control module is specifically used to: determine the target transmission delay range for actually correctly transmitting DQ data from the initial transmission delay range using a binary search method.

[0028] In one possible implementation of the second aspect embodiment, the control module is specifically configured to: divide the initial transmission delay range into two parts from the middle position, namely a first interval and a second interval, wherein neither the first interval nor the second interval contains the middle value of the initial transmission delay range; determine whether the first interval includes a first transmission delay range for correctly transmitting DQ data; if the first interval does not include a first transmission delay range for correctly transmitting DQ data, determine a target transmission delay range for correctly transmitting DQ data from the second interval.

[0029] In one possible implementation of the second aspect embodiment, if the first interval includes a first transmission delay range for correctly transmitting DQ data, the control module is specifically configured to: determine whether the median value of the initial transmission delay range can correctly transmit DQ data; if the median value of the initial transmission delay range cannot correctly transmit DQ data, determine the first transmission delay range as the target transmission delay range; if the median value of the initial transmission delay range can correctly transmit DQ data, determine a second transmission delay range for correctly transmitting DQ data from the second interval; and determine the target transmission delay range based on the first transmission delay range, the median value of the initial transmission delay range, and the second transmission delay range.

[0030] In one possible implementation of the second aspect embodiment, the control module is specifically configured to: divide the initial transmission delay range into a first interval and a second interval from its middle position, wherein neither the first interval nor the second interval contains the middle value of the initial transmission delay range; determine whether the middle value of the initial transmission delay range can correctly transmit DQ data; if the middle value of the initial transmission delay range can correctly transmit DQ data, determine a first transmission delay range and a second transmission delay range for correctly transmitting DQ data from the first interval and the second interval, respectively; and determine the target transmission delay range based on the first transmission delay range, the middle value of the initial transmission delay range, and the second transmission delay range.

[0031] In one possible implementation of the second aspect embodiment, if the intermediate value of the initial transmission delay range cannot correctly transmit DQ data, the control module is specifically configured to: if the first interval includes a first transmission delay range for correctly transmitting DQ data, determine the first transmission delay range as the target transmission delay range; if the first interval does not include a first transmission delay range for correctly transmitting DQ data, determine the target transmission delay range for correctly transmitting DQ data from the second interval.

[0032] Thirdly, embodiments of this application also provide a processor, including: a processor core and a memory controller provided as described in the second aspect embodiments above and / or in combination with any possible implementation of the second aspect embodiments above; the processor core is configured to send training instructions to the memory controller; the memory controller is configured to perform memory training in response to the training instructions.

[0033] Fourthly, embodiments of this application also provide an electronic device, including: a memory chip and a processor as provided in the third aspect of the embodiments above, wherein the memory chip is connected to a memory controller in the processor.

[0034] Fifthly, embodiments of this application also provide an electronic device, including: a processor, a memory chip, and a memory controller provided as described in the second aspect embodiments above and / or in combination with any possible implementation of the second aspect embodiments above, wherein the memory controller is connected to the processor and the memory chip respectively; the processor is configured to send training instructions to the memory controller; and the memory controller is configured to perform memory training in response to the training instructions.

[0035] Other features and advantages of this application will be set forth in the following description. The objectives and other advantages of this application can be realized and obtained through the structures specifically pointed out in the written description and the accompanying drawings. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the accompanying drawings used in the embodiments will be briefly described below. Obviously, the drawings described below are only some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings. The above and other objects, features, and advantages of this application will become clearer through the accompanying drawings.

[0037] Figure 1 shows a schematic diagram of the connection between a memory controller and a memory chip according to an embodiment of this application.

[0038] Figure 2 shows a flowchart of a memory training method provided in an embodiment of this application.

[0039] Figure 3 shows a flowchart illustrating the first implementation of S2 provided in this application.

[0040] Figure 4 shows a flowchart illustrating a second implementation of S2 provided in this application.

[0041] Figure 5 shows a flowchart illustrating a third implementation of S2 provided in this application.

[0042] Figure 6 shows a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0043] The technical solutions of the embodiments of this application will now be described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. The following embodiments are provided as examples to more clearly illustrate the technical solutions of this application, and should not be used to limit the scope of protection of this application. Those skilled in the art will understand that, without conflict, the following embodiments and features can be combined with each other.

[0044] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, relational terms such as "first," "second," etc., in the description of this application are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus.

[0045] In the description of the embodiments of this application, unless otherwise expressly specified and limited, the technical term "connection" can be a direct connection or an indirect connection through an intermediate medium.

[0046] In electronic devices, the memory controller and memory chip are connected via a memory bus. As shown in Figure 1, the memory bus mainly includes at least one data signal line (denoted by DQ), a timing signal line (denoted by DQS), and a signal line for sending read and write commands (denoted by CA). Among them, CA is the bus for the memory controller to send read and write commands, DQ is the bus for sending and receiving data between the memory controller and the memory chip, and DQS is the reference signal sampled by the receiving end.

[0047] The memory training method shown in the embodiments of this application can occur in a scenario where the memory controller writes data to the memory chip, or in a scenario where the memory controller reads data from the memory chip.

[0048] In one possible implementation, as shown in Figure 1, multiple data signal lines (such as DQ0 to DQn) share a single DQS and CA bus. Compared to each data signal line corresponding to a separate DQS and CA bus, this can save on the number of buses and thus save power consumption.

[0049] To improve the accuracy of data transmission between the memory controller and the memory chip, this application provides a memory training method, a memory controller, a processor, and an electronic device. The memory training method provided in this application will be described below with reference to the method shown in Figure 2. The memory training method provided in this application can be applied to a memory controller; that is, the execution entity of this memory training method can be a memory controller.

[0050] S1: Obtain the initial transmission delay range.

[0051] When training the memory, the initial transmission delay range (i.e., the initial delay line range) can be obtained. This initial transmission delay range is the theoretically correct transmission delay range for DQ data, meaning it represents the theoretically correct transmission delay range between the memory controller and the memory chip for DQ data. This initial transmission delay range represents the theoretical relative timing margin between the DQ data signal and the DQS timing signal, and it can be obtained through testing before the memory chip leaves the factory.

[0052] In one implementation, the initial transfer delay range can be pre-stored in a register set. After receiving a training instruction from the processor (or processor core), the memory controller can directly retrieve the initial transfer delay range from the register set, thereby initiating memory training. In another implementation, the initial transfer delay range can also be sent by the processor (or processor core). After receiving the initial transfer delay range sent by the processor (or processor core), the memory controller initiates memory training.

[0053] S2: Adjust the transmission delay of the DQS timing signal or DQ data signal based on the initial transmission delay range, and determine the target transmission delay range for actual correct transmission of DQ data from the initial transmission delay range.

[0054] After obtaining the initial transmission delay range, the transmission delay of the DQS timing signal or DQ data signal can be adjusted based on this range. From the initial transmission delay range, the target transmission delay range for correctly transmitting DQ data can be determined. The target transmission delay range is less than or equal to the initial transmission delay range. The target transmission delay range represents the relative timing margin between the DQ data signal and the DQS timing signal. Within this relative timing margin, the memory controller and memory chip can correctly transmit DQ data. The purpose of memory training is to ensure that the DQ data transmitted between the memory controller and memory chip maintains sufficient timing margin.

[0055] Understandably, in real-world scenarios, the DQS timing signal and the DQ data signal are affected by factors such as chip voltage, temperature, and frequency, which may reduce the actual transmission delay range between the memory controller and the memory chip that can correctly transmit DQ data. Therefore, it is necessary to determine the target transmission delay range for correctly transmitting DQ data from the initial transmission delay range.

[0056] In practical scenarios, there is usually a delay line range in the middle of the initial transmission delay range that can be successfully sampled, i.e., the effective window of the delay line (i.e., the target transmission delay range). Values ​​at both ends of the initial transmission delay range will fail to be sampled. If the DQ data transmitted using the DQS timing signal is successfully sampled, the DQ data is considered to be transmitted correctly. If the DQ data transmitted using the DQS timing signal fails to be sampled, the DQ data is considered to be transmitted incorrectly. Taking reading and writing data as an example, if the data at the transmitting end matches the data sampled at the receiving end, the sampling is considered successful; otherwise, the sampling is considered to have failed. To ensure correct data transmission, multiple samplings can be performed. If all multiple samplings are successful, the DQ data is considered to be transmitted correctly. If at least one sampling fails, the DQ data is considered to be transmitted incorrectly. Typically, the receiving end acquires the DQ data signal during the DQS transition and uses the instantaneous level state of the acquired DQ signal as the DQ data.

[0057] Adjusting the transmission delay of the DQS timing signal or DQ data signal based on the initial transmission delay range can be achieved by keeping the transmission delay of the DQS timing signal constant and adjusting the transmission delay of the DQ data signal within the initial transmission delay range; or by keeping the transmission delay of the DQ data signal constant and adjusting the transmission delay of the DQS timing signal within the initial transmission delay range. In the example shown in Figure 1, multiple DQ lines correspond to one DQS line. The preferred approach is to keep the transmission delay of the DQS timing signal constant and adjust the transmission delay of the DQ data signal within the initial transmission delay range. When there are many DQ lines to be trained, the same training method can be used for each DQ line to determine the relative timing margin between each DQ line and the DQS line. When adjusting the transmission delay, the increase or decrease in the relative transmission delay between the DQS timing signal and the DQ data signal cannot exceed the initial transmission delay range.

[0058] Since this application provides a maximum adjustable transmission delay range (i.e., the initial transmission delay range) in advance, during adjustment, the transmission delay of the DQS timing signal or DQ data signal is adjusted only within this initial transmission delay range, without exceeding it. This reduces unnecessary adjustment processes and allows the target transmission delay range for correctly transmitting DQ data to be quickly determined from the initial transmission delay range, which is beneficial for improving the efficiency of memory training.

[0059] Adjusting the transmission delay of the DQS timing signal or DQ data signal can be achieved by iterating through every value in the initial transmission delay range to determine the target transmission delay range. In this implementation, it is necessary to iterate through every value in the initial transmission delay range. For example, assuming the initial transmission delay range is (-0.5, -0.4, -0.3, -0.2, -0.1, 0, 0.1, 0.2, 0.3, 0.4, 0.5), each value within this range needs to be iterated through to determine whether DQ data can be correctly transmitted under each transmission delay, thereby determining the target transmission delay range. In the above ranges, the plus or minus signs indicate the offset direction. For example, -0.3 in the range can be seen as shifting the transmission delay of the DQ or DQS signal to the left by 0.3t, and 0.2 can be seen as shifting the transmission delay of the DQ or DQS signal to the right by 0.2t, where t is the signal period. The other values ​​are similar. The numerical values ​​shown here are for illustrative purposes only and should not be construed as limitations on this application.

[0060] To further improve the efficiency of memory training, in one implementation, when determining the target transmission delay range for correctly transmitting DQ data from the initial transmission delay range, a binary search method can be used. Binary search is a search algorithm for finding a specific element in an ordered array. It quickly locates the target value by halving the search range each time. This avoids traversing every value within the initial transmission delay range, thus quickly determining the target transmission delay range for correctly transmitting DQ data and improving the efficiency of memory training.

[0061] In some implementations, other methods can be used to determine the target transmission delay range for correctly transmitting DQ data from the initial transmission delay range. For example, the binary search method can be replaced with a ternary search method or other methods, which can theoretically improve the efficiency of memory training.

[0062] In one possible implementation, when using the binary search method to determine the target transmission delay range for correctly transmitting DQ data from the initial transmission delay range, the principle can be illustrated in Figure 3, including the following steps.

[0063] S21: Divide the initial transmission delay range into two parts from the middle position, into a first interval and a second interval.

[0064] The initial transmission delay range is divided into two parts at the middle position, namely the first interval and the second interval. Neither the first interval nor the second interval contains the middle value of the initial transmission delay range. The first interval can be the left interval, and correspondingly, the second interval is the right interval; conversely, the first interval can be the right interval, and correspondingly, the second interval is the left interval. For example, using the initial transmission delay range (-0.5, -0.4, -0.3, -0.2, -0.1, 0, 0.1, 0.2, 0.3, 0.4, 0.5) as an example, the first interval could be (-0.5, -0.4, -0.3, -0.2, -0.1), and the second interval could be (0.1, 0.2, 0.3, 0.4, 0.5).

[0065] Understandably, the middle value can be one or two. For example, for an initial transmission delay range of (-0.4, -0.3, -0.2, -0.1, 0, 0.1, 0.2, 0.3, 0.4, 0.5), the first interval could be (-0.4, -0.3, -0.2, -0.1), the second interval could be (0.2, 0.3, 0.4, 0.5), and the middle value would be (0, 0.1). As another example, for an initial transmission delay range of (-0.5, -0.4, -0.3, -0.2, -0.1, 0, 0.1, 0.2, 0.3, 0.4), the first interval could be (-0.5, -0.3, -0.2), the second interval could be (0.1, 0.2, 0.3, 0.4), and the middle value would be (-0.1, 0).

[0066] S22: Determine whether the first interval includes the first transmission delay range for correctly transmitting DQ data.

[0067] After dividing the initial transmission delay range into a first interval and a second interval, it is determined whether the first interval includes the first transmission delay range for correctly transmitting DQ data. That is, it is determined whether the first transmission delay range for correctly transmitting DQ data can be determined from the first interval. If the first transmission delay range for correctly transmitting DQ data cannot be determined from the first interval, that is, the first interval does not include the first transmission delay range for correctly transmitting DQ data, then S23 is executed. If the first transmission delay range for correctly transmitting DQ data can be determined from the first interval, that is, the first interval includes the first transmission delay range for correctly transmitting DQ data, then S24 is executed.

[0068] In determining the first transmission delay range for correctly transmitting DQ data from the first interval, one approach is to iterate through each value in the first interval to determine whether the first transmission delay range for correctly transmitting DQ data can be determined from the first interval. To improve the efficiency of memory training, one implementation method is to use a binary search to determine the first transmission delay range for correctly transmitting DQ data from the first interval. In this case, the process of determining whether the first transmission delay range for correctly transmitting DQ data can be determined is as follows: determine whether the first transmission delay range for correctly transmitting DQ data can be determined from the first interval using a binary search.

[0069] When using the bisection method to determine the first transmission delay range for correctly transmitting DQ data from the first interval, first determine whether the median value of the first interval can correctly transmit DQ data. If it can, it means that the median value is within the valid window, and the valid boundary is distributed to the left and right sides of the median value. If it cannot, it means that the valid boundary is distributed to the left or right of the median value. Then, determine whether the median values ​​in the regions to the left and right of the median value can correctly transmit DQ data, and so on, until a median value for a certain range (e.g., the range has only 2 values) cannot be found. When the bisection method cannot find a median value for a certain range (e.g., the range has only 2 values), prioritize determining whether the value closer to the initial median value (the median value of the initial transmission delay range) within the range can correctly transmit DQ data. If it can correctly transmit DQ data, then determine whether the other value within the range can correctly transmit DQ data. If the value closer to the initial median value cannot correctly transmit DQ data, then there is no need to determine whether the value farther from the initial median value (the other value within the range) can correctly transmit DQ data.

[0070] S23: Determine the target transmission delay range for correctly transmitting DQ data from the second interval.

[0071] When the first transmission delay range for correctly transmitting DQ data cannot be determined from the first interval, i.e., the first interval does not include the first transmission delay range, the target transmission delay range for correctly transmitting DQ data is determined from the second interval.

[0072] When determining the target transmission delay range for correctly transmitting DQ data from the second interval, it is also possible to determine the target transmission delay range for correctly transmitting DQ data by traversing each value in the second interval. To improve the efficiency of memory training, one implementation method is to use a binary search method to determine the target transmission delay range for correctly transmitting DQ data from the second interval.

[0073] S24: Determine whether the median value of the initial transmission delay range can correctly transmit DQ data.

[0074] When a first transmission delay range for correctly transmitting DQ data can be determined from the first interval, it is determined whether the median value of the initial transmission delay range can correctly transmit DQ data. If the median value of the initial transmission delay range cannot correctly transmit DQ data, S25 is executed; if the median value of the initial transmission delay range can correctly transmit DQ data, S26 is executed.

[0075] S25: Determine the first transmission delay range as the target transmission delay range.

[0076] If the DQ data cannot be transmitted correctly at the midpoint of the initial transmission delay range, the first transmission delay range is determined as the target transmission delay range.

[0077] S26: Determine the second transmission delay range for correctly transmitting DQ data from the second interval.

[0078] When the DQ data can be correctly transmitted at the midpoint of the initial transmission delay range, a second transmission delay range for correctly transmitting DQ data is determined from the second interval.

[0079] When determining the second transmission delay range for correctly transmitting DQ data from the second interval, it is also possible to determine the second transmission delay range for correctly transmitting DQ data by traversing each value in the second interval. To improve the efficiency of memory training, in one implementation, a binary search method can be used to determine the second transmission delay range for correctly transmitting DQ data from the second interval.

[0080] S27: Determine the target transmission delay range based on the first transmission delay range, the median value of the initial transmission delay range, and the second transmission delay range.

[0081] After determining the second transmission delay range for correctly transmitting DQ data from the second interval, the target transmission delay range is determined based on the first transmission delay range, the median value of the initial transmission delay range, and the second transmission delay range. The target transmission delay range is then the union of the first transmission delay range, the median value of the initial transmission delay range, and the second transmission delay range. For example, taking the initial transmission delay range (-0.5, -0.4, -0.3, -0.2, -0.1, 0, 0.1, 0.2, 0.3, 0.4, 0.5) from the example above, assuming the first transmission delay range is (-0.3, -0.2, -0.1) and the second transmission delay range is (0.1, 0.2), then the target transmission delay range is (-0.3, -0.2, -0.1, 0, 0.1, 0.2).

[0082] In another possible implementation, when using the binary search method to determine the target transmission delay range for correctly transmitting DQ data from the initial transmission delay range, the principle can be shown in Figure 4, including the following steps.

[0083] S201: Divide the initial transmission delay range into two parts from the middle position, into a first interval and a second interval, and determine whether the middle value of the initial transmission delay range can correctly transmit DQ data.

[0084] The initial transmission delay range is divided into a first interval and a second interval. It is then determined whether the middle value of the initial transmission delay range can correctly transmit DQ data. If the middle value of the initial transmission delay range can correctly transmit DQ data, S202 is executed; otherwise, S204 is executed.

[0085] S202: Determine the first transmission delay range and the second transmission delay range for correctly transmitting DQ data from the first interval and the second interval, respectively.

[0086] When DQ data can be correctly transmitted at the midpoint of the initial transmission delay range, the first transmission delay range and the second transmission delay range for correctly transmitting DQ data are determined from the first interval and the second interval, respectively.

[0087] S203: Determine the target transmission delay range based on the first transmission delay range, the median value of the initial transmission delay range, and the second transmission delay range.

[0088] After determining the first transmission delay range and the second transmission delay range, the target transmission delay range is determined based on the first transmission delay range, the median value of the initial transmission delay range, and the second transmission delay range.

[0089] S204: Determine whether the first interval includes the first transmission delay range for correctly transmitting DQ data.

[0090] If the DQ data cannot be transmitted correctly at the midpoint of the initial transmission delay range, it is determined whether the first interval includes the first transmission delay range for correctly transmitting DQ data; that is, it is determined whether the first transmission delay range for correctly transmitting DQ data can be determined from the first interval. If the first transmission delay range for correctly transmitting DQ data can be determined from the first interval, then S205 is executed; if the first transmission delay range for correctly transmitting DQ data cannot be determined from the first interval, then S206 is executed.

[0091] S205: Determine the first transmission delay range as the target transmission delay range.

[0092] When a first transmission delay range for correctly transmitting DQ data can be determined from the first interval, that is, when the first interval includes the first transmission delay range for correctly transmitting DQ data, the first transmission delay range is determined as the target transmission delay range.

[0093] S206: Determine the target transmission delay range for correctly transmitting DQ data from the second interval.

[0094] When the first transmission delay range for correctly transmitting DQ data cannot be determined from the first interval, i.e., when the first interval does not include the first transmission delay range for correctly transmitting DQ data, the target transmission delay range for correctly transmitting DQ data is determined from the second interval.

[0095] The embodiment shown in Figure 4 differs from the embodiment shown in Figure 3 mainly in that the order of determining whether the intermediate value of the initial transmission delay range can correctly transmit DQ data is different from the order of determining whether the first interval includes the first transmission delay range for correctly transmitting DQ data.

[0096] In another possible implementation, when using the binary search method to determine the target transmission delay range for correctly transmitting DQ data from the initial transmission delay range, the principle can be shown in Figure 5, including the following steps.

[0097] S200: Divide the initial transmission delay range into two parts from the middle position, into a first interval and a second interval.

[0098] S202: Determine the first transmission delay range and the second transmission delay range for correctly transmitting DQ data from the first interval and the second interval, respectively.

[0099] After dividing the initial transmission delay range into a first interval and a second interval, the first transmission delay range and the second transmission delay range for correctly transmitting DQ data are determined from the first interval and the second interval, respectively.

[0100] S203: Determine the target transmission delay range based on the first transmission delay range, the median value of the initial transmission delay range, and the second transmission delay range.

[0101] After determining the first transmission delay range and the second transmission delay range, the target transmission delay range is determined based on the first transmission delay range, the median value of the initial transmission delay range, and the second transmission delay range.

[0102] In determining the first and second transmission delay ranges for correctly transmitting DQ data from the first and second intervals, respectively, one implementation involves iterating through each value in the first and second intervals to determine these ranges. Another implementation uses a binary search method to determine these ranges from the first and second intervals. The embodiment shown in Figure 5 differs from the embodiment shown in Figure 4 primarily in that it lacks the logic for making a judgment, defaulting to the assumption that the intermediate value of the initial transmission delay range can correctly transmit DQ data.

[0103] To better understand the above memory training method, the following example will illustrate it. Assume the initial delay line range is [-0.5:0.5], and the final effective window is [-0.3:0.1].

[0104] The following explanation uses the logic shown in Figure 4 above. Using the intermediate value 0 as the dividing point, the initial delay line range is divided into two: a left interval [-0.5:-0.1] and a right interval [0.1:0.5]. It is then determined whether the intermediate value 0 can correctly transmit DQ data. Based on this intermediate value 0, the transmission delay of the DQS timing signal or the DQ data signal is adjusted. Then, the DQ data transmitted by the DQ data signal is sampled and trained using the DQS timing signal. If the DQ data can be transmitted correctly (training successful or sampling successful), it means that 0 is within the effective window, and the effective boundary is distributed to the left and right sides of the intermediate value 0. If the intermediate value 0 cannot transmit DQ data correctly (training failed or sampling failed), it means that the effective boundary is distributed to the left or right of the intermediate value 0. The principle of the first scan training is shown in Table 1, where the gray area represents the effective window.

[0105] Table 1

[0106] Taking the first scan of the left interval as an example, the midpoint of the left interval [-0.5:-0.1] is -0.3. The second scan returns to the midpoint of the left interval, -0.3, to determine if DQ data can be transmitted correctly. This involves adjusting the transmission delay of the DQS timing signal or the DQ data signal based on the midpoint -0.3. Then, the DQ data transmitted using the DQS timing signal is sampled and trained. If the DQ data can be transmitted correctly (sampling successful), it means -0.3 is within the valid window, and the valid boundary is distributed to the left and right of the midpoint -0.3. If the midpoint -0.3 cannot transmit the DQ data correctly (sampling failed), it means the valid boundary is distributed to the left or right of the midpoint -0.3. The principle of the second scan training is shown in Table 2, where the gray area represents the valid window.

[0107] Table 2

[0108] In this example, the middle value -0.3 can correctly transmit DQ data, so we continue scanning the range [-0.5:-0.4] to the left of the middle value -0.3. Since this range only contains two values, we cannot scan the middle value. At this time, we prioritize scanning -0.4, which is closer to the center of the window (0). If -0.4 cannot correctly transmit DQ data, it means that the left boundary is -0.3. The principle of the third training scan is shown in Table 3. The gray part in Table 3 is the part where the effective window is located.

[0109] Table 3

[0110] In this example, -0.4 cannot correctly transmit DQ data, i.e., training fails. Therefore, the scan of the left interval ends, and the process switches to the right interval. The midpoint of the right interval [0.1:0.5] is 0.3. To determine if 0.3 can correctly transmit DQ data, the transmission delay of the DQS timing signal or DQ data signal is adjusted based on the midpoint 0.3. Then, the DQ data transmitted by the DQ data signal is sampled and trained using the DQS timing signal. If the DQ data can be transmitted correctly (sampling successful), it means 0.3 is within the effective window, and the effective boundary is distributed to the left and right of the midpoint -0.3. If the midpoint 0.3 cannot correctly transmit DQ data (sampling failed), it means the effective boundary is distributed to the left or right of the midpoint 0.3. The principle of the first scan training of the right interval is shown in Table 4. The gray area in Table 4 represents the effective window.

[0111] Table 4

[0112] In this example, 0.3 cannot correctly transmit DQ data, indicating training failure. This means the right boundary of the window is between [0.1:0.2]. Since this scanning interval has no center value, 0.1, which is closer to the window center, is scanned first. If 0.1 can correctly transmit DQ data, then 0.2 is scanned. In this example, 0.2 cannot correctly transmit DQ data, so the right boundary is 0.1. The principle of the second scan training right interval is shown in Table 5. The gray area in Table 5 represents the effective window area.

[0113] Table 5

[0114] In the example above, the first transmission delay range is (-0.3, -0.2, -0.1), the second transmission delay range is 0.1, the median value of the initial transmission delay range is 0, and the target transmission delay range is (-0.3:0.1), which is the gray part in Tables 1 to 5.

[0115] The above example clearly demonstrates that using the binary search method to determine the target transmission delay range for correctly transmitting DQ data from the initial transmission delay range is significantly more efficient than iterating through every value in the initial transmission delay range.

[0116] This application also provides a memory controller, which can receive training instructions sent by a processor (or processor core) and execute memory training in response to the training instructions. The memory controller includes a latency adjustment module and a control module, through which memory training is completed.

[0117] The delay adjustment module is used to adjust the transmission delay of the DQS timing signal or the DQ data signal, wherein the DQS timing signal and the DQ data signal are interaction signals between the memory controller and the memory chip. Under the control of the control module, the delay adjustment module can adjust the transmission delay of the DQS timing signal or the DQ data signal, thereby adjusting the phase of the DQS timing signal or the DQ data signal.

[0118] In one possible implementation, the delay adjustment module may include a register group and a phase adjuster. The phase adjuster can adjust the transmission delay of the DQS timing signal or the DQ data signal according to the value in the register group. The register group can serve as a control interface for the control module to control the delay circuit, so that the control module can configure the value in the register group based on the initial transmission delay range to control the delay adjustment module.

[0119] The control module can be a logic circuit with certain logic operation capabilities or include a software module. It can control the delay adjustment module to adjust the transmission delay of the DQS timing signal or the DQ data signal, so that the memory controller can execute the memory training method shown in the embodiments of this application.

[0120] A control module is used to obtain an initial transmission delay range, wherein the initial transmission delay range is the theoretical transmission delay range for correctly transmitting DQ data; and to control the delay adjustment module to adjust the transmission delay of the DQS timing signal or the DQ data signal based on the initial transmission delay range, and to determine the target transmission delay range for actually correctly transmitting DQ data from the initial transmission delay range, wherein the target transmission delay range is less than or equal to the initial transmission delay range, and the target transmission delay range is the relative timing margin between the DQ data signal and the DQS timing signal.

[0121] In one possible implementation, the control module is specifically used to: determine the target transmission delay range for correctly transmitting DQ data from the initial transmission delay range using a binary search method.

[0122] In one possible implementation, the control module is specifically used to: divide the initial transmission delay range into two parts from the middle position, into a first interval and a second interval; determine whether the first interval includes the first transmission delay range for correctly transmitting DQ data; if the first interval does not include the first transmission delay range for correctly transmitting DQ data, determine the target transmission delay range for correctly transmitting DQ data from the second interval.

[0123] In one possible implementation, if the first interval includes a first transmission delay range for correctly transmitting DQ data, the control module is further configured to: determine whether the median value of the initial transmission delay range can correctly transmit DQ data; if the median value of the initial transmission delay range cannot correctly transmit DQ data, determine the first transmission delay range as the target transmission delay range; if the median value of the initial transmission delay range can correctly transmit DQ data, determine a second transmission delay range for correctly transmitting DQ data from the second interval; and determine the target transmission delay range based on the first transmission delay range, the median value of the initial transmission delay range, and the second transmission delay range.

[0124] In one possible implementation, the control module is specifically configured to: divide the initial transmission delay range in half from its midpoint into a first interval and a second interval, and determine whether the midpoint of the initial transmission delay range can correctly transmit DQ data; if the midpoint of the initial transmission delay range can correctly transmit DQ data, determine a first transmission delay range and a second transmission delay range for correctly transmitting DQ data from the first interval and the second interval, respectively; and determine the target transmission delay range based on the first transmission delay range, the midpoint of the initial transmission delay range, and the second transmission delay range.

[0125] In one possible implementation, if the intermediate value of the initial transmission delay range cannot correctly transmit DQ data, the control module is specifically configured to: if the first interval includes a first transmission delay range for correctly transmitting DQ data, determine the first transmission delay range as the target transmission delay range; if the first interval does not include a first transmission delay range for correctly transmitting DQ data, determine the target transmission delay range for correctly transmitting DQ data from the second interval.

[0126] The implementation principle and technical effects provided by the memory controller embodiment are the same as those of the aforementioned method embodiment. For the sake of brevity, any parts not mentioned in the memory controller embodiment can be referred to the corresponding content in the aforementioned method embodiment.

[0127] This application also provides a processor, which includes a processor core and the aforementioned memory controller. In this embodiment, the memory controller is integrated into the processor. In some implementations, the processor and the memory controller may be parallel devices rather than being inclusive of each other.

[0128] The processor core is used to send training instructions to the memory controller; the memory controller is used to execute memory training in response to the training instructions, thereby executing the memory training method described above.

[0129] Based on the same inventive concept, this application also provides an electronic device, which includes a memory chip and a processor. The memory chip is connected to a memory controller in the processor. In this case, the processor core in the processor is used to send training instructions to the memory controller; the memory controller is used to respond to the training instructions to perform memory training, thereby executing the above-described memory training method.

[0130] In one implementation, when the memory controller is no longer integrated into the processor, the electronic device includes: a processor, a memory chip, and the aforementioned memory controller, wherein the memory controller is connected to both the processor and the memory chip; the processor is used to send training instructions to the memory controller; and the memory controller is used to execute memory training in response to the training instructions, thereby executing the aforementioned memory training method.

[0131] In one embodiment, as shown in FIG6, the electronic device 200 includes: a transceiver 210, a memory 220, a communication bus 230, and a processor 240. The processor includes the memory controller described above.

[0132] The transceiver 210, memory 220, and processor 240 are electrically connected directly or indirectly to achieve data transmission or interaction. For example, these components can be electrically connected to each other through one or more communication buses 230 or signal lines. The transceiver 210 is used to send and receive data. The memory 220 is used to store computer programs, wherein the computer programs include at least one software functional module that can be stored in the memory 220 in the form of software or firmware or embedded in the operating system (OS) of the electronic device 200. The processor 240 is used to execute the software functional modules or computer programs stored in the memory 220. For example, the processor 240 is used to execute the memory training method described above.

[0133] The memory 220 may be, but is not limited to, random access memory (RAM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), etc.

[0134] Processor 240 may be an integrated circuit chip with signal processing capabilities. The aforementioned processor can be a general-purpose processor, including a Central Processing Unit (CPU), Network Processor (NP), Graphics Processing Unit (GPU), Accelerated Processing Unit (ACCU), Multimedia Application Processor (MAP), microprocessor, etc.; it can also be a Digital Signal Processor (DSP), Application Specific Integrated Circuit (ASIC), Field Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. Alternatively, processor 240 can also be any conventional processor.

[0135] Among them, the aforementioned electronic devices 200 include, but are not limited to, smartphones, tablets, servers, base stations, smart cameras, autonomous vehicles, etc.

[0136] This application embodiment also provides a non-volatile computer-readable storage medium (hereinafter referred to as the storage medium) storing a computer program, which is executed by a computer such as the electronic device 200 described above to perform the memory training method described above.

[0137] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0138] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0139] In addition, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0140] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a computer-readable storage medium and includes several instructions to cause a computer device (which may be a personal computer, laptop, server, or electronic device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned computer-readable storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0141] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A memory training method, characterized in that, Applied to a memory controller, the method includes: Obtain the initial transmission delay range; wherein, the initial transmission delay range is the theoretical transmission delay range for correctly transmitting DQ data; The transmission delay of the DQS timing signal or the DQ data signal is adjusted based on the initial transmission delay range, and the target transmission delay range for actually correctly transmitting DQ data is determined from the initial transmission delay range. The DQS timing signal and the DQ data signal are interaction signals between the memory controller and the memory chip. The target transmission delay range is less than or equal to the initial transmission delay range.

2. The method according to claim 1, characterized in that, Determining the target transmission delay range for correct actual transmission of DQ data from the initial transmission delay range includes: The target transmission delay range for correctly transmitting DQ data is determined from the initial transmission delay range using a binary search method.

3. The method according to claim 2, characterized in that, Determining the target transmission delay range for correctly transmitting DQ data from the initial transmission delay range using a binary search method includes: The initial transmission delay range is divided into two parts from the middle position, namely the first interval and the second interval, wherein neither the first interval nor the second interval contains the middle value of the initial transmission delay range; Determine whether the first interval includes the first transmission delay range for correctly transmitting DQ data; If the first interval does not include the first transmission delay range for correctly transmitting DQ data, the target transmission delay range for correctly transmitting DQ data is determined from the second interval.

4. The method according to claim 3, characterized in that, If the first interval includes a first transmission delay range for correctly transmitting DQ data, the method further includes: Determine whether the median value of the initial transmission delay range can correctly transmit DQ data; If the median value of the initial transmission delay range cannot correctly transmit DQ data, the first transmission delay range is determined to be the target transmission delay range.

5. The method according to claim 4, characterized in that, If the median value of the initial transmission delay range can correctly transmit DQ data, the method further includes: Determine the second transmission delay range for correctly transmitting DQ data from the second interval; The target transmission delay range is determined based on the first transmission delay range, the median value of the initial transmission delay range, and the second transmission delay range.

6. The method according to claim 2, characterized in that, Determining the target transmission delay range for correctly transmitting DQ data from the initial transmission delay range using a binary search method includes: The initial transmission delay range is divided into two parts from the middle position, namely the first interval and the second interval, wherein neither the first interval nor the second interval contains the middle value of the initial transmission delay range; Determine whether the median value of the initial transmission delay range can correctly transmit DQ data; If the median value of the initial transmission delay range can correctly transmit DQ data, the first transmission delay range and the second transmission delay range for correctly transmitting DQ data are determined from the first interval and the second interval, respectively. The target transmission delay range is determined based on the first transmission delay range, the median value of the initial transmission delay range, and the second transmission delay range.

7. The method according to claim 6, characterized in that, If the median value of the initial transmission delay range cannot correctly transmit DQ data, the method further includes: If the first interval includes a first transmission delay range for correctly transmitting DQ data, then the first transmission delay range is determined to be the target transmission delay range; If the first interval does not include the first transmission delay range for correctly transmitting DQ data, the target transmission delay range for correctly transmitting DQ data is determined from the second interval.

8. The method according to claim 6, characterized in that, The first transmission delay range and the second transmission delay range for correctly transmitting DQ data are determined from the first interval and the second interval, respectively, including: The first transmission delay range and the second transmission delay range for correctly transmitting DQ data are determined from the first interval and the second interval respectively using the binary search method.

9. A memory controller, characterized in that, include: The delay adjustment module is used to adjust the transmission delay of the DQS timing signal or the DQ data signal, wherein the DQS timing signal and the DQ data signal are interaction signals between the memory controller and the memory chip; A control module is used to obtain an initial transmission delay range, wherein the initial transmission delay range is the theoretical transmission delay range for correctly transmitting DQ data; and to control the delay adjustment module to adjust the transmission delay of the DQS timing signal or DQ data signal based on the initial transmission delay range, and to determine the target transmission delay range for actually correctly transmitting DQ data from the initial transmission delay range, wherein the target transmission delay range is less than or equal to the initial transmission delay range.

10. The memory controller according to claim 9, characterized in that, The control module is specifically used for: The target transmission delay range for correctly transmitting DQ data is determined from the initial transmission delay range using a binary search method.

11. The memory controller according to claim 10, characterized in that, The control module is specifically used for: The initial transmission delay range is divided into two parts from the middle position, namely a first interval and a second interval, wherein neither the first interval nor the second interval contains the middle value of the initial transmission delay range; it is determined whether the first interval includes the first transmission delay range for correctly transmitting DQ data; if the first interval does not include the first transmission delay range for correctly transmitting DQ data, the target transmission delay range for correctly transmitting DQ data is determined from the second interval.

12. The memory controller according to claim 11, characterized in that, If the first interval includes a first transmission delay range for correctly transmitting DQ data, the control module is specifically used for: Determine whether the median value of the initial transmission delay range can correctly transmit DQ data; If the median value of the initial transmission delay range cannot correctly transmit DQ data, the first transmission delay range is determined to be the target transmission delay range; If the median value of the initial transmission delay range can correctly transmit DQ data, a second transmission delay range for correctly transmitting DQ data is determined from the second interval; the target transmission delay range is determined based on the first transmission delay range, the median value of the initial transmission delay range, and the second transmission delay range.

13. The memory controller according to claim 10, characterized in that, The control module is specifically used for: The initial transmission delay range is divided into two parts from the middle position, namely the first interval and the second interval, wherein neither the first interval nor the second interval contains the middle value of the initial transmission delay range; Determine whether the median value of the initial transmission delay range can correctly transmit DQ data; If the median value of the initial transmission delay range can correctly transmit DQ data, the first transmission delay range and the second transmission delay range for correctly transmitting DQ data are determined from the first interval and the second interval, respectively. The target transmission delay range is determined based on the first transmission delay range, the median value of the initial transmission delay range, and the second transmission delay range.

14. The memory controller according to claim 13, characterized in that, If the median value of the initial transmission delay range cannot correctly transmit DQ data, the control module is specifically used for: If the first interval includes a first transmission delay range for correctly transmitting DQ data, then the first transmission delay range is determined to be the target transmission delay range; If the first interval does not include the first transmission delay range for correctly transmitting DQ data, the target transmission delay range for correctly transmitting DQ data is determined from the second interval.

15. A processor, characterized in that, include: The processor core and the memory controller as described in any one of claims 9-14; The processor core is used to send training instructions to the memory controller; The memory controller is used to perform memory training in response to the training instructions.

16. An electronic device, characterized in that, include: The memory chip and the processor as described in claim 15, wherein the memory chip is connected to the memory controller in the processor.

17. An electronic device, characterized in that, include: The processor, the memory chip, and the memory controller as described in any one of claims 9-14, wherein the memory controller is connected to the processor and the memory chip, respectively; The processor is used to send training instructions to the memory controller; The memory controller is used to perform memory training in response to the training instructions.

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