A device and method for multi-level message caching of distributed communication equipment

Abstract

The present invention relates to the field of communication technology, and in particular to a device and method for multi-level message caching of distributed communication equipment. It includes a TM chip, and at least one group of PP chips and PIC chips. Specifically: the TM chip is connected to the switching network, sends the service message to the PP chip, and controls the sending and pausing of the service message according to the first flow control signal of the PP chip; the PP chip is the back stage of the TM chip, the PP chip processes the service message, controls the sending and pausing of the traffic according to the second flow control signal of the PIC chip, and sends the corresponding first flow control signal to the TM chip according to its own cached data volume; the PIC chip is the back stage of the PP chip, connected to the physical port of the panel, processes the physical port of the panel, and sends the corresponding second flow control signal to the PP chip according to its own cached data volume, so that the traffic lower than the panel port rate does not enter the cache. The present invention can meet the requirements of the 5G bearer network for port cache delay and solve the problem of single-chip cache bottleneck.

Description

[Technical field]

[0001] The present invention relates to the field of communication technology, and in particular to a device and method for multi-level message caching of distributed communication equipment. [Background technology]

[0002] Large video services such as short videos, live TV, HD video on demand, and virtual reality (VR) are the main application scenarios in the early stages of 5G development. One of the key technologies for these video services is the large-scale message cache of 5G bearer network equipment. Only sufficient message cache can support smooth HD video playback6. When 5G networks carry large video services such as short videos, live TV, HD video on demand, and VR, according to the statistics of various operators, communication equipment needs to have the ability to cache 60ms messages on ports to ensure smooth playback of various HD videos.

[0003] Taking the 800G service disk most commonly used in the core equipment of operators as an example, a single port rate of 100Gbits / s and a message buffering capacity of 60ms are required. Calculate the buffering requirements of a service disk:

[0004] 1*10 11 bits / s*6*10 -2 s*8=6*10 9 bits*8=6G Bytes.

[0005] That is, a business disk requires 6GB of cache to meet the demand.

[0006] On the other hand, the maximum on-chip cache of all current commercial switch chips is less than 1GB, far from the 6GB specification. If the cache is expanded by external DDR, it can only reach 4GB, which is still a long way from the 6GB capacity. Moreover, the expansion of the DDR specification outside the single chip also greatly increases the hardware cost of the equipment.

[0007] At present, the cache of all single commercial chips in the industry cannot meet the cache time requirement of 60ms cache of 100G port proposed by the operator. If the equipment does not meet the packet cache time required by the operator's technical specifications, centralized procurement will result in a deduction or veto; this has resulted in the unavailability of new functions such as video on demand in 5G engineering scenarios.

[0008] In view of this, how to overcome the defects of the prior art and solve the problem that the current single-chip cache cannot meet the usage requirements is a problem to be solved in this technical field. [Summary of the invention]

[0009] In view of the above defects or improvement requirements of the prior art, the present invention solves the problem that the existing single-chip cache capacity cannot meet the requirements.

[0010] The embodiment of the present invention adopts the following technical solution:

[0011] In the first aspect, the present invention provides a multi-level message cache device of a distributed communication device, specifically comprising: a TM chip 1, and at least one group of PP chips 2 and PIC chips 3, wherein the TM chip 1 is connected to a switching network, sends service messages to the PP chip 2, and controls the sending and pausing of the service messages according to a first flow control signal of the PP chip 2; the PP chip 2 is a subsequent stage of the TM chip 1, the PP chip 2 processes the service messages, controls the sending and pausing of the traffic according to a second flow control signal of the PIC chip 3, and sends a corresponding first flow control signal to the TM chip 1 according to the amount of data cached by itself; the PIC chip 3 is a subsequent stage of the PP chip 2, is connected to a physical port of a panel, processes the physical port of the panel, and sends a corresponding second flow control signal to the PP chip 2 according to the amount of data cached by itself, so that traffic lower than the panel port rate does not enter the cache.

[0012] Preferably, the method further comprises: the TM chip 1 and each PP chip 2 , and each group of PP chips 2 and the PIC chip 3 are connected via a channel of an Interlaken port of chip interconnection.

[0013] Preferably, the method further comprises: the PIC chip 3 is connected to an external DDR expansion cache 4 to expand the cache capacity of the PIC chip 3 .

[0014] On the other hand, the present invention provides a method for multi-level message caching of a distributed communication device, specifically: connecting the TM chip in the multi-level message caching device of the distributed communication device provided in the first aspect to a switching network; configuring a flow control threshold for each chip, and each chip sends a flow control signal to the previous chip when the amount of data cached by itself reaches its own flow control threshold, so as to control the previous chip to stop sending traffic, so that traffic lower than the panel port rate does not enter the cache.

[0015] Preferably, configuring a flow control threshold for each chip specifically includes: calculating the flow control threshold of each chip according to the port rate, the maximum buffer of the port and the flow control reaction time of the chip.

[0016] Preferably, each chip sends a flow control signal to the preceding chip when the amount of data cached in the chip reaches its own flow control threshold, specifically including: when the message cache of the PIC chip reaches its own flow control threshold, triggering the PIC chip to send a second flow control signal to the PP chip; the PP chip stops sending traffic after receiving the second flow control signal, and the unsent traffic is cached in the PP chip.

[0017] Preferably, each chip sends a flow control signal to the preceding chip when the amount of data in its own cache reaches the flow control threshold, specifically including: when the message cache of the PP chip reaches its own flow control threshold, triggering the PP chip to send a first flow control signal to the TM chip; after receiving the first flow control signal, the TM chip stops sending traffic, and the unsent service messages are cached in the TM chip.

[0018] Preferably, each chip sends a flow control signal to the preceding chip when the amount of data in its own cache reaches the flow control threshold, specifically including: configuring a meter at the egress of the PP chip, setting the PHB of the message exceeding the panel port rate to 0, and then mapping it to the cos field of the private message header and sending it to the PIC chip; giving priority to scheduling the flow below the panel port rate, the flow below the panel port rate does not enter the cache, and the flow exceeding the panel port rate enters the cache of the PP chip.

[0019] Preferably, the method further comprises: configuring CIR and / or PIR in each channel of the PP chip according to the receiving bandwidth and chip processing capability of the PIC chip.

[0020] Preferably, the method further includes: configuring a meter at the egress of the PP chip, setting the PHB of the message exceeding the CIR to a low priority, and then mapping it to the cos field of the private VLAN in the message header and sending it to the PIC chip; when the PIC chip sends traffic from the panel port, stripping the private VLAN in the traffic and restoring the service message.

[0021] Compared with the prior art, the beneficial effect of the embodiment of the present invention is that: the present invention proposes a new multi-level cache implementation method, which adopts a multi-level chip linkage configuration cache, triggers a multi-level flow control method, effectively expands the packet cache capacity of a single board, and can meet the requirements of the 5G bearer network for port cache latency. At the same time, it solves the bottleneck problem of single-chip cache, no longer relies on the high cache of a single chip, reduces the device's requirements for chip specifications, and also reduces the device cost.

Brief Description of the Drawings

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0023] Figure 1 A schematic diagram of a device architecture of a multi-level message cache of a distributed communication device provided by an embodiment of the present invention;

[0024] Figure 2 A schematic diagram of the device architecture of a multi-level message cache of another distributed communication device provided by an embodiment of the present invention;

[0025] Figure 3 A schematic diagram of the device architecture of a multi-level message cache of another distributed communication device provided by an embodiment of the present invention;

[0026] Figure 4 A flow chart of a method for multi-level message caching of a distributed communication device provided in an embodiment of the present invention;

[0027] Figure 5 A schematic diagram of the connection relationship of devices in a method for multi-level message caching of a distributed communication device provided by an embodiment of the present invention;

[0028] Figure 6 A schematic diagram of flow control signal transmission in a multi-level message caching method of a distributed communication device provided in an embodiment of the present invention. [Specific implementation method]

[0029] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0030] The present invention is an architecture of a specific functional system, so the specific embodiments mainly illustrate the functional logical relationship between the various structural modules, and do not limit the specific software and hardware implementation methods.

[0031] In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other. The present invention will be described in detail below with reference to the accompanying drawings and embodiments.

[0032] Some terms used in the embodiments of the present invention are explained as follows:

[0033] (1) Packet buffer: Most switches now use the store-and-forward mode. The so-called store-and-forward mode is that the switch receives data packets, starting from the preamble code to the CRC at the end of the packet. After the packet is received, the forwarding process is started. Before starting the forwarding, these data packets must be stored in the switch cache. This is the store-and-forward mode. The packet buffer is like a pool with an outlet pipe and an inlet pipe. When the inlet pipe is opened large and the outlet pipe is opened small, the water in the pool will fill up quickly until it overflows. If the inlet pipe is opened small and the outlet pipe is opened large, there will be almost no water in the pool, but the water flow rate will be slow. This is a process of weighing the pros and cons.

[0034] (2) Flow control: The flow control mentioned in this article is a software flow control, namely the XON / XOFF asynchronous communication protocol. The receiving device uses special characters to control the data flow of the sending device. When the receiving end on the communication line is overloaded, it sends an XOFF character to the sending end. After receiving the XOFF character, the sending end stops sending data. After the receiving end processes the data in the buffer and the overload is restored, it sends another XON character to the sending end to notify the sending end to resume data transmission. During a data transmission process, the XOFF and XON cycles can be repeated multiple times.

[0035] (3) Channel: A subchannel within an interlaken port.

[0036] (4) PIC: Physical Interface Card, physical interface card.

[0037] (5)PP: Packet Process.

[0038] (6) TM: Traffic Manage.

[0039] (7) PIR: Peak Information Rate, which generally refers to the peak rate provided to users.

[0040] (8) CIR: Committed Information Rate, generally refers to the guaranteed rate provided to users.

[0041] Embodiment 1:

[0042] In this embodiment, a plurality of chips with different functions are used to form a multi-level cache, and multi-level flow control is triggered by linkage between the multiple chips to expand the packet cache capacity of the single board.

[0043] like Figure 1 As shown, it is a schematic diagram of chip connection of a typical communication equipment service board of a device for multi-level message caching of a distributed communication device provided in this embodiment. In the device provided in this embodiment, each single board is connected by multi-level chips, including a TM chip 1, and at least one group of PP chips 2 and PIC chips 3. Each group of PP chips 2 and PIC chips 3 are connected in series and connected to an interface of the TM chip 1 to complete the parsing and processing of the message and the physical interface transmission and reception. Each group of PP chips 2 and PIC chips 3 is connected in parallel to realize the processing and forwarding of multiple groups of messages without interference, thereby improving the bandwidth of the single board.

[0044] When acquiring and forwarding messages, TM chip 1 is connected to the backplane of the single board card and serves as the control chip for the service message traffic of other chips in the single board card. The scheduling of message sending and receiving queues is implemented in TM chip 1. PIC chip 3 has an out-of-panel port, which is connected to the external physical interface. The conversion of various physical interfaces is implemented in PIC chip 3. PP chip 2 is between the two. Message parsing, encapsulation / decapsulation and other processing are implemented in PP chip 2.

[0045] In this embodiment, the TM chip 1, the PP chip 2 and the PIC chip 3 have dual bidirectional connections of data lines and control lines. Through the data lines, bidirectional forwarding of service messages can be achieved. Through the control lines, the PP chip 2 and the PIC chip 3 can send their respective status information to the TM chip 1. According to the received status signal, the TM chip 1 sends corresponding flow control signals to the PP chip 2 and the PIC chip 3 to control the flow adjustment of the multi-stage chip linkage. Specifically, the TM chip 1 is connected to the switching network, sends the service message to the PP chip 2, and controls the sending and pausing of the service message according to the first flow control signal of the PP chip 2. The PP chip 2 is the back stage of the TM chip 1. The PP chip 2 processes the service message, controls the sending and pausing of the flow according to the second flow control signal of the PIC chip 3, and sends the corresponding first flow control signal to the TM chip 1 according to the amount of data cached by itself. The PIC chip 3 is the back stage of the PP chip 2, connected to the physical port of the panel, processes the physical port of the panel, and sends the corresponding second flow control signal to the PP chip 2 according to the amount of data cached by itself, so that the flow lower than the panel port rate does not enter the cache.

[0046] When the service traffic enters the service card from the backplane, the service message is forwarded to the PP chip 2 via the data line of the TM chip 1, enters the message processing queue in the cache of the PP chip 2, and then the PP chip 2 performs message parsing, label encapsulation or decapsulation and other operations in sequence. Usually, the processing capacity of the TM chip 1 is greater than that of the PP chip 2. Therefore, it is possible that the sending rate of the TM chip 1 is greater than the processing rate of the PP chip 2, resulting in the PP chip 2 cache being full, and the data packets of the service message cannot enter the cache of the PP chip 2, resulting in packet loss. At this time, the PP chip 2 can send a first flow control signal to the TM chip 1 through the control line. After receiving the first flow control signal, the TM chip 1 stops sending service messages, avoiding packet loss caused by the PP chip 2 cache being full.

[0047] Similarly, after the service message is processed by PP chip 2, it is forwarded to PIC chip 3 through the data line, enters the physical interface forwarding queue in the cache of PIC chip 3, and then PIC chip 3 performs the connection and forwarding operations of the corresponding texture interface in sequence. Usually, the processing capacity of PP chip 2 is greater than that of PIC chip 3. Therefore, it is possible that the sending rate of PP chip 2 is greater than the processing rate of PIC chip 3, resulting in the cache of PIC chip 3 being full, and the data packets of the service message cannot enter the cache of PIC chip 3, resulting in packet loss. At this time, PIC chip 3 can send a second flow control signal to PP chip 2 through the control line, and PP chip 2 stops sending service messages after receiving the first flow control signal, thereby avoiding packet loss caused by the full cache of PIC chip 3.

[0048] Through the linkage flow control of the above-mentioned multi-chips, the reception, processing, and physical port forwarding of business messages are allocated to three dedicated chips. Each chip has a corresponding cache. In addition, the processing speeds of the three chips are balanced through the linkage flow control of the multiple chips, which fully utilizes the cache capacity of the three chips, improves the cache utilization of the three chips, and avoids packet loss in business message forwarding without relying on the high cache of a single chip.

[0049] In this embodiment, for the multi-level chips on the same data path, both reliable data packet transmission of service messages and control signal transmission are required. In actual implementation, this may be achieved by connecting different pins of the chip. Figure 2 As shown, in the preferred solution of this embodiment, the TM chip 1 and each PP chip 2, as well as each group of PP chips 2 and PIC chips 3, are connected through the channel of the chip interconnected Interlaken port. Interlaken (abbreviated as ILK) is a high-speed channelized C2C interface protocol, an interconnection protocol optimized for high-bandwidth and reliable packet transmission. The protocol uses multiple serial links to establish logical connections between devices, and utilizes multi-channels, back pressure capabilities and data integrity protection to improve the performance of communication equipment. In the device provided in this embodiment, the characteristics of Interlaken can be utilized to achieve multiple groups of high-speed data throughput, and the back pressure capability can be utilized to achieve the triggering and response of the flow control signal between each group of chips, so as to realize a dynamically linked multi-level cache. Ideally, the bandwidth of each pair of Interlake pins is 800Mbps, which can enable the throughput of the device to reach 10Gbps, which can meet the user's usage requirements.

[0050] In a specific implementation scenario, each panel port of the switching network corresponds to an ILK channel, and the panel port rate is M. Since the ILK bandwidth is usually 1.5 times the port rate, that is, 150G / 300G / 600G corresponds to 100G / 200G / 400G port, excluding overhead, the utilization rate is 0.8; 1.5*0.8=1.2, then the channel bandwidth configured for TM chip 1 and PP chip 2 is 1.2*M.

[0051] In the usage scenario of 10G / 25G / 50G / 100G / 200G / 400G, it is assumed that the flow control reaction time of PP chip 2 is T1(s), the flow control reaction time of TM chip 1 is T2(s), the port buffer of PIC chip 3 is B1(Gb), the port buffer of PP chip 2 is B2(Gb), and the port rate of the egress port is N. In actual use, appropriate models can be selected for each functional chip as needed, for example: TM chip 1 uses J+ chip, PP chip 2 uses NP chip, PIC chip 3 uses Q2A chip, and other chip models that can implement the method provided in this embodiment and meet the communication performance requirements can also be selected.

[0052] To prevent packet loss before the cache of each chip is full and to avoid triggering frequent flow control of multiple chips, the port reserved buffer space of PIC is calculated using the difference between the port maximum buffer and the back pressure threshold. The buffer space is set to the sum of the traffic within the flow control reaction time of TM chip 1 and PP chip 2. The port reserved buffer space of PP chip 2 should be the traffic within the flow control reaction time of TM chip 1.

[0053] In order to prevent packet loss due to the response time, actual tests are performed based on the above data, and the back pressure threshold of the buffer of PIC chip 3 can be obtained as: (B1-(1.2NN)*T1-1.2N*T2) / B1*80%. Among them, B1 is the port buffer size of PIC chip 3, N is the port rate of the egress port, T1 is the flow control response time of PP chip 2, and T2 is the flow control response time of TM chip 1.

[0054] Similarly, the back pressure threshold of the cache of PP chip 2 is: (B2-1.2N*T2) / B2*80%.

[0055] Configure the egress meter of PP chip 2. The CIR of the meter is the port bandwidth, and the PIR is the channel bandwidth between chips. When the service message traffic enters PIC chip 3 from the NP chip, according to the CIR and PIR configuration, the traffic that is less than the egress rate will not enter the cache of PIC chip 3; the priority of the burst traffic that exceeds the egress rate is reduced and occupies the cache of PIC chip 3. When the cache reaches the back pressure threshold, the PIC is triggered to send a flow control signal to the PP. PP chip 2 receives the flow control, reduces the sending rate, and the service message is cached in PP chip 2. When the cache reaches the PP back pressure threshold, the PP is triggered to send a flow control signal to the TM. TM receives the flow control, reduces the sending rate, and the message is cached in TM chip 1, thus forming a multi-level cache.

[0056] In actual use, in order to further expand the cache capacity of the single board card, the chip cache can also be expanded through external DDR. Figure 3 For example, the PIC chip 3 is connected to the external DDR expansion cache 4 to expand the cache capacity of the PIC chip 3. Other chips can also use the external DDR for cache expansion to further improve the overall cache capacity of the single board.

[0057] This embodiment provides a device for multi-level message caching of a distributed communication device, which uses multi-level chip splicing and inter-chip linkage to configure flow control thresholds to achieve multi-level back pressure and multi-level caching, thereby improving the overall cache capacity of the system and no longer relying on a single chip external large-specification DDR to meet the port large cache requirements of 5G business scenarios. Compared with the existing multi-level cache implementation method, the device provided in this embodiment can cache messages in chips regardless of the storage medium type when the system encounters a traffic burst, reducing the specification requirements for a single chip and improving the utilization of hardware resources.

[0058] Embodiment 2:

[0059] Based on the apparatus for multi-level message caching of a distributed communication device provided in the above-mentioned embodiment 1, the present invention further provides a method for performing message caching by using the above-mentioned apparatus.

[0060] like Figure 4 As shown, the method for multi-level message caching of a distributed communication device provided by an embodiment of the present invention has the following specific steps:

[0061] Step 101: Use the TM chip in the multi-level message buffering device of the distributed communication equipment provided in Example 1 to connect to a switching network.

[0062] Using the device provided in Example 1, multi-level chip connection is realized on the service board of the distributed device. Figure 5As shown: the TM chip is connected to the switching network and is used for traffic management of the entire service board. The PP chip is located before the TM and is used for message processing, such as message parsing, encapsulation / decapsulation labeling, etc. The PIC chip is located before the TM and is used for physical port processing of various rates on the panel, such as 10G / 25G / 50G / 100G port mixing, ETH and FLEXE port switching, etc. In the general implementation scenario of this embodiment, the processing capacity of the TM chip > the processing capacity of the PP chip > the processing capacity of the PIC chip.

[0063] Step 102: Configure a flow control threshold for each chip. When the amount of data in its own cache reaches its own flow control threshold, each chip sends a flow control signal to the previous chip to control the previous chip to stop sending traffic, so that traffic lower than the panel port rate does not enter the cache.

[0064] In order to further improve the single-port rate, the chips in the device provided in Example 1 are preferably interconnected by Interlaken, and each panel port of the PIC chip is correspondingly configured with a channel of the chip-interconnected Interlaken port. When the service traffic enters the service card from the backplane, the service flow is from the TM chip to the PP chip, and then from the PP chip to the PIC chip. When the bandwidth of the channel on the PIC chip is less than the panel port rate, the service traffic is directly dispatched and forwarded by the corresponding chip and does not enter the chip cache. Figure 6 As shown in the figure, when the bandwidth of the channel on the PIC chip is greater than the panel port rate, the service traffic burst is greater than the panel port rate, causing congestion of the PIC chip. All service messages sent from the PP chip to the PIC chip are congested in the PIC chip, occupying the cache of the PIC chip. At this time, the PIC chip sends its own corresponding second flow control signal to the PP chip at the previous level. After receiving the flow control signal, the PP chip stops sending traffic to avoid packet loss caused by buffer fullness. At the same time, since the PP chip stops sending traffic to the PIC chip, the received and processed service messages are retained in the cache of the PP chip. Since the PP chip is still continuously receiving data messages sent by the TM chip, all service messages sent from the TIM chip to the PP chip are congested in the PP chip, which may cause the cache of the PP chip to be full. Therefore, the PP chip also needs to send the first flow control signal to the TM chip when the cache capacity reaches the preset flow control threshold, so that the TM chip stops sending service traffic. On the other hand, when the amount of cache data in the PP chip and the PIC chip is reduced to a certain extent, the TM chip and the PP chip begin to resume data transmission to transmit message data in time.

[0065] After step 101-step 102 provided in this embodiment, the device provided in Example 1 can be used to control the flow control signal between multiple chips to adjust the storage location of the current cache data, so that the subsequent chip can also cache the data of the previous chip, without distinguishing any message content or any storage medium, and only regulating according to the real-time traffic size to realize the function of multiple cache pools.

[0066] In actual use, in order to achieve the best coordination effect between the caches of multi-level chips, it is also necessary to calculate the flow control threshold of each chip based on the port rate, maximum port cache and flow control reaction time of the chip.

[0067] Generally, the Interlaken bandwidth corresponding to the 100G / 200G / 400G panel port is 150G / 300G / 600G, that is, the Interlaken bandwidth is 1.5 times the port bandwidth. Excluding the Interlaken protocol overhead, the bandwidth utilization is 80%. Assuming that the PIC chip panel port bandwidth is N, each panel port corresponds to an Interlaken channel, the calculated configured channel bandwidth is:

[0068] N*1.5*80%=1.2*N

[0069] like Figure 6 As shown in the figure, in order to prevent packet loss before the cache of each chip is full, each chip needs to be configured with a flow control threshold. The flow control signal is triggered before the port cache is full, and the traffic transmission of the interconnected chip is stopped. The difference between the maximum cache of the port and the flow control threshold is called the port reserved cache:

[0070] Port reserved buffer = port maximum buffer - flow control threshold

[0071] Assume that the flow control response time of the PP chip is T1(s), the flow control response time of the J+ chip is T2(s), the port buffer of the PIC chip is B1(Gbits), the port buffer of the PP chip is B2(Gbits), the port buffer of the TM chip is B3(Gbits), and the port rate of the panel port is N.

[0072] Then the flow rate received by the PIC chip during the flow control reaction time of the PP chip is:

[0073] (1.2N (PIC channel receiving rate) - 1N (PIC panel port sending rate)) * T1

[0074] The flow rate received by the PP chip during the flow control response time of the TM chip is:

[0075] (1.2N (PP channel receiving rate) - 0 (PP stops sending after receiving flow control)) * T2

[0076] The reserved buffer of the PIC chip port should be configured as the sum of the flow control reaction time flow of the PP chip and the TM chip, which is calculated according to the above formula:

[0077] PIC port reserved buffer = (1.2NN)*T1+1.2N*T2

[0078] The port reserved buffer of the PP chip should be configured as the flow control reaction time flow of the TM chip:

[0079] PP port reserved buffer = B2-1.2N*T2

[0080] In addition, to prevent packet loss caused by buffer configuration and chip flow control reaction time, the redundancy factor is 80% based on multiple experimental data.

[0081] In summary, the flow control threshold (calculated as a percentage) of the PIC chip port cache is configured as follows:

[0082] (B1-(1.2NN)*T1-1.2N*T2) / B1*80%

[0083] The flow control threshold configuration of the PP chip cache is:

[0084] (B2-1.2N*T2) / B2*80%

[0085] At this point, the single-port buffer space of the entire service card reaches:

[0086] (B1-(1.2NN)*T1-1.2N*T2)*80%+(B2-1.2N*T2)*80%+B3

[0087] From the above calculations, it can be seen that through reasonable flow control threshold limits between multiple chips, the amount of data cached in each chip can be dynamically adjusted, thereby achieving a dynamic balance of data volume among the three chips. This can not only fully utilize the cache capacity of the three chips, but also ensure that there will be no packet loss due to cache fullness, thereby ensuring the stability of data transmission.

[0088] In the method provided in this embodiment, each chip sends a flow control signal to the previous chip according to its own cache capacity to inform the previous chip to send or stop sending traffic. When the amount of cached data is lower than the flow control threshold, it indicates that there is sufficient free storage space in the cache of the chip at this level, and the previous chip sends normally to make full use of the cache space of the chip at this level; when the amount of cached data is higher than the flow control threshold, it indicates that the cache of the chip at this level is about to be full, and the previous chip stops sending to avoid packet loss due to cache fullness. The specific processing method of each chip is as follows.

[0089] (1) PIC chip: When the message buffer of the PIC chip reaches its own flow control threshold, the PIC chip is triggered to send a second flow control signal to the PP chip; after receiving the second flow control signal, the PP chip stops sending traffic, and the unsent traffic is buffered in the PP chip.

[0090] According to the above calculation process, a flow control threshold is configured for the message buffer of the PIC chip. When the message buffer reaches the flow control threshold, the PIC chip is triggered to send a flow control signal XOFF to the PP chip. After receiving XOFF, the PP chip stops sending traffic.

[0091] (2) When the message buffer of the PP chip reaches its own flow control threshold, the PP chip is triggered to send a first flow control signal to the TM chip; after receiving the first flow control signal, the TM chip stops sending traffic, and the unsent service messages are buffered in the TM chip.

[0092] According to the above calculation process, a flow control threshold is configured for the message buffer of the PP chip. When the message buffer reaches the flow control threshold of the PP chip, the PP chip is triggered to send a flow control signal XOFF to the TM chip. After receiving XOFF, the TM chip stops sending traffic, and finally all service messages are buffered in the TM chip.

[0093] Through the above method, the usage of the cache between the three-level chips can be adjusted to make full use of the cache of the three-level chip, rather than indiscriminately sending all data to the subsequent chip, causing the cache of the subsequent chip to be full and causing packet loss.

[0094] In addition, in general, the receiving bandwidth of the PIC chip is greater than the chip processing capacity. If the receiving traffic rate is greater than the chip processing capacity and the traffic has no priority distinction, the message will be fully cached and then forwarded. In this process, the problem of packet loss will occur after the cache access bandwidth exceeds the chip processing capacity. To solve this problem, the message can be scheduled in a hierarchical manner. Configure meter at the egress of the PP chip, set the PHB of the message that exceeds the panel port rate to 0, and then map it to the cos field of the private message header and send it to the PIC chip. When processing burst traffic, the chip will prioritize the traffic that is lower than the panel port rate. The traffic that is lower than the panel port rate will not enter the cache, but will be directly processed and forwarded. The traffic that exceeds the panel port rate will enter the cache of the PP chip. In this way, only a part of the traffic can enter the cache, saving cache space, avoiding the problem of packet loss after the cache access bandwidth exceeds the chip processing capacity due to the need for all burst traffic to enter the cache, and also avoiding the reduction in forwarding efficiency due to the message being written into the cache and then read out.

[0095] Specifically, configure the egress meter of the PP chip. The CIR of the meter is the port bandwidth, and the PIR is the channel bandwidth of Interlaken used by the chip. The meter colors the message according to the traffic. The traffic that is less than the egress rate of the PP chip is green, and the traffic that is greater than the egress rate of the PP chip is red and yellow. Then set the PHB of the yellow and red messages to 0 and map it to the COS field of the private VLAN of the message. The PIC chip strips off the private VLAN when sending traffic. When the traffic enters the PIC chip from the NP, according to the CIR and PIR configuration, the traffic that is less than the egress rate is green and will not enter the PIC chip cache; the priority of the burst traffic that exceeds the egress rate is reduced, and it occupies the PIC chip cache. When the cache reaches the flow control threshold, the PIC chip is triggered to send a back pressure flow control signal to the PP chip. After receiving the flow control signal, the PP reduces the sending rate and the message is cached in the PP chip. When the cache reaches the flow control threshold of the PP chip, the PP chip is triggered to send a back pressure flow control signal to the TM chip. The TM chip receives the flow control, reduces the sending rate, and the message is cached in the TM chip, thus forming a multi-level cache.

[0096] In order to regulate the traffic problem of the PP chip, CIR and PIR are configured in each channel of the PP chip according to the receiving bandwidth and chip processing capacity of the PIC chip. The effect of configuring CIR / PIR is to set the PHB of the message with bandwidth greater than N to 0, and set the PHB of the message with bandwidth less than or equal to N to 7 and map it to the COS field of the private VLAN in the message header. When the PIC chip processes a burst, it will give priority to scheduling the traffic with COS of 7. This part of the traffic will not enter the cache, and only the traffic with COS of 0 may enter the cache. In this way, the bandwidth for accessing the cache will not exceed the chip processing capacity. In the specific implementation, according to the actual usage, the preferred configuration is: CIR = N, PIR = 1.2N. Among them, N is the port rate of the panel port.

[0097] After configuring CIR and PIR, since PHB is mapped to the COS field of the private VLAN in the packet header, when the PIC chip sends traffic from the panel port, it is also necessary to strip off the private VLAN to restore the service message. Configure meter at the egress of the PP chip, set the PHB of the message exceeding CIR to a low priority, and then map it to the cos field of the private VLAN in the packet header and send it to the PIC chip. When the PIC chip sends traffic from the panel port, it strips off the private VLAN in the traffic and restores the service message.

[0098] The multi-level message caching method of the distributed communication device provided in this embodiment can effectively expand the packet cache capacity of the single board card, no longer require high cache requirements for a single chip, reduce the device's requirements for chip specifications, and indirectly reduce costs.

[0099] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A multi-level message caching device for distributed communication equipment, characterized in that: The invention comprises a TM chip (1), and at least one group of a PP chip (2) and a PIC chip (3), specifically: The TM chip (1) is connected to the switching network, sends the service message to the PP chip (2), and controls the sending and suspension of the service message according to the first flow control signal of the PP chip (2); The PP chip (2) is a subsequent stage of the TM chip (1). The PP chip (2) processes the service message, controls the sending and pausing of the flow according to the second flow control signal of the PIC chip (3), and sends a corresponding first flow control signal to the TM chip (1) according to the amount of data cached by itself; The PIC chip (3) is a subsequent stage of the PP chip (2), connected to the physical port of the panel, processes the physical port of the panel, and sends a corresponding second flow control signal to the PP chip (2) according to the amount of data cached by itself, so that the flow rate lower than the panel port rate does not enter the cache; Each chip needs to be configured with a flow control threshold. Before the port buffer is full, the flow control signal is triggered to stop the traffic transmission of the interconnected chip. The difference between the maximum port buffer and the flow control threshold is called the port reserved buffer: port reserved buffer = port maximum buffer - flow control threshold; The port reserved buffer of the PIC chip should be configured as the sum of the flow control reaction time flow of the PP chip and the TM chip; the port reserved buffer of the PP chip should be configured as the flow control reaction time flow of the TM chip.

2. The apparatus for multi-level message caching of a distributed communication device according to claim 1, characterized in that: Also includes: The TM chip (1) and each PP chip (2), as well as each group of PP chips (2) and the PIC chip (3), are connected via channels of the Interlaken ports of chip interconnection.

3. The apparatus for multi-level message caching of a distributed communication device according to claim 1, characterized in that: Also includes: The PIC chip (3) is connected to an external DDR expansion buffer (4) to expand the buffer capacity of the PIC chip (3).

4. A method for multi-level message caching of a distributed communication device, characterized in that: Connecting the TM chip in the multi-level message cache device of any one of claims 1 to 3 to a switching network; A flow control threshold is configured for each chip. When the amount of data in its own cache reaches its own flow control threshold, each chip sends a flow control signal to the previous chip to control the previous chip to stop sending traffic, so that traffic lower than the panel port rate does not enter the cache.

5. The method for multi-level message caching of distributed communication equipment according to claim 4, characterized in that: The configuration of the flow control threshold for each chip specifically includes: The flow control threshold of each chip is calculated according to the port rate, maximum port buffer and flow control reaction time of the chip.

6. The method for multi-level message caching of a distributed communication device according to claim 4, characterized in that: When the amount of data cached by each chip reaches its own flow control threshold, the chip sends a flow control signal to the preceding chip, specifically including: When the message buffer of the PIC chip reaches its own flow control threshold, the PIC chip is triggered to send a second flow control signal to the PP chip; After receiving the second flow control signal, the PP chip stops sending traffic, and the unsent traffic is buffered in the PP chip.

7. The method for multi-level message caching of a distributed communication device according to claim 4, characterized in that: When the amount of data cached by each chip reaches the flow control threshold, the chip sends a flow control signal to the preceding chip, specifically including: When the message buffer of the PP chip reaches its own flow control threshold, the PP chip is triggered to send a first flow control signal to the TM chip; After receiving the first flow control signal, the TM chip stops sending traffic, and the unsent service messages are buffered in the TM chip.

8. The method for multi-level message caching of a distributed communication device according to claim 4, characterized in that: When the amount of data cached by each chip reaches the flow control threshold, the chip sends a flow control signal to the preceding chip, specifically including: Configure meter at the egress of the PP chip, set the PHB of the message that exceeds the panel port rate to 0, and then map it to the cos field in the private message header and send it to the PIC chip; Prioritize the scheduling of traffic that is lower than the panel port rate. Traffic that is lower than the panel port rate does not enter the cache, and traffic that exceeds the panel port rate enters the cache of the PP chip.

9. The method for multi-level message caching of a distributed communication device according to claim 4, characterized in that: Also includes: According to the receiving bandwidth and processing capability of the PIC chip, CIR and / or PIR are configured on each channel of the PP chip.

10. The method for multi-level message caching of distributed communication equipment according to claim 9, characterized in that: Also includes: Configure meter at the egress of the PP chip to set the PHB of the packets exceeding the CIR to a low priority, and then map it to the cos field of the private VLAN in the packet header and send it to the PIC chip; When the PIC chip sends traffic from the panel port, it strips off the private VLAN in the traffic and restores the service message.

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