Three-dimensional memory devices with isolated source side lines and methods of manufacturing the same

Abstract

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers over at least one source layer; and a set of memory opening fill structures vertically extending through the alternating stack. Each memory opening fill structure can include a vertical stack of memory elements and a vertical semiconductor channel. A plurality of source side select gate electrodes can be laterally spaced apart by a source select level dielectric isolation structure. Alternatively or additionally, the at least one source layer can include a plurality of source layers. A set of memory opening fill structures can be selected by a select source layer and / or by a select source level electrically conductive layer.

Description

[0001] Related applications

[0002] This application claims priority to U.S. non-provisional application No. 16 / 951,325 and U.S. non-provisional application No. 16 / 951,354, both filed November 18, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates in its entirety to the field of semiconductor devices, and more particularly to three-dimensional memory devices including separate source-side select lines and / or separate source lines, and methods for manufacturing the same. Background Technology

[0004] Each cell has a three-dimensional vertical NAND string with one bit, as disclosed in the article “Novel UltraHigh Density Memory With A Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell” by T. Endoh et al., IEDM Proc. (2001) 33-36. Summary of the Invention

[0005] According to another aspect of this disclosure, a three-dimensional memory device is provided, comprising: an alternating stack of insulating and conductive layers over a plurality of source layers, wherein the alternating stack is located between a pair of back-side trench fill structures; a group of memory openings extending vertically through the alternating stack; and a group of memory opening fill structures located within the group of memory openings, wherein each of the memory opening fill structures includes: a respective vertical stack of memory elements; a respective vertical semiconductor channel having a first end contacting a respective one of the plurality of source layers; and a respective drain region contacting a second end of the respective vertical semiconductor channel; wherein: the plurality of source layers are laterally spaced apart from each other and electrically isolated; and each group of memory opening fill structures contacts a respective one of the plurality of source layers.

[0006] According to another aspect of the present disclosure, a method of forming a three-dimensional memory device includes forming an alternating stack of insulating layers and spacer material layers over a substrate, wherein the spacer material layers are formed as or are subsequently replaced with electrically conductive layers; forming a set of memory openings through the alternating stack; forming a set of memory opening fill structures in the memory openings, wherein each of the set of memory opening fill structures includes a respective vertical stack of memory elements and a respective vertical semiconductor channel; forming a source-level material layer by thinning the substrate, by removing the substrate, or by replacing the substrate with at least one electrically conductive material layer; and forming a plurality of source layers by patterning the source-level material layer, wherein the plurality of source layers are laterally spaced apart from one another and electrically isolated, wherein each group of memory opening fill structures contacts a respective one of the plurality of source layers.

[0007] According to one aspect of the present disclosure, a three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers over at least one source layer and between a pair of backside trench fill structures; a set of memory openings vertically extending through the alternating stack; and a set of memory opening fill structures in the set of memory openings, wherein each of the memory opening fill structures includes: a respective vertical stack of memory elements; a respective vertical semiconductor channel having a first end contacting the at least one source layer; and a respective drain region contacting a second end of the respective vertical semiconductor channel; wherein the electrically conductive layers include: word lines continuously laterally extending between and contacting each of the pair of backside trench fill structures; and a plurality of source-side select gate electrodes between the at least one source layer and the word lines in a vertical direction and between the pair of backside trench fill structures in a horizontal direction, wherein the plurality of source-side select gate electrodes are laterally spaced apart by source-select-level dielectric isolation structures.

[0008] According to another aspect of the present disclosure, a method of forming a three-dimensional memory device is provided that includes forming an alternating stack of insulating layers and spacer material layers over a substrate, where the spacer material layers are formed as or are subsequently replaced with electrically conductive layers; forming a set of memory openings through the alternating stack; forming a set of memory opening fill structures in the memory openings, where each of the set of memory opening fill structures includes a respective vertical stack of memory elements, a respective vertical semiconductor channel, and a respective drain region; forming a source-level material layer by thinning the substrate or by replacing the substrate with at least one electrically conductive material layer, where each set of memory opening fill structures contacts a respective one of the plurality of source levels; and forming a plurality of source-side select gate electrodes by forming source-side trenches through a first subset of the electrically conductive layers either before or after forming the source-level material layer, where the source-side trenches do not divide a second subset of the electrically conductive layers. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1A is a vertical cross-sectional view of a first exemplary structure after a first vertical alternating sequence of first-tier insulating layers and first-tier sacrificial material layers is formed in accordance with a first embodiment of the present disclosure.

[0010] Figure 1B illustrates a layout of a semiconductor die within the first exemplary structure of Figure 1A

[0011] Figure 2 is a vertical cross-sectional view of a first exemplary structure after a first stepped surface is patterned and a first back-stepped dielectric material portion is formed on the first vertical alternating sequence in accordance with an embodiment of the present disclosure.

[0012] Figure 3A is a vertical cross-sectional view of a first exemplary structure after a first-tier set of memory openings and a first-tier set of support openings are formed in accordance with an embodiment of the present disclosure.

[0013] Figure 3B is a horizontal cross-sectional view of the first exemplary structure taken along a horizontal plane B-B’ in Figure 3A Figure 3A corresponds to the plane of the vertical cross-sectional view of

[0014] Figure 4 is a vertical cross-sectional view of a first exemplary structure after an optional pedestal channel portion is formed in each of the first-tier set of memory openings and the first-tier set of support openings in accordance with an embodiment of the present disclosure.

[0015] Figure 5A is a vertical cross-sectional view of a first exemplary structure after a first-tier set of sacrificial memory opening fill structures and a first-tier set of sacrificial support structures are formed in accordance with an embodiment of the present disclosure.​​

[0016] Figure 5B is a horizontal cross-sectional view of the first exemplary structure taken along the horizontal plane B-B’ in Figure 5A corresponds to the plane of the vertical cross-sectional view of Figure 5A .

[0017] Figure 6 is a vertical cross-sectional view of the first exemplary structure after formation of a second vertical alternating sequence of second-tier insulating layers and second-tier sacrificial material layers, second-tier backside stepped dielectric material portions, and second-tier insulating cap layers in accordance with an embodiment of the present disclosure.

[0018] Figure 7A is a vertical cross-sectional view of the first exemplary structure after formation of second-tier memory openings and second-tier support openings in accordance with an embodiment of the present disclosure.

[0019] Figure 7B is a horizontal cross-sectional view of the first exemplary structure taken along the horizontal plane B-B’ in Figure 7A corresponds to the plane of the vertical cross-sectional view of Figure 7A .

[0020] Figure 7C shows horizontal cross-sectional views of various configurations for arranging second-tier memory openings in accordance with an embodiment of the present disclosure.

[0021] Figure 8 is a vertical cross-sectional view of the first exemplary structure after formation of inter-tier memory openings and inter-tier support openings in accordance with an embodiment of the present disclosure.

[0022] Figures 9A to 9H is a sequential vertical cross-sectional view of an inter-tier memory opening during formation of a memory opening fill structure in accordance with an embodiment of the present disclosure.

[0023] Figure 10A is a vertical cross-sectional view of the first exemplary structure after formation of a memory opening fill structure and a main support pillar structure in accordance with an embodiment of the present disclosure.

[0024] Figure 10B is a horizontal cross-sectional view of the first exemplary structure taken along the horizontal plane B-B’ in Figure 10A corresponds to the plane of the vertical cross-sectional view of Figure 10A .

[0025] Figure 11A is a vertical cross-sectional view of the first exemplary structure after formation of a backside trench and a source region in accordance with an embodiment of the present disclosure.

[0026] Figure 11Bis a horizontal cross-sectional view of the first exemplary structure taken along the horizontal plane B-B' in Figure 11A corresponds to the plane of the vertical cross-sectional view of Figure 11A

[0027] Figure 11C illustrates a layout of a semiconductor die within the first exemplary structure of Figure 11A and Figure 11B

[0028] Figure 12A is a vertical cross-sectional view of the first exemplary structure after forming backside recesses according to an embodiment of the disclosure.

[0029] Figure 12B is a horizontal cross-sectional view of the first exemplary structure taken along the horizontal plane B-B' in Figure 12A corresponds to the plane of the vertical cross-sectional view of Figure 12A

[0030] Figure 13A is a vertical cross-sectional view of the first exemplary structure after replacing the sacrificial material layers with electrically conductive layers according to an embodiment of the disclosure.

[0031] Figure 13B is a horizontal cross-sectional view of the first exemplary structure taken along the horizontal plane B-B' in Figure 13A corresponds to the plane of the vertical cross-sectional view of Figure 13A

[0032] Figure 14A is a vertical cross-sectional view of the first exemplary structure after forming backside insulating spacers and backside via structures according to an embodiment of the disclosure.

[0033] Figure 14B is a horizontal cross-sectional view of the first exemplary structure taken along the horizontal plane B-B' in Figure 14A corresponds to the plane of the vertical cross-sectional view of Figure 14A

[0034] illustrates a layout of a semiconductor die within the first exemplary structure of Figure 14C and Figure 14A Figure 14B

[0035] Figure 15A is a vertical cross-sectional view of the first exemplary structure after forming drain contact via cavities and wordline contact via cavities according to an embodiment of the disclosure.

[0036] Figure 15B is a horizontal cross-sectional view of the first exemplary structure taken along the horizontal plane B-B' in Figure 15A ​​​​​​a horizontal cross-sectional view of the first exemplary structure taken along the horizontal plane B-B’ in FIG. 1A. The hinged vertical plane A-A’ corresponds to Figure 15A the vertical cross-sectional view of FIG. 1A.

[0037] Figure 16A is a vertical cross-sectional view of a first exemplary structure after forming a bit line level metal interconnect structure in accordance with the first embodiment of the disclosure.

[0038] Figure 16B is a plan view of a region of the first exemplary structure of Figure 16A

[0039] Figure 16C and Figure 16D illustrates an alternative word line layout of a semiconductor die within the first exemplary structure of Figure 16A and Figure 16B

[0040] Figure 17A is a vertical cross-sectional view of a logic die in accordance with the first embodiment of the disclosure.

[0041] Figure 17B illustrates a layout of the logic die of Figure 17A

[0042] Figure 18A and Figure 18B is a vertical cross-sectional view of a first exemplary structure after bonding a semiconductor die to a logic die in accordance with the first embodiment of the disclosure.

[0043] Figure 19A and Figure 19B is a vertical cross-sectional view of a first exemplary structure after backside thinning of a semiconductor die in accordance with the first embodiment of the disclosure.

[0044] Figure 20A and Figure 20B is a vertical cross-sectional view of a first exemplary structure after forming a plurality of source layers in accordance with the first embodiment of the disclosure.

[0045] Figure 21 is a vertical cross-sectional view of a first alternative configuration of a first exemplary structure after forming a plurality of source layers in accordance with the first embodiment of the disclosure.

[0046] Figures 22A to 22D is a vertical cross-sectional view of an alternative configuration of a memory opening during formation of a memory opening fill structure in accordance with the second embodiment of the disclosure.

[0047] Figure 23 is a vertical cross-sectional view of a second exemplary structure after removing a substrate in accordance with the second embodiment of the disclosure. ​​​

[0048] Figure 24A and Figure 24B This is a vertical cross-sectional view of the memory opening filling structure during the removal of the bottom portion of the memory film according to a second embodiment of the present disclosure.

[0049] Figure 25A This is a vertical cross-sectional view of a second exemplary structure after the formation of the source-level material layer, according to a second embodiment of the present disclosure.

[0050] Figure 25B yes Figure 25A A vertical cross-sectional view of the memory opening filling structure within the second exemplary structure.

[0051] Figure 26A and Figure 26B This is a vertical cross-sectional view of a second exemplary structure after the formation of the source layer, according to a second embodiment of the present disclosure.

[0052] Figure 27 yes Figure 26A and Figure 26B A circuit diagram of the second exemplary structure.

[0053] Figure 28 This is a vertical cross-sectional view of a third exemplary structure after the formation of a source selection hierarchical trench, according to a third embodiment of this disclosure.

[0054] Figure 29 This is a vertical cross-sectional view of a third exemplary structure after the formation of a source selection layer dielectric isolation structure according to a third embodiment of this disclosure.

[0055] Figure 30 This is a vertical cross-sectional view of a third exemplary structure after the formation of the source layer, according to a third embodiment of the present disclosure.

[0056] Figure 31A yes Figure 30 A circuit diagram of the third exemplary structure.

[0057] Figure 31B This is a schematic top view of the third exemplary structure.

[0058] Figure 32 This is a vertical cross-sectional view of a fourth exemplary structure after the formation of the source layer, according to a fourth embodiment of the present disclosure.

[0059] Figure 33 This is a vertical cross-sectional view of a fourth exemplary structure after the formation of a source-side trench, according to a fourth embodiment of the present disclosure.

[0060] Figure 34is a vertical cross-sectional view of a first alternative configuration of the fourth exemplary structure after formation of the source-level dielectric isolation layer according to the fourth embodiment of the present disclosure.

[0061] Figure 35 is a vertical cross-sectional view of a second alternative configuration of the fourth exemplary structure after formation of the source-level dielectric isolation layer according to the fourth embodiment of the present disclosure.

[0062] Figure 36 is Figure 35 circuit schematic diagrams of various configurations of the fourth exemplary structure.

[0063] Figure 37 is a vertical cross-sectional view of an exemplary structure for providing electrical connections to a source layer according to an embodiment of the present disclosure.

[0064] Figure 38 is a vertical cross-sectional view of another exemplary structure for providing electrical connections to a source layer according to an embodiment of the present disclosure.

[0065] Figure 39A is a vertical cross-sectional view of a fifth exemplary structure after formation of a memory opening fill structure according to a fifth embodiment of the present disclosure.

[0066] Figure 39B is a horizontal cross-sectional view of the fifth exemplary structure taken along a horizontal plane B-B' of Figure 39B

[0067] Figure 40A is a vertical cross-sectional view of a fifth exemplary structure after formation of a drain-level select-level dielectric isolation structure according to a fifth embodiment of the present disclosure.

[0068] Figure 40B is a horizontal cross-sectional view of the fifth exemplary structure taken along a horizontal plane B-B' of Figure 40A

[0069] Figure 41 is a vertical cross-sectional view of a fifth exemplary structure after formation of a source select-level trench according to a fifth embodiment of the present disclosure.

[0070] Figure 42 is a vertical cross-sectional view of a region of the fifth exemplary structure of Figure 41 along a vertical plane A-A'.

[0071] Figure 43 is a vertical cross-sectional view of a region of the fifth exemplary structure after formation of a source select-level trench according to a fifth embodiment of the present disclosure.

[0072] Figure 44A ​​is a vertical cross-sectional view of a region of a fifth exemplary structure after forming a source select level dielectric isolation structure according to the fifth embodiment of the disclosure.

[0073] Figure 44B is a horizontal cross-sectional view taken along horizontal plane B-B' of the fifth exemplary structure. Figure 44A

[0074] Figure 45 is a vertical cross-sectional view of a fifth exemplary structure after forming a source layer according to the fifth embodiment of the disclosure.

[0075] Figure 46 is a vertical cross-sectional view of a fifth exemplary structure after dividing the source layer into a plurality of source layers according to the fifth embodiment of the disclosure. DETAILED DESCRIPTION

[0076] As described above, embodiments of the disclosure relate to three-dimensional memory devices including isolated source lines and / or isolated source side select lines and methods of manufacturing the same, various aspects of which are described in detail herein.

[0077] The drawings are not drawn to scale. Where a single instance of an element is illustrated in a figure, multiple instances of the element can be repeated unless expressly described or otherwise clear from the context that no repetition of the element is intended. Numerical designators such as “first,” “second,” and “third” are merely used to identify like elements and different numerical designators can be employed throughout the specification and claims of this disclosure. The term “at least one” element means all possibilities including the possibility of a single element and the possibility of multiple elements.

[0078] Like reference numbers indicate like elements or similar elements. Unless otherwise specified, elements having the same reference numbers are assumed to have the same composition and the same function. Unless otherwise indicated, “contacting” between elements means direct contact between elements that provides an edge or surface shared by the elements. Two or more elements are “isolated” from each other if they are not in direct contact with each other or are not in direct contact with each other. As used herein, a first element positioned “on” a second element can be positioned on an outer side of a surface of the second element or on an inner side of the second element. As used herein, a first element is “directly” positioned on a second element if there is physical contact between a surface of the first element and a surface of the second element. As used herein, a first element is “electrically connected to” a second element if there is an electrically conductive path between the first element and the second element that is comprised of at least one electrically conductive material. As used herein, a “prototype” structure or “in-process” structure refers to a transient structure that is subsequently modified in shape or composition of at least one component thereof.

[0079] ​As used herein, a“layer” refers to a portion of material that includes a region having a thickness. A layer can extend over the entirety of an underlying or overlying structure, or can have a scope that is less than the scope of an underlying or overlying structure. Additionally, a layer can be a region of uniform or non-uniform thickness that is less than the thickness of a continuous structure. For example, a layer can be positioned between or at any pair of horizontal planes between a top surface and a bottom surface of a continuous structure. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, can include one or more layers therein, or can have one or more layers thereon, thereabove, and / or therebelow.

[0080] As used herein, first and second surfaces are“vertically coincident” with one another if the second surface is above or below the first surface and if there is a vertical plane or a substantially vertical plane that includes the first and second surfaces. A substantially vertical plane is a plane that extends linearly in a direction that is angled less than 5 degrees from a vertical direction. A vertical plane or a substantially vertical plane is straight along a vertical direction or a substantially vertical direction, and can or can not include a curvature along a direction that is perpendicular to the vertical direction or the substantially vertical direction.

[0081] In general, a semiconductor package (or“package”) refers to a unit semiconductor device that can be attached to a circuit board through a set of pins or solder balls. A semiconductor package can include one or more semiconductor chips (or“chips”) that are bonded therein, for example, through flip-chip bonding or another chip-to-chip bonding. A package or chip can include a single semiconductor die (or“die”) or multiple semiconductor dies. A die is the smallest unit that can independently execute external commands or report status. Typically, a package or chip with multiple dies is capable of executing as many external commands concurrently as the total number of planes therein. Each die includes one or more planes. The same concurrent operation can be executed in each plane within the same die, but there can be some limitations. In the case where a die is a memory die (i.e., a die that includes memory elements), a concurrent read operation, a concurrent write operation, or a concurrent erase operation can be executed in each plane within the same memory die. In a memory die, each plane contains a plurality of memory blocks (or“blocks”), which are the smallest units that can be erased by a single erase operation. Each memory block contains a plurality of pages, which are the smallest units that can be selected for programming. Pages are also the smallest units that can be selected for read operations.

[0082] Reference Figure 1A and Figure 1BFIG. 1 illustrates a first exemplary structure according to a first embodiment of the present disclosure. The first exemplary structure includes a substrate 8 that contains a substrate semiconductor layer 9 at least at an upper portion thereof. In one embodiment, the substrate semiconductor layer 9 can be a layer of single crystalline semiconductor material in a semiconductor substrate (such as a silicon wafer) or a doped well. In another embodiment, the substrate 8 can include a substrate semiconductor layer (not shown) with semiconductor devices (not shown) thereon and a lower level dielectric material layer (not shown) embedded in a lower level metal interconnect structure (not shown) and located above the semiconductor devices. In this case, the substrate semiconductor layer 9 can be formed above the lower level dielectric material layer. The substrate semiconductor layer 9 can have a doping of a second conductivity type, which can be p-type or n-type, that is opposite to a first conductivity type used to dope a subsequently formed vertical semiconductor channel. The substrate semiconductor layer 9 can include single crystalline semiconductor material or polycrystalline semiconductor material (such as polysilicon or polysilicon germanium alloy).

[0083] As used herein, a “semiconductor material” refers to a material having electrical conductivity in the range from 1.0 x 10 -6 S / cm to 1.0 x 10 5 S / cm. As used herein, a “semiconductor material” refers to a material having electrical conductivity in the range from 1.0 x 10 -6 S / cm to 1.0 x 10 5 S / cm in the absence of electrical dopants therein, and capable of producing a doped material having electrical conductivity in the range from 1.0 S / cm to 1.0 x 10 5 S / cm upon suitable doping with electrical dopants. As used herein, an “electrical dopant” refers to a p-type dopant that adds holes to a valence band within a band structure or an n-type dopant that adds electrons to a conduction band within a band structure. As used herein, an “electrically conductive material” refers to a material having electrical conductivity greater than 1.0 x 10 5 S / cm. As used herein, an “insulator material” or “dielectric material” refers to a material having electrical conductivity less than 1.0 x 10 -6 S / cm. As used herein, a “heavily doped semiconductor material” refers to a semiconductor material that is doped with electrical dopants at a sufficiently high atomic concentration to become an electrically conductive material (i.e., have electrical conductivity greater than 1.0 x 10 5 S / cm) when formed as a crystalline material or in the case of being converted to a crystalline material (e.g., starting from an initial amorphous state) by an annealing process. A “doped semiconductor material” can be a heavily doped semiconductor material, or can be a semiconductor material that includes electrical dopants at a concentration in the range from 1.0 x 10 -6 S / cm to 1.0 x 10 5semiconductor material. An "intrinsic semiconductor material" refers to a semiconductor material that is not doped with electrical dopants. Thus, a semiconductor material can be semiconducting or electrically conductive, and can be an intrinsic semiconductor material or a doped semiconductor material. A doped semiconductor material can be semiconducting or electrically conductive, depending on the atomic concentration of electrical dopants therein. As used herein, a "metallic material" refers to an electrically conductive material that includes at least one metallic element therein. All electrical conductivity measurements are made under standard conditions.

[0084] A vertically alternating sequence of first material layers and second material layers is subsequently formed. Each first material layer can include a first material, and each second material layer can include a second material different from the first material. Where at least another vertically alternating sequence of material layers is subsequently formed over the vertically alternating sequence of first material layers and second material layers, the vertically alternating sequence is referred to herein as a first vertically alternating sequence. The level of the first vertically alternating sequence is referred to herein as a first tier level, and the level of a vertically alternating sequence to be subsequently formed directly above the first tier level is referred to herein as a second tier level, and so on.

[0085] The first vertically alternating sequence can include a first tier insulating layer 132 as a first material layer and a first tier sacrificial material layer 142 as a second material layer. In one embodiment, each first tier insulating layer 132 can include a first insulating material, and each first tier sacrificial material layer 142 can include a first sacrificial material. A plurality of first tier insulating layers 132 and first tier sacrificial material layers 142 are formed over the substrate semiconductor layer 9 in an alternating manner. As used herein, a "sacrificial material" refers to a material that is removed during a subsequent processing step.

[0086] The first vertically alternating sequence (132, 142) can include a first tier insulating layer 132 of a first material and a first tier sacrificial material layer 142 of a second material different from the first material. The first material of the first tier insulating layer 132 can be at least one insulating material. Insulating materials that can be used for the first tier insulating layer 132 include, but are not limited to, silicon oxide (including doped silicate glass or undoped silicate glass), silicon nitride, silicon oxynitride, organosilicate glass (OSG), spin-on dielectrics, dielectric metal oxides (e.g., aluminum oxide, hafnium oxide, etc.) and silicates thereof, dielectric metal oxynitrides and silicates thereof, and organic insulating materials. In one embodiment, the first material of the first tier insulating layer 132 can be silicon oxide.

[0087] The second material of the first-tier sacrificial material layers 142 is a sacrificial material that can be selectively removed over the first material of the first-tier insulating layers 132. As used herein, the removal of the first material is "selective" over the second material if the removal process removes the first material at a rate that is at least twice the removal rate of the second material. The ratio of the removal rate of the first material to the removal rate of the second material is referred to herein as the "selectivity" of the removal process for the first material over the second material.

[0088] The first-tier sacrificial material layers 142 can include an insulating material, a semiconducting material, or a conductive material. The second material of the first-tier sacrificial material layers 142 can be subsequently replaced with a conductive electrode that can be used as, for example, a control gate electrode of a vertical NAND device. In one embodiment, the first-tier sacrificial material layers 142 can be a material layer that includes silicon nitride.

[0089] In one embodiment, the first-tier insulating layers 132 can include silicon oxide, and the sacrificial material layers can include silicon nitride sacrificial material layers. The first material of the first-tier insulating layers 132 can be deposited, for example, by chemical vapor deposition (CVD). If silicon oxide is used for the first-tier insulating layers 132, for example, tetraethyl orthosilicate (TEOS) can be used as a precursor material for the CVD process. The second material of the first-tier sacrificial material layers 142 can be formed, for example, by CVD or atomic layer deposition (ALD).

[0090] The thickness of the first-tier insulating layers 132 and the first-tier sacrificial material layers 142 can be in the range of 20 nm to 50 nm, although lesser and greater thicknesses can be employed for each of the first-tier insulating layers 132 and each of the first-tier sacrificial material layers 142. The number of repetitions of the pair of the first-tier insulating layers 132 and the first-tier sacrificial material layers 142 can be in the range of 2 to 1024, and typically in the range of 8 to 256, although greater numbers of repetitions can also be employed. In one embodiment, each of the first-tier sacrificial material layers 142 in the first vertically alternating sequence (132, 142) can have a uniform thickness that is substantially constant within each respective first-tier sacrificial material layer 142. Each layer within the first vertically alternating sequence (132, 142) can be a continuous material layer, without any openings therein. Thus, the first vertically alternating sequence (132, 142) can include a vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers.

[0091] A first insulative cap layer 170 is then formed over the stack (132, 142). The first insulative cap layer 170 includes a dielectric material, which can be any dielectric material that can be used for the first layer insulative layer 132. In one embodiment, the first insulative cap layer 170 includes the same dielectric material as the first layer insulative layer 132. The thickness of the first insulative cap layer 170 can be in a range from 20 nm to 300 nm, although lesser and greater thicknesses can also be employed.

[0092] In general, a memory die can be formed using the substrate semiconductor layer 9 and material layers thereon. The memory die can include a plurality of planes (P0-P7). Figure 1B The illustrated example layout includes eight planes (P0-P7), which can be independently operable within the memory die. Each plane (P0-P7) can include a respective three-dimensional memory array that contains a plurality of blocks at completion of the memory die. Each plane (P0-P7) can include a respective memory array region 100, a respective contact region 200, and a respective peripheral region 300. A gap region G can be disposed between an adjacent pair of planes (P0-P7). In one embodiment, the gap region G can extend laterally along a first horizontal direction (i.e., word line direction) hdl, and an adjacent pair of adjacent planes (P0 and Pl; P2 and P3; P4 and P5; P6 and P7) can be spaced apart laterally by the gap region G along a second horizontal direction (e.g., bit line direction) hd2 that is perpendicular to the first horizontal direction hdl. According to aspects of the disclosure, the width of each gap region G can be the same as the width of a respective backside trench subsequently formed between adjacent blocks in the same memory plane. In an illustrative example, the width of each gap region G can be in a range from 300 nm to 3,000 nm, although lesser and greater widths can also be employed. An adjacent pair of planes (P0 and P2; P4 and P6; Pl and P3; P5 and P7) that are adjacent along the first horizontal direction hdl can be spaced apart laterally by the respective contact region 200.

[0093] Reference is made to Figure 2The first insulating cap layer 170 and the first vertically-alternating sequence (132, 142) can be patterned to form a first stepped surface in a contact region 200. The contact region 200 can include a respective first stepped region in which the first stepped surface is formed and a second stepped region in which an additional stepped surface is subsequently formed in a second layer structure (which is subsequently formed over the first layer structure) and / or an additional layer structure. The first stepped surface can be formed, for example, by forming a mask layer having openings therein, etching a cavity within the level of the first insulating cap layer 170 and iteratively expanding the etched region, and by etching each pair of a first layer insulating layer 132 and a first layer sacrificial material layer 142 positioned immediately below a bottom surface of the etched cavity within the etched region to vertically recess the cavity. The first stepped surface extends continuously from a bottom-most layer within the first vertically-alternating sequence (132, 142) to a top-most layer within the first vertically-alternating sequence (132, 142). The cavity overlying the first stepped surface is referred to herein as a first stepped cavity.

[0094] A dielectric material, such as a silicate glass, can be deposited in the first stepped cavity. The dielectric material is subsequently planarized to provide a planar surface within a horizontal plane that includes a top surface of the first insulating cap layer. The contiguous remaining portion of the dielectric material overlying the first stepped surface and filling the first stepped cavity is referred to herein as a first backward-stepped dielectric material portion 165, which includes and can consist of a first silicate glass material. As used herein, a "backward-stepped" element refers to an element having a stepped surface and a horizontal cross-sectional area that monotonically increases as a function of a vertical distance from a substrate on which a top surface of the element exists. The first vertically-alternating sequence (132, 142) and the first backward-stepped dielectric material portion 165 collectively constitute a first layer structure, which is a structure in process that is subsequently modified.

[0095] An interlayer dielectric layer 180 can optionally be deposited over the first layer structure (132, 142, 165, 170). The interlayer dielectric layer 180 includes a dielectric material, such as a silicate glass material. The thickness of the interlayer dielectric layer 180 can be in a range from 30 nm to 300 nm, although lesser and greater thicknesses can also be employed. In one embodiment, the interlayer dielectric layer 180 can include a silicate glass that provides a greater etch rate in hydrofluoric acid than an undoped silicate glass. For example, the interlayer dielectric layer 180 can include a borosilicate glass.

[0096] The combination of all material portions formed over the top surface of the substrate semiconductor layer 9 and under the interlayer dielectric layer 180 constitutes a first layer structure (132, 142, 165). The first layer structure (132, 142, 165) includes a first vertically-alternating sequence of first layer insulating layers 132 and first layer sacrificial material layers 142 and a first backside stepped dielectric material portion 165 overlying and contacting a first stepped surface of the first vertically-alternating sequence (132, 142). The first stepped surface extends continuously from a bottom-most layer within the first vertically-alternating sequence (132, 142) to a top-most layer within the first vertically-alternating sequence (132, 142) and contacts vertical surfaces and horizontal bottom surfaces of the first backside stepped dielectric material portion 165.

[0097] Referring to Figure 3A and Figure 3B The first layer memory openings 149 and the first layer support openings 119 can be formed. In Figure 3B the location of a step S in the first vertically-alternating sequence (132, 142) is shown in dashed lines. The first layer memory openings 149 and the first layer support openings 119 extend through the first vertically-alternating sequence (132, 142) at least to the top surface of the substrate semiconductor layer 9. The first layer memory openings 149 can be formed at locations in the memory array region 100 at which memory stack structures including vertical stacks of memory elements are to be subsequently formed. The first layer support openings 119 can be formed in the contact region 200. The first layer support openings 119 can be formed within a first region of the first stepped surface at which the first backside stepped dielectric material portion 165 contacts the first vertically-alternating sequence (132, 142) and within a second region of the contact region 200 at which a second stepped surface of a second vertically-alternating sequence is to be subsequently formed. The second region of the contact region 200 is located between the first region of the word line contact region and the memory array region 100.

[0098] For example, a photoresist material stack (not shown) including at least a photoresist layer can be formed over the first insulative cap layer 170 (and optional interlayer dielectric layer 180, if present), and the photoresist material stack can be lithographically patterned to form openings within the photoresist material stack. At least one anisotropic etch employing the patterned photoresist material stack as an etch mask can be performed through the first insulative cap layer 170 (and optional interlayer dielectric layer 180), and the pattern in the photoresist material stack can be transferred through the entire first vertically alternating sequence (132, 142). Portions of the first insulative cap layer 170 (and optional interlayer dielectric layer 180) and the first vertically alternating sequence (132, 142) underlying the openings in the patterned photoresist material stack are etched to form first-tier memory openings 149 and first-tier support openings 119. In other words, transfer of the pattern in the patterned photoresist material stack through the first insulative cap layer 170 and the first vertically alternating sequence (132, 142) forms the first-tier memory openings 149 and the first-tier support openings 119.

[0099] In one embodiment, the chemical reactions of the anisotropic etch process used to etch through the material of the first vertically alternating sequence (132, 142) can alternate to optimize etching of the first and second materials in the first vertically alternating sequence (132, 142). The anisotropic etch can be, for example, a series of reactive ion etches or a single etch (e.g., CF4 / O2 / Ar etch). The sidewalls of the first-tier memory openings 149 and support openings 119. Subsequently, the patterned photoresist material stack can be subsequently removed, for example, by ashing.

[0100] Generally, groups of first-tier memory openings 149 can be formed through the first vertically alternating sequence (132, 142). Each group of first-tier memory openings 149 can be formed within a rectangular region (e.g., a region of a memory block) extending laterally along a first horizontal direction (e.g., a word line direction) hdl. Each group of first-tier memory openings 149 can include a plurality of rows of first-tier memory openings 149. The first-tier memory openings 149 of each row can extend laterally along the first horizontal direction hdl. The rows of first-tier memory openings 149 can be laterally spaced apart from one another along a second horizontal direction (e.g., a bit line direction) hd2.

[0101] Optionally, portions of the first-tier memory openings 149 and first-tier support openings 119 at the level of the interlayer dielectric layer 180 can be laterally expanded by an isotropic etch. For example, if the interlayer dielectric layer 180 includes a dielectric material (such as borosilicate glass) having a greater etch rate than the first insulative layer 132 (which can include undoped silicate glass), an isotropic etch (such as a wet etch employing HF) can be used to expand the lateral dimensions of the first-tier memory openings at the level of the interlayer dielectric layer 180.

[0102] Referring to Figure 4 A pedestal channel portion 11 can optionally be formed at a bottom of each of the first-tier memory openings 149 and the first-tier support openings 119. The pedestal channel portion 11 can be formed by a selective semiconductor deposition process that deposits a doped semiconductor material having a first conductivity type of doping. If the pedestal channel portion 11 is formed, a top surface of the pedestal channel portion 11 can be formed at or above a horizontal plane that includes a top surface of the bottommost first-tier sacrificial material layer 142 and at or above a horizontal plane that includes a bottom surface of the first-tier sacrificial material layer 42 that is closest to the bottommost first-tier sacrificial material layer 142 (i.e., the second-from-the-bottom first-tier sacrificial material layer 142).

[0103] Referring to Figure 5A and Figure 5B A first-tier sacrificial memory opening fill structure 148 can be formed in the first-tier memory openings 149 and a first-tier sacrificial support structure 118 can be formed in the first-tier support openings 119. For example, a fill material layer including a fill material is deposited in the first-tier memory openings 149 and the first-tier support openings 119.

[0104] Referring to Figure 6 A second-tier structure can be formed over the first-tier structure (132, 142, 170, 148, 118). The second-tier structure can include an additional vertically-alternating sequence of insulating layers and sacrificial material layers, which can be sacrificial material layers. For example, a second vertically-alternating sequence of material layers (232, 242) can be subsequently formed on a top surface of the first vertically-alternating sequence (132, 142). The second stack (232, 242) includes a plurality of third material layers and fourth material layers that are alternating. Each third material layer can include a third material and each fourth material layer can include a fourth material that is different from the third material. In one embodiment, the third material can be the same as the first material of the first-tier insulating layers 132 and the fourth material can be the same as the second material of the first-tier sacrificial material layers 142.

[0105] In one embodiment, the third material layers can be second-tier insulating layers 232 and the fourth material layers can be second-tier sacrificial material layers 242 that provide a vertical spacing between each vertically-adjacent pair of second-tier insulating layers 232. In one embodiment, the third material layers and the fourth material layers can be second-tier insulating layers 232 and second-tier sacrificial material layers 242, respectively.

[0106] The third material of the second-tier insulating layers 232 can be at least one insulating material. The fourth material of the second-tier sacrificial material layers 242 can be a sacrificial material that is selectively removable with respect to the third material of the second-tier insulating layers 232. The second-tier sacrificial material layers 242 can comprise an insulating material, a semiconducting material, or a conductive material. The fourth material of the second-tier sacrificial material layers 242 can be subsequently replaced with a conductive electrode that can function as, for example, a control gate electrode of a vertical NAND device.

[0107] In one embodiment, each second-tier insulating layer 232 can comprise a second insulating material, and each second-tier sacrificial material layer 242 can comprise a second sacrificial material. In this case, the second stack (232, 242) can comprise a plurality of second-tier insulating layers 232 and second-tier sacrificial material layers 242 that alternate. The third material of the second-tier insulating layers 232 can be deposited, for example, by chemical vapor deposition (CVD). The fourth material of the second-tier sacrificial material layers 242 can be formed, for example, by CVD or atomic layer deposition (ALD).

[0108] The third material of the second-tier insulating layers 232 can be at least one insulating material. The insulating material that can be used for the second-tier insulating layers 232 can be any of the materials that can be used for the first-tier insulating layers 132. The fourth material of the second-tier sacrificial material layers 242 is a sacrificial material that is selectively removable with respect to the third material of the second-tier insulating layers 232. The sacrificial material that can be used for the second-tier sacrificial material layers 242 can be any of the materials that can be used for the first-tier sacrificial material layers 142. In one embodiment, the second insulating material can be the same as the first insulating material, and the second sacrificial material can be the same as the first sacrificial material.

[0109] The thickness of the second-tier insulating layers 232 and the second-tier sacrificial material layers 242 can be in a range from 20 nm to 50 nm, although lesser and greater thicknesses can be used for each second-tier insulating layer 232 and each second-tier sacrificial material layer 242. The number of repetitions of pairs of the second-tier insulating layers 232 and the second-tier sacrificial material layers 242 can be in a range from 2 to 1024, and typically in a range from 8 to 256, although greater numbers of repetitions can also be employed. In one embodiment, each second-tier sacrificial material layer 242 in the second stack (232, 242) can have a uniform thickness that is substantially constant within each respective second-tier sacrificial material layer 242.

[0110] A second vertically-alternating sequence (232, 242) can be patterned to form second stepped surfaces in second stepped regions within the contact region 200. The second stepped regions are closer to the memory array region 100 than the first stepped regions including the first stepped surfaces to the memory array region. The second stepped surfaces can be formed, for example, by forming a mask layer with openings therein, etching cavities within the topmost second layer of sacrificial material layer 242 and the topmost second layer of insulating layer 232 and iteratively expanding the etched region, and by etching each first layer of insulating layer 132 and first layer of sacrificial material layer 142 located directly below the bottom surface of the etched cavities within the etched region to vertically recess the cavities. The second stepped surfaces extend continuously from the bottommost layer within the second vertically-alternating sequence (232, 242) to the topmost layer within the first vertically-alternating sequence (132, 142). The cavities overlying the second stepped surfaces are referred to herein as first stepped cavities.

[0111] A dielectric material such as silicon oxide can be deposited over the second stepped surfaces. Portions of the dielectric material overlying the second vertically-alternating sequence (232, 242) can be removed by a planarization process such as a chemical-mechanical planarization (CMP) process. The contiguous remaining portions of the dielectric material overlying the second stepped surfaces and filling the second stepped cavities are referred to herein as second back-stepped dielectric material portions 265. The second vertically-alternating sequence (232, 242) and the second back-stepped dielectric material portions 265 collectively comprise a second layer structure, which is an in-process structure that is subsequently modified. The second stepped surfaces extend continuously from the bottommost layer within the second vertically-alternating sequence (232, 242) to the topmost layer within the second vertically-alternating sequence (232, 242) and contact vertical surfaces and horizontal bottom surfaces of the second back-stepped dielectric material portions 265.

[0112] A second insulative cap layer 270 can be subsequently formed over the second vertically-alternating sequence (232, 242). The second insulative cap layer 270 comprises a dielectric material that is different from the material of the second layer of sacrificial material layer 242. In one embodiment, the second insulative cap layer 270 can comprise silicon oxide.

[0113] Optionally, a drain-select-level dielectric isolation structure 72 can be formed through a subset of the layers in the upper portion of the second vertically-alternating sequence (232, 242). The second layer of sacrificial material layer 242 that is cut by the drain-select-level dielectric isolation structure 72 corresponds to the level at which a drain-select-level conductive layer is subsequently formed. The drain-select-level dielectric isolation structure 72 comprises a dielectric material such as silicon oxide.

[0114] Generally, a subset of the spacer material layers, such as a distal subset of the second layer of sacrificial material layers 246 farthest from a distal side of a substrate including the substrate semiconductor layer 9, can be divided by forming the drain-select-level trenches after the set of memory opening fill structures 58 are formed. The drain-select-level dielectric isolation structures 72 can be formed by depositing a dielectric material in the drain-select-level trenches. The drain-select-level dielectric isolation structures 72 can laterally extend along the first horizontal direction hd1.

[0115] Referring to Figures 7A to 7C Second layer memory openings 249 and second layer support openings 219 extending through the second layer of structures (232, 242, 270, 265) are formed in regions overlying the sacrificial memory opening fill portions 148. A photoresist layer can be applied over the second layer of structures (232, 242, 270, 265) and can be lithographically patterned to form a pattern identical to the pattern of the sacrificial memory opening fill portions 148 and the first layer of sacrificial support structures 118, i.e., the pattern of the first layer memory openings 149 and the first layer support openings 119. An anisotropic etch can be performed to transfer the pattern of the lithographically patterned photoresist layer through the second layer of structures (232, 242, 270, 265). In one embodiment, the chemistry of the anisotropic etch process used to etch through the materials of the second vertically-alternating sequence (232, 242) can be alternated to optimize etching of the alternating material layers in the second vertically-alternating sequence (232, 242). The anisotropic etch can be, for example, a series of reactive ion etches. The patterned photoresist material stack can be removed, for example, by ashing after the anisotropic etch process.

[0116] A top surface of the underlying sacrificial memory opening fill portions 148 can be physically exposed at a bottom of each second layer memory opening 249. A top surface of the underlying first layer of sacrificial support structures 118 can be physically exposed at a bottom of each second layer support opening 219.

[0117] Generally, a group of second-tier memory openings 249 can be formed through the second vertically alternating sequence (232, 242). Each group of second-tier memory openings 249 can be formed within a rectangular region (e.g., a memory block region) that extends laterally along a first horizontal direction hd1. Each group of second-tier memory openings 249 can include a plurality of rows of second-tier memory openings 249. Each row of second-tier memory openings 249 can extend laterally along the first horizontal direction hd1. The rows of second-tier memory openings 249 can be laterally spaced apart from each other along a second horizontal direction (e.g., a bit line direction) hd2. The number of rows (e.g., in a memory string unit) within each group of second-tier memory openings 249 depends on the total number of drain-select-level dielectric isolation structures 72 per group of second-tier memory openings 249. In one embodiment, the drain-select-level dielectric isolation structures 72 are formed such that the area of each drain-select-level dielectric isolation structure 72 overlaps with a row of second-tier memory openings 249. Figure 7C Examples are shown in which the total number of rows of drain-select-level dielectric isolation structures 72 within each memory block (i.e., within each group of second-tier memory openings 249) is 1, 4, or 7, which results in memory blocks having 8, 20, or 32 interleaved rows of second-tier memory openings 249, respectively. In these memory blocks, 2, 5, or 8 drain-side select lines are formed in the drain-select line level, respectively, which results in 2, 5, or 8 memory string units in each memory block, respectively. As can be seen in Figure 7C In the example shown in FIG. 1A, the memory block size increases as the number of interleaved rows of second-tier memory openings 249 increases.

[0118] Referring to Figure 8 The etching process can be performed after the top surfaces of the sacrificial memory opening fill portions 148 and the first-tier sacrificial support structures 118 are physically exposed. The etching process selectively removes the sacrificial material (e.g., C4F8 / O2 / Ar etch) of the sacrificial memory opening fill portions 148 and the first-tier sacrificial support structures 118 for the materials of the second vertically alternating sequence (232, 242) and the first vertically alternating sequence (132, 142). The etching process can include an anisotropic etching process or an isotropic etching process.

[0119] Upon removal of the sacrificial memory opening fill portions 148, each vertically adjacent pair of second-tier memory openings 249 and first-tier memory openings 149 forms a continuous cavity extending through the first vertical alternating sequence (132, 142) and the second vertical alternating sequence (232, 242), which is referred to herein as an inter-tier memory opening 49 or memory opening 49. Likewise, upon removal of the first-tier sacrificial support structures 118, each vertically adjacent pair of second-tier support openings 219 and first-tier support openings 119 forms a continuous cavity extending through the first vertical alternating sequence (132, 142) and the second vertical alternating sequence (232, 242), which is referred to herein as an inter-tier support opening 19 or support opening 19. The top surface of the substrate semiconductor layer 9 can be physically exposed at the bottom of each memory opening and at the bottom of each support opening. The locations of the steps S in the first vertical alternating sequence (132, 142) and the second vertical alternating sequence (232, 242) are shown in dashed lines.

[0120] Generally, at least one vertical alternating sequence of a continuous insulating layer and a continuous sacrificial material layer can be formed over a substrate. The memory openings 49 are formed through the at least one vertical alternating sequence.

[0121] Figures 9A to 9H Sequential cross-sectional views of the memory openings 49 or support openings 19 during formation of the memory opening fill structures 58 or the main support pillar structures 20 are provided. Although structural variations of the memory openings 49 are shown in Figures 9A to 9H , it is to be understood that the same structural variations occur in each of the memory openings 49 and support openings 19 during the same set of processing steps.

[0122] Reference is made to Figure 9A , which shows the memory openings 49 in the exemplary device structure of Figure 14. The memory openings 49 extend through the first-tier structure and the second-tier structure. Likewise, each support opening 19 extends through the first-tier structure and the second-tier structure. A pedestal channel portion 11 can or can not be present within each memory opening 49 and within each support opening 19. A cavity 49' is present in the unfilled portion of the memory opening 49 (or support opening) above the pedestal channel portion 11.

[0123] Reference is made to Figure 9BA stack of layers including a blocking dielectric layer 52, a charge storage layer 54, and a tunneling dielectric layer 56 can be sequentially deposited in the memory opening 49. The blocking dielectric layer 52 can include a single layer of dielectric material or a stack of multiple layers of dielectric material. In one embodiment, the blocking dielectric layer can include a dielectric metal oxide layer that consists essentially of a dielectric metal oxide. As used herein, a dielectric metal oxide refers to a dielectric material that includes at least one metallic element and at least oxygen. The dielectric metal oxide can consist essentially of at least one metallic element and oxygen, or can consist essentially of at least one metallic element, oxygen, and at least one non-metallic element such as nitrogen.

[0124] In one embodiment, the blocking dielectric layer 52 can include a dielectric metal oxide having a dielectric constant greater than 7.9 (i.e., having a dielectric constant greater than that of silicon nitride). Non-limiting examples of dielectric metal oxides include aluminum oxide (AI2O3), hafnium oxide (HfO2), lanthanum oxide (LaO2), yttrium oxide (Y2O3), tantalum oxide (Ta2O5), silicates thereof, nitrogen-doped compounds thereof, alloys thereof, and stacks thereof.

[0125] The dielectric metal oxide layer can be deposited, for example, by chemical vapor deposition (CVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), liquid source misted chemical deposition, or combinations thereof. The thickness of the dielectric metal oxide layer can be in a range from 1 nm to 20 nm, although lesser and greater thicknesses can also be employed. Subsequently, the dielectric metal oxide layer can serve as a dielectric material portion that blocks the stored charge from leaking to the control gate electrode. In one embodiment, the blocking dielectric layer 52 includes aluminum oxide. In one embodiment, the blocking dielectric layer 52 can include multiple dielectric metal oxide layers having different material compositions.

[0126] Alternatively or additionally, the blocking dielectric layer 52 can include a dielectric silicon compound such as silicon oxide, silicon oxynitride, silicon nitride, or combinations thereof. In one embodiment, the blocking dielectric layer 52 can include silicon oxide. In this case, the dielectric semiconductor compound of the blocking dielectric layer 52 can be formed by a conformal deposition method such as low pressure chemical vapor deposition, atomic layer deposition, or combinations thereof.

[0127] The thickness of the dielectric semiconductor compound can be in a range from 1 nm to 20 nm, although lesser and greater thicknesses can also be employed. Alternatively, the blocking dielectric layer 52 can be omitted, and a backside blocking dielectric layer can be formed after forming a backside recess on the surface of the memory film to be subsequently formed.

[0128] Subsequently, a charge storage layer 54 can be formed. In one embodiment, the charge storage layer 54 can be a continuous layer or patterned discrete portions of charge trapping material including a dielectric charge trapping material, such as which can be silicon nitride. Alternatively, the charge storage layer 54 can include a continuous layer or patterned discrete portions of conductive material, such as doped polysilicon or a metallic material, that is patterned into a plurality of electrically isolated portions (e.g., floating gates), such as by being formed as a sacrificial material layer (142, 242) within lateral recesses. In one embodiment, the charge storage layer 54 includes a silicon nitride layer. In one embodiment, the sacrificial material layer (142, 242) and the insulating layer (132, 232) can have vertically coincident sidewalls, and the charge storage layer 54 can be formed as a single continuous layer.

[0129] In another embodiment, the sacrificial material layer (142, 242) can be laterally recessed relative to the sidewalls of the insulating layer (132, 232), and a combination of deposition and anisotropic etching processes can be employed to form the charge storage layer 54 as a plurality of vertically spaced apart memory material portions. While the present disclosure is described with embodiments in which the charge storage layer 54 is a single continuous layer, embodiments in which the charge storage layer 54 is replaced by a plurality of vertically spaced apart memory material portions, which can be charge trapping material portions or electrically isolated conductive material portions, are expressly contemplated herein.

[0130] The charge storage layer 54 can be formed as a single charge storage layer of uniform composition, or can include a stack of multiple charge storage layers. The multiple charge storage layers, if employed, can include a plurality of spaced apart floating gate material layers that include a conductive material (e.g., a metal such as tungsten, molybdenum, tantalum, titanium, platinum, ruthenium, and alloys thereof, or a metal silicide such as tungsten silicide, molybdenum silicide, tantalum silicide, titanium silicide, nickel silicide, cobalt silicide, or combinations thereof) and / or a semiconductor material (e.g., a polycrystalline or amorphous semiconductor material including at least one elemental semiconductor element or at least one compound semiconductor material). Alternatively or additionally, the charge storage layer 54 can include an insulating charge trapping material, such as one or more segments of silicon nitride. Alternatively, the charge storage layer 54 can include conductive nanoparticles, such as metal nanoparticles, which can be, for example, ruthenium nanoparticles. The charge storage layer 54 can be formed, for example, by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or any suitable deposition technique for storing charge therein. The thickness of the charge storage layer 54 can be in a range from 2 nm to 20 nm, although lesser and greater thicknesses can also be employed.

[0131] The tunneling dielectric layer 56 includes a dielectric material through which charge tunneling can be performed under suitable electrical bias conditions. Charge tunneling can be performed by hot carrier injection or by Fowler-Nordheim tunneling induced charge transfer, depending on the mode of operation of the unit three-dimensional NAND string memory device to be formed. The tunneling dielectric layer 56 can include silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides such as aluminum oxide and hafnium oxide, dielectric metal oxynitrides, dielectric metal silicates, alloys thereof, and / or combinations thereof. In one embodiment, the tunneling dielectric layer 56 can include a stack of a first silicon oxide layer, a silicon oxynitride layer, and a second silicon oxide layer, which stack is commonly referred to as an ONO stack. In one embodiment, the tunneling dielectric layer 56 can include a silicon oxide layer that is substantially free of carbon or a silicon oxynitride layer that is substantially free of carbon. The thickness of the tunneling dielectric layer 56 can be in a range from 2 nm to 20 nm, although lesser and greater thicknesses can also be employed.

[0132] Reference is made to Figure 9C The optional first semiconductor channel layer 601 can be deposited by a conformal deposition process. The optional first semiconductor channel layer 601 includes a semiconductor material such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II- VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the first semiconductor channel layer 601 includes amorphous silicon or polysilicon. The first semiconductor channel layer 601 can be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The thickness of the first semiconductor channel layer 601 can be in a range from 2 nm to 10 nm, although lesser and greater thicknesses can also be employed. The cavity 49’ is formed in the volume of each memory opening 49 that is not filled with the deposited material layers (52, 54, 56, 601).

[0133] Reference is made to Figure 9D The optional first semiconductor channel layer 601, the tunneling dielectric layer 56, the charge storage layer 54, the blocking dielectric layer 52 are sequentially anisotropically etched by at least one anisotropic etching process. Portions of the first semiconductor channel layer 601, the tunneling dielectric layer 56, the charge storage layer 54, and the blocking dielectric layer 52 that are located above the top surface of the second insulating cap layer 270 can be removed by the at least one anisotropic etching process. In addition, horizontal portions of the first semiconductor channel layer 601, the tunneling dielectric layer 56, the charge storage layer 54, and the blocking dielectric layer 52 at the bottom of each cavity 49’ can be removed to form an opening in the remaining portions thereof. Each of the first semiconductor channel layer 601, the tunneling dielectric layer 56, the charge storage layer 54, and the blocking dielectric layer 52 can be etched by a respective anisotropic etching process that employs a respective etching chemistry, which can be the same or different for the various material layers.

[0134] Each remaining portion of the first semiconductor channel layer 601 can have a tubular configuration. The charge storage layer 54 can include a charge trapping material or a floating gate material. In one embodiment, each charge storage layer 54 can include a vertical stack of charge storage regions that store charge during programming. In one embodiment, the charge storage layer 54 can be a charge storage layer in which each portion of the adjacent sacrificial material layer (142, 242) constitutes a charge storage region.

[0135] The surface of the base channel portion 11 (or the surface of the substrate semiconductor layer 9 in the case where the base channel portion 11 is not employed) can be physically exposed under the openings through the first semiconductor channel layer 601, the tunneling dielectric layer 56, the charge storage layer 54, and the blocking dielectric layer 52. Optionally, the physically exposed semiconductor surface at the bottom of each cavity 49’ can be vertically recessed such that the recessed semiconductor surface under the cavity 49’ is vertically offset from the topmost surface of the base channel portion 11 (or the semiconductor material layer 10 in the case where the base channel portion 11 is not employed) by a recessed distance. The tunneling dielectric layer 56 is positioned over the charge storage layer 54. The set of blocking dielectric layer 52, charge storage layer 54, and tunneling dielectric layer 56 in the memory opening 49 constitutes a memory film 50 that includes a plurality of charge storage regions (as embodied as the charge storage layer 54) that are insulated from surrounding material by the blocking dielectric layer 52 and the tunneling dielectric layer 56. In one embodiment, the first semiconductor channel layer 601, the tunneling dielectric layer 56, the charge storage layer 54, and the blocking dielectric layer 52 can have vertically coinciding sidewalls.

[0136] Referring to Figure 9E The second semiconductor channel layer 602 can be deposited directly on the semiconductor surface of the base channel portion 11 or on the semiconductor material layer 10 (if the base channel portion 11 is omitted) and directly on the first semiconductor channel layer 601. The second semiconductor channel layer 602 includes a semiconductor material, such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II- VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the second semiconductor channel layer 602 includes amorphous or polysilicon. The second semiconductor channel layer 602 can be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The thickness of the second semiconductor channel layer 602 can be in a range from 2 nm to 10 nm, although lesser and greater thicknesses can also be employed. The second semiconductor channel layer 602 can partially fill the cavity 49’ in each memory opening, or can completely fill the cavity in each memory opening.

[0137] The materials of the first semiconductor channel layer 601 and the second semiconductor channel layer 602 are collectively referred to as semiconductor channel material. In other words, the semiconductor channel material is the collective of all the semiconductor materials in the first semiconductor channel layer 601 and the second semiconductor channel layer 602.

[0138] Referring Figure 9F In cases where the cavity 49’ in each memory opening is not completely filled by the second semiconductor channel layer 602, a dielectric core layer 62L can be deposited in the cavity 49’ to fill any remaining portion of the cavity 49’ within each memory opening. The dielectric core layer 62L includes a dielectric material such as silicon oxide or organosilicate glass. The dielectric core layer 62L can be deposited by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD) or by a self-planarizing deposition process such as spin-on.

[0139] Referring Figure 9G The horizontal portions of the dielectric core layer 62L can be removed, for example, by recess etching from above the top surface of the second insulating cap layer 270. Each remaining portion of the dielectric core layer 62L constitutes a dielectric core 62. In addition, the horizontal portions of the second semiconductor channel layer 602 that are located above the top surface of the second insulating cap layer 270 can be removed by a planarization process that can employ either a recess etch or chemical mechanical planarization (CMP). Each remaining portion of the second semiconductor channel layer 602 can be positioned entirely within the memory openings 49 or entirely within the support openings 19.

[0140] Each contiguous pair of the first semiconductor channel layer 601 and the second semiconductor channel layer 602 can collectively form a vertical semiconductor channel 60 through which electrical current can flow when the vertical NAND device including the vertical semiconductor channel 60 is turned on. The tunneling dielectric layer 56 is surrounded by the charge storage layer 54 and laterally surrounds portions of the vertical semiconductor channel 60. Each set of contiguous blocking dielectric layer 52, charge storage layer 54, and tunneling dielectric layer 56 collectively constitutes a memory film 50 that can store electrical charge with a macroscopic retention time. In some embodiments, there can be no blocking dielectric layer 52 in the memory film 50 at this step, and the blocking dielectric layer can be formed subsequently after the formation of the backside recess. As used herein, a macroscopic retention time refers to a retention time suitable for operation of a memory device as a permanent memory device, such as a retention time of more than 24 hours.

[0141] Referring Figure 9HThe top surface of each dielectric core 62 can be further recessed into each memory opening, for example by a recess etch to a depth between a top surface of the second insulative cap layer 270 and a bottom surface of the second insulative cap layer 270. A drain region 63 can be formed by depositing a doped semiconductor material in each recessed region over the dielectric core 62. The drain region 63 can have a second conductivity type that is opposite to the first conductivity type. For example, if the first conductivity type is p-type, then the second conductivity type is n-type, and vice versa. The dopant concentration of the drain region 63 can be in a range from 5.0 x 1019 / cm3to 2.0 x 1020 / cm3, although lesser and greater dopant concentrations can also be employed. The doped semiconductor material can be, for example, doped polysilicon. Excess portions of the deposited semiconductor material can be removed from above the top surface of the second insulative cap layer 270, for example by chemical mechanical planarization (CMP) or a recess etch, to form the drain region 63. 18 / cm 3 / cm 21 / cm 3 / cm3, although lesser and greater dopant concentrations can also be employed. The doped semiconductor material can be, for example, doped polysilicon. Excess portions of the deposited semiconductor material can be removed from above the top surface of the second insulative cap layer 270, for example by chemical mechanical planarization (CMP) or a recess etch, to form the drain region 63.

[0142] Each combination of a memory film 50 and a vertical semiconductor channel 60 (which is a vertical semiconductor channel) within a memory opening 49 constitutes a memory stack structure 55. The memory stack structure 55 is a combination of a semiconductor channel, a tunneling dielectric layer, a plurality of memory elements embodied as portions of a charge storage layer 54, and an optional blocking dielectric layer 52. Each combination of a base channel portion 11 (if present), a memory stack structure 55, a dielectric core 62, and a drain region 63 within a memory opening 49 constitutes a memory opening fill structure 58. Each combination of a base channel portion 11 (if present), a memory film 50, a vertical semiconductor channel 60, a dielectric core 62, and a drain region 63 within each support opening 19 fills the respective support opening 19 and constitutes a main support pillar structure 20.

[0143] The first tier structure (132, 142, 170, 165), the second tier structure (232, 242, 270, 265), the inter-tier dielectric layer 180, the memory opening fill structure 58, and the main support pillar structure 20 collectively constitute a memory level assembly. The memory level assembly is formed over the substrate semiconductor layer 9 such that the substrate semiconductor layer 9 includes a horizontal semiconductor channel that is electrically connected to the vertical semiconductor channel 60 within the memory stack structure 55.

[0144] Referring to Figure 10A and Figure 10B , a first exemplary structure is shown after forming the memory opening fill structure 58 within each memory opening 49 and forming the main support pillar structure 20 within each support opening 19. Each memory opening fill structure 58 includes a respective vertical semiconductor channel 60.

[0145] Reference Figures 11A to 11C A first contact level dielectric layer 280 can be formed over the memory level assembly. The first contact level dielectric layer 280 is formed at a contact level through which various contact via structures are subsequently formed to the drain regions 63, and various conductive layers are formed in subsequent processing steps in place of the sacrificial material layers (142, 242).

[0146] Subsequently, backside trenches 79 are formed through the first contact level dielectric layer 280 and the memory level assembly. For example, a photoresist layer can be applied and lithographically patterned over the first contact level dielectric layer 280 to form elongated openings extending along the first horizontal direction hd1. An anisotropic etch is performed to transfer the pattern in the patterned photoresist layer through the first contact level dielectric layer 280 and the memory level assembly to the top surface of the substrate semiconductor layer 9. The photoresist layer can be subsequently removed, e.g., by ashing.

[0147] The backside trenches 79 extend along the first horizontal direction hd1, and are thus elongated along the first horizontal direction hd1. The backside trenches 79 can be laterally spaced apart from one another along a second horizontal direction hd2, which can be perpendicular to the first horizontal direction hd1. The backside trenches 79 can extend through the memory array regions (e.g., memory planes) 100 and the contact regions 200 within each plane (P0-P7).

[0148] In one embodiment, the backside trenches 79 can laterally extend along the first horizontal direction hd1 and be laterally spaced apart along the second horizontal direction hd2. In one embodiment, the planes (P0-P7) can be arranged such that each even plane (P0, P2, P4, P6) is laterally spaced apart from a respective odd plane (P1, P3, P5, P7) by a respective backside trench 79, which is referred to herein as an inter-array backside trench 793. In general, the backside trenches 79 can include first backside trenches 791 laterally extending through a respective one of the even planes (P0, P2, P4, P6), second backside trenches 792 laterally extending through a respective one of the odd planes (P1, P3, P5, P7), and inter-array backside trenches 793 formed within respective gap regions G Figure 1BThe first and second backside trenches (791, 792) separate the memory blocks within each respective plane. In general, the first backside trench 791, the second backside trench 792, and the interarray backside trench 793 can be formed simultaneously by forming a patterned etch mask layer (not shown) on the at least one vertically alternating sequence of continuous insulative layers (132, 232) and continuous sacrificial material layers (142, 242), and by anisotropically etching unmasked portions of the at least one vertically alternating sequence with an anisotropic etching process. In one embodiment, the patterned etch mask layer can be a patterned photoresist layer. In one embodiment, the first backside trench 791, the second backside trench 792, and the interarray backside trench 793 can have the same width along the second horizontal direction hd2. In one embodiment, the first backside trench 791, the second backside trench 792, and the interarray backside trench 793 can be formed as a periodic one-dimensional array that repeats periodically along the second horizontal direction hd2.

[0149] The portion of the continuous insulative layer (132, 232) divided by the first backside trench 791 is referred to herein as a first insulative layer (132, 232). The portion of the continuous insulative layer (132, 232) divided by the second backside trench 792 is referred to herein as a second insulative layer (132, 232). The portion of the continuous sacrificial material layer (142, 242) divided by the first backside trench 791 is referred to herein as a first sacrificial material layer (142, 242). The portion of the continuous sacrificial material layer (142, 242) divided by the second backside trench 792 is referred to herein as a second sacrificial material layer (142, 242).

[0150] In general, the vertically alternating sequence of continuous insulative layers (132, 232) and continuous sacrificial material layers (142, 242) is divided into a first alternating stack of first insulative layers (132, 232) and first sacrificial material layers (142, 242) laterally spaced apart by the first backside trench 791, and a second alternating stack of second insulative layers (132, 232) and second sacrificial material layers (142, 242) laterally spaced apart by the second backside trench 792. The first and second alternating stacks are laterally spaced apart by the interarray backside trench 793. A first subset of the memory opening fill structures 58 vertically extend through a respective one of the first alternating stack, and a second subset of the memory opening fill structures 58 vertically extend through a respective one of the second alternating stack.

[0151] Dopants having a second conductivity type opposite the first conductivity type of the substrate semiconductor layer 9 can be implanted into surface portions of the substrate semiconductor layer 9 to form source regions 61 below bottom surfaces of each of the backside trenches 79.

[0152] Reference is made to Figure 12Aand Figure 12B For example, an isotropic etching process can be used to introduce an etchant into the back-side trench 79 to selectively etch the materials of the first and second insulating layers (132, 232), the first and second insulating cap layers (170, 270), and the outermost layer of the memory film 50 relative to the materials of the first and second sacrificial material layers (142, 242). A first back-side recess 143 is formed in the volume from which the first sacrificial material layer 142 is removed. A second back-side recess 243 is formed in the volume from which the second sacrificial material layer 242 is removed. In one embodiment, the first and second sacrificial material layers (142, 242) may comprise silicon nitride, and the materials of the first and second insulating layers (132, 232) may be silicon oxide. In another embodiment, the first and second sacrificial material layers (142, 242) may comprise semiconductor materials such as germanium or silicon-germanium alloys, and the materials of the first and second insulating layers (132, 232) may be selected from silicon oxide and silicon nitride.

[0153] The isotropic etching process can be a wet etching process using a wet etching solution, or a vapor-phase (dry) etching process in which the etchant is introduced in the vapor phase into the back-side trench 79. For example, if the first and second sacrificial material layers (142, 242) comprise silicon nitride, the etching process can be a wet etching process in which the first exemplary structure is immersed in a wet etching bath comprising phosphoric acid, which selectively etches silicon nitride for silicon oxide, silicon, and various other materials used in the art. In cases where the sacrificial material layers (142, 242) comprise semiconductor materials, a wet etching process (which may employ a wet etchant such as a KOH solution) or a dry etching process (which may include vapor-phase HCl) can be used.

[0154] Each of the first and second back-side recesses (143, 243) can be a laterally extending cavity, the lateral dimension of which is greater than the vertical extent of the cavity. In other words, the lateral dimension of each of the first and second back-side recesses (143, 243) can be greater than the height of the corresponding back-side recess. A plurality of first back-side recesses 143 can be formed in the volume from which the first sacrificial material layer 142 is removed. A plurality of second back-side recesses 243 can be formed in the volume from which the second sacrificial material layer 242 is removed. Each of the first and second back-side recesses (143, 243) can extend substantially parallel to the top surface of the substrate, which can be the top surface of the substrate semiconductor layer 9. The back-side recesses (143, 243) can be vertically defined by the top surface of the underlying insulating layer (132 or 232) and the bottom surface of the insulating layer (132 or 232) covering it. In one embodiment, each of the first dorsal recess and the second dorsal recess may always have a uniform height.

[0155] In one embodiment, after removing the first and second sacrificial material layers (142, 242), the sidewall surfaces of each base channel portion 11 are physically exposed at each bottommost first back-side recess. Furthermore, the top surface of the substrate semiconductor layer 9 is physically exposed at the bottom of each back-side trench 79. An annular dielectric spacer 116 is formed around each base channel portion 11 by oxidizing the physically exposed peripheral portions of the base channel portion 11. Additionally, a semiconductor oxide portion (not shown) can be formed from each physically exposed surface portion of the substrate semiconductor layer 9 simultaneously with the formation of the annular dielectric spacer.

[0156] refer to Figures 13A to 13B A back-side barrier dielectric layer (not shown) may optionally be deposited in the back-side recess and back-side trench 79 and above the first contact-level dielectric layer 280. The back-side barrier dielectric layer may be deposited on a physically exposed portion of the outer surface of the memory stack structure 55. The back-side barrier dielectric layer comprises a dielectric material, such as a dielectric metal oxide, silicon oxide, or a combination thereof. If used, the back-side barrier dielectric layer may be formed by conformal deposition processes such as atomic layer deposition or chemical vapor deposition. The thickness of the back-side barrier dielectric layer may range from 1 nm to 60 nm, but smaller and larger thicknesses are also possible.

[0157] At least one conductive material may be deposited in the plurality of back-side recesses, on the sidewalls of the back-side trench 79, and above the first contact-level dielectric layer 280. The at least one conductive material may include at least one metallic material, i.e., a conductive material comprising at least one metallic element.

[0158] Multiple first conductive layers 146 can be formed in multiple first back-side recesses 143, multiple second conductive layers 246 can be formed in multiple second back-side recesses 243, and a continuous metal material layer (not shown) can be formed on the sidewalls of each back-side trench 79 and above the first contact level dielectric layer 280. Therefore, the first sacrificial material layer and the second sacrificial material layer (142, 242) can be replaced by the first conductive material layer and the second conductive material layer (146, 246), respectively. Specifically, each first sacrificial material layer 142 can be replaced by an optional portion of the back-side barrier dielectric layer and the first conductive layer 146, and each second sacrificial material layer 242 can be replaced by an optional portion of the back-side barrier dielectric layer and the second conductive layer 246. A back-side cavity exists within the portion of each back-side trench 79 that is not filled with the continuous metal material layer.

[0159] Metallic materials can be deposited using conformal deposition methods, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating, or combinations thereof. The metallic material can be an elemental metal, an intermetallic alloy of at least two elemental metals, a conductive nitride of at least one elemental metal, a conductive metal oxide, a conductive doped semiconductor material, a conductive metal-semiconductor alloy, such as metal silicides, alloys thereof, and combinations or stacks thereof. Non-limiting exemplary metallic materials that can be deposited in the backside recess include tungsten, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride, cobalt, and ruthenium. In one embodiment, the metallic material may include metals such as tungsten and / or metal nitrides. In one embodiment, the metallic material used to fill the backside recess may be a combination of a titanium nitride layer and a tungsten filler material. In one embodiment, the metallic material can be deposited using chemical vapor deposition or atomic layer deposition.

[0160] Residual conductive material can be removed from inside the back trench 79. Specifically, the deposited metal material can be etched back from the sidewalls of each back trench 79 and from above the first contact level dielectric layer 280, for example, by anisotropic or isotropic etching. Each remaining portion of the deposited metal material in the first back recess constitutes a first conductive layer 146. Each remaining portion of the deposited metal material in the second back recess constitutes a second conductive layer 246. Each conductive layer (146, 246) can be a conductive line structure.

[0161] A subset of the second conductive layer 246 located at the level of the drain-select layer dielectric isolation structure 72 constitutes the drain-select gate electrode. A subset of the first conductive layer 146 located at each level of the annular dielectric spacer (not shown) constitutes the source-select gate electrode. A subset of the conductive layers (146, 246) located between the drain-select gate electrode and the source-select gate electrode can be used as a combination of control gate and word line located at the same level. The control gate electrode within each conductive layer (146, 246) is the control gate electrode for a vertical memory device including the memory stack structure 55.

[0162] Each of the memory stack structure 55 comprises a vertically stacked memory element located at each level of the conductive layers (146, 246). A subset of the conductive layers (146, 246) may include word lines for the memory elements. The memory level assembly is positioned above the substrate semiconductor layer 9. The memory level assembly comprises at least one vertically alternating sequence (132, 146, 232, 246) and a memory stack structure 55 extending vertically through at least one vertically alternating sequence (132, 146, 232, 246). Each alternating stack (132, 146, 232, 246) comprises alternating layers of a corresponding insulating layer (132, 232) and a corresponding conductive layer (146, 246). Each alternating stack (132, 146, 232, 246) includes a stepped region comprising steps in which each underlying conductive layer (146, 246) extends further along a first horizontal direction hd1 than any overlying conductive layer (146, 246) within the memory hierarchy assembly. Typically, the first sacrificial material layer 142 and the second sacrificial material layer 242 may be replaced by the first conductive layer 146 and the second conductive layer 246, respectively.

[0163] refer to Figures 14A to 14C The back-side groove filling structure 76 can be formed in the remaining volume of each back-side groove 79. Figures 14A to 14C and Figures 42 to 44A In the illustrated embodiment, the back-side trench filling structure 76 comprises a dielectric separator. Dielectric isolation can be formed, for example, by depositing at least one dielectric material and removing excess portions of the deposited at least one dielectric material above a horizontal plane including the top surface of the first contact-level dielectric layer 280 via a planarization process (such as chemical mechanical planarization or recessed etching).

[0164] exist Figures 18A to 21In an alternative embodiment shown, the back-side trench fill structure 76 includes a back-side insulating spacer 74 and conductive local interconnects (e.g., source contacts) 75. The back-side insulating spacer 74 can be formed by depositing a relatively thin dielectric layer in the back-side trench 79, followed by performing anisotropic sidewall spacer etching to remove horizontal portions of the dielectric layer and leaving the back-side insulating spacer 74 on the sidewalls of the back-side trench 79. A conductive material (e.g., a metal, metal nitride, metal silicide, or heavily doped semiconductor) is then deposited on the back-side insulating spacer 74 and planarized to the top surface of the first contact-level dielectric layer 280 to form the local interconnects 75.

[0165] The back-side trench fill structure 76 provides electrical isolation in all lateral directions and extends laterally along the first horizontal direction hd1. Therefore, the back-side trench fill structure 76 is laterally elongated along the first horizontal direction hd1. As used herein, a structure is "laterally elongated" if its maximum lateral dimension along the first horizontal direction is greater than its maximum lateral dimension along a second horizontal direction that is laterally transverse to the first horizontal direction by at least a factor of 5.

[0166] The back-side trench filling structure 76 may include a first back-side trench filling structure 761 filling a first back-side trench 791, a second back-side trench filling structure 762 filling a second back-side trench 792, and an inter-array back-side trench filling structure 763 filling an inter-array back-side trench 793. Typically, the first back-side trench filling structure 761, the second back-side trench filling structure 762, and the inter-array back-side trench 793 can be formed by simultaneously depositing at least a dielectric material and optionally a conductive material (such as a metallic material) within the first back-side trench 791, the second back-side trench 792, and the inter-array back-side trench 793. Inter-array back-side insulating material portions (such as back-side insulating spacers 74) may be deposited directly on the sidewall of one of the first alternating stacks comprising the first three-dimensional memory array and directly deposited on the sidewall of one of the second alternating stacks comprising the second three-dimensional memory array within each inter-array back-side trench 793.

[0167] refer to Figure 15A and Figure 15B A second contact-level dielectric layer 282 may optionally be formed above the first contact-level dielectric layer 280. The second contact-level dielectric layer 282 comprises a dielectric material, such as silicon oxide or silicon nitride. The thickness of the second contact-level dielectric layer 282 may be in the range of 30 nm to 300 nm, but smaller and larger thicknesses are also possible.

[0168] A photoresist layer (not shown) may be applied over the second contact-level dielectric layer 282 and may be photolithographically patterned to form openings at locations where various contact via structures are subsequently formed. The openings in the photoresist layer include word line contact openings covering the horizontal surfaces of the first and second stepped surfaces in the contact region 200. Additionally, the openings in the photoresist layer include drain contact openings covering the top surface of the memory stack structure 55.

[0169] A reactive ion etching process is performed to transfer the pattern of openings in the photoresist layer through the underlying dielectric layer. Contact via cavities are formed through the underlying dielectric portions (282, 280, 270, 265, 165). The contact via cavities include drain contact via cavities formed through a second contact-level dielectric layer 282, a first contact-level dielectric layer 280, and a second insulating cap layer 270 above the top surface of the drain region 63 within the memory stack structure 55. The top surface of the drain region 63 is physically exposed at the bottom of the drain contact via cavities. The contact via cavities further include word line contact via cavities formed by an anisotropic etching process through the second contact-level dielectric layer 282, the first contact-level dielectric layer 280, the second insulating cap layer 270, and the second backward-stepped dielectric portion and the first backward-stepped dielectric portion (165, 265). The top surfaces (146, 246) of the first and second conductive layers are physically exposed at the bottom region of the word line contact via cavity.

[0170] At least one conductive material may be deposited in the contact via cavity. Excess portions of the at least one conductive material may be removed from above a horizontal plane comprising the top surface of the second contact-level dielectric layer 282 by a planarization process such as recess etching or chemical mechanical planarization (CMP). Each remaining portion of the at least one conductive material in the word line contact via cavity constitutes a layer contact via structure 86, and each remaining portion of the at least one conductive material in the drain contact via cavity constitutes a drain contact via structure 88.

[0171] The first contact via structure 86 within the first subset of the layer contact via structures 86 extends vertically through the second backward stepped dielectric portion 265 and the first backward stepped dielectric portion 165, and contacts the top surface of a corresponding one of the first conductive layers 146. The second contact via structure 86 within the second subset of the layer contact via structures 86 extends vertically through the second backward stepped dielectric portion 265, and contacts the top surface of a corresponding one of the second conductive layers 246.

[0172] refer to Figures 16A to 16DAt least one upper interconnect level dielectric layer 284 may be formed above the contact level dielectric layers (280, 282). Various upper interconnect level metal structures may be formed in the at least one upper interconnect level dielectric layer 284. For example, various upper interconnect level metal structures may include line level metal interconnect structures (96, 98). The line level metal interconnect structures (96, 98) may include a corresponding one of the contact drain contact via structures 88 and a bit line 98 extending along a second horizontal direction (e.g., bit line direction) hd2 and perpendicular to a first horizontal direction (e.g., word line direction) hd1. Note that only two subsets of bit lines 98 are shown in each plane (P0-P7), and some bit lines 98 are schematically indicated by dashed lines between the two sets of bit lines 98 in each plane (P0-P7). Furthermore, the line-level metal interconnect structure (96, 98) may include an upper metal line structure 96, the upper metal line structure contact layer contact via structure 86 and / or vertically extending through the top surface of another contact via structure (not shown) of a backward stepped dielectric material portion (165, 265) or other dielectric material portion (not shown). Additional metal interconnect structures (not shown) and additional dielectric material layers (not shown) may be formed to provide electrical interconnects between various components of the three-dimensional memory device in the first exemplary structure.

[0173] exist Figure 16C In one embodiment shown, bit line 98 includes a first bit line 981 formed in the even-numbered planes (P0, P2, P4, P6) and a second bit line 98 formed in the odd-numbered planes (P1, P3, P5, P7). Typically, the first bit line 981 and the second bit line 982 may be formed on a first alternating stack of a first insulating layer (132, 232) and a first conductive layer (146, 246) in each even-numbered plane (P0, P2, P4, P6), and on a second alternating stack of a second insulating layer (132, 232) and a second conductive layer (146, 246) in each odd-numbered plane (P1, P3, P5, P7). The first bit line 981 is electrically connected to a corresponding subset of the first vertical semiconductor channel 60 in the corresponding first three-dimensional memory array in one of the even-numbered planes (P0, P2, P4, P6), and is electrically isolated from the second vertical semiconductor channel 60 in any other three-dimensional memory array. The second bit line 982 is electrically connected to a corresponding subset of the second vertical semiconductor channel 60 in the corresponding second three-dimensional memory array in one of the odd planes (P1, P3, P5, P7), and is electrically isolated from the first vertical semiconductor channel 60 in any other three-dimensional memory array.

[0174] In an alternative implementation, bit line 98 may extend across both even and odd planes, such as Figure 16DAs shown. Each bit line 98 may be formed over an alternating stack of insulating layers (132, 232) and conductive layers (146, 246) within an even-numbered plane (P0, P2, P4, P6) and an odd-numbered plane (P1, P3, P5, P7). The bit line 98 is electrically connected to a vertical semiconductor channel 60 in the corresponding even-numbered plane (P0, P2, P4, P6) and the corresponding odd-numbered plane (P1, P3, P5, P7).

[0175] refer to Figure 17A and Figure 17B The diagram illustrates a logic die 700 according to an embodiment of the present disclosure. The logic die 700 may include a logic die substrate 708 and peripheral circuitry 710 formed thereon. The logic die substrate 708 includes a logic die substrate semiconductor layer 709 at least at its upper portion. A shallow trench isolation structure 720 may be formed in the upper portion of the logic die substrate semiconductor layer 709 to provide electrical isolation from other semiconductor devices. The peripheral circuitry 710 may include, for example, field-effect transistors (FETs) including respective transistor active regions 742 (i.e., source and drain regions), channel regions 746, and gate structures 750. The FETs may be arranged in a CMOS configuration. Each gate structure 750 may include, for example, a gate dielectric 752, a gate electrode 754, a dielectric gate spacer 756, and a gate cap dielectric 758.

[0176] The logic die 700 may have multiple planar peripheral (i.e., driver or control) circuits (Q0-Q7), each of which may have the same characteristics as... Figures 16C to 16D The corresponding planes (P0-P7) of the semiconductor die shown are identical regions. A logic die 700 may be one of multiple logic dies 700 disposed above the semiconductor wafer. Each plane of the logic die 700 includes peripheral circuitry (Q0-Q7) comprising peripheral circuitry 710, which is configured to... Figures 16C to 16D The corresponding three-dimensional memory array is operated within one of the planes (P0-P7) of the illustrated semiconductor die. In one embodiment, each plane peripheral circuit (Q0-Q7) of the logic die 700 may include: a word line driver circuit 620 including a word line switching transistor; a bit line driver circuit 630 including a sense amplifier; and miscellaneous peripheral circuitry 610 for subsequently electrically connected thereto to operate the corresponding three-dimensional memory array in the corresponding plane.

[0177] A dielectric material layer is formed over the semiconductor device, and the dielectric material layer is referred to herein as dielectric material layer 760. Dielectric material layer 760 may include, for example, a dielectric pad 762 (such as a silicon nitride pad that blocks the diffusion of mobile ions and / or applies appropriate stress to the underlying structure), an interconnect dielectric layer 764 over the dielectric pad 762, a silicon nitride layer (e.g., a hydrogen diffusion barrier layer) 766 over the interconnect dielectric layer 764, and a bonding pad-level dielectric layer 768.

[0178] A dielectric material layer 760 serves as a matrix for the metal interconnect structure 780, providing electrical connections between the peripheral circuitry 710 and the logic-side bonding pads 798. The logic-side bonding pads 798 are embedded within the bonding pad-level dielectric layer 768. Each dielectric material layer within the interconnect dielectric layer 764 may include any of doped silicate glass, undoped silicate glass, organosilicon glass, silicon nitride, silicon oxynitride, and dielectric metal oxides (such as aluminum oxide). In one embodiment, the interconnect dielectric layer 764 may include or be substantially composed of a dielectric material layer with a dielectric constant not exceeding 3.9 of undoped silicate glass (silicon oxide). The metal interconnect structure 780 is formed within the dielectric layer stack of the lower-level dielectric material layer 760. The metal interconnect structure 780 may include various metal via structures 786 and various metal line structures 788.

[0179] Typically, logic die 700 includes support circuitry configured to control the operation of memory die 900, which includes... Figures 16A to 16D A three-dimensional memory array within a plane (P0-P7). The logic-side bonding pad 798 may have Figure 18A and Figure 18B The pattern shown is a mirror image of the pattern of the memory-side bonding pad 998.

[0180] refer to Figure 18A and Figure 18B The logic die 700 can be coupled to Figures 16A to 16D The memory die 900. In Figure 18A In this context, the substrate semiconductor layer 9 includes a doped top portion of a semiconductor (e.g., silicon) substrate 8, such as a doped well in a silicon substrate. Figure 18B In the semiconductor layer 9, the substrate semiconductor layer includes a buried source line (e.g., a heavily doped polysilicon layer) located between the substrate (e.g., a silicon wafer) 8 and the first layer of alternating stacks (132, 146).

[0181] For example, wafer-to-wafer bonding can be used to integrate... Figures 16A to 16DA first wafer of multiple instances of a semiconductor die is bonded to a second wafer of multiple instances of a logic die 700. A logic-side bonding pad 798 is bonded to a corresponding memory-side bonding pad 998 via a metal-to-metal bonding. Where the bonding pad level dielectric layer 768 and the topmost dielectric layer 968 of the memory die 900 comprise silicon oxide, oxide-to-oxide bonding may be used in addition to or in place of metal-to-metal bonding.

[0182] Typically, logic-side bonding pad 798 can be bonded to a corresponding one of memory-side bonding pads 998. Logic die 700 includes support circuitry (i.e., peripheral circuitry) configured to control the operation of a three-dimensional memory device within memory die 900. If using... Figure 16C The configuration, then Figure 23 The optional cut region CR shown can be set at the bit line level between the first bit line 981 and the second bit line 982 of an adjacent pair of even and odd planes. Alternatively, if using Figure 16D In this configuration, the cutting region is omitted and each bit line 98 extends continuously on adjacent odd and even planes, such as... Figure 18A and Figure 18B As shown. The lateral spacing between adjacent pairs of planes of different sets of bit lines 98 can be the same as the width of the back groove filling structure 76.

[0183] Typically, bit line 98 can directly contact the corresponding subset of drain contact via structure 88, or can be electrically connected to the corresponding subset of drain contact via structure 88 through additional connection via structure 188.

[0184] Typically, alternating stacks of insulating layers (132, 232) and spacer material layers (such as sacrificial material layers (142, 242)) may be formed over the substrate. The spacer material layers may be formed as conductive layers (146, 246), or may subsequently be replaced by these conductive layers. Groups of memory openings 49 may be formed through the alternating stacks (132, 232). Groups of memory opening-filling structures 58 may be formed in the memory openings 49. Each of the memory opening-filling structures 58 includes a memory stack structure 55 comprising a respective vertical stack of memory elements (which may include portions of memory films 50 located at the levels of the conductive layers (146, 246)) and a respective vertical semiconductor channel 60. Each of the memory opening-filling structures 58 may include a vertical NAND string containing the vertical stack of memory elements. Alternating stacks of insulating layers (132, 132) and conductive layers (146, 246) may be formed over the substrate. The back-side trench-filled structure 76 can be formed through alternating stacks {(132,146), (232,246)}. For each alternating stack of insulating layer (132,232) and conductive layer (146,246), a pair of back-side trench-filled structures 76 can be formed through alternating stacks {(132,146), (232,246)}.

[0185] refer to Figure 19A and Figure 19B The back side of substrate 8 can be thinned, for example, by grinding, polishing, anisotropic etching, and / or isotropic etching. The thickness of the substrate semiconductor layer 9 after thinning (i.e., Figure 19A doped wells or Figure 19B Buried source lines (in this context) can range from 100 nm to 6,000 nm, but smaller and larger thicknesses are also possible. Figure 19A In one embodiment shown, the substrate semiconductor layer 9 may be a single-crystal semiconductor material layer, such as a single-crystal silicon layer. Figure 19B In another embodiment shown, the substrate semiconductor layer 9 may be a polycrystalline semiconductor material layer, such as a doped polycrystalline silicon layer. The substrate semiconductor layer 9 constitutes a source-level material layer (e.g., a source line). In one embodiment, the source-level material layer may be doped with a second conductivity type dopant, for example, by ion implantation or vapor diffusion. In an alternative embodiment, the second conductivity type dopant may be implanted or diffused from the front side of the substrate semiconductor layer 9 before the formation of the first alternating stack of the first insulating layer 132 and the first sacrificial material layer 142. Figure 19B In another alternative embodiment shown, a dopant of a second conductivity type may be provided in situ during the growth of the buried source line.

[0186] refer to Figure 20A and Figure 20BA photoresist layer may be applied over the back side of the substrate semiconductor layer 9 and may be photolithographically patterned to form linear openings extending laterally along a first horizontal direction hd1. An anisotropic etching process may be performed to divide the substrate semiconductor layer 9 into a plurality of semiconductor material layers, which serve as source regions (or combinations of source regions and source lines) of corresponding groups of vertical semiconductor channels 60 located in the same region (e.g., a string cell region). These plurality of semiconductor material layers are referred to below as source layers 9. A thinned substrate semiconductor layer 9 doped with a second conductivity type serves as a source level material layer, and a plurality of source layers 9 are formed by patterning the thinned substrate semiconductor layer 9. A plurality of source-side trenches 21 are formed through the source level material layers such that each adjacent pair of source layers 9 is laterally spaced from each other by a corresponding one of the plurality of source-side trenches 21. The plurality of source layers 9 are laterally spaced from each other and electrically isolated. Each group of memory aperture-filled structures 58 contacts a corresponding one of the plurality of source layers 9. Each adjacent pair of source layers 9 is laterally spaced from each other by a corresponding one of the plurality of source-side trenches 21. Dielectric material may be deposited in the source-side trenches 21 and over the source layers 9 to form a source-level dielectric isolation structure 23 located in the corresponding trench 21.

[0187] refer to Figure 21 This illustrates the formation of multiple source layers 9 (e.g., Figure 18A The type shown or Figure 18B This is a first alternative configuration of the first exemplary structure following the buried source line shown. In this first alternative configuration, the plurality of source-side trenches 21 extend through the source layer material to form a source layer 9 and through at least one topmost conductive layer 146 below the source layer 9 to form separate source-side selected gate electrodes (SGS) (i.e., source-side selected gate lines) 146S. Each patterned first conductive layer 146 within a first subset of conductive layers (146, 246) can be partitioned into a plurality of source-side selected gate electrodes 146S by forming the source-side trenches 21. The source-side trenches 21 do not partition a second subset of conductive layers that serves as word lines (i.e., word lines) (146W, 246W) extending laterally between adjacent pairs of back-side trench-filled structures 76 along the word line direction hd1. The source-side trenches 21 also do not partition the drain-side selected gate electrodes 246D separated by the drain-side selected layer dielectric isolation structure 72. Dielectric material can be deposited in the source-side trench 21 and above the source layer 9 to form a source-level dielectric isolation structure 23 located in the corresponding trench 21.

[0188] Figures 22A to 22D An alternative configuration of the memory opening 49 during the formation of the memory opening filling structure 58, according to a second embodiment of the present disclosure, is shown.

[0189] refer to Figure 22A Interlayer memory opening 49 (i.e., memory opening 49) or interlayer support opening 19 in Figure 8 The processing steps are shown in the diagram.

[0190] refer to Figure 22B The blocking dielectric layer 52, charge storage layer 54, and tunneling dielectric layer 56 can be executed Figure 9B The processing steps are deposited in the interlayer memory opening 49. The combination of the barrier dielectric layer 52, the charge storage layer 54 and the tunneling dielectric layer 56 constitutes the memory film 50.

[0191] refer to Figure 22C The semiconductor channel layer 60L can be deposited on the memory film 50. The semiconductor channel layer 60L can be deposited in the same manner as the first semiconductor channel layer 601 or the second semiconductor channel layer 602 described above, and can have the same material composition as the first semiconductor channel layer 601 and / or the second semiconductor channel layer 602. The thickness of the semiconductor channel layer 60L can be the same as the sum of the thicknesses of the first semiconductor channel layer 601 or the second semiconductor channel layer 602.

[0192] refer to Figure 22D Executable Figure 9F , 9G The processing steps of 9H are used to form the dielectric core 62 and drain region 63 within each memory opening filling structure 58. Each remaining portion of the semiconductor channel layer 60L constitutes a vertical semiconductor channel 60.

[0193] Subsequently, the processing steps of Figures 10 to 18 can be performed to form a second exemplary structure of a bonding assembly including a memory die 900 and a logic die 700 according to a second embodiment of the present disclosure. Each alternating stack of insulating layers (132, 232) and conductive layers (146, 246) may be laterally defined by a pair of back-side trench-filled structures 76.

[0194] refer to Figure 23 , Figure 16C The optional cut region CR between the first bit line 981 and the second bit line 982 shown may exist in the memory die 900 between adjacent planes P0 and P1. Alternatively, the cut region CR may be omitted, and alternatively provided Figure 16D And the continuous bit line 98 shown in Figure 20.

[0195] refer to Figure 23 and Figure 24AThe substrate semiconductor layer 9 can be removed from the back side of the bonding assembly, for example, by grinding, polishing, anisotropic etching, or isotropic etching. For example, the substrate semiconductor layer 9 can be thinned from the back side by grinding, and an isotropic or anisotropic etching process can be performed to selectively remove the remaining portion of the substrate semiconductor layer 9 from the memory film 50. For example, the isotropic etching process may include a wet etching process using potassium hydroxide.

[0196] refer to Figure 24B A series of isotropic etching processes can be performed to etch the physically exposed portion (i.e., the bottom portion) of the storage film 50. This series of isotropic etching processes can be selected to selectively etch the materials of the barrier dielectric layer 52, the charge storage layer 54, and the tunneling dielectric layer 56 sequentially for the materials of the vertical semiconductor channel 60, thereby exposing at least the bottom portion of the vertical semiconductor channel 60.

[0197] refer to Figure 25A and Figure 25B The source-level material layer 109 may be deposited on the physically exposed end face of the vertical semiconductor channel 60, referred to herein as the near end face. The source-level material layer 109 includes at least one conductive material. In one embodiment, the source-level material layer 109 includes a heavily doped semiconductor material, such as polycrystalline silicon. In another embodiment, the source-level material layer 109 may comprise a vertical stack of a heavily doped polycrystalline source semiconductor (e.g., polycrystalline silicon) layer 109A with doping of a second conductivity type and a metal source layer 109B (such as a metal silicide (e.g., titanium silicide, tungsten silicide, cobalt silicide, or nickel silicide) or a metal (e.g., tungsten, aluminum, molybdenum, copper, etc.). Typically, the source-level material layer 109 can be formed by replacing the substrate with at least one conductive material layer.

[0198] refer to Figure 26A and Figure 26B Source-side trenches 21 can be formed through source-level material layers 109. Each of the source-side trenches 21 can extend laterally along a first horizontal direction (i.e., word line direction) hd1, and the source-level material layers 109 can be laterally divided into multiple source structures, referred to herein as source lines 109. A subset of source-side trenches 21A extends to a proximal subset near the first conductive layer 146 of the source layer 109. An optional second subset of source-side trenches 21B extends vertically to the back-side trench-filling structure 76. Dielectric material can be deposited in the source-side trenches 21 and above the source layer 9 to form source-level dielectric isolation structures 23 located in the respective trenches 21. Figure 26A It shows Figure 16C The configuration of the dividing lines (981, 982), and Figure 26B It shows Figure 16D The configuration of the continuous position line 98.

[0199] refer to Figure 27 , showed Figure 26A and Figure 26B A circuit diagram of the second exemplary structure is shown below. For clarity, Figure 27 The device is shown in 16 staggered rows, while Figure 26A and Figure 26B The device is shown with 24 interleaved rows. The source lines (SL1, SL2, SL3, SL4) may include... Figure 26A and Figure 26B The source layer 109 shown is or Figure 20A or Figure 20B Source layer 9 is shown. By dividing a single source line into four source layers (e.g., source lines), smaller erase cells EU with a smaller number of memory cells can be erased during the erase step (including gate-induced drain leakage (GIDL) erase step), during which an erase voltage is applied to the corresponding source line (e.g., Figure 27 (SL1 in the example). Therefore, the size of the functional memory block (i.e., the erase cell EU) is reduced. This reduces the operating leakage current.

[0200] Referring to both the first and second exemplary structures, a plurality of source layers (9 or 109) can be formed by patterning source-level material layers. The plurality of source layers (9 or 109) are laterally spaced and electrically isolated from each other, and each group of memory opening-fill structures 58 is accessible to a corresponding one of the plurality of source layers (9 or 109). A plurality of source-side trenches 21 can be formed through the source-level material layers, wherein each adjacent pair of source layers (9, 109) is laterally spaced from each other by a corresponding one of the plurality of source-side trenches 21.

[0201] refer to Figure 28This illustrates a third exemplary structure according to a third embodiment of the present disclosure after the removal of the substrate semiconductor layer 9 and after the formation of the source select level trench 17. In this case, the source select level trench 17 is formed through a first subset of the conductive layers (i.e., source-side select gate electrodes) 146S after the removal of the substrate 8 and before the formation of the at least one conductive material layer subsequently used to form the source layer 109. Typically, a plurality of source-side select gate electrodes (i.e., source select level conductive layers) 146S can be formed by forming the source select level trench 17 through the plurality of source-side select gate electrodes 146S before or after the formation of the source level material layers. The source select level trench 17 does not divide word lines (146W, 246W) or drain-side select gate electrodes 146D. The source select level trench 17 are source-side trenches that extend vertically through the source-side select gate electrodes 146S, which are subsets of the conductive layers (146, 246). The source-side gate electrode 146S can activate or deactivate a corresponding string group of the vertical semiconductor channel 60 of the NAND string, thereby selecting or deselecting the NAND string group within the three-dimensional memory array. Although Figure 28 The configuration of the dividing bit line 98 is shown, but it should be understood that alternatives can be used. Figure 16D or Figure 26B The configuration of the continuous position line 98.

[0202] refer to Figure 29 Dielectric materials such as silicon oxide can be deposited in the source selection layer trench 17. Excess dielectric material can be removed from above a horizontal plane including the topmost insulating layer (such as the nearest first insulating layer 132) by a planarization process. A source selection layer dielectric isolation structure 22 including the remaining portion of the dielectric material can be formed in the source selection layer trench 17.

[0203] refer to Figure 30 Executable Figure 25A and Figure 25B The processing steps involve forming a source-level material layer 109, referred to herein as the near-end face, on the physically exposed end face of the vertical semiconductor channel 60. The source-level material layer 109 includes at least one conductive material. In one embodiment, the source-level material layer 109 may comprise a vertical stack of a polycrystalline source semiconductor layer 109A doped with a second conductivity type and a metal source layer 109B comprising a metallic material. Typically, the source-level material layer 109 can be formed by replacing the substrate 8 with at least one conductive material layer 109. In a third embodiment, it may be present or omitted. Figure 26A and Figure 26B Source side trench 21.

[0204] refer to Figure 31A , showed Figure 30A circuit diagram of the third exemplary structure. Four split source-side gate electrodes 146S1, 146S2, 146S3, and 146S4 are used in... Figure 31A As shown in the diagram. However, there may be two, three, or more than four split source-side select gate electrodes. A single source line SL may include Figure 20A or Figure 20B Source layer 9 or shown Figure 29 The source layer 109 is shown. In this embodiment, a smaller erase cell EU with a smaller number of memory cells can be erased during the erase step, during which an erase voltage is applied to the common source line SL. Therefore, the size of the functional memory block (i.e., the erase cell EU) is reduced. This reduces operating leakage current.

[0205] refer to Figure 31B A schematic top view of a third exemplary structure is shown. A plurality of source-side select gate electrodes 146S located at the same vertical level are laterally spaced from each other in the horizontal direction by a source-select level dielectric isolation structure 22. These plurality of source-side select gate electrodes 146S are located vertically between at least one source layer (9, 109) and word lines (146w, 246w).

[0206] refer to Figure 32 This illustrates a fourth exemplary structure according to a fourth embodiment of the present disclosure, which can be used with... Figure 25A and Figure 25B The second exemplary structure shown is the same. This structure may include... Figure 16C The dividing lines (981, 982) or Figure 16D The continuous position line is 98.

[0207] refer to Figure 33 A source-side trench 21 can be formed by passing through the source-level material layer 109 and through a first subset of the conductive layers (such as the proximal subset of the first conductive layer 146). The pattern of the source-side trench 21 can be consistent with... Figure 26A and Figure 26B The source-side trenches in the exemplary structure shown have identical patterns. Multiple source layers 109 are formed by patterning the source-level material layers 109. These multiple source layers 109 are laterally spaced and electrically isolated from each other. Each string group of the memory aperture-filled structure 58 contacts a corresponding one of the multiple source layers 109.

[0208] Each patterned first conductive layer 146 within a first subset of conductive layers (146, 246) can be divided into multiple source-side selected gate electrodes 146S by forming source-side trenches 21. The source-side trenches do not divide word lines (146W, 246W) or drain-side selected gate electrodes 246D. Dielectric material can be deposited in the source-side trenches 21 and over the source layer 109 to form source-level dielectric isolation structures 23 located within the respective trenches 21.

[0209] A first subset of the source-side trench 21 extends into a corresponding one of the back-side trench-filled structures 76. A second subset of the source-side trench 21 extends into a proximal subset of one or more conductive layers 146 and divides it into a corresponding plurality of source-side selected gate electrodes 146S.

[0210] refer to Figure 34 This illustrates a first alternative configuration of a fourth exemplary structure according to a fourth embodiment of the present disclosure. The first alternative configuration of the fourth exemplary structure can be achieved by depositing dielectric material in the source-side trench 21 and over the source layer 109. Figure 33 The fourth exemplary structure is derived to form a source-level dielectric isolation layer 122, such that each portion of the layer 122 protruding downward into the corresponding trench 21 includes a combination of a source-level isolation structure 23 and a source-selection-level isolation structure 22.

[0211] refer to Figure 35 A second alternative configuration of the fourth exemplary structure according to the fourth embodiment of this disclosure can be achieved by partitioning the source-level material layer 109 and partitioning the source-side selected gate layer 146S in separate steps. Figure 30 Derived from the third exemplary structure. For example, as Figure 29 As shown, a source selection layer dielectric isolation structure 22 is first formed in the source-side selected gate layer 146S. Then, a source layer material layer 109 is deposited over the source selection layer dielectric isolation structure 22 and the source-side selected gate layer 146S, followed by... Figure 26A and Figure 26B The method shown forms source-side trenches 21 in the source-level material layer 109 to divide the layer 109 into the plurality of source layers 109. Dielectric material may be deposited in the source-side trenches 21 and above the source layers 9 to form source-level dielectric isolation structures 23 located in the respective trenches 21.

[0212] refer to Figure 36 , showed Figures 32 to 35Circuit diagrams of various configurations of the fourth exemplary structure are shown. Multiple segmented source lines (SL1, SL2, SL3, SL4) and multiple segmented source-side selected gate electrodes (146S1, 146S2, 146S3, 146S4) may be formed between a pair of back-side trench-filled structures 76. Each block of the vertical NAND string can be activated or deactivated via the source layer (9, 109), via the source-side selected gate electrodes 146S, or via a combination of the source layer and the source-side selected gate electrodes 146S.

[0213] refer to Figure 37 An exemplary structure for providing electrical connections to the source layers (9 or 109) is illustrated according to embodiments of this disclosure. Specifically, a back-side metal interconnect structure 930, such as an aluminum strip, may be employed to provide electrical connections between the metal interconnect structure 980A (i.e., a subset of the structure 980 described above) and each source layer (9 or 109). The subset of the back-side metal interconnect structure 930 may contact the back-side surface of a corresponding one of the source layers (9 or 109).

[0214] refer to Figure 38 Another exemplary structure for providing electrical connections to the source layer (9 or 109) is illustrated according to an embodiment of the present disclosure. In this case, the metal interconnect structure 980A may contact the front surface of a corresponding one of the source layers (9 or 109).

[0215] refer to Figure 39A and Figure 39B By modifying the pattern of the memory opening filling structure 58, it is possible to... Figure 10A and Figure 10B The first exemplary structure derives a fifth exemplary structure according to a fifth embodiment of the present disclosure. Specifically, the memory opening 49 and the memory opening fill structure 58 may be formed at a distance such that all memory opening fill structures 58 remain effective after the formation of the drain selection layer dielectric isolation structure 72. Conversely, in Figure 10A and FIG. 10B In the first exemplary structure, each fifth row of the memory aperture filling structure 58 acts as a dummy memory aperture filling structure 58 because it is cut in half by the corresponding drain selection level dielectric isolation structure 72.

[0216] refer to FIG. 40A and FIG. 40BA drain-selection layer dielectric isolation structure 72 can be formed through a distal subset of the second sacrificial material layer 242 away from the substrate semiconductor layer 9. In this case, the drain-selection layer dielectric isolation structure 72 can be formed between rows of a pair of memory opening-fill structures 58, and the edge portions of each memory opening-fill structure 58 in the row of the pair of memory opening-fill structures 58 can be cut. Each drain-selection layer dielectric isolation structure 72 can extend laterally along a first horizontal direction hd1.

[0217] refer to FIG. 41 and FIG. 42 The processing steps shown in Figures 11 to 19 can be executed. FIG. 23 The processing steps. In one implementation, the following can be adopted: FIGS. 22A-22D The processing steps form each of the memory opening-filled structures 58. In this case, a series of isotropic etching processes can be used to remove the proximal portion of the memory film 50 and physically expose the proximal portion of the vertical semiconductor channel 60.

[0218] refer to FIG. 43 A photoresist layer (not shown) may be applied to the physically exposed proximal surfaces of alternating stacks {(132,146), (232,246)} and may be photolithographically patterned to form linear openings in the region covering the drain-select-level dielectric isolation structure 72. An anisotropic etching process may be performed to etch through a first subset of the conductive layers (such as the proximal subset of the first conductive layer 146) to form a source-side select-gate electrode 146S. A source-select-level trench 17 may be formed through the first subset of the conductive layers into the source-side select-gate electrode 146S.

[0219] refer to FIG. 44A and FIG. 44B Source selection level dielectric isolation structure 22 can be formed in source selection level trench 17 by depositing dielectric material such as silicon oxide and removing excess portion of dielectric material from above the alternating stack of insulating layers (132, 232) and conductive layers (146, 246).

[0220] refer to FIG. 45 Executable FIG. 32 The processing steps are used to form a source layer material layer 109, which can be used as a single source layer 109.

[0221] refer to FIG. 46 Optional execution FIG. 35The processing steps divide the source-level material layer 109 into multiple source layers 109. Dielectric material may be deposited in the source-side trench 21 and above the source layers 109 to form source-level dielectric isolation structures 23 located in the respective trenches 21. Typically, multiple source layers 109 can be formed by patterning the source-level material layer. The multiple source layers 109 are laterally spaced and electrically isolated from each other. Each group of memory aperture-filled structures 58 contacts a corresponding one of the multiple source layers 109.

[0222] Referring to all the accompanying drawings and according to various embodiments of the present disclosure, a three-dimensional memory device includes: an alternating stack of insulating layers (132, 232) and conductive layers (146, 246) over a plurality of source layers (9, 109), wherein the alternating stack is located between a pair of back-side trench-filled structures 76; a memory opening 49 extending vertically through the alternating stack {(132, 146), (232, 246)}; and a group of memory opening-filled structures 58 located in the memory opening 49, wherein the memory opening-filled structures 58 are... Each includes a corresponding vertical stack of memory elements (which may include a portion of charge storage layer 54 located at the word line (146W, 246W) level); a corresponding vertical semiconductor channel 60 having a first end contacting a corresponding one of the plurality of source layers (9, 109); and a corresponding drain region 63 contacting a second end of the corresponding vertical semiconductor channel 60; wherein: the plurality of source layers (9, 109) are laterally spaced apart from each other and electrically isolated; and each group of memory opening-fill structures 58 contacts a corresponding one of the plurality of source layers.

[0223] In one embodiment, the plurality of source layers 9 comprise a plurality of single-crystal semiconductor material layers having the same crystallographic orientation. In one embodiment, each of the memory aperture-fill structures 58 includes a base channel portion 11 comprising a single-crystal semiconductor material having dopants of an opposite conductivity type to the plurality of single-crystal semiconductor material layers and contacting a corresponding one of the plurality of single-crystal semiconductor material layers.

[0224] In one embodiment, the plurality of source layers 109 include a plurality of polycrystalline source semiconductor layers 109A; and each of the memory aperture filling structures 58 contacts a corresponding one of the plurality of polycrystalline source semiconductor layers 109A. In one embodiment, each of the plurality of source layers 109 includes a corresponding stack of source semiconductor layers 109A and metal source layers 109B.

[0225] In one embodiment, the plurality of source layers (9, 109) are laterally spaced apart from each other by respective source layer dielectric isolation structures 23. In one embodiment, the conductive layer includes: word lines (146w, 246w) that extend laterally continuously between the pair of back-side trench fill structures 76 and contact each of the pair of back-side trench fill structures; and a plurality of source-side select gate electrodes 146S located vertically between the plurality of source layers (9, 109) and the word lines (146w, 246w). The plurality of source-side select gate electrodes 146S are laterally spaced apart by source-select layer dielectric isolation structures 23.

[0226] In one implementation, each of the source-level dielectric isolation structures 23 contacts a corresponding one of the source-level dielectric isolation structures 22. FIG. 21 In the configuration, each of the source-level dielectric isolation structures 23 has a sidewall that vertically coincides with the corresponding one in the source-selection-level dielectric isolation structure (i.e., a continuous straight sidewall with either a continuous taper or no taper in the vertical direction). FIG. 35 In this configuration, a horizontal step exists between each of the source-level dielectric isolation structures 23 and the corresponding one of the source-selection-level dielectric isolation structures 22. FIG. 34 In the configuration, the source horizontal isolation dielectric layer 120 contacts the back side of each of the plurality of source layers 109 and includes vertically downward protruding portions 122, which include both source layer dielectric isolation structure 23 and source selection layer dielectric isolation structure 22.

[0227] In one embodiment, each of the plurality of source layers (9, 109) contacts only one of the pairs of back-side trench fill structures 76 or does not contact either of the pairs of back-side trench fill structures 76. In one embodiment, each of the plurality of source-side selected gate electrodes 146S laterally surrounds a corresponding group of memory opening fill structures 58 and is laterally spaced from any other group of memory opening fill structures 58 in the group of memory opening fill structures 58.

[0228] In one embodiment, the three-dimensional memory device includes a bit line 98 and a drain contact via structure 88 for contacting a drain region 63. The conductive layers (146, 246) include a plurality of drain select level conductive layers 246D, which are vertically positioned between the word line (146w, 246w) and the bit line 98 and laterally spaced by drain select level dielectric isolation structures 72. In one embodiment, each of the back-side trench fill structures 76 includes a dielectric structure or conductive local interconnect 75 surrounded by insulating spacers 74, such as... FIG. 18A As shown.

[0229] According to another aspect of this disclosure, a three-dimensional memory device includes: an alternating stack of insulating layers (132, 232) and conductive layers (146, 246) located above at least one source layer (9, 109) and between a pair of back-side trench filling structures 76; a group of memory openings 49 extending vertically through the alternating stack {(132, 146), (232, 246)}; and a group of memory opening filling structures 58 located within the group of memory openings 49, wherein each of the memory opening filling structures 58 includes a corresponding vertical stack of memory elements (including a portion of a charge storage layer 54 located at the level of word lines (146W, 246W); a corresponding vertical semiconductor channel 60 having a first end contacting the at least one source layer (9, 109); and a corresponding drain region 63 contacting a second end of the corresponding vertical semiconductor channel 60. The conductive layers (146, 246) include: word lines (146w, 246w) that extend laterally continuously between the pair of back-side trench fill structures 76 and contact each of the pair of back-side trench fill structures; and a plurality of source-side select gate electrodes 146S that are located vertically between the at least one source layer (9, 109) and the word lines (146w, 246w) and horizontally between the pair of back-side trench fill structures 76, wherein the plurality of source-side select gate electrodes 146S are laterally spaced apart by a source select layer dielectric isolation structure 22.

[0230] In one embodiment, the vertical semiconductor channel 60 comprises a semiconductor material doped with a first conductivity type; and the at least one source layer (9, 109) comprises a semiconductor material layer doped with a second conductivity type opposite to the first conductivity type. In one embodiment, the at least one source layer (9, 109) comprises a continuous source layer contacting each of the first ends of each of the vertical semiconductor channels 60. In one embodiment, each of the source selection layer dielectric isolation structures 22 comprises a first horizontal surface contacting one of the insulating layers (132, 232) and a second horizontal surface contacting the at least one source layer (9, 109).

[0231] In another embodiment, the at least one source layer (9, 109) comprises a plurality of source layers laterally spaced apart from each other. Each group of memory opening-fill structures 58 contacts a corresponding one of the plurality of source layers (9, 109) and is electrically isolated from all other source layers (9, 109).

[0232] In one embodiment, the plurality of source layers (9, 109) are laterally spaced apart from each other by respective source-level dielectric isolation structures 23. In one embodiment, each of the source-level dielectric isolation structures 23 contacts a corresponding one of the source-selective dielectric isolation structures 22. FIG. 21 In the configuration, each of the source-level dielectric isolation structures 23 has a sidewall that vertically coincides with the corresponding one in the source-selection-level dielectric isolation structure (i.e., a continuous straight sidewall with either a continuous taper or no taper in the vertical direction). FIG. 35 In this configuration, a horizontal step exists between each of the source-level dielectric isolation structures 23 and the corresponding one of the source-selection-level dielectric isolation structures 22. FIG. 34 In the configuration, the source horizontal isolation dielectric layer 120 contacts the back side of each of the plurality of source layers 109 and includes vertically downward protruding portions 122, which include both source layer dielectric isolation structure 23 and source selection layer dielectric isolation structure 22.

[0233] In one embodiment, each of the back-side trench-filled structures 76 includes a dielectric structure or conductive local interconnect 75 surrounded by insulating spacers 74, such as FIG. 18A As shown.

[0234] In one embodiment, the plurality of source layers 109 include a plurality of polycrystalline semiconductor layers 109A. In one embodiment, each of the plurality of source layers (9, 109) contacts only one of the pairs of back-side trench fill structures 76 or does not contact either of the pairs of back-side trench fill structures 76. In one embodiment, each of the plurality of source-side selected gate electrodes 146S laterally surrounds a corresponding group of memory aperture fill structures 58 and is laterally spaced from any other group of memory aperture fill structures 58 in the group of memory aperture fill structures 58.

[0235] In one implementation, the number of reprogramming steps is reduced by performing erase operations on smaller memory strings instead of the entire memory block. This improves programming speed. Furthermore, select / unselect operations are performed on the string cells with higher precision. The area of ​​interfering memory cells in the erase unit EU is reduced. Therefore, stress on unselected NAND strings is reduced and cell degradation is improved.

[0236] Although specific embodiments have been mentioned for the foregoing, it should be understood that this disclosure is not limited thereto. Those skilled in the art will appreciate that various modifications can be made to the disclosed embodiments, and such modifications are intended to fall within the scope of this disclosure. Compatibility is assumed in all embodiments that are not alternatives to each other. Unless otherwise expressly stated, the words “comprising” or “including” contemplate that the words “substantially constitute…” or “consist of…” replace all embodiments in which the words “comprising” or “including” are used. While embodiments employing specific structures and / or configurations are shown in this disclosure, it should be understood that this disclosure can be practiced with any other functionally equivalent compatible structures and / or configurations, provided that such substitutions are not expressly prohibited or otherwise considered impossible by those skilled in the art. All publications, patent applications, and patents cited herein are incorporated herein by reference in their entirety.

Claims

1. A three-dimensional memory device, comprising: an alternating stack of insulating layers and electrically conductive layers over a plurality of source layers, wherein the alternating stack is between a pair of backside trench fill structures, wherein the electrically conductive layers comprise word lines and a plurality of source-side select gate electrodes between the plurality of source layers and the word lines in a vertical direction, source-side trenches extending through both the source-side select gate electrodes and the plurality of source layers, wherein the source-side trenches do not divide the word lines; a set of memory openings vertically extending through the alternating stack; and a set of memory opening fill structures in the set of memory openings, wherein each of the memory opening fill structures comprises: a respective vertical stack of memory elements; a respective vertical semiconductor channel having a first end contacting a respective one of the plurality of source layers; and a respective drain region contacting a second end of the respective vertical semiconductor channel, wherein: the plurality of source layers are laterally spaced apart from one another and electrically isolated; and each set of memory opening fill structures contacts a respective one of the plurality of source layers.

2. The three-dimensional memory device of Claim 1, wherein the plurality of source layers comprise a plurality of monocrystalline semiconductor material layers having a same crystallographic orientation.

3. The three-dimensional memory device of Claim 2, wherein each of the memory opening fill structures comprises a base channel portion comprising a monocrystalline semiconductor material having a doping of opposite conductivity type relative to the plurality of monocrystalline semiconductor material layers and contacting a respective one of the plurality of monocrystalline semiconductor material layers.

4. The three-dimensional memory device of Claim 1, wherein: the plurality of source layers comprise a plurality of polycrystalline source semiconductor layers; and each of the memory opening fill structures contacts a respective one of the plurality of polycrystalline source semiconductor layers.

5. The three-dimensional memory device of Claim 1, wherein each of the plurality of source layers comprises a respective stack of a source semiconductor layer and a metal source layer.

6. The three-dimensional memory device of Claim 1, wherein: the plurality of source layers are laterally spaced apart from one another by respective source layer-level dielectric isolation structures filling the source-side trenches; and each of the source-side select gate electrodes comprises a respective sidewall contacting one of the source layer-level dielectric isolation structures.

7. The three-dimensional memory device of Claim 6, wherein the plurality of source-side select gate electrodes are laterally spaced apart by a source select level dielectric isolation structure.

8. The three-dimensional memory device of Claim 7, wherein each of the source layer-level dielectric isolation structures contacts a respective one of the source select level dielectric isolation structures.

9. The three-dimensional memory device of Claim 8, wherein each of the source-level dielectric isolation structures has a sidewall that is vertically coincident with the corresponding one of the source-select-level dielectric isolation structures.

10. The three-dimensional memory device of Claim 8, wherein there is a horizontal step between each of the source-level dielectric isolation structures and a corresponding one of the source-select-level dielectric isolation structures.

11. The three-dimensional memory device of Claim 8, further comprising a source-level isolation dielectric layer that contacts a backside of each of the plurality of source layers and comprises a vertically downward protruding portion that includes the source-level dielectric isolation structures.

12. The three-dimensional memory device of Claim 7, wherein: each of the pair of backside trench fill structures comprises a dielectric structure surrounded by an insulating spacer or a conductive partial interconnect; each of the plurality of source layers contacts only one of the pair of backside trench fill structures or does not contact either of the pair of backside trench fill structures; and each of the plurality of source-side select gate electrodes laterally surrounds a respective set of memory opening fill structures and is laterally spaced apart from any other set of memory opening fill structures of the memory opening fill structure set.

13. The three-dimensional memory device of Claim 8, further comprising bit lines and drain contact via structures that contact the drain regions, wherein the conductive layers comprise a plurality of drain-select-level conductive layers that are located in a vertical direction between the word lines and the bit lines and are laterally spaced apart by drain-select-level dielectric isolation structures.

14. A method of forming a three-dimensional memory device, the method comprising: forming an alternating stack of insulating layers and spacer material layers over a substrate, wherein the spacer material layers are formed as conductive layers or are subsequently replaced with conductive layers; forming a set of memory openings through the alternating stack; forming a set of memory opening fill structures in the memory openings, wherein each of the set of memory opening fill structures comprises a respective vertical stack of memory elements and a respective vertical semiconductor channel; forming a source-level material layer by thinning the substrate, by removing the substrate, or by replacing the substrate with at least one conductive material layer; and forming a plurality of source layers by patterning the source-level material layer, wherein the plurality of source layers are laterally spaced apart from one another and electrically isolated, and wherein each set of memory opening fill structures contacts a respective one of the plurality of source layers; and wherein the conductive layers comprise word lines and source-side select gate electrodes that are located in a vertical direction between the plurality of source layers and the word lines, and the three-dimensional memory device comprises source-side trenches that extend through both the source-side select gate electrodes and the plurality of source layers, wherein the source-side trenches do not divide the word lines.

15. The method of claim 14, wherein the substrate comprises a semiconductor material, and the source-level material layer is formed by thinning the substrate.

16. The method of claim 14, further comprising forming a buried source line between the substrate and the alternating stack, and the source-level material layer comprises the buried source line exposed after the step of removing the substrate.

17. The method of claim 14, wherein the source-level material layer is formed by replacing the substrate with the at least one electrically conductive material layer.

18. The method of claim 14, further comprising: forming a plurality of source-side trenches through the source-level material layer, wherein each adjacent pair of source layers in the plurality of source layers is laterally spaced apart from one another by a respective one of the plurality of source-side trenches; and forming a plurality of source-level dielectric isolation structures in respective source-side trenches.

19. The method of claim 18, further comprising forming a pair of backside trench fill structures through the alternating stack, wherein: a first subset of the source-side trenches vertically extend into the pair of backside trench fill structures; and a second subset of the source-side trenches extend into a proximal subset of the electrically conductive layers and divide each electrically conductive layer within the proximal subset of the electrically conductive layers into a respective plurality of source-side select gate electrodes.

20. The method of claim 18, further comprising forming source-select-level dielectric isolation structures by depositing a dielectric material in the plurality of source-side trenches.

21. A three-dimensional memory device, comprising: an alternating stack of insulating layers and electrically conductive layers over at least one source layer and between a pair of backside trench fill structures; a set of memory openings vertically extending through the alternating stack; and a set of memory opening fill structures in the set of memory openings, wherein each of the memory opening fill structures comprises: a respective vertical stack of memory elements; a respective vertical semiconductor channel having a first end contacting the at least one source layer; and a respective drain region contacting a second end of the respective vertical semiconductor channel; wherein the electrically conductive layers comprise: a word line continuously laterally extending between and contacting each of the pair of backside trench fill structures; and a plurality of source-side select gate electrodes between the at least one source layer and the word line in a vertical direction and between the pair of backside trench fill structures in a horizontal direction, wherein the plurality of source-side select gate electrodes are laterally spaced apart by source-select-level dielectric isolation structures; and the three-dimensional memory device further comprises a source-side trench extending through both the source-side select gate electrodes and the at least one source layer, wherein the source-side trench does not divide the word line. ​ 22. The three-dimensional memory device of Claim 21, wherein: the vertical semiconductor channels include a semiconductor material having a first conductivity type of doping; and the at least one source layer comprises a layer of semiconductor material having a second conductivity type of doping opposite the first conductivity type.

23. The three-dimensional memory device of Claim 21, wherein the at least one source layer comprises a continuous source layer contacting each of the first ends of each of the vertical semiconductor channels.

24. The three-dimensional memory device of Claim 23, wherein each of the source-select-level dielectric isolation structures comprises a first horizontal surface contacting one of the insulating layers and a second horizontal surface contacting the at least one source layer.

25. The three-dimensional memory device of Claim 21, wherein: the at least one source layer comprises a plurality of source layers laterally spaced apart from one another; and each group of memory opening fill structures of the group of memory opening fill structures contacts a respective one of the plurality of source layers and is electrically isolated from all other source layers of the plurality of source layers.

26. The three-dimensional memory device of Claim 25, wherein the plurality of source layers are laterally spaced apart from one another by respective source-layer-level dielectric isolation structures.

27. The three-dimensional memory device of Claim 26, wherein each of the source-layer-level dielectric isolation structures contacts a respective one of the source-select-level dielectric isolation structures.

28. The three-dimensional memory device of Claim 27, wherein each of the source-layer-level dielectric isolation structures has a sidewall vertically coincident with the respective one of the source-select-level dielectric isolation structures.

29. The three-dimensional memory device of Claim 27, wherein there is a horizontal step between each of the source-layer-level dielectric isolation structures and the respective one of the source-select-level dielectric isolation structures.

30. The three-dimensional memory device of Claim 25, further comprising a source-layer-level isolation dielectric layer contacting a backside of each of the plurality of source layers and comprising a vertically downward protruding portion comprising a source-layer-level dielectric isolation structure.

31. The three-dimensional memory device of Claim 21, wherein each of the pair of backside trench fill structures comprises a dielectric structure surrounded by an insulating spacer or a conductive partial interconnect.

32. The three-dimensional memory device of Claim 21, wherein each of the plurality of source-side-select gate electrodes laterally surrounds a respective group of memory opening fill structures and is laterally spaced apart from any other group of memory opening fill structures of the group of memory opening fill structures.

33. The three-dimensional memory device of Claim 25, wherein the plurality of source layers comprises a plurality of polycrystalline semiconductor layers.

34. A method of forming a three-dimensional memory device, the method comprising: forming an alternating stack of insulating layers and spacer material layers over a substrate, wherein the spacer material layers are formed as electrically conductive layers or are subsequently replaced with electrically conductive layers; forming a set of memory opening fill structures in the memory openings, wherein each of the set of memory opening fill structures includes a respective vertical stack of memory elements, a respective vertical semiconductor channel, and a respective drain region; forming a source-level material layer by thinning the substrate or by replacing the substrate with at least one electrically conductive material layer, wherein each set of memory opening fill structures contacts a respective one of a plurality of source levels; and forming a plurality of source-side select gate electrodes by forming source-side trenches through a first subset of the electrically conductive layers before or after forming the source-level material layer, wherein the source-side trenches do not divide a second subset of the electrically conductive layers; and wherein the method further includes, before forming the source-level material layer and before forming the source-side trenches, forming a pair of backside trench fill structures through the alternating stack; and the second subset of the electrically conductive layers serving as word lines extending laterally between an adjacent pair of backside trench fill structures in a word line direction.

35. The method of claim 34, wherein: the substrate comprises a semiconductor material; the source-level material layer is formed by thinning the substrate; and the source-side trenches are formed through the source-level material layer.

36. The method of claim 34, wherein the source-level material layer is formed by replacing the substrate with the at least one electrically conductive material layer.

37. The method of claim 36, wherein the source-side trenches are formed through the first subset of the electrically conductive layers after removing the substrate and before forming the at least one electrically conductive material layer.

38. The method of claim 36, wherein the source-side trenches are formed through the at least one electrically conductive material layer after forming the at least one electrically conductive material layer.

39. The method of claim 34, further comprising forming trenches through the source-level material layer to separate the source-level material layer into a plurality of source levels. ​

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