Data processing method, processing core, many-core system, and computer-readable medium

Abstract

The present disclosure provides a data processing method, comprising: determining a connection weight value between at least one target neuron and at least one first neuron according to first weight data in on-chip storage and second weight data in off-chip storage, the target neuron being one of at least one second neuron, and the first neuron being a predecessor neuron of the second neuron; the second weight data comprising an index part and a weight part, the weight part comprising non-zero connection weight values between a neuron and at least one predecessor neuron or at least one successor neuron of the neuron, and the index part representing predecessor neurons or successor neurons of the neuron corresponding to each non-zero connection weight value in the weight part; and calculating a membrane potential of each target neuron according to the connection weight value between the at least one target neuron and the at least one first neuron. The present disclosure also provides a processing core, a many-core system, and a computer readable medium.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to a data processing method, a processing core, a many-core system, and a computer-readable medium. Background Art

[0002] Spiking Neural Networks (SNNs) are considered third-generation neural networks, aiming to bridge the gap between neuroscience and machine learning. They use a model that best reflects the mechanisms of biological neurons to perform computations. In SNNs, weights are used to represent the strength of the connection between two neurons. The neuron's membrane potential is calculated based on these weights to determine whether to fire a spike.

[0003] In some related technologies, a large number of weights will occupy too many resources. Summary of the Invention

[0004] The present disclosure provides a data processing method, a processing core, a many-core system, and a computer-readable medium.

[0005] In a first aspect, the present disclosure provides a data processing method, comprising:

[0006] Determining a connection weight value between at least one target neuron and at least one first neuron based on first weight data stored on-chip and second weight data stored off-chip, wherein the target neuron is one of at least one second neuron and the first neuron is a predecessor neuron of the second neuron; the second weight data includes an index portion and a weight portion, wherein the weight portion includes non-zero connection weight values ​​between the neuron and at least one predecessor neuron or at least one successor neuron of the neuron, and the index portion represents the predecessor neuron or successor neuron of the neuron corresponding to each non-zero connection weight value in the weight portion;

[0007] The membrane potential of each target neuron is calculated according to the connection weight value between the at least one target neuron and the at least one first neuron.

[0008] In some embodiments, for any one of the target neurons, when the target neuron and / or at least one of the first neurons is a non-sparse neuron, the weight data of the target neuron is first weight data; and the step of determining the connection weight value between at least one target neuron and at least one first neuron based on the first weight data in on-chip storage and the second weight data in off-chip storage includes:

[0009] Retrieving first weight data of the target neuron from the on-chip storage in response to at least one of the first neurons firing;

[0010] The connection weight value between the target neuron and each of the first neurons is determined according to the first weight data of the target neuron.

[0011] In some embodiments, when the at least one first neuron includes at least one non-sparse first neuron, the weight data of the non-sparse first neuron is first weight data; and the step of determining the connection weight value between the at least one target neuron and the at least one first neuron based on the first weight data in on-chip storage and the second weight data in off-chip storage includes:

[0012] In response to any non-sparse first neuron firing, receiving first weight data of the fired non-sparse first neuron;

[0013] According to the first weight data of the emitted non-sparse first neurons, the connection weight value between each of the target neurons and the emitted non-sparse first neurons is determined.

[0014] In some embodiments, the at least one first neuron further includes at least one sparse first neuron, and the weight data of the sparse first neuron is the second weight data; and the step of determining the connection weight value between the at least one target neuron and the at least one first neuron based on the first weight data stored on-chip and the second weight data stored off-chip further includes:

[0015] In response to any one of the sparse first neurons firing, receiving second weight data of the fired sparse first neurons;

[0016] According to the second weight data of the emitted sparse first neurons, the connection weight value between each of the target neurons and the emitted sparse first neurons is determined.

[0017] In some embodiments, at least one of the second neurons is a sparse neuron and / or at least one of the first neurons is a sparse neuron, wherein the weight data of the sparse neuron is the second weight data; and the step of determining the connection weight value between at least one target neuron and at least one first neuron based on the first weight data stored on-chip and the second weight data stored off-chip comprises:

[0018] A connection weight value between at least one target neuron and at least one first neuron is determined based on the second weight data of the sparse second neuron or the second weight data of the sparse first neuron.

[0019] In some embodiments, at least one of the first neurons is a sparse neuron, the weight part of the second weight data of the sparse first neuron comprises non-zero connection weight values between the sparse first neuron and each of the second neurons, and the index part comprises an identification sequence composed of identification information of each of the second neurons in a first predetermined order, the identification information representing whether the connection weight value between the corresponding second neuron and the sparse first neuron is a non-zero weight value; the non-zero connection weight values in the weight part of the second weight data of the sparse first neuron correspond one-to-one to the identification information representing the non-zero connection weight values in the identification sequence; and the step of determining the connection weight values between at least one target neuron and at least one first neuron according to the second weight data of the sparse second neuron or the second weight data of the sparse first neuron comprises:

[0020] determining, according to the identification sequence in the second weight data of the sparse first neuron, the second neurons having non-zero connection weight values with the sparse first neuron as the target neurons;

[0021] determining, according to the correspondence between the non-zero connection weight values in the weight part of the second weight data of the sparse first neuron and the identification information representing the non-zero connection weight values in the identification sequence, the connection weight values between each of the target neurons and the sparse first neuron.

[0022] In some embodiments, the step of determining, according to the identification sequence in the second weight data of the sparse first neuron, the second neurons having non-zero connection weight values with the sparse first neuron as the target neurons comprises:

[0023] determining, according to the firing information of each of the sparse first neurons in each time interval, a target predecessor neuron corresponding to a target time interval, the firing information representing whether each of the sparse first neurons fires in each time interval, the target predecessor neuron being a first neuron firing in the target time interval;

[0024] determining, according to the identification sequence in the second weight data of at least one of the target predecessor neurons, the second neurons having non-zero connection weight values with at least one of the target predecessor neurons as the target neurons.

[0025] In some embodiments, at least one of the second neurons is a sparse neuron, the weight part of the second weight data of the sparse second neuron comprises non-zero connection weight values between the sparse second neuron and each of the first neurons, and the index part comprises an identification sequence composed of identification information of each of the first neurons in a second predetermined order, the identification information indicating whether the connection weight value between the corresponding first neuron and the sparse second neuron is a non-zero weight value; the non-zero connection weight values in the weight part of the second weight data of the sparse second neuron correspond one-to-one to the identification information in the identification sequence indicating the non-zero connection weight values; and the step of determining the connection weight values between the at least one target neuron and the at least one first neuron according to the second weight data of the sparse second neuron or the second weight data of the sparse first neuron comprises:

[0026] determining, according to the identification sequence in the second weight data of the sparse second neuron, the second neurons whose connection weight values with the fired first neurons are non-zero connection weight values as the target neurons;

[0027] determining, according to the correspondence between the non-zero connection weight values in the weight part of the second weight data of the target neurons and the identification information in the identification sequence indicating the non-zero connection weight values, the connection weight values between each of the target neurons and the sparse first neurons.

[0028] In some embodiments, the step of determining, according to the identification sequence in the second weight data of the sparse first neuron, the second neurons whose connection weight values with the sparse first neurons are non-zero connection weight values as the target neurons comprises:

[0029] determining, according to the firing information of each of the sparse first neurons in each time interval indicating whether each of the sparse first neurons fires in each time interval, a target predecessor neuron corresponding to a target time interval, the target predecessor neuron being a first neuron firing in the target time interval;

[0030] determining, according to the identification sequence in the second weight data of the at least one target predecessor neuron, the second neurons whose connection weight values with the at least one target predecessor neuron are non-zero connection weight values as the target neurons.

[0031] In some embodiments, for any one of the target neurons, the step of calculating the membrane potential of each of the target neurons according to the connection weight values between the at least one target neuron and the at least one first neuron comprises:

[0032] The membrane potential of the target neuron is calculated according to a historical membrane potential of the target neuron and a connection weight value between the target neuron and the at least one first neuron.

[0033] In a second aspect, the embodiments of the present disclosure provide a processing core, comprising a calculation unit and a cache;

[0034] The calculation unit is capable of implementing any one of the data processing methods in the first aspect of the embodiments of the present disclosure.

[0035] In a third aspect, the embodiments of the present disclosure provide a many-core system, comprising:

[0036] a plurality of processing cores; and

[0037] a network-on-chip configured to interact data between the plurality of processing cores and external data;

[0038] One or more instructions are stored in one or more of the processing cores, and the one or more instructions are executed by one or more of the processing cores to enable one or more of the processing cores to implement any one of the data processing methods in the first aspect of the embodiments of the present disclosure.

[0039] In a fourth aspect, the embodiments of the present disclosure provide a computer readable medium having a computer program stored thereon, wherein the computer program, when executed by a processing core, implements any one of the data processing methods in the first aspect of the embodiments of the present disclosure.

[0040] In the data processing method provided by the embodiments of the present disclosure, in the scenario that the weight data of part of the neurons in the neural network is stored in off-chip storage and the weight data of part of the neurons is stored in on-chip storage, the weight data of the neurons in the neural network can also be processed, and the format of the weight data stored off-chip satisfies: including an index part and a weight part, the weight part includes non-zero connection weight values between a neuron and at least one predecessor neuron or at least one successor neuron of the neuron, and the index part represents the predecessor neuron or the successor neuron of the neuron corresponding to each non-zero connection weight value in the weight part. Therefore, the storage of the connection weight values is optimized, the utilization efficiency of the on-chip storage is improved, and the operation rate of the processor is improved.

[0041] It should be understood that the content described in this part is not intended to identify key or important features of the embodiments of the present disclosure, nor is it used to limit the scope of the present disclosure. Other features of the present disclosure will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0042] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of the specification, illustrate embodiments of the present disclosure and are used to explain the present disclosure and are not intended to limit the present disclosure. The above and other features and advantages will become more apparent from the detailed description of the detailed examples, taken in conjunction with the accompanying drawings, in which:

[0043] Figure 1 is a flowchart of a data processing method in an embodiment of the present disclosure;

[0044] Figure 2 is a schematic diagram of the connection relationship of part of neurons in an embodiment of the present disclosure;

[0045] Figure 3 is a schematic diagram of a neuromorphic chip in an embodiment of the present disclosure;

[0046] Figure 4 is a schematic diagram of the correspondence relationship between a neuron and a processing core in an embodiment of the present disclosure;

[0047] Figure 5 is a schematic diagram of a processing core of a neuromorphic chip in an embodiment of the present disclosure;

[0048] Figure 6 is a schematic diagram of the format of weight data in an embodiment of the present disclosure;

[0049] Figure 7 is a flowchart of part of steps in another data processing method in an embodiment of the present disclosure;

[0050] Figure 8 is a flowchart of part of steps in another data processing method in an embodiment of the present disclosure;

[0051] Figure 9 is a flowchart of part of steps in another data processing method in an embodiment of the present disclosure;

[0052] Figure 10 is a flowchart of part of steps in another data processing method in an embodiment of the present disclosure;

[0053] Figure 11 is a flowchart of part of steps in another data processing method in an embodiment of the present disclosure;

[0054] Figure 12 is a schematic diagram of another format of weight data in an embodiment of the present disclosure;

[0055] Figure 13 is a flowchart of part of steps in another data processing method in an embodiment of the present disclosure;

[0056] Figure 14A schematic diagram of performing neural network operation according to a time axis in an embodiment of the present disclosure;

[0057] Figure 15 A schematic diagram of performing neural network operation according to a time axis in an embodiment of the present disclosure;

[0058] Figure 16 is a flowchart of part of steps in another data processing method in an embodiment of the present disclosure;

[0059] Figure 17 is a flowchart of part of steps in another data processing method in an embodiment of the present disclosure;

[0060] Figure 18 is a constituent block diagram of a processing core in an embodiment of the present disclosure;

[0061] Figure 19 is a constituent block diagram of a many-core system in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0062] In order to enable one skilled in the art to better understand the technical solutions of the present disclosure, the exemplary embodiments of the present disclosure are described below with reference to the accompanying drawings, which include various details of the embodiments of the present disclosure to help understanding, and should be considered as merely exemplary. Therefore, those of ordinary skill in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Also, in order to be clear and concise, the description below omits the description of well-known functions and structures.

[0063] In the case of no conflict, each embodiment of the present disclosure and each feature in the embodiments can be combined with each other.

[0064] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0065] The terms used herein are only used to describe specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. The words "connected" or "coupled" and similar alike terms are not limited to physical or mechanical connections or couplings, but can include electrical connections, whether direct or indirect.

[0066] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure and will not be interpreted in an overly literal or overly formal sense unless expressly so defined herein.

[0067] The inventors of the present disclosure have found that in some related technologies, when a spiking neural network is run with a processor having on-chip storage, the connection weight values of all neurons are usually stored in the on-chip storage. The connection weight values are usually int 8 or half-precision floating-point (fp, floating-point) 16, which usually has high precision and occupies too much on-chip storage resources. Especially when the neurons of the spiking neural network are sparse neurons, the utilization rate of the on-chip storage will decrease sharply. Sparse neurons refer to neurons with low firing frequency. In some embodiments, sparse neurons refer to neurons with a working state parameter less than a parameter threshold, and non-sparse neurons refer to neurons with a working state parameter greater than or equal to the parameter threshold.

[0068] In view of this, in a first aspect, with reference to Figure 1 The embodiments of the present disclosure provide a data processing method, comprising:

[0069] In step S100, the connection weight values between at least one target neuron and at least one first neuron are determined according to first weight data in on-chip storage and second weight data in off-chip storage, the target neuron is one of at least one second neuron, and the first neuron is a predecessor neuron of the second neuron; the second weight data includes an index part and a weight part, the weight part includes non-zero connection weight values between a neuron and at least one predecessor neuron or at least one successor neuron of the neuron, and the index part represents the predecessor neuron or successor neuron of the neuron corresponding to each non-zero connection weight value in the weight part;

[0070] In step S200, the membrane potential of each target neuron is calculated according to the connection weight values between the at least one target neuron and the at least one first neuron.

[0071] Figure 2 A schematic diagram of the connection relationship of some neurons in the embodiments of the present disclosure. As shown in FIG. 1, the neurons are divided into two groups, the first group of neurons and the second group of neurons. The first group of neurons includes neurons 1, 2, 3, 4, 5, and 6, and the second group of neurons includes neurons 7, 8, 9, 10, 11, and 12. The neurons in the first group of neurons are predecessor neurons of the neurons in the second group of neurons, and the neurons in the second group of neurons are successor neurons of the neurons in the first group of neurons. The connection relationship between the neurons in the first group of neurons and the neurons in the second group of neurons is shown in FIG. 1. Figure 2As shown, neurons A1, A2, and A3 are the first neurons, and neurons C1, C2, C3, and C4 are the second neurons. Neurons A1, A2, and A3 are fully connected to neurons C1, C2, C3, and C4. For neuron C1, neurons A1, A2, and A3 are its predecessors; for neuron A1, neurons C1, C2, C3, and C4 are its successors. The predecessor and successor relationships of other neurons can be derived similarly.

[0072] In some embodiments, a neural network is run on a neuromorphic chip. In some embodiments, the neuromorphic chip is a many-core system. Figure 3 As shown, the neuromorphic chip includes a plurality of processing cores 10. Each processing core has independent computing power and on-chip storage. In the embodiment of the present disclosure, each processing core corresponds to at least one neuron. In addition, the many-core system also includes off-chip storage, and the weight data of the neuron can be stored in the on-chip storage of the corresponding processing core, or in the off-chip storage of the many-core system. Weight data can be transferred between the on-chip storage and off-chip storage of the processing core. For example, the processing core can read the weight data in its on-chip storage and write it to the off-chip storage, or read the weight data in the off-chip storage and write it to its off-chip storage; the processing core can also read the weight data from its on-chip storage or off-chip storage and transfer it to other processing cores.

[0073] like Figure 4 As shown, neurons A1, A2, A3, and A4 correspond to processing core 1, neurons C1, C2, C3, and C4 correspond to processing core 2, and neurons B1, B2, and B3 correspond to processing core 3.

[0074] To further illustrate the correspondence between neurons and neuropsychology chips in the embodiments of the present disclosure, Figure 5 for Figure 3 A schematic diagram of the structure of a processing core. Figure 5 As shown, each processing core typically includes a group (or multiple) of neurons, a group of axons, a group of dendrites, and a synaptic array, which can simulate the behavior of a biological neuron cluster. Each processing core in a neuromorphic chip can complete the dendrite integral calculation process and cell body operation process for the corresponding group of neurons. Among them, dendrites are structures used to receive external stimuli and generate input current, axons are structures used to transmit impulses to the synapses of subsequent neurons, and synapses are structures used to connect neurons. The synaptic array is an array of synapses that connects a group of axons and a group of dendrites.

[0075] For each neuron in a processing core, a dendrite integration calculation process is used to describe the process of integrating the pulse data of all input axons connected to the dendrites of the neuron, which is also referred to as a membrane potential integration operation in the embodiments of the present disclosure. A soma operation process is responsible for the update of the membrane potential of the neuron and the judgment of pulse emission, which is also referred to as a firing operation in the embodiments of the present disclosure. If the membrane potential of any neuron meets the firing condition, the axon of the neuron will emit a pulse represented by 1 to the subsequent neuron connected to the neuron; otherwise, the axon of the neuron will emit a pulse represented by 0 to the subsequent neuron connected to the neuron. This enables the neuromorphic chip, as a super large scale integrated system of electronic analog circuits, to more accurately simulate the neurobiological structure in the nervous system.

[0076] In the related art, a synaptic array is usually used to simulate the connection relationship between a group of neurons of one processing core and a group of neurons of another processing core, as an array storage structure for storing the connection topology and connection weights (also referred to as synaptic weights) between a group of neurons of one processing core and a group of neurons of another processing core.

[0077] In the embodiments of the present disclosure, the weight data of neurons in a neural network is divided into first weight data and second weight data, where the first weight data is stored in off-chip storage, and the second weight data is stored in on-chip storage. The embodiments of the present disclosure do not make special limitations on how to divide the first weight data and the second weight data. In some embodiments, the weight data of non-sparse neurons is the first weight data, and the weight data of sparse neurons is the second weight data. Storing the weight data of non-sparse neurons in on-chip storage and storing the weight data of sparse neurons in off-chip storage can save on-chip storage resources, improve the utilization efficiency of on-chip storage, and at the same time, can avoid the excessive cost of frequently reading the weight data of non-sparse neurons from off-chip storage.

[0078] In the embodiments of the present disclosure, the format of the first weight data can be the same as or different from the format of the second weight data. The embodiments of the present disclosure do not make special limitations on this.

[0079] The format of the second weight data in the embodiments of the present disclosure is as shown in Figure 6 The second weight data of each neuron includes an index part and a weight part.

[0080] In the embodiments of the present disclosure, the second weight data can be used to store the connection weight values of the neuron and all or part of the successor neurons of the neuron; at this time, one second weight data corresponds to one first neuron, and the weight part of the second weight data includes the non-zero connection weight values in the connection weight values between the corresponding first neuron and each second neuron. The second weight data can also be used to store the connection weight values of the neuron and all or part of the predecessor neurons of the neuron; at this time, one second weight data corresponds to one second neuron, and the weight part of the second weight data includes the non-zero connection weight values in the connection weight values between the corresponding second neuron and each first neuron.

[0081] In some embodiments, the target neuron is a second neuron that needs to make a firing judgment. In the embodiments of the present disclosure, the neuron fires when the membrane potential of the neuron is greater than the firing threshold; the neuron needs to make a firing judgment means that the membrane potential of the neuron needs to be calculated, and whether the neuron fires is determined by judging whether the membrane potential is greater than the firing threshold. In some embodiments, the neuron makes a firing judgment in response to the firing of the predecessor neuron. In some embodiments, the target neuron is a second neuron whose connection weight value with the fired first neuron is a non-zero connection weight value.

[0082] In the embodiments of the present disclosure, the firing judgment can be made on all second neurons or on part of the second neurons through steps S100 to S200. The present disclosure does not specially limit this.

[0083] In the data processing method provided by the disclosed embodiments, the weight data of part of the neurons of the neural network is stored in off-chip storage, the weight data of part of the neurons is stored in on-chip storage, and the weight data stored in the off-chip storage and the weight data stored in the on-chip storage can be processed, wherein the format of the weight data stored in the off-chip storage satisfies: including an index part and a weight part, the weight part includes non-zero connection weight values between a neuron and at least one predecessor neuron or at least one successor neuron of the neuron, and the index part represents the predecessor neuron or the successor neuron of the neuron corresponding to each non-zero connection weight value in the weight part. Thus, the storage of the connection weight values can be optimized, the utilization efficiency of the on-chip storage can be improved, and the operation rate of the processor can be improved.

[0084] In the embodiments of the present disclosure, the weight data stored in the on-chip storage can include weight data of non-sparse neurons; and can also include weight data of non-sparse neurons and weight data of successor neurons of the non-sparse neurons. The embodiments of the present disclosure do not make special limitation on this. Since the non-sparse neurons are non-sparse firing, the successor neurons of the non-sparse neurons need to frequently obtain their weight data for firing judgment. Storing the weight data of the non-sparse neurons and the weight data of the successor neurons of the non-sparse neurons in the on-chip storage can reduce the cost of the successor neurons of the non-sparse neurons reading the weight data, thereby improving the operation rate of the processor.

[0085] Correspondingly, in some embodiments, with reference to Figure 7 For any one of the target neurons, when the target neuron and / or at least one of the first neurons is a non-sparse neuron, the weight data of the target neuron is first weight data; and step S100 includes:

[0086] In step S101, in response to firing of at least one of the first neurons, the first weight data of the target neuron is obtained from the on-chip storage;

[0087] In step S102, the connection weight values between the target neuron and each of the first neurons are determined according to the first weight data of the target neuron.

[0088] It should be noted that in steps S101 to S102, the first weight data of the target neuron includes the connection weight value between the target neuron and the first neuron. The weight data of the first neuron can include the connection weight value between the first neuron and its predecessor neuron, or can include the connection weight value between the first neuron and the second neuron. The embodiments of the present disclosure do not make special limitations on this. For example, the first neuron is a non-sparse neuron, the target neuron is a non-sparse neuron, the first weight data of the first neuron includes the connection weight value between the first neuron and its predecessor neuron, and the first weight data of the target neuron includes the connection weight value between the target neuron and the first neuron. For example, the first neuron is a sparse neuron, the target neuron is a non-sparse neuron, the second weight data of the first neuron includes the connection weight value between the first neuron and its predecessor neuron, and the first weight data of the target neuron includes the connection weight value between the target neuron and the first neuron. For example, the first neuron is a sparse neuron, the target neuron is a non-sparse neuron, the second weight data of the first neuron includes the connection weight value between the first neuron and the second neuron, and the first weight data of the target neuron includes the connection weight value between the target neuron and the first neuron. For example, the first neuron is a non-sparse neuron, the target neuron is a sparse neuron, the first weight data of the first neuron includes the connection weight value between the first neuron and its predecessor neuron, and the first weight data of the target neuron includes the connection weight value between the target neuron and the first neuron.

[0089] In some embodiments, the weight data stored in the on-chip storage can include the weight data of the non-sparse neuron, and the weight data of the non-sparse neuron includes the connection weight value between the non-sparse neuron and its successor neuron. When the non-sparse neuron fires when the membrane potential is greater than the firing threshold, the first weight data stored in the on-chip storage of the non-sparse neuron is transmitted to the successor neuron, so that when the successor neuron of the non-sparse neuron is a sparse neuron and the weight data of the successor neuron is stored in the off-chip storage, the firing judgment can also be performed according to the received weight data without frequently obtaining the weight data from the off-chip storage.

[0090] Correspondingly, in some embodiments, with reference to Figure 8 When the at least one first neuron includes at least one non-sparse first neuron, the weight data of the non-sparse first neuron is the first weight data; step S100 includes:

[0091] In step S111, in response to firing of any one non-sparse first neuron, the first weight data of the fired non-sparse first neuron is received;

[0092] In step S112, the connection weight value between each target neuron and the issued non-sparse first neuron is determined according to the first weight data of the issued non-sparse first neuron.

[0093] It should be noted that in steps S111 to S112, each second neuron can be used as a target neuron, or a second neuron whose connection weight value with at least one sparse or non-sparse first neuron is a non-zero connection weight value can be used as a target neuron. This embodiment of the present disclosure does not specifically limit this. It should be noted that in steps S111 to S112, the first weight data of the non-sparse first neuron includes the connection weight value between the non-sparse first neuron and the second neuron. The weight data of the target neuron can include the connection weight value between the target neuron and the first neuron, or can include the connection weight value between the target neuron and its successor neuron. This embodiment of the present disclosure does not specifically limit this. For example, if the target neuron is a non-sparse neuron, the first weight data of the target neuron includes the connection weight value between the target neuron and its successor neuron. For example, if the target neuron is a sparse neuron, the second weight data of the target neuron includes the connection weight value between the target neuron and its successor neuron. For example, if the target neuron is a sparse neuron, the second weight data of the target neuron includes the connection weight value between the target neuron and the first neuron.

[0094] It should be noted that, in the embodiment of the present disclosure, the first weight data stored in the on-chip storage may also include the connection weight value between the neuron and its predecessor neuron and the connection weight value between the neuron and its successor neuron. When the first weight data includes the connection weight value between the neuron and its predecessor neuron and the connection weight value between the neuron and its successor neuron, the connection weight value between the target neuron and the first neuron can be determined according to steps S101 to S102, or the connection weight value between the target neuron and the first neuron can be determined according to steps S111 to S112. The embodiment of the present disclosure does not specifically limit this.

[0095] In some embodiments, reference Figure 9 , the at least one first neuron further includes at least one sparse first neuron, and the weight data of the sparse first neuron is the second weight data; step S100, in addition to the above steps S111 to S112, further includes:

[0096] In step S113, in response to any one of the sparse first neurons firing, receiving second weight data of the fired sparse first neurons;

[0097] In step S114, the connection weight value between each target neuron and the emitted sparse first neuron is determined according to the second weight data of the emitted sparse first neuron.

[0098] It should be noted that in steps S113 to S114, the target neuron is a non-sparse neuron, and the first weight data of the target neuron includes the connection weight value between the target neuron and its successor neuron. Furthermore, in steps S113 to S114, each second neuron can be used as a target neuron, or a second neuron whose connection weight value with at least one emitted sparse or non-sparse first neuron is a non-zero connection weight value can be used as a target neuron. This embodiment of the present disclosure does not specifically limit this.

[0099] In some embodiments, reference Figure 10 , at least one of the second neurons is a sparse neuron and / or at least one of the first neurons is a sparse neuron, wherein the weight data of the sparse neuron is the second weight data; step S100 includes:

[0100] In step S120 , a connection weight value between at least one target neuron and at least one first neuron is determined based on the second weight data of the sparse second neuron or the second weight data of the sparse first neuron.

[0101] The embodiment of the present disclosure does not specifically limit the specific formats of the second weight data index part and the weight part.

[0102] In some embodiments, at least one of the first neurons is a sparse neuron, and the weight portion of the second weight data of the sparse first neuron includes a non-zero connection weight value between the sparse first neuron and each of the second neurons; the index portion includes an identification sequence composed of identification information of each of the second neurons in a first predetermined order, and the identification information indicates whether the connection weight value between the corresponding second neuron and the sparse first neuron is a non-zero weight value; the non-zero connection weight value in the weight portion of the second weight data of the sparse first neuron corresponds one-to-one to the identification information indicating the non-zero connection weight value in the identification sequence of the second weight data; with reference to Figure 11 , step S120 includes:

[0103] In step S121, according to the identification sequence in the second weight data of the sparse first neuron, a second neuron having a connection weight value with the sparse first neuron that is a non-zero connection weight value is determined as the target neuron;

[0104] In step S122, according to the correspondence between the non-zero connection weight values in the weight part of the second weight data of the sparse first neuron and the identification information representing the non-zero connection weight values in the identification sequence, the connection weight values between each of the target neurons and the sparse first neuron are determined.

[0105] In some embodiments, the identification information includes 1 and 0, wherein 1 represents that the connection weight value between the first neuron and the second neuron is a non-zero connection weight value; and 0 represents that the connection weight value between the first neuron and the second neuron is zero. Accordingly, the identification sequence is a sequence composed of 1 and 0, each identification bit in the sequence corresponds to a second neuron. In step S121, the target neuron can be determined according to whether the identification bit in the identification sequence is 0 or 1. In some embodiments, the non-zero connection weight values in the weight part of the second weight data are arranged in a first predetermined order, and the non-zero connection weight values one-to-one correspond to the identification bits with value 1 in the identification sequence. In step S122, the connection weight values between the target neuron and the first neuron can be determined according to the one-to-one correspondence.

[0106] For example, referring to Figure 2 and Figure 12 , the identification sequence of the index part in the second weight data of neuron A1 is 1001, representing that the connection weight values between neurons C1 and C4 and neuron A1 are non-zero connection weight values, and the connection weight values between neurons C2 and C3 and neuron A1 are zero; the weight part includes the connection weight value a and the connection weight value b arranged in order, representing that the connection weight value between neuron C1 and neuron A1 is a, and the weight value between neuron C4 and neuron A1 is b. The identification sequence of the index part in the weight data of neuron A2 is 1000, representing that the connection weight value between neuron C1 and neuron A2 is a non-zero connection weight value, and the connection weight values between neurons C2, C3 and C4 and neuron A2 are zero; the weight part includes the connection weight value c, representing that the connection weight value between neuron C1 and neuron A1 is c. When only neuron A1 fires, in step S121, neurons C1 and C4 are determined as the target neurons, and in step S122, it can be determined that the connection weight value between neuron C1 and neuron A1 is a, and the weight value between neuron C4 and neuron A1 is b. When neuron A1 and neuron A2 fire, in step S121, neurons C1 and C4 are determined as the target neurons, and in step S122, it can be determined that the connection weight value between neuron C1 and neuron A1 is a, the connection weight value between neuron C1 and neuron A2 is c, and the weight value between neuron C4 and neuron A1 is b.

[0107] In the embodiments of the present disclosure, in the same time interval, multiple first neurons may all fire, partially fire, or not fire at all. This embodiment of the present disclosure does not specifically limit this. In some embodiments, for any second neuron, the firing judgment of the second neuron is made only based on the second weight data of the first neuron that fired in the same time interval. In the embodiments of the present disclosure, a time interval can be a period of time, a moment, or an operating cycle. This embodiment of the present disclosure does not specifically limit this.

[0108] Accordingly, in some embodiments, reference Figure 13 , step S121 includes:

[0109] In step S1211, a target predecessor neuron corresponding to a target time interval is determined based on the firing information of each sparse first neuron in each time interval, wherein the firing information indicates whether each sparse first neuron in each time interval fires, and the target predecessor neuron is the first neuron that fires in the target time interval;

[0110] In step S1212, based on the identification sequence in the second weight data of at least one of the target predecessor neurons, a second neuron having a non-zero connection weight value with at least one of the target predecessor neurons is determined as the target neuron.

[0111] Figure 14 and Figure 15 Schematic diagram of executing neural network operation according to the time axis in the embodiment of the present disclosure. At time t1 to t6, the pulses emitted by neurons A1, A2, and A3 and the second weight data of neurons A1, A2, and A3 are as follows: Figure 14 As shown. From t1 to t6, the corresponding connection weight values ​​when neurons C1, C2, C3, and C4 calculate the membrane potential are as follows: Figure 15 As shown. Taking neuron C1 as an example, at time t1, neurons A1 and A2 fire, while A3 does not. The connection weight between neurons A1 and C1 is a non-zero connection weight a, and the connection weight between neurons A2 and C1 is a non-zero connection weight c. At time t1, the membrane potential of neuron C1 is equal to the historical membrane potential at time t1 plus the connection weights a and c. At time t2, neurons A1, A2, and A3 do not fire, and no firing judgment is required. At time t3, neurons A1 and A3 fire, while A2 does not fire. The connection weight between neurons A1 and C1 is a non-zero connection weight a, and the connection weight between neurons A3 and C1 is zero. At time t3, the membrane potential of neuron C1 is equal to the historical membrane potential at time t3 plus the connection weight a.

[0112] In some embodiments, at least one of the second neurons is a sparse neuron, the weight part of the second weight data of the sparse second neuron comprises non-zero connection weight values between the sparse second neuron and each of the first neurons, and the index part comprises an identification sequence composed of identification information of each of the first neurons in a second predetermined order, the identification information indicating whether the connection weight value between the corresponding first neuron and the sparse second neuron is a non-zero weight value; the non-zero connection weight values in the weight part of the second weight data of the sparse second neuron correspond to the identification information indicating the non-zero connection weight values in the identification sequence one by one. Figure 16 Step S120 comprises:

[0113] In step S123, the second neurons having non-zero connection weight values with the fired first neurons are determined as the target neurons according to the identification sequence in the second weight data of the sparse second neurons.

[0114] In step S124, the connection weight values between each of the target neurons and the sparse first neurons are determined according to the correspondence between the non-zero connection weight values in the weight part of the second weight data of the target neurons and the identification information indicating the non-zero connection weight values in the identification sequence.

[0115] In some embodiments, referring to Figure 17 Step S123 comprises:

[0116] In step S1231, the target predecessor neurons corresponding to the target time interval are determined according to the firing information of each of the sparse first neurons in each time interval, the firing information indicating whether each of the sparse first neurons fires in each time interval, and the target predecessor neurons being the first neurons firing in the target time interval.

[0117] In step S1232, the second neurons having non-zero connection weight values with at least one of the target predecessor neurons are determined as the target neurons according to the identification sequence in the second weight data of at least one of the target predecessor neurons.

[0118] In some embodiments, the format of the second weight data provided by the embodiments of the present disclosure is used to store the connection weight values between neurons in a neural network in a many-core system. In the many-core system, one processing core corresponds to at least one neuron of the neural network. In some embodiments, one second weight data corresponds to one first neuron, the weight part of the second weight data includes the non-zero connection weight values between the corresponding first neuron and each second neuron, and the second weight data of the first neuron is stored in an off-chip memory of the many-core system. When any first neuron fires, the second weight data of the neuron is obtained from the off-chip memory, and the second weight data of the neuron is fired together with the second neuron.

[0119] Correspondingly, in some embodiments, the second neuron is the neuron corresponding to the current processing core, wherein the many-core system includes a plurality of processing cores, and one processing core corresponds to at least one neuron of the neural network; the second weight data is the second weight data of the first neuron, and the weight part of the second weight data includes the non-zero connection weight values between the first neuron and each second neuron; before the step of determining the connection weight values between the at least one target neuron and the at least one first neuron according to the second weight data of the sparse second neuron or the second weight data of the sparse first neuron, the data processing method further includes: receiving the second weight data fired by the at least one first neuron.

[0120] Correspondingly, in some embodiments, after the step of calculating the membrane potential of each target neuron according to the connection weight values between the at least one target neuron and the at least one first neuron, the data processing method further includes: firing the second weight data of the target neuron when the membrane potential of any target neuron is greater than the firing threshold.

[0121] In some embodiments, one second weight data corresponds to one second neuron, the weight part of the second weight data includes the non-zero connection weight values between the corresponding second neuron and each first neuron, and the second weight data of the second neuron is stored in an off-chip memory of the many-core system. When any first neuron fires, the current processing core obtains the second weight data of the corresponding second neuron from the off-chip memory.

[0122] Accordingly, the second neuron is a neuron corresponding to a current processing core, wherein the many-core system includes a plurality of processing cores, and one of the processing cores corresponds to at least one neuron of the neural network; the second weight data is second weight data of the second neuron, and a weight part of the second weight data includes non-zero connection weight values between the second neuron and each first neuron; before the step of determining the connection weight values between the at least one target neuron and the at least one first neuron according to the second weight data of the sparse second neuron or the second weight data of the sparse first neuron, the data processing method further includes: in response to the firing of the at least one first neuron, obtaining the second weight data of the at least one target neuron from off-chip storage of the many-core system.

[0123] In some embodiments, the second weight data of the target neuron obtained by the current processing core from the off-chip storage includes connection weight values between the target neuron and all predecessor neurons of the target neuron.

[0124] In some embodiments, the on-chip storage of the current processing core stores index information of the second weight data of each second neuron in the off-chip storage; and the step of obtaining the second weight data of the at least one target neuron from the off-chip storage of the many-core system includes: obtaining the second weight data of the at least one target neuron from the off-chip storage of the many-core system according to the index information.

[0125] In embodiments of the present disclosure, the many-core system can be composed of a single chip, and the chip has a plurality of processing cores. A processing core is the smallest computing unit in the many-core system that can be independently scheduled and has complete computing capability. The many-core system can also be composed of a plurality of chips, and each chip can have a plurality of processing cores. Embodiments of the present disclosure do not specially limit this. In embodiments of the present disclosure, the many-core system further includes off-chip storage. Embodiments of the present disclosure do not specially limit the off-chip storage of the many-core system. For example, the off-chip storage can be any one of a double data rate (DDR), a non-volatile memory (NVM), a flash, and the like.

[0126] In embodiments of the present disclosure, the plurality of processing cores in the many-core system can respectively independently run program instructions, or jointly work to accelerate the running speed of the program by using the parallel computing capability and provide multi-task processing capability. Each processing core in the many-core system has an independent on-chip storage, which can store data such as computing results obtained by the processing core performing operations.

[0127] In some embodiments, for any one of the target neurons, the step of calculating the membrane potential of each of the target neurons based on the connection weight value between the at least one target neuron and the at least one first neuron includes: calculating the membrane potential of the target neuron based on the historical membrane potential of the target neuron and the connection weight value between the target neuron and the at least one first neuron.

[0128] It should be noted that the data processing method provided in the embodiment of the present disclosure may be used in the process of executing one or more of image processing tasks, speech processing tasks, text processing tasks, etc. The embodiment of the present disclosure does not specifically limit this.

[0129] Secondly, refer to Figure 18 , an embodiment of the present disclosure provides a processing core, including a computing unit 101 and a cache 102;

[0130] The computing unit 101 can implement any one of the data processing methods described in the first aspect of the embodiments of this disclosure.

[0131] Thirdly, refer to Figure 19 The embodiment of the present disclosure provides a many-core system, including: multiple processing cores 201 and an on-chip network 202, wherein the multiple processing cores 201 are connected to the on-chip network 202, and the on-chip network 202 is used to exchange data between the multiple processing cores and external data.

[0132] Among them, one or more instructions are stored in one or more processing cores 201, and one or more instructions are executed by one or more processing cores 201, so that one or more processing cores 201 can implement any data processing method described in the first aspect of the embodiment of this disclosure.

[0133] In addition, an embodiment of the present disclosure further provides a computer-readable medium on which a computer program is stored, wherein the computer program, when executed by a processing core, can implement any one of the data processing methods described in the first aspect of the embodiment of the present disclosure.

[0134] Those of ordinary skill in the art will realize and understand that all or some of the steps in the methods disclosed above and the functional modules / units in the systems and devices can be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementation, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component can have multiple functions, or one function or step can be performed by several physical components in cooperation. Some or all of the physical components can be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable medium, which can include computer storage media (or non-transitory media) and communication media (or transitory media).

[0135] As is well known to those of ordinary skill in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Further, it is well known to those of ordinary skill in the art that communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media. In this document, the terms "computer storage medium" or "computer storage media" are used to generally refer to media such as removable storage drives, memory, volatile and non-volatile memory modules, and circuits such as solid-state memory circuits. Computer storage media are non-transitory and include volatile and non-volatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer.

[0136] Example embodiments have been disclosed herein and, although the use of specific terms is exemplified during the course of this specification, these are employed only for descriptive purposes and should not be construed as limiting in nature. In some instances, it will be apparent to those skilled in the art that variations of the features, attributes and / or elements described can be practiced without departing from the spirit and scope of the present disclosure as set forth in the following claims. Accordingly, the reader is to understand that the disclosure is not limited to the specific embodiments disclosed and that modifications and / or changes are intended to be implied.

Claims

1. A data processing method, comprising: Determining a connection weight value between at least one target neuron and at least one first neuron based on first weight data stored on-chip and second weight data stored off-chip, wherein the target neuron is one of at least one second neuron, and the first neuron is a predecessor neuron of the second neuron; the second weight data includes an index portion and a weight portion, wherein the weight portion includes non-zero connection weight values ​​between the neuron and at least one predecessor neuron or at least one successor neuron of the neuron, and the index portion represents the predecessor neuron or successor neuron of the neuron corresponding to each non-zero connection weight value in the weight portion; the first weight data includes weight data of neurons whose working state parameters are greater than or equal to a parameter threshold, and the second weight data includes weight data of neurons whose working state parameters are less than the parameter threshold; The membrane potential of each target neuron is calculated according to the connection weight value between the at least one target neuron and the at least one first neuron.

2. The data processing method according to claim 1, wherein: For any one of the target neurons, when the target neuron and / or at least one of the first neurons is a non-sparse neuron, the weight data of the target neuron is the first weight data; The step of determining a connection weight value between at least one target neuron and at least one first neuron according to the first weight data in the on-chip storage and the second weight data in the off-chip storage includes: Retrieving first weight data of the target neuron from the on-chip storage in response to at least one of the first neurons firing; The connection weight value between the target neuron and each of the first neurons is determined according to the first weight data of the target neuron.

3. The data processing method according to claim 1, wherein: When the at least one first neuron includes at least one non-sparse first neuron, the weight data of the non-sparse first neuron is the first weight data; The step of determining a connection weight value between at least one target neuron and at least one first neuron according to the first weight data in the on-chip storage and the second weight data in the off-chip storage includes: In response to any non-sparse first neuron firing, receiving first weight data of the fired non-sparse first neuron; According to the first weight data of the emitted non-sparse first neurons, the connection weight value between each of the target neurons and the emitted non-sparse first neurons is determined.

4. The data processing method according to claim 3, wherein: The at least one first neuron further includes at least one sparse first neuron, and the weight data of the sparse first neuron is the second weight data; The step of determining a connection weight value between at least one target neuron and at least one first neuron based on the first weight data stored on the chip and the second weight data stored off-chip further includes: In response to any one of the sparse first neurons firing, receiving second weight data of the fired sparse first neurons; According to the second weight data of the emitted sparse first neurons, the connection weight value between each of the target neurons and the emitted sparse first neurons is determined.

5. The data processing method according to claim 1, wherein: At least one of the second neurons is a sparse neuron and / or at least one of the first neurons is a sparse neuron, wherein the weight data of the sparse neuron is the second weight data; and the step of determining the connection weight value between at least one target neuron and at least one first neuron based on the first weight data stored on-chip and the second weight data stored off-chip comprises: A connection weight value between at least one target neuron and at least one first neuron is determined based on the second weight data of the sparse second neuron or the second weight data of the sparse first neuron.

6. The data processing method according to claim 5, wherein: At least one of the first neurons is a sparse neuron, and the weight portion of the second weight data of the sparse first neuron includes a non-zero connection weight value between the sparse first neuron and each of the second neurons; the index portion includes an identification sequence composed of identification information of each of the second neurons in a first predetermined order, and the identification information indicates whether the connection weight value between the corresponding second neuron and the sparse first neuron is a non-zero weight value; The non-zero connection weight values ​​in the weight part of the second weight data of the sparse first neuron correspond one-to-one to the identification information representing the non-zero connection weight values ​​in the identification sequence; The step of determining a connection weight value between at least one target neuron and at least one first neuron according to the sparse second weight data of the second neuron or the sparse second weight data of the first neuron includes: Determining, according to an identification sequence in the second weight data of the sparse first neuron, a second neuron having a non-zero connection weight value with the sparse first neuron as the target neuron; The connection weight value between each target neuron and the sparse first neuron is determined based on the correspondence between the non-zero connection weight value in the weight part of the second weight data of the sparse first neuron and the identification information representing the non-zero connection weight value in the identification sequence.

7. The data processing method according to claim 6, wherein: The step of determining, based on the identification sequence in the second weight data of the sparse first neuron, a second neuron having a connection weight value with the sparse first neuron and a non-zero connection weight value as the target neuron includes: Determine a target predecessor neuron corresponding to a target time interval based on the firing information of each sparse first neuron in each time interval, wherein the firing information indicates whether each sparse first neuron in each time interval fires, and the target predecessor neuron is the first neuron that fires in the target time interval; According to an identification sequence in the second weight data of at least one of the target predecessor neurons, a second neuron having a non-zero connection weight value with at least one of the target predecessor neurons is determined as the target neuron.

8. The data processing method according to claim 5, wherein: At least one of the second neurons is a sparse neuron, and the weight portion of the second weight data of the sparse second neuron includes a non-zero connection weight value between the sparse second neuron and each of the first neurons; the index portion includes an identification sequence composed of identification information of each of the first neurons in a second predetermined order, and the identification information indicates whether the connection weight value between the corresponding first neuron and the sparse second neuron is a non-zero weight value; The non-zero connection weight values ​​in the weight part of the second weight data of the sparse second neuron correspond one-to-one to the identification information representing the non-zero connection weight values ​​in the identification sequence; The step of determining a connection weight value between at least one target neuron and at least one first neuron according to the sparse second weight data of the second neuron or the sparse second weight data of the first neuron includes: Determine, according to an identification sequence in the second weight data of the sparse second neuron, a second neuron having a non-zero connection weight value with the emitted first neuron as the target neuron; The connection weight value between each target neuron and the sparse first neuron is determined based on the correspondence between the non-zero connection weight value in the weight part of the second weight data of the target neuron and the identification information representing the non-zero connection weight value in the identification sequence.

9. The data processing method according to claim 8, wherein: The step of determining, based on the identification sequence in the second weight data of the sparse first neuron, a second neuron having a connection weight value with the sparse first neuron and a non-zero connection weight value as the target neuron includes: Determine a target predecessor neuron corresponding to a target time interval based on the firing information of each sparse first neuron in each time interval, wherein the firing information indicates whether each sparse first neuron in each time interval fires, and the target predecessor neuron is the first neuron that fires in the target time interval; According to an identification sequence in the second weight data of at least one of the target predecessor neurons, a second neuron having a non-zero connection weight value with at least one of the target predecessor neurons is determined as the target neuron.

10. The data processing method according to any one of claims 1 to 9, wherein: For any one of the target neurons, the step of calculating the membrane potential of each of the target neurons according to the connection weight value between the at least one target neuron and the at least one first neuron includes: The membrane potential of the target neuron is calculated according to the historical membrane potential of the target neuron and the connection weight value between the target neuron and the at least one first neuron.

11. A processing core comprising a computing unit and a cache; The computing unit can implement the data processing method according to any one of claims 1 to 10.

12. A many-core system comprising: Multiple processing cores; as well as an on-chip network configured to exchange data between the plurality of processing cores and external data; One or more instructions are stored in one or more of the processing cores, and one or more of the instructions are executed by one or more of the processing cores, so that one or more of the processing cores can implement the data processing method according to any one of claims 1 to 10.

13. A computer-readable medium having a computer program stored thereon, wherein: When the computer program is executed by the processing core, the computer program implements the data processing method according to any one of claims 1 to 10.

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