Embedded software architecture method applied to digital power supply

Abstract

The invention discloses an embedded software architecture method applied to a digital power supply. The embedded software architecture method comprises the following steps: S1, timed scheduling basis: generating a tick mark; a hardware timer of the MCU / DSP is taken as a core, and a tick mark with a fixed period is generated and is taken as a time reference of task scheduling of the whole system; s2, task cycle division: according to product requirements, disassembling functions into different tasks, and allocating corresponding execution cycles; s3, a time-sharing scheduling mechanism: only executing a task of a current time slice in each ticking cycle; s4, simulating operation system logic: realizing multi-task processing through'round-robin '; s5, core interruption: a loop control algorithm; pWM period interruption or ADC sampling interruption is used for triggering, the priority is the highest, and only loop control is executed. According to the invention, the problems that the real-time performance is low and the response time is uncontrollable and long when a general embedded operating system is applied to digital power supply control software are solved.

Description

Technical Field

[0001] This invention relates to the field of digital power supply technology, specifically an embedded software architecture method applied to digital power supplies. Background Technology

[0002] The core requirements for software in digital power control systems are primarily real-time performance, requiring microsecond-level response times. Critical control tasks, such as overcurrent protection and PWM waveform generation, need to respond within 10µs; otherwise, there is a risk of switching transistor damage or output malfunction. Current and voltage sampling periods typically need to be less than 5µs to accurately capture sudden load changes. Simultaneously, deterministic timing must be ensured. Control loops (such as PID algorithms and zero-pole compensation filters) must strictly adhere to a fixed-cycle execution, with timing jitter controlled within ±50ns to avoid switching frequency drift. ADC sampling points must be synchronized with the PWM carrier to reduce noise interference.

[0003] Based on the above requirements, the key requirements for software design mainly lie in the implementation of efficient algorithms and support for hardware acceleration. Complex control algorithms (such as PFC power factor correction and LLC resonant control) need to optimize computational load to ensure that floating-point operations are completed within a single control cycle. Lightweight real-time operating systems (RTOS) need to remove unnecessary modules, and kernel interrupt latency must be less than 500ns. Critical interrupt service routines (ISRs) need to run independently of the operating system and directly respond to hardware events. Non-volatile memory needs to back up parameters in real time to cope with sudden power outages.

[0004] Timeliness Challenges and Countermeasures. When the load changes abruptly, output fluctuations must be suppressed within 50µs. The solution typically involves dynamically adjusting PID parameters and using feedforward compensation. Contention for multi-task resources often results in communication tasks blocking control task execution; this can be addressed by setting task priorities and using DMA data transfer.

[0005] In digital power control systems with extremely high real-time requirements, the shortcomings and deficiencies of embedded operating systems are mainly reflected in the following aspects: Real-time defects: Kernel scheduling latency; task switching consumes microseconds (typically 1-10μs), while the PWM control loop of digital power supplies requires nanosecond-level jitter (≤50ns), which may lead to switching timing deviations and affect voltage regulation accuracy. Non-real-time kernels do not support preemption in kernel mode; low-priority kernel tasks may block high-priority real-time tasks (such as overcurrent protection), and the response latency may exceed 100μs. Interrupt response is limited; the operating system interrupt service process requires context switching, and the interrupt disable time is too long, which cannot meet the requirement of ≤200ns for interrupt response in high-frequency switching power supplies (>500kHz). When multiple tasks compete for interrupt resources, high-priority tasks still need to wait for the system call to complete, increasing the risk of delayed protection actions. Summary of the Invention

[0006] The purpose of this invention is to provide an embedded software architecture method for digital power supplies to solve the problems in the prior art.

[0007] To achieve the above objectives, the present invention provides the following technical solution: an embedded software architecture method applied to digital power supplies, comprising the following steps:

[0008] S1. Basics of Timed Scheduling: Generation of Tick Flags; Using the hardware timer of the MCU / DSP as the core, tick flags with fixed periods are generated as the "time base" for task scheduling of the entire system.

[0009] S2. Task Cycle Division: Based on product requirements, break down functions into different tasks and assign corresponding execution cycles;

[0010] S3, Time-sharing scheduling mechanism: Only the task in the "current time slice" is executed within each tick cycle;

[0011] S4, Operating System Imitation Logic: Multitasking is achieved through "time-slice rotation";

[0012] S5, Core Interrupt: Loop Control Algorithm; Triggered by PWM periodic interrupt or ADC sampling interrupt, with the highest priority, only loop control is executed;

[0013] S6. State Machine Programming: Program according to the concept of state machines;

[0014] S7. Data Interaction Protection: Data interaction protection between loop algorithm interruption and periodic task function.

[0015] Preferably, it also includes S8, execution time testing: the execution time of each task function and loop algorithm needs to be tested; use a timer to calculate the time or use the IO port output to test the time on an oscilloscope to observe whether it is within the required time boundary, otherwise it needs to be adjusted to meet the requirements.

[0016] Preferably, the cycle time in S1 is set to 500us or 1ms (the time can be adjusted according to the task situation, and the general adjustment range is 500us-5ms).

[0017] Preferably, the tasks in S2 include data acquisition, communication processing, status monitoring, and human-computer interaction; the execution cycle is a multiple of the tick mark cycle, and the multiple is 2^N.

[0018] Preferably, in S4, only the task function of that time slice is executed within each scheduling tick cycle, and it does not overlap with the task functions of other time slices.

[0019] Preferably, the method used in S7 is either a switch interruption or a signal mutual exclusion flag for read / write protection.

[0020] Compared with the prior art, the beneficial effects of the present invention are:

[0021] 1. This invention overcomes the problems of low real-time performance and uncontrollable and long response times in general embedded operating systems used in digital power control software applications. Its importance is particularly evident in applications with short interrupt cycles in high-frequency digital loop algorithms.

[0022] 2. This invention enables the execution of task functions that strictly adhere to a fixed-cycle scheduling. The execution jitter of the task function can be controlled within the maximum PWM cycle time. For example, if the PWM loop algorithm cycle is 100kHz, the time is 10µs. The execution jitter time of the PWM loop algorithm cycle (without nesting with other interrupts) is the execution time of other interrupts. Because the communication receive interrupt processing only receives data, the time is extremely short, typically less than 1µs. Furthermore, because the execution time of the loop algorithm code is less than the loop algorithm cycle time, typically less than 70% of the loop algorithm cycle time, the processing time of the communication receive data interrupt does not cause PWM switching frequency drift, enabling precise ADC sampling point and PWM carrier synchronization.

[0023] 3. Protection of loop algorithm interruptions and periodic task interaction data can prevent data corruption and accidents. If data such as the bus voltage setpoint is not protected, its value will change abruptly if corrupted, causing the loop regulation output to fluctuate violently, resulting in abnormal overvoltage and overcurrent, and even damaging the device.

[0024] 4. The task functions are written according to the concept of state machines. The execution cycle and time of the code that has been written and the task functions that have been successfully tested are not affected by the task functions that follow. Each task function runs independently with very low coupling, which saves development cycle and testing workload.

[0025] 5. It can accurately monitor the execution time of each task function and loop algorithm to prevent the execution time from exceeding expectations and disrupting the precise execution time of each task. Attached Figure Description

[0026] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings:

[0027] Figure 1 This is a flowchart of the present invention. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention.

[0029] Please see Figure 1 In this embodiment of the invention, an embedded software architecture method applied to digital power supplies includes the following steps:

[0030] S1. Basic Timing Scheduling: Generation of Tick Marks; Using the hardware timer of the MCU / DSP as the core, tick marks with a fixed period are generated as the "time base" for task scheduling of the entire system; the period time is set to 500us or 1ms (the time can be adjusted according to the task situation, and the general adjustment range is: 500us-5ms); A hardware timer TIMER of the MCU / DSP control chip is used to generate tick marks for task period scheduling. According to the actual control requirements, the period time is usually set to 500us or 1ms.

[0031] S2. Task Cycle Division: Based on product requirements, the functions are broken down into different tasks and corresponding execution cycles are assigned. Tasks include data collection, communication processing, status monitoring, and human-computer interaction. The execution cycle is a multiple of the tick mark cycle, where the multiple is 2^N, and N = 0, 1, 2, 3, etc.

[0032] S3, Time-sharing scheduling mechanism: Only the task in the "current time slice" is executed within each tick cycle; the execution functions and execution cycles of each task are divided according to the actual needs of the product.

[0033] The digital power supply software primarily plans for a loop control algorithm interrupt, triggered by either a PWM periodic interrupt or an ADC sampling interrupt. No additional interrupt handlers are added unless absolutely necessary. High-frequency communication tasks can receive data via interrupts, but the receive interrupt function only receives the data and does not perform protocol analysis. Protocol analysis and processing are handled within the periodic task function to reduce the processing time of the receive interrupt function and avoid excessive delays in the loop control algorithm interrupt.

[0034] S4, Operating System Imitation Logic: Multi-task processing is achieved through "time slice rotation"; within each scheduling tick cycle, only the task function of that time slice is executed, without overlapping with the task functions of other time slices, to prevent the total processing time from exceeding the time slice cycle, such as 500us or 1ms (the time can be adjusted according to the task situation, and the general adjustment range is: 500us-5ms).

[0035] S5, Core Interrupt: Loop Control Algorithm; Triggered by PWM periodic interrupt or ADC sampling interrupt, with the highest priority, only loop control is executed;

[0036] S6. State Machine Programming: Programs are written according to the concept of state machines to improve reliability and portability. Each time a task function is added, its execution does not affect the execution of other tasks.

[0037] S7. Data Interaction Protection: Data interaction protection between loop algorithm interrupt and periodic task function; the method used is to switch the interrupt or use a signal mutual exclusion flag for read / write protection.

[0038] S8. Execution Time Test: The execution time of each task function and loop algorithm needs to be tested; use a timer to calculate the time or use the I / O port output to test the time on an oscilloscope to observe whether it is within the required time boundary. Otherwise, adjustments need to be made to meet the requirements.

[0039] I. Description of Task Function Time Slice Division

[0040] 1) For example, the task timer period is 0.5ms, and each consecutive timer period is numbered 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23. After the period is numbered to 23, the next period continues to be numbered from 0.

[0041] 2) Since the time interval between each number is 0.5ms, then the time interval of 1ms is 1ms after two consecutive numbers.

[0042] Starting from number 0, a cycle is: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22.

[0043] 3) Similarly, the 4ms interval cycle tasks are: 1, 9, 17; or 3, 11, 19; or 5, 13, 21.

[0044] 4) The remaining 3 numbers are individual 12ms task cycles.

[0045] II. Pseudocode of the main function

[0046]

[0047]

[0048] III. Loop Algorithm Interruption Pseudocode

[0049]

[0050] IV. Pseudocode of the Task Function

[0051]

[0052]

[0053] Finally, it should be noted that the above descriptions are merely preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. An embedded software architecture method applied to digital power supplies, characterized in that, Includes the following steps: S1. Basics of Timed Scheduling: Generation of Tick Flags; Using the hardware timer of the MCU / DSP as the core, tick flags with fixed periods are generated as the "time base" for task scheduling of the entire system. S2. Task Cycle Division: Based on product requirements, break down functions into different tasks and assign corresponding execution cycles; S3, Time-sharing scheduling mechanism: Only the task in the "current time slice" is executed within each tick cycle; S4, Operating System Imitation Logic: Multitasking is achieved through "time-slice rotation"; S5, Core Interrupt: Loop Control Algorithm; Triggered by PWM periodic interrupt or ADC sampling interrupt, with the highest priority, only loop control is executed; S6. State Machine Programming: Program according to the concept of state machines; S7. Data Interaction Protection: Data interaction protection between loop algorithm interrupts and periodic task functions.

2. The embedded software architecture method for digital power supply according to claim 1, characterized in that, This also includes S8 and execution time testing: the execution time of each task function and loop algorithm needs to be tested; Use a timer to calculate the time or use the I / O port to output the time on an oscilloscope to test whether it is within the required time boundary. Otherwise, adjustments are needed to meet the requirements.

3. The embedded software architecture method for digital power supply according to claim 1, characterized in that, The period time in S1 is set to 500us or 1ms.

4. The embedded software architecture method for digital power supply according to claim 1, characterized in that, The tasks in S2 include data acquisition, communication processing, status monitoring, and human-computer interaction; the execution cycle is a multiple of the tick mark cycle, and the multiple is 2^N.

5. The embedded software architecture method for digital power supply according to claim 1, characterized in that, In S4, only the task function of that time slice is executed within each scheduling tick cycle, and it does not overlap with the task functions of other time slices.

6. The embedded software architecture method for digital power supply according to claim 1, characterized in that, The method used in S7 is either a switch interruption or a signal mutual exclusion flag for read / write protection.

Images