Driving circuit and display device

Abstract

The present application discloses a driving circuit and a display device. The driving circuit of the present application provides a level signal to the first node under the control of the first signal control terminal and the second signal control terminal, and then provides the signal of the first power supply terminal or the second power supply terminal to the output terminal under the control of the level signal of the first node, thereby outputting different level signals under the control of two control signals to solve the problem that the timing controller cannot be directly matched with different gate drive chips.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a driving circuit and a display device. Background Art

[0002] Display devices, as display components of electronic devices, have been widely used in various electronic products, among which the gate driver chip is an important component of the display device. The gate driver chip can also be called a GOA (Gate Driver On Array) chip, which uses the array process of the thin film transistor display device to make the gate row scanning drive signal circuit on the array substrate to realize a technology of driving the gate row by row scanning.

[0003] The main driving principle of the thin-film transistor display device is that the system motherboard connects the R / G / B compression signal, control signal and power to the connector on the circuit board through wires. After the data is processed by the timing controller on the circuit board, it is connected to the display pixels through the source driver chip and the gate driver chip respectively, so that the display device obtains the required power and signal. The timing controller controls the gate driver chip, which requires multiple control signals. However, the gate driver chips of different manufacturers use the high and low levels of the control signals differently, which makes the timing controller unable to be directly matched with different types of gate driver chips. Therefore, different types of gate driver chips need to be matched with corresponding timing controllers, which requires the design of different versions of circuit boards, resulting in an increase in material production costs. Summary of the invention

[0004] The present application provides a driving circuit and a display device to solve the problem that a timing controller cannot be directly matched with different gate driving chips.

[0005] The present application provides a driving circuit, which includes:

[0006] An input module, the input module is connected to the first signal control end, the second signal control end and the first node respectively, and the input module is used to provide a level signal to the first node under the control of the first signal control end and the second signal control end;

[0007] An output module, wherein the output module is respectively connected to the first power supply terminal, the second power supply terminal, the first node and the output terminal, and the output module is used to provide the signal of the first power supply terminal or the second power supply terminal to the output terminal under the control of the level signal of the first node.

[0008] Optionally, in some embodiments of the present application, the input module includes:

[0009] a first transistor, wherein a gate of the first transistor is connected to the first signal control terminal, one of a source and a drain of the first transistor is connected to the second signal control terminal, and the other of the source and the drain of the first transistor is connected to the first node;

[0010] a second transistor, wherein a gate of the second transistor is connected to the first signal control terminal, one of a source and a drain of the second transistor is connected to the second signal control terminal, and the other of the source and the drain of the second transistor is connected to the first node;

[0011] The first transistor is one of a P-type transistor and an N-type transistor, and the second transistor is the other of the P-type transistor and the N-type transistor.

[0012] Optionally, in some embodiments of the present application, the output module includes:

[0013] a third transistor, wherein a gate of the third transistor is connected to the first node, one of a source and a drain of the third transistor is connected to the first power supply terminal, and the other of the source and the drain of the third transistor is connected to the output terminal;

[0014] a fourth transistor, wherein a gate of the fourth transistor is connected to the first node, one of a source and a drain of the fourth transistor is connected to the second power supply terminal, and the other of the source and the drain of the fourth transistor is connected to the output terminal;

[0015] The third transistor is one of a P-type transistor and an N-type transistor, and the fourth transistor is the other of the P-type transistor and the N-type transistor.

[0016] Optionally, in some embodiments of the present application, the input module further includes:

[0017] a fifth transistor, wherein a gate of the fifth transistor is connected to the second node, one of a source and a drain of the fifth transistor is connected to a third power supply terminal, and the other of the source and the drain of the fifth transistor is connected to the first node;

[0018] a sixth transistor, a gate of the sixth transistor being connected to the second node, one of a source and a drain of the sixth transistor being connected to a fourth power supply terminal, and the other of a source and a drain of the sixth transistor being connected to the first node;

[0019] The other of the source and the drain of the first transistor is connected to the second node, the fifth transistor is one of a P-type transistor and an N-type transistor, and the sixth transistor is the other of the P-type transistor and the N-type transistor.

[0020] Optionally, in some embodiments of the present application, the output module further includes:

[0021] a seventh transistor, a gate of the seventh transistor being connected to the third node, one of a source and a drain of the seventh transistor being connected to the fourth node, and the other of the source and the drain of the seventh transistor being connected to the output terminal;

[0022] an eighth transistor, a gate of the eighth transistor being connected to the third node, one of a source and a drain of the eighth transistor being connected to the fourth node, and the other of the source and the drain of the eighth transistor being connected to the output terminal;

[0023] The other of the source and the drain of the third transistor is connected to the fourth node, and the other of the source and the drain of the fourth transistor is connected to the fourth node;

[0024] The first signal control terminal is connected to the third node, the seventh transistor is one of a P-type transistor and an N-type transistor, and the eighth transistor is the other of a P-type transistor and an N-type transistor.

[0025] Optionally, in some embodiments of the present application, the output module further includes:

[0026] a seventh transistor, a gate of the seventh transistor being connected to the third node, one of a source and a drain of the seventh transistor being connected to the fourth node, and the other of the source and the drain of the seventh transistor being connected to the output terminal;

[0027] an eighth transistor, a gate of the eighth transistor being connected to the third node, one of a source and a drain of the eighth transistor being connected to the fourth node, and the other of the source and the drain of the eighth transistor being connected to the output terminal;

[0028] The other of the source and the drain of the third transistor is connected to the fourth node, and the other of the source and the drain of the fourth transistor is connected to the fourth node;

[0029] The second signal control terminal is connected to the third node, the seventh transistor is one of a P-type transistor and an N-type transistor, and the eighth transistor is the other of a P-type transistor and an N-type transistor.

[0030] Optionally, in some embodiments of the present application, the first power terminal and the third power terminal are the same power terminal; the second power terminal and the fourth power terminal are the same power terminal.

[0031] Optionally, in some embodiments of the present application, the first power terminal and the fourth power terminal are the same power terminal; the second power terminal and the third power terminal are the same power terminal.

[0032] Correspondingly, the present application also provides a display device, which includes the driving circuit as described above.

[0033] Optionally, in some embodiments of the present application, the display device further includes:

[0034] A timing controller connected to the first signal control terminal and the second signal control terminal of the driving circuit,

[0035] A gate driving chip is connected to the output end of the driving circuit.

[0036] The present application provides a driving circuit and a display device, wherein the driving circuit includes: an input module, the input module is respectively connected to a first signal control terminal, a second signal control terminal and a first node, the input module is used to provide a level signal to the first node under the control of the first signal control terminal and the second signal control terminal; an output module, the output module is respectively connected to a first power supply terminal, a second power supply terminal, the first node and an output terminal, the output module is used to provide a signal of the first power supply terminal or the second power supply terminal to the output terminal under the control of the level signal of the first node. The present application provides a level signal to the first node under the control of the first signal control terminal and the second signal control terminal, and then provides a signal of the first power supply terminal or the second power supply terminal to the output terminal under the control of the level signal of the first node, thereby realizing the output of different level signals under the control of two control signals, so as to solve the problem that the timing controller cannot be directly matched with different gate drive chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0038] Figure 1 A first structural schematic diagram of a driving circuit provided in this application;

[0039] Figure 2 A second structural schematic diagram of the driving circuit provided in this application;

[0040] Figure 3 A schematic diagram of a display device provided in this application;

[0041] Figure 4 A third structural schematic diagram of the driving circuit provided in this application;

[0042] Figure 5 A fourth structural schematic diagram of the driving circuit provided in this application;

[0043] Figure 6 A fifth structural schematic diagram of the driving circuit provided in this application;

[0044] Figure 7 A sixth structural schematic diagram of the driving circuit provided in this application;

[0045] Figure 8 A seventh structural schematic diagram of the driving circuit provided in this application;

[0046] Fig. 9 An eighth structural schematic diagram of the driving circuit provided in the present application;

[0047] Fig.10 A ninth structural schematic diagram of the driving circuit provided in the present application;

[0048] Fig.11 A tenth structural schematic diagram of the driving circuit provided in the present application;

[0049] Fig.12 This is an eleventh structural schematic diagram of the driving circuit provided in this application;

[0050] Fig.13 A twelfth structural schematic diagram of the driving circuit provided in the present application;

[0051] Fig.14 This is the thirteenth structural schematic diagram of the driving circuit provided in this application. DETAILED DESCRIPTION

[0052] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of this application.

[0053] In the description of the present application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present application, "plurality" means two or more, unless otherwise clearly and specifically defined.

[0054] The transistors used in all embodiments of the present application can be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain of the transistors used here are symmetrical, their source and drain are interchangeable. In the embodiment of the present application, in order to distinguish the two poles of the transistor except the gate, one of the poles is called the source and the other is called the drain. According to the form in the accompanying drawings, the middle end of the control module is specified as the gate, the signal input end is the source, and the output end is the drain. In addition, the transistors used in the embodiments of the present application may include P-type transistors and / or N-type transistors, wherein the P-type transistor is turned on when the gate is low and turned off when the gate is high, and the N-type transistor is turned on when the gate is high and turned off when the gate is low.

[0055] The present application provides a driving circuit and a display device, which are described in detail below. It should be noted that the description order of the following embodiments is not intended to limit the preferred order of the embodiments of the present application.

[0056] See also Figure 1 , Figure 1 The first structural diagram of the driving circuit 100 provided in the present application is shown in FIG.

[0057] The input module 10 is connected to the first signal control terminal S1, the second signal control terminal S2 and the first node P1 respectively, and the input module 10 is used to provide a level signal to the first node P1 under the control of the first signal control terminal S1 and the second signal control terminal S2;

[0058] The output module 20 is respectively connected to the first power supply terminal V1, the second power supply terminal V2, the first node P1 and the output terminal OUT, and the output module 20 is used to provide the signal of the first power supply terminal V1 or the second power supply terminal V2 to the output terminal OUT under the control of the level signal of the first node P1.

[0059] Specifically, during operation, the input module 10 is used to provide a level signal to the first node P1 under the control of the first signal control terminal S1 and the second signal control terminal S2, and the level signal of the first node P1 can be a high level or a low level, and then the output module 20 provides a signal of the first power supply terminal V1 or the second power supply terminal V2 to the output terminal OUT under the control of the level signal of the first node P1, wherein the signal of the first power supply terminal V1 is one of a high level and a low level, and the signal of the second power supply terminal V2 is the other of a high level and a low level. In actual use, the timing controller is connected to the first signal control terminal S1 and the second signal control terminal S2, and the gate drive chip is connected to the output terminal OUT, and then the level of the first power supply terminal V1 and the second power supply terminal V2 is set, and the timing controller inputs an accurate control signal to the gate drive chip through the output terminal OUT, thereby solving the problem that the timing controller cannot be directly matched with different gate drive chips.

[0060] See also Figure 2 , Figure 2 The second structural diagram of the driving circuit 100 provided in the present application. The input module 10 includes a first transistor T1 and a second transistor T2, wherein the gate of the first transistor T1 is connected to the first signal control terminal S1, one of the source and the drain of the first transistor T1 is connected to the second signal control terminal S2, and the other of the source and the drain of the first transistor T1 is connected to the first node P1; the gate of the second transistor T2 is connected to the first signal control terminal S1, one of the source and the drain of the second transistor T2 is connected to the second signal control terminal S2, and the other of the source and the drain of the second transistor T2 is connected to the first node P1; the first transistor T1 is one of a P-type transistor and an N-type transistor, and the second transistor T2 is the other of a P-type transistor and an N-type transistor.

[0061] That is, the first transistor T1 is one of a P-type transistor and an N-type transistor, the second transistor T2 is the other of a P-type transistor and an N-type transistor, the first transistor T1 and the second transistor T2 are different types of transistors, and can alternately output signals of different levels to the first node P1 under the control of the first signal control terminal S1 and the second signal control terminal S2. At the same time, the first transistor T1 and the second transistor T2 are alternately turned on instead of working continuously, which can improve the life of the transistors.

[0062] In some embodiments, the output module 20 includes a third transistor T3 and a fourth transistor T4, the gate of the third transistor T3 is connected to the first node P1, one of the source and the drain of the third transistor T3 is connected to the first power supply terminal V1, and the other of the source and the drain of the third transistor T3 is connected to the output terminal OUT; the gate of the fourth transistor T4 is connected to the first node P1, one of the source and the drain of the fourth transistor T4 is connected to the second power supply terminal V2, and the other of the source and the drain of the fourth transistor T4 is connected to the output terminal OUT; the third transistor T3 is one of a P-type transistor and an N-type transistor, and the fourth transistor T4 is the other of a P-type transistor and an N-type transistor.

[0063] That is, the third transistor T3 is one of a P-type transistor and an N-type transistor, the fourth transistor T4 is the other of a P-type transistor and an N-type transistor, the third transistor T3 and the fourth transistor T4 are different types of transistors, and the third transistor T3 or the fourth transistor T4 is turned on according to the level of the first node P1, so as to provide the output terminal OUT with the signal of the first power supply terminal V1 or the second power supply terminal V2. At the same time, the third transistor T3 and the fourth transistor T4 are alternately turned on instead of continuously working, which can improve the life of the transistors.

[0064] Specifically, in this embodiment, the first transistor T1 is an N-type transistor, the second transistor T2 is a P-type transistor, the third transistor T3 is a P-type transistor, and the fourth transistor T4 is an N-type transistor. The first power supply terminal V1 is connected to a high level signal, and the second power supply terminal V2 is connected to a low level signal.

[0065] In this embodiment, the specific working process is as follows: when the signals of the first signal control terminal S1 and the second signal control terminal S2 are both high-level signals, the first transistor T1 is turned on, the second transistor T2 is turned off, the first transistor T1 transmits the high-level signal of the second signal control terminal S2 to the first node P1, the first node P1 turns on the fourth transistor T4, and the fourth transistor T4 transmits the low-level signal of the second power supply terminal V2 to the output terminal OUT; when the signals of the first signal control terminal S1 and the second signal control terminal S2 are both low-level signals, the first transistor T1 is turned off, the second transistor T2 is turned on, the second transistor T2 transmits the low-level signal of the second signal control terminal S2 to the first node P1, the first node P1 turns on the third transistor T3, and the third transistor T3 transmits the high-level signal of the first power supply terminal V1 to the output terminal OUT; when the signal of the first signal control terminal S1 is a high-level signal , when the signal of the second signal control terminal S2 is a low level signal, the first transistor T1 is turned on and the second transistor T2 is turned off, the first transistor T1 transmits the low level signal of the second signal control terminal S2 to the first node P1, the first node P1 turns on the third transistor T3, and the third transistor T3 transmits the high level signal of the first power supply terminal V1 to the output terminal OUT; when the signal of the first signal control terminal S1 is a low level signal and the signal of the second signal control terminal S2 is a high level signal, the signals of the first signal control terminal S1 are all low level signals, and when the signal of the second signal control terminal S2 is a high level signal, the first transistor T1 is turned off and the second transistor T2 is turned on, the second transistor T2 transmits the high level signal of the second signal control terminal S2 to the first node P1, the first node P1 turns on the fourth transistor T4, and the fourth transistor T4 transmits the low level signal of the second power supply terminal V2 to the output terminal OUT.

[0066] See also Figure 3 , Figure 3 This is a schematic diagram of a display device provided by the present application. The present application also provides a display device 1000, which includes the driving circuit 100 as described above.

[0067] The display device 1000 further includes a timing controller 200 and a gate driving chip 300 . The timing controller 200 is connected to the first signal control terminal S1 and the second signal control terminal S2 of the driving circuit 100 . The gate driving chip 300 is connected to the output terminal OUT of the driving circuit 100 .

[0068] The timing controller 200 of the present application inputs an accurate control signal to the gate driving chip 300 through the output terminal OUT, thereby solving the problem that the timing controller cannot be directly matched with different gate driving chips.

[0069] The principle of solving the problem of the display device is similar to that of the aforementioned driving circuit 100, so the implementation and beneficial effects of the display device can refer to the description of the aforementioned driving circuit 100, and the repeated parts will not be repeated here.

[0070] See also Figure 4 , Figure 4 The third structural diagram of the driving circuit 100 provided in the present application is shown in FIG. 1. In other embodiments of the present application, the first transistor T1 is a P-type transistor, the second transistor T2 is an N-type transistor, the third transistor T3 is a P-type transistor, and the fourth transistor T4 is an N-type transistor.

[0071] See also Figure 5 , Figure 5 This is a fourth structural diagram of the driving circuit 100 provided in the present application. In other embodiments of the present application, the first transistor T1 is a P-type transistor, the second transistor T2 is an N-type transistor, the third transistor T3 is an N-type transistor, and the fourth transistor T4 is a P-type transistor.

[0072] See also Figure 6 , Figure 6 The fifth structural diagram of the driving circuit 100 provided in the present application. In other embodiments of the present application, the first transistor T1 is an N-type transistor, the second transistor T2 is a P-type transistor, the third transistor T3 is an N-type transistor, and the fourth transistor T4 is a P-type transistor.

[0073] See also Figure 7 , Figure 7 6 is a schematic diagram of the structure of the driving circuit 100 provided in the present application. Figure 1 The provided driving circuit 100 is different in that: in some embodiments of the present application, the input module 10 also includes: a fifth transistor T5 and a sixth transistor T6, the gate of the fifth transistor T5 is connected to the second node P2, one of the source and the drain of the fifth transistor T5 is connected to the third power supply terminal V3, and the other of the source and the drain of the fifth transistor T5 is connected to the first node P1; the gate of the sixth transistor T6 is connected to the second node P2, one of the source and the drain of the sixth transistor T6 is connected to the fourth power supply terminal V4, and the other of the source and the drain of the sixth transistor T6 is connected to the first node P1; the other of the source and the drain of the first transistor T1 is connected to the second node P2, the fifth transistor T5 is one of a P-type transistor and an N-type transistor, and the sixth transistor T6 is the other of a P-type transistor and an N-type transistor.

[0074] That is, the fifth transistor T5 is one of a P-type transistor and an N-type transistor, the sixth transistor T6 is the other of a P-type transistor and an N-type transistor, the fifth transistor T5 and the sixth transistor T6 are different types of transistors, and the fifth transistor T5 or the sixth transistor T6 is turned on according to the level signal of the second node P2, so that different level signals can be alternately output to the first node P1. At the same time, the fifth transistor T5 and the sixth transistor T6 are alternately turned on instead of continuously working, which can improve the life of the transistors.

[0075] Specifically, in this embodiment, the fifth transistor T5 is an N-type transistor, and the sixth transistor T6 is a P-type transistor. The signals of the first power supply terminal V1 and the third power supply terminal V3 are high-level signals, and the signals of the second power supply terminal V2 and the fourth power supply terminal V4 are low-level signals.

[0076] In this embodiment, the specific working process is as follows: when the signals of the first signal control terminal S1 and the second signal control terminal S2 are both high-level signals, the first transistor T1 is turned on, the second transistor T2 is turned off, the first transistor T1 transmits the high-level signal of the second signal control terminal S2 to the second node P2, the second node P2 turns on the sixth transistor T6, the sixth transistor T6 transmits the low-level signal of the fourth power supply terminal V4 to the first node P1, the first node P1 turns on the third transistor T3, and the third transistor T3 transmits the high-level signal of the first power supply terminal V1 to the output terminal OUT; when the signals of the first signal control terminal S1 and the second signal control terminal S2 are both low-level signals, the first transistor T1 is turned off, the second transistor T2 is turned on, the second transistor T2 transmits the low-level signal of the second signal control terminal S2 to the first node P1, the first node P1 turns on the third transistor T3, and the third transistor T3 transmits the high-level signal of the first power supply terminal V1 to the output terminal OUT ; When the signal of the first signal control terminal S1 is a high-level signal and the signal of the second signal control terminal S2 is a low-level signal, the first transistor T1 is turned on and the second transistor T2 is turned off. The first transistor T1 transmits the low-level signal of the second signal control terminal S2 to the second node P2. The second node P2 turns on the fifth transistor T5. The fifth transistor T5 transmits the high-level signal of the third power supply terminal V3 to the first node P1. The first node P1 turns on the fourth transistor T4. The fourth transistor T4 transmits the low-level signal of the second power supply terminal V2 to the output terminal OUT; when the signal of the first signal control terminal S1 is a low-level signal and the signal of the second signal control terminal S2 is a high-level signal, the first transistor T1 is turned off and the second transistor T2 is turned on. The second transistor T2 transmits the high-level signal of the second signal control terminal S2 to the first node P1. The first node P1 turns on the fourth transistor T4. The fourth transistor T4 transmits the low-level signal of the second power supply terminal V2 to the output terminal OUT.

[0077] See also Figure 8 , Figure 8 The seventh structural diagram of the driving circuit 100 provided in the present application is shown in FIG. 1. In some embodiments, the first power terminal V1 and the third power terminal V3 are the same power terminal; the second power terminal V2 and the fourth power terminal V4 are the same power terminal.

[0078] See also Fig. 9 , Fig. 9 This is an eighth structural diagram of the driving circuit 100 provided in the present application. In other embodiments of the present application, the fifth transistor T5 is a P-type transistor, and the sixth transistor T6 is an N-type transistor.

[0079] In other embodiments of the present application, the signals of the first power terminal V1 and the third power terminal V3 are low level signals, and the signals of the second power terminal V2 and the fourth power terminal V4 are high level signals. The first power terminal V1 and the third power terminal V3 are the same power terminal; the second power terminal V2 and the fourth power terminal V4 are the same power terminal.

[0080] See also Fig.10 , Fig.10 The ninth structural diagram of the driving circuit 100 provided in the present application. In other embodiments of the present application, the signals of the first power supply terminal V1 and the fourth power supply terminal V4 are low-level signals, and the signals of the second power supply terminal V2 and the third power supply terminal V3 are high-level signals. The first power supply terminal V1 and the fourth power supply terminal V4 are the same power supply terminal; the second power supply terminal V2 and the third power supply terminal V3 are the same power supply terminal.

[0081] In other embodiments of the present application, the signals of the first power terminal V1 and the fourth power terminal V4 are high level signals, and the signals of the second power terminal V2 and the third power terminal V3 are low level signals. In some embodiments of the present application, the first power terminal V1 and the fourth power terminal V4 are the same power terminal; the second power terminal V2 and the third power terminal V3 are the same power terminal.

[0082] See also Fig.11 , Fig.11 10 is a schematic diagram of the structure of the driving circuit 100 provided in the present application. Figure 7 The provided driving circuit 100 is different in that: the output module 20 further includes: a seventh transistor T7 and an eighth transistor T8, the gate of the seventh transistor T7 is connected to the third node P3, one of the source and the drain of the seventh transistor T7 is connected to the fourth node P4, and the other of the source and the drain of the seventh transistor T7 is connected to the output terminal OUT; the gate of the eighth transistor T8 is connected to the third node P3, one of the source and the drain of the eighth transistor T8 is connected to the fourth node P4, and the other of the source and the drain of the eighth transistor T8 is connected to the output terminal OUT; the other of the source and the drain of the third transistor T3 is connected to the fourth node P4, and the other of the source and the drain of the fourth transistor T4 is connected to the fourth node P4; the first signal control terminal S1 is connected to the third node P3, the seventh transistor T7 is one of a P-type transistor and an N-type transistor, and the eighth transistor T8 is the other of a P-type transistor and an N-type transistor.

[0083] That is, in this embodiment, the seventh transistor T7 and the eighth transistor T8 are connected between the fourth node P4 and the output terminal OUT, the seventh transistor T7 is one of a P-type transistor and an N-type transistor, and the eighth transistor T8 is the other of a P-type transistor and an N-type transistor. The first signal control terminal S1 is used to control one of the seventh transistor T7 and the eighth transistor T8 to be turned on through the first signal control terminal S1, thereby providing the signal of the first power supply terminal V1 or the second power supply terminal V2 to the output terminal OUT.

[0084] Specifically, the seventh transistor T7 is a P-type transistor, and the eighth transistor T8 is an N-type transistor. The signals of the first power supply terminal V1 and the third power supply terminal V3 are high level signals, and the signals of the second power supply terminal V2 and the fourth power supply terminal V4 are low level signals.

[0085] In this embodiment, the specific working process is as follows: when the signals of the first signal control terminal S1 and the second signal control terminal S2 are both high-level signals, the first transistor T1 is turned on, the second transistor T2 is turned off, the seventh transistor T7 is turned off, and the eighth transistor T8 is turned on. The first transistor T1 transmits the high-level signal of the second signal control terminal S2 to the second node P2. The second node P2 turns on the sixth transistor T6. The sixth transistor T6 transmits the low-level signal of the fourth power supply terminal V4 to the first node P1. The first node P1 turns on the third transistor T3. The third transistor T3 transmits the high-level signal of the first power supply terminal V1 to the fourth node P4. The eighth transistor T8 transmits the high-level signal of the first power supply terminal V1 to the output terminal OUT.

[0086] When the signals of the first signal control terminal S1 and the second signal control terminal S2 are both low-level signals, the first transistor T1 is turned off, the second transistor T2 is turned on, the seventh transistor T7 is turned on, and the eighth transistor T8 is turned off. The second transistor T2 transmits the low-level signal of the second signal control terminal S2 to the first node P1. The first node P1 turns on the third transistor T3. The third transistor T3 transmits the high-level signal of the first power supply terminal V1 to the fourth node P4. The seventh transistor T7 transmits the high-level signal of the first power supply terminal V1 to the output terminal OUT.

[0087] When the signal of the first signal control terminal S1 is a high-level signal and the signal of the second signal control terminal S2 is a low-level signal, the first transistor T1 is turned on, the second transistor T2 is turned off, the seventh transistor T7 is turned off, and the eighth transistor T8 is turned on. The first transistor T1 transmits the low-level signal of the second signal control terminal S2 to the second node P2. The second node P2 turns on the fifth transistor T5. The fifth transistor T5 transmits the high-level signal of the third power supply terminal V3 to the first node P1. The first node P1 turns on the fourth transistor T4. The fourth transistor T4 transmits the low-level signal of the second power supply terminal V2 to the fourth node P4. The eighth transistor T8 transmits the low-level signal of the second power supply terminal V2 to the output terminal OUT.

[0088] When the signal of the first signal control terminal S1 is a low level signal and the signal of the second signal control terminal S2 is a high level signal, the first transistor T1 is turned off, the second transistor T2 is turned on, the seventh transistor T7 is turned on, and the eighth transistor T8 is turned off. The second transistor T2 transmits the high level signal of the second signal control terminal S2 to the first node P1. The first node P1 turns on the fourth transistor T4, and the fourth transistor T4 transmits the low level signal of the second power supply terminal V2 to the fourth node P4. The seventh transistor T7 transmits the low level signal of the second power supply terminal V2 to the output terminal OUT.

[0089] See also Fig.12 , Fig.12 This is an eleventh structural diagram of the driving circuit 100 provided in the present application. In other embodiments of the present application, the seventh transistor T7 is an N-type transistor, and the eighth transistor T8 is a P-type transistor.

[0090] See also Fig.13 , Fig.13 This is a twelfth structural diagram of the driving circuit 100 provided in this application. Figure 7The provided driving circuit 100 is different in that: the output module 20 further includes: a seventh transistor T7 and an eighth transistor T8, the gate of the seventh transistor T7 is connected to the third node P3, one of the source and the drain of the seventh transistor T7 is connected to the fourth node P4, and the other of the source and the drain of the seventh transistor T7 is connected to the output terminal OUT; the gate of the eighth transistor T8 is connected to the third node P3, one of the source and the drain of the eighth transistor T8 is connected to the fourth node P4, and the other of the source and the drain of the eighth transistor T8 is connected to the output terminal OUT; the other of the source and the drain of the third transistor T3 is connected to the fourth node P4, and the other of the source and the drain of the fourth transistor T4 is connected to the fourth node P4; the second signal control terminal S2 is connected to the third node P3, the seventh transistor T7 is one of a P-type transistor and an N-type transistor, and the eighth transistor T8 is the other of a P-type transistor and an N-type transistor.

[0091] That is, in this embodiment, the seventh transistor T7 and the eighth transistor T8 are connected between the fourth node P4 and the output terminal OUT, the seventh transistor T7 is one of a P-type transistor and an N-type transistor, and the eighth transistor T8 is the other of a P-type transistor and an N-type transistor, and the second signal control terminal S2 is used to control one of the seventh transistor T7 and the eighth transistor T8 to be turned on through the first signal control terminal S1, thereby providing the signal of the first power supply terminal V1 or the second power supply terminal V2 to the output terminal OUT.

[0092] Specifically, the seventh transistor T7 is a P-type transistor, and the eighth transistor T8 is an N-type transistor. The signals of the first power supply terminal V1 and the third power supply terminal V3 are high level signals, and the signals of the second power supply terminal V2 and the fourth power supply terminal V4 are low level signals.

[0093] In this embodiment, the specific working process is as follows: when the signals of the first signal control terminal S1 and the second signal control terminal S2 are both high-level signals, the first transistor T1 is turned on, the second transistor T2 is turned off, the seventh transistor T7 is turned off, and the eighth transistor T8 is turned on. The first transistor T1 transmits the high-level signal of the second signal control terminal S2 to the second node P2. The second node P2 turns on the sixth transistor T6. The sixth transistor T6 transmits the low-level signal of the fourth power supply terminal V4 to the first node P1. The first node P1 turns on the third transistor T3. The third transistor T3 transmits the high-level signal of the first power supply terminal V1 to the fourth node P4. The eighth transistor T8 transmits the high-level signal of the first power supply terminal V1 to the output terminal OUT.

[0094] When the signals of the first signal control terminal S1 and the second signal control terminal S2 are both low-level signals, the first transistor T1 is turned off, the second transistor T2 is turned on, the seventh transistor T7 is turned on, and the eighth transistor T8 is turned off. The second transistor T2 transmits the low-level signal of the second signal control terminal S2 to the first node P1. The first node P1 turns on the third transistor T3. The third transistor T3 transmits the high-level signal of the first power supply terminal V1 to the fourth node P4. The seventh transistor T7 transmits the high-level signal of the first power supply terminal V1 to the output terminal OUT.

[0095] When the signal of the first signal control terminal S1 is a high-level signal and the signal of the second signal control terminal S2 is a low-level signal, the first transistor T1 is turned on, the second transistor T2 is turned off, the seventh transistor T7 is turned on, and the eighth transistor T8 is turned off. The first transistor T1 transmits the low-level signal of the second signal control terminal S2 to the second node P2. The second node P2 turns on the fifth transistor T5. The fifth transistor T5 transmits the high-level signal of the third power supply terminal V3 to the first node P1. The first node P1 turns on the fourth transistor T4. The fourth transistor T4 transmits the low-level signal of the second power supply terminal V2 to the fourth node P4. The seventh transistor T7 transmits the low-level signal of the second power supply terminal V2 to the output terminal OUT.

[0096] When the signal of the first signal control terminal S1 is a low level signal and the signal of the second signal control terminal S2 is a high level signal, the first transistor T1 is turned off, the second transistor T2 is turned on, the seventh transistor T7 is turned off, and the eighth transistor T8 is turned on. The second transistor T2 transmits the high level signal of the second signal control terminal S2 to the first node P1. The first node P1 turns on the fourth transistor T4, and the fourth transistor T4 transmits the low level signal of the second power supply terminal V2 to the fourth node P4. The eighth transistor T8 transmits the low level signal of the second power supply terminal V2 to the output terminal OUT.

[0097] See also Fig.14 , Fig.14 This is a thirteenth structural diagram of the driving circuit 100 provided in the present application. In other embodiments of the present application, the seventh transistor T7 is an N-type transistor, and the eighth transistor T8 is a P-type transistor.

[0098] The above is a detailed introduction to a driving circuit and a display device provided in an embodiment of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technicians in this field, according to the idea of ​​the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A driving circuit, characterized in that: include: An input module, the input module is connected to the first signal control end, the second signal control end and the first node respectively, and the input module is used to provide a level signal to the first node under the control of the first signal control end and the second signal control end; an output module, the output module being connected to the first power supply end, the second power supply end, the first node and the output end respectively, and the output module being used to provide a signal of the first power supply end or the second power supply end to the output end under the control of the level signal of the first node; The input module comprises: a first transistor, wherein a gate of the first transistor is connected to the first signal control terminal, one of a source and a drain of the first transistor is connected to the second signal control terminal, and the other of the source and the drain of the first transistor is connected to the first node; a second transistor, wherein a gate of the second transistor is connected to the first signal control terminal, one of a source and a drain of the second transistor is connected to the second signal control terminal, and the other of a source and a drain of the second transistor is connected to the first node; The first transistor is one of a P-type transistor and an N-type transistor, and the second transistor is the other of a P-type transistor and an N-type transistor; The input module also includes: a fifth transistor, wherein a gate of the fifth transistor is connected to the second node, one of a source and a drain of the fifth transistor is connected to a third power supply terminal, and the other of the source and the drain of the fifth transistor is connected to the first node; a sixth transistor, wherein a gate of the sixth transistor is connected to the second node, one of a source and a drain of the sixth transistor is connected to a fourth power supply terminal, and the other of the source and the drain of the sixth transistor is connected to the first node; The other of the source and the drain of the first transistor is connected to the second node, the fifth transistor is one of a P-type transistor and an N-type transistor, and the sixth transistor is the other of the P-type transistor and the N-type transistor.

2. The driving circuit according to claim 1, characterized in that: The output module comprises: a third transistor, wherein a gate of the third transistor is connected to the first node, one of a source and a drain of the third transistor is connected to the first power supply terminal, and the other of the source and the drain of the third transistor is connected to the output terminal; a fourth transistor, wherein a gate of the fourth transistor is connected to the first node, one of a source and a drain of the fourth transistor is connected to the second power supply terminal, and the other of the source and the drain of the fourth transistor is connected to the output terminal; The third transistor is one of a P-type transistor and an N-type transistor, and the fourth transistor is the other of the P-type transistor and the N-type transistor.

3. The driving circuit according to claim 2, characterized in that: The output module also includes: a seventh transistor, a gate of the seventh transistor being connected to the third node, one of a source and a drain of the seventh transistor being connected to the fourth node, and the other of the source and the drain of the seventh transistor being connected to the output terminal; an eighth transistor, a gate of the eighth transistor being connected to the third node, one of a source and a drain of the eighth transistor being connected to the fourth node, and the other of the source and the drain of the eighth transistor being connected to the output terminal; The other of the source and the drain of the third transistor is connected to the fourth node, and the other of the source and the drain of the fourth transistor is connected to the fourth node; The first signal control terminal is connected to the third node, the seventh transistor is one of a P-type transistor and an N-type transistor, and the eighth transistor is the other of the P-type transistor and the N-type transistor.

4. The driving circuit according to claim 2, characterized in that: The output module also includes: a seventh transistor, a gate of the seventh transistor being connected to the third node, one of a source and a drain of the seventh transistor being connected to the fourth node, and the other of the source and the drain of the seventh transistor being connected to the output terminal; an eighth transistor, a gate of the eighth transistor being connected to the third node, one of a source and a drain of the eighth transistor being connected to the fourth node, and the other of the source and the drain of the eighth transistor being connected to the output terminal; The other of the source and the drain of the third transistor is connected to the fourth node, and the other of the source and the drain of the fourth transistor is connected to the fourth node; The second signal control terminal is connected to the third node, the seventh transistor is one of a P-type transistor and an N-type transistor, and the eighth transistor is the other of a P-type transistor and an N-type transistor.

5. The driving circuit according to claim 1, characterized in that: The first power supply terminal and the third power supply terminal are the same power supply terminal; the second power supply terminal and the fourth power supply terminal are the same power supply terminal.

6. The driving circuit according to claim 1, characterized in that: The first power supply terminal and the fourth power supply terminal are the same power supply terminal; the second power supply terminal and the third power supply terminal are the same power supply terminal.

7. A display device, characterized in that: The invention comprises a driving circuit as claimed in any one of claims 1 to 6.

8. The display device according to claim 7, characterized in that: The display device further includes: A timing controller connected to the first signal control terminal and the second signal control terminal of the driving circuit, A gate driving chip is connected to the output end of the driving circuit.

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