Shift register, driving method thereof, gate driving circuit and display device

Abstract

The shift register, its driving method, gate driving circuit, and display device disclosed herein include an input circuit configured to provide a signal from the input signal terminal to a first node in response to a signal from the input signal terminal; a drive output circuit configured to provide a signal from the clock signal terminal as a gate driving signal to a drive signal output terminal in response to a signal from the first node; and a residual charge release circuit configured to provide a first reference signal from the first reference signal terminal to the drive signal output terminal in response to a signal from the discharge signal terminal, wherein the level of the first reference signal is the same as the level of the gate driving signal.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to a shift register, a driving method thereof, a gate driving circuit and a display device. BACKGROUND

[0002] With the vigorous development of display technology, the cost requirement of display devices is lower and lower, and how to effectively reduce the manufacturing cost of panels is related to the strength of product competitiveness. In order to reduce the manufacturing cost of display devices, the related technology designs a gate driving circuit at the edge of the display device, the gate driving circuit includes a plurality of shift registers arranged in cascade, and in the display stage, each row of shift registers controls the display of the row of pixels. Such design can save the space for placing the chip on film and printed circuit board on the display device, not only can realize the narrow frame design of the display device, but also can reduce the manufacturing cost of the display device at the same time, and improve the competitiveness of the product. SUMMARY

[0003] The embodiments of the present disclosure provide a shift register, a driving method thereof, a gate driving circuit and a display device, to solve the problem that the residual charge in the display area cannot be normally released, resulting in abnormal display in the prior art.

[0004] Therefore, the shift register provided by the embodiments of the present disclosure comprises:

[0005] The input circuit is configured to provide a signal of an input signal end to a first node in response to a signal of the input signal end.

[0006] The driving output circuit is configured to provide a signal of a clock signal end to a driving signal output end as a gate driving signal in response to a signal of the first node.

[0007] The residual charge release circuit is configured to provide a first reference signal of a first reference signal end to the driving signal output end in response to a signal of a discharge signal end, and a level of the first reference signal is the same as a level of the gate driving signal.

[0008] In some embodiments, in the above-mentioned shift register provided by the embodiments of the present disclosure, the discharge signal end comprises at least one sub-discharge signal end, and the residual charge release circuit comprises a sub-discharge circuit corresponding to each sub-discharge signal end, and the sub-discharge circuit is configured to provide the first reference signal to the driving signal output end in response to a signal of the corresponding sub-discharge signal end.

[0009] In some embodiments, in the shift register provided by the embodiments of the present disclosure, the sub-discharge circuit comprises: a first transistor, a gate of the first transistor is coupled with the corresponding sub-discharge signal end, a first electrode of the first transistor is coupled with the first reference signal end, and a second electrode of the first transistor is coupled with the driving signal output end.

[0010] In some embodiments, in the shift register provided by the embodiments of the present disclosure, at least part of the sub-discharge circuit further comprises: a first capacitor, in the same sub-discharge circuit, the first capacitor is coupled between the gate of the first transistor and the first reference signal end.

[0011] In some embodiments, in the shift register provided by the embodiments of the present disclosure, further comprising: a reset circuit, configured to provide a signal of a second reference signal end to the first node in response to a signal of an initial reset signal end;

[0012] At least part of the sub-discharge signal end is multiplexed with the initial reset signal end and / or the first reference signal end, or all the sub-discharge signal ends are independently provided with the initial reset signal end and the first reference signal end.

[0013] In some embodiments, in the shift register provided by the embodiments of the present disclosure, the reset circuit is further configured to provide a signal of the second reference signal end to the first node and provide a second reference signal of the first reference signal end to the driving signal output end in response to a signal of a reset signal end, a level of the signal of the second reference signal end and a level of the second reference signal are opposite to a level of the first reference signal.

[0014] In some embodiments, in the shift register provided by the embodiments of the present disclosure, the reset circuit comprises: a second transistor, a third transistor and a fourth transistor, wherein,

[0015] A gate of the second transistor is coupled with the initial reset signal end, a first electrode of the second transistor is coupled with the second reference signal end, and a second electrode of the second transistor is coupled with the first node;

[0016] A gate of the third transistor is coupled with the reset signal end, a first electrode of the third transistor is coupled with the second reference signal end, and a second electrode of the third transistor is coupled with the first node;

[0017] A gate of the fourth transistor is coupled with the reset signal end, a first electrode of the fourth transistor is coupled with the first reference signal end, and a second electrode of the fourth transistor is coupled with the driving signal output end.

[0018] In some embodiments, the shift register further comprises at least one control circuit.

[0019] The control circuit is configured to control the level of the second node and the level of the first node to be opposite in response to the signal of the input signal terminal and the signal of the selection signal terminal, wherein the selection signal terminal and the second node each correspond to the control circuit one by one.

[0020] The driving output circuit is further configured to provide the second reference signal of the first reference signal terminal to the driving signal output terminal in response to the signal of the second node, and the level of the second reference signal is opposite to the level of the first reference signal.

[0021] In some embodiments, the shift register further comprises at least one control circuit.

[0022] The gate of the fifth transistor and the first pole of the fifth transistor are each coupled to the corresponding selection signal terminal, and the second pole of the fifth transistor is coupled to the second pole of the sixth transistor.

[0023] The gate of the sixth transistor is coupled to the first node, and the first pole of the sixth transistor is coupled to the second reference signal terminal.

[0024] The gate of the seventh transistor is coupled to the input signal terminal, the first pole of the seventh transistor is coupled to the second reference signal terminal, and the second pole of the seventh transistor is coupled to the corresponding second node.

[0025] The gate of the eighth transistor is coupled to the corresponding second node, the first pole of the eighth transistor is coupled to the second reference signal terminal, and the second pole of the eighth transistor is coupled to the first node.

[0026] In some embodiments, the shift register further comprises at least one control circuit.

[0027] The second capacitor is coupled between the first node and the driving signal output terminal.

[0028] The gate of the ninth transistor is coupled to the first node, the first pole of the ninth transistor is coupled to the clock signal terminal, and the second pole of the ninth transistor is coupled to the driving signal output terminal.

[0029] A gate of the tenth transistor is coupled with the corresponding second node, a first pole of the tenth transistor is coupled with the first reference signal end, and a second pole of the tenth transistor is coupled with the driving signal output end.

[0030] In some embodiments, in the above shift register provided by the embodiments of the present disclosure, a cascade output circuit is further included, which is configured to provide the signal of the clock signal end to a cascade signal output end in response to the signal of the first node, and provide the signal of the second reference signal end to the cascade signal output end in response to the signal of the second node.

[0031] In some embodiments, in the above shift register provided by the embodiments of the present disclosure, the cascade output circuit includes an eleventh transistor and a twelfth transistor corresponding to the second node, wherein,

[0032] A gate of the eleventh transistor is coupled with the first node, a first pole of the eleventh transistor is coupled with the clock signal end, and a second pole of the eleventh transistor is coupled with the cascade signal output end;

[0033] A gate of the twelfth transistor is coupled with the corresponding second node, a first pole of the twelfth transistor is coupled with the second reference signal end, and a second pole of the twelfth transistor is coupled with the cascade signal output end.

[0034] In some embodiments, in the above shift register provided by the embodiments of the present disclosure, the input circuit includes a thirteenth transistor, a gate of the thirteenth transistor and a first pole of the thirteenth transistor are both coupled with the input signal end, and a second pole of the thirteenth transistor is coupled with the first node.

[0035] Based on the same inventive concept, the embodiments of the present disclosure provide a gate drive circuit, including a plurality of the above shift registers provided by the embodiments of the present disclosure in cascade;

[0036] The input signal end of the first-stage shift register is coupled with the frame trigger signal end.

[0037] The input signal end of each shift register other than the first-stage shift register is respectively coupled with the cascade signal output end of the adjacent upper-stage shift register.

[0038] The driving signal output end of each shift register is connected with the gate line of the corresponding row.

[0039] Based on the same inventive concept, the embodiments of the present disclosure provide a display device including the above gate drive circuit provided by the embodiments of the present disclosure.

[0040] Based on the same inventive concept, the disclosure provides a driving method of the shift register, comprising:

[0041] In the input stage, the input circuit provides the signal of the input signal end to the first node in response to the signal of the input signal end.

[0042] In the output stage, the cascade output circuit provides the signal of the clock signal end as the gate driving signal to the driving signal output end in response to at least the signal of the first node.

[0043] In the shutdown stage, the residual charge release circuit provides the first reference signal of the first reference signal end to the driving signal output end in response to the signal of the discharge signal end, and the level of the first reference signal is the same as that of the gate driving signal.

[0044] The disclosure has the following advantages:

[0045] The shift register, the driving method thereof, the gate driving circuit and the display device provided by the disclosure comprise an input circuit configured to provide the signal of the input signal end to the first node in response to the signal of the input signal end; a driving output circuit configured to provide the signal of the clock signal end as the gate driving signal to the driving signal output end in response to at least the signal of the first node; and a residual charge release circuit configured to provide the first reference signal of the first reference signal end to the driving signal output end in response to the signal of the discharge signal end, and the level of the first reference signal is the same as that of the gate driving signal. In each frame of display time, the input circuit and the output circuit cooperate with each other to provide the gate driving signal to the driving signal output end, so that the gate driving signal is transmitted to the transistor in the display area through the gate line, the transistor is opened under the control of the gate driving signal to charge the pixel, and the picture display is realized. By adding the residual charge release circuit, the first reference signal with the same level as the gate driving signal can be provided to the driving signal output end at the shutdown moment, so that the first reference signal is transmitted to the transistor in the display area through the gate line, the transistor is opened under the control of the first reference signal, and the residual charge in the transistor is fully released. Therefore, abnormal display caused by residual charge can be avoided when picture display is needed. BRIEF DESCRIPTION OF DRAWINGS

[0046] Figure 1 The structural schematic diagram of the display device provided by the disclosure is shown;

[0047] Figure 2 The structural schematic diagram of the shift register provided by the disclosure is shown;

[0048] Figure 3 The comparison schematic diagram of the level curve of the driving signal output end before and after the reliability operation provided by the disclosure is shown;

[0049] Figure 4 A level curve comparison diagram of the driving signal output end before and after the reliability operation in the related art is shown;

[0050] Figure 5 A specific structure diagram of a shift register provided by the embodiment of the present disclosure is shown;

[0051] Figure 6 Another specific structure diagram of a shift register provided by the embodiment of the present disclosure is shown;

[0052] Figure 7 Another specific structure diagram of a shift register provided by the embodiment of the present disclosure is shown;

[0053] Figure 8 Another specific structure diagram of a shift register provided by the embodiment of the present disclosure is shown;

[0054] Figure 9 Another specific structure diagram of a shift register provided by the embodiment of the present disclosure is shown;

[0055] Figure 10 Another specific structure diagram of a shift register provided by the embodiment of the present disclosure is shown;

[0056] Figure 11 Another specific structure diagram of a shift register provided by the embodiment of the present disclosure is shown;

[0057] Figure 12 Another specific structure diagram of a shift register provided by the embodiment of the present disclosure is shown;

[0058] Figure 13 A signal timing diagram provided by the embodiment of the present disclosure is shown;

[0059] Figure 14 A work flow diagram of a shift register provided by the embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0060] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. It should be noted that the sizes and shapes of the figures in the drawings do not reflect the true proportions, and the purpose is only to illustrate the present disclosure. And the same or similar reference numbers represent the same or similar elements or elements with the same or similar functions throughout. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits the detailed description of known functions and known components.

[0061] Unless otherwise defined, technical terms or scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first", "second", and similar terms do not imply any order, quantity, or importance, but are used to distinguish one element from another, and are used arbitrarily. The terms "comprises", "comprising", "includes", "including" and the like can mean the inclusion of a stated element or item but not the exclusion of any other element or item. The terms "inner", "outer", "up", "down", and the like are used only to indicate relative positional relationships, and can change accordingly when the absolute positions of the described objects change.

[0062] As shown in Figure 1 The display device can include a plurality of arrayed pixels, a plurality of gate lines (e.g., G1, G2, G3, G4, etc.), a plurality of data lines (e.g., D1, D2, D3, etc.), and a gate drive circuit (GOA) composed of a plurality of cascade arranged shift registers. Each pixel includes a plurality of sub-pixels SPX, a column of sub-pixels SPX corresponds to a data line, a row of pixels corresponds to a gate line, and a plurality of shift registers are coupled one-to-one with each gate line. In some embodiments, the pixel can include a red sub-pixel, a green sub-pixel, and a blue sub-pixel, so that color mixing can be performed by red, green, and blue to achieve color display. Alternatively, the pixel can include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, so that color mixing can be performed by red, green, blue, and white to achieve color display. Of course, in actual applications, the light-emitting colors of the sub-pixels in the pixel can be designed and determined according to the actual application environment, which is not limited herein.

[0063] However, the display device in the related art cannot provide sufficient voltage to open the transistors of the display area for residual charge release in the shutdown stage after the reliability test, so that residual images caused by residual charges are easily generated, especially abnormal color of solid color images, accompanied by horizontal line defects.

[0064] To solve the above technical problems existing in the related art, the embodiments of the present disclosure provide a shift register, as shown in Figure 2 The shift register includes:

[0065] The input circuit 101 is configured to provide the signal of the input signal end In to the first node Pu in response to the signal of the input signal end In;

[0066] The drive output circuit 102 is at least configured to provide the signal of the clock signal end Clk as a gate drive signal to the drive signal output end Gout in response to the signal of the first node Pu;

[0067] The residual charge release circuit 103 is configured to provide the first reference signal of the first reference signal terminal Ref1 to the driving signal output terminal Gout in response to the signal of the discharging signal terminal V, and the level of the first reference signal is the same as the level of the gate driving signal.

[0068] In the above shift register provided by the embodiments of the present disclosure, during each frame display time, the input circuit 101 and the driving output circuit 102 cooperate to provide the gate driving signal to the driving signal output terminal Gout, so that the gate driving signal is transmitted to the transistor in the display area (AA) through the gate line, and the transistor is opened to charge the pixel under the control of the gate driving signal, so as to realize the picture display. By adding the residual charge release circuit 103, the first reference signal with the same level as the gate driving signal can be provided to the driving signal output terminal Gout at the moment of power-off, so that the first reference signal is transmitted to the transistor in the display area through the gate line, and the transistor is opened under the control of the first reference signal, and the residual charge in the transistor is fully released, so that abnormal display caused by residual charge will not occur when picture display is needed.

[0069] Figure 3 The level curve comparison diagram of the driving signal output terminal before and after the reliability operation provided by the embodiments of the present disclosure is shown in FIG. 5. Figure 4 The level curve comparison diagram of the driving signal output terminal before and after the reliability operation in the related art is shown in FIG. 6. Figure 3 and Figure 4 The solid line in FIGS. 5 and 6 represents the level curve of the driving signal output terminal before the reliability operation, and the dashed line represents the level curve of the driving signal output terminal after the reliability operation. Figure 3 and Figure 4 As can be seen from FIGS. 5 and 6, after the reliability operation, the level of the driving signal terminal in the present disclosure is about 17v, which is only decreased by 3v, i.e. only decreased by 6%, compared with 20v before the reliability operation; the level of the driving signal terminal in the related art is about 9v after the reliability operation, which is decreased by 11v, i.e. decreased by 55%, compared with 20v before the reliability operation. Therefore, the present disclosure has less impact on the level of the driving signal output terminal compared with the related art, which is beneficial to provide sufficient voltage to open the transistor in the display area, so as to fully release the residual charge.

[0070] In some embodiments, in the above shift register provided by the embodiments of the present disclosure, as shown in FIG. 7, the residual charge release circuit 103 is configured to provide the first reference signal of the first reference signal terminal Ref1 to the driving signal output terminal Gout in response to the signal of the discharging signal terminal V, and the level of the first reference signal is the same as the level of the gate driving signal. Figures 5 to 12As shown, the discharge signal terminal V includes at least one sub-discharge signal terminal (e.g., V_1, V_2, etc.), and the residual charge release circuit 103 includes sub-discharge circuits (e.g., 103_1, 103_2, etc.) corresponding one-to-one with the sub-discharge signal terminals (e.g., V_1, V_2, etc.). The sub-discharge circuits (e.g., 103_1, 103_2, etc.) are configured to provide a first reference signal to the drive signal output terminal Gout in response to the signal of the corresponding sub-discharge signal terminal (e.g., V_1, V_2, etc.).

[0071] When there are multiple sub-discharge signal terminals (e.g., V_1, V_2, etc.), each sub-discharge signal terminal (e.g., V_1, V_2, etc.) can control each sub-discharge circuit (e.g., 103_1, 103_2, etc.) to work simultaneously. This allows the first reference signal to be provided to the drive signal output terminal Gout under the multiple actions of each sub-discharge circuit (e.g., 103_1, 103_2, etc.), effectively ensuring the level of the drive signal output terminal Gout, thus facilitating the full release of residual charge. Furthermore, since more sub-discharge circuits (e.g., 103_1, 103_2, etc.) require more space, which is not conducive to achieving a narrow bezel design, this disclosure can provide one or two sub-discharge circuits (e.g., 103_1 and / or 103_2) to balance the residual charge release effect and narrow bezel design.

[0072] In some embodiments, in the shift registers provided in the present disclosure, such as Figures 5 to 12 As shown, each sub-discharge circuit (e.g., 103_1 or 103_2, etc.) includes: a first transistor M1, the gate of which is coupled to a corresponding sub-discharge signal terminal (e.g., V_1 or V_2, etc.), the first terminal of which is coupled to a first reference signal terminal Ref1, and the second terminal of which is coupled to a drive signal output terminal Gout. In a specific implementation, the first transistor M1 is in a conducting state in response to the signal at the corresponding sub-discharge signal terminal (e.g., V_1 or V_2, etc.), and the first reference signal at the first reference signal terminal Ref1 is provided to the drive signal output terminal Gout via the conducting first transistor M1.

[0073] In some embodiments, in the display device provided in the present disclosure, such as Figure 6 , Figure 8 , Figure 11 and Figure 12As shown, at least part of the sub-discharge circuit (e.g. 103_1, 103_2, etc.) can further include, in addition to the first transistor M1, a first capacitor C1, which is coupled between the gate of the first transistor M1 and the first reference signal end Ref1 in the same sub-discharge circuit (e.g. 103_1 or 103_2, etc.). In a specific implementation, the bootstrap function of the first capacitor C1 makes the gate voltage of the first transistor M1 further increase by, for example, 1.5 times of the first reference signal, which is beneficial to the first reference signal being provided to the drive signal output end Gout more quickly at the instant of shutdown, so as to increase the release time length of the residual charge and ensure that the residual charge is released more fully.

[0074] The above is only an example of the specific structure of the sub-discharge circuit (e.g. 103_1, 103_2, etc.) provided by the embodiments of the present disclosure, and in a specific implementation, the specific structure of the sub-discharge circuit (e.g. 103_1, 103_2, etc.) is not limited to the above structure provided by the embodiments of the present disclosure, but can also be other structures known to those skilled in the art, which are not limited herein.

[0075] In some embodiments, in the above shift register provided by the embodiments of the present disclosure, as Figure 2 , Figures 5 to 12As shown, the reset circuit 104 can also be configured to provide a signal of the second reference signal terminal Ref2 to the first node Pu in response to a signal of the initial reset signal terminal TRst. Optionally, the number of signal terminals can be reduced to simplify the circuit design. For example, all the sub-discharge signal terminals (e.g., V_1 and / or V_2, etc.) can be multiplexed with the first reference signal terminal Ref1; or all the sub-discharge signal terminals (e.g., V_1 and / or V_2, etc.) can be multiplexed with the initial reset signal terminal TRst; or in the case where the number of sub-discharge signal terminals is more than one, some of the sub-discharge signal terminals (e.g., V_1) can be multiplexed with the initial reset signal terminal TRst, and the rest of the sub-discharge signal terminals (e.g., V_1) can be multiplexed with the first reference signal terminal Ref1; or some of the sub-discharge signal terminals (e.g., V_1 and / or V_2, etc.) can be multiplexed with the initial reset signal terminal TRst and / or the first reference signal terminal Ref1, and the rest of the sub-discharge signal terminals (not shown in the figure) can be independently provided with the initial reset signal terminal TRst and the first reference signal terminal Ref1. Of course, in some embodiments, all the sub-discharge signal terminals (e.g., V_1, V_2, etc.) can be independently provided with the initial reset signal terminal TRst and the first reference signal terminal Ref1, in which case, the chip (IC) can be configured to load a signal to each of the sub-discharge signal terminals (e.g., V_1, V_2, etc.) or configured to leave each of the sub-discharge signal terminals (e.g., V_1, V_2, etc.) in a floating state without loading any signal.

[0076] In addition, in the pre-frame phase and the post-frame phase of each frame display time t, the initial reset signal terminal TRst can output a signal having the same level as that in the power-off phase. Therefore, in the pre-frame phase and the post-frame phase, the sub-discharge circuits (e.g., 103_1, 103_2, etc.) corresponding to the sub-discharge signal terminals (e.g., V_1, V_2, etc.) multiplexed with the initial reset signal terminal TRst are also in the on state. Thus, the drive signal output terminal Gout can be discharged by the sub-discharge circuits (e.g., 103_1, 103_2, etc.) to prevent the residual charge of the drive signal output terminal Gout from affecting the normal display of the display area.

[0077] In some embodiments, in the shift register provided in the embodiments of the present disclosure, as described above, Figure 2 Figures 5 to 12 ​As shown, the reset circuit 104 is further configured to provide the signal of the second reference signal terminal Ref2 to the first node Pu and provide the second reference signal of the first reference signal terminal Ref1 to the driving signal output terminal Gout in response to the signal of the reset signal terminal Rst, and the level of the signal of the second reference signal terminal Ref2 is opposite to the level of the first reference signal. In this way, the first node Pu and the driving signal output terminal Gout can be reset by the reset circuit 104, and the noise of the first node Pu and the driving signal output terminal Gout can be reduced.

[0078] In some embodiments, in the shift register provided by the embodiments of the present disclosure, as shown in Figures 5 to 12 As shown, the reset circuit 104 includes a second transistor M2, a third transistor M3 and a fourth transistor M4, wherein the gate of the second transistor M2 is coupled with the initial reset signal terminal TRst, the first electrode of the second transistor M2 is coupled with the second reference signal terminal Ref2, and the second electrode of the second transistor M2 is coupled with the first node Pu; the gate of the third transistor M3 is coupled with the reset signal terminal Rst, the first electrode of the third transistor M3 is coupled with the second reference signal terminal Ref2, and the second electrode of the third transistor M3 is coupled with the first node Pu; the gate of the fourth transistor M4 is coupled with the reset signal terminal Rst, the first electrode of the fourth transistor M4 is coupled with the first reference signal terminal Ref1, and the second electrode of the fourth transistor M4 is coupled with the driving signal output terminal Gout.

[0079] In specific implementation, the second transistor M2 is in a conductive state in response to the signal of the initial reset signal terminal TRst, so that the signal of the second reference signal terminal Ref2 is provided to the first node Pu through the conductive second transistor M2; the third transistor M3 is in a conductive state in response to the signal of the reset signal terminal Rst, so that the signal of the second reference signal terminal Ref2 is provided to the first node Pu through the conductive third transistor M3; and the fourth transistor M4 is in a conductive state in response to the signal of the reset signal terminal Rst, so that the second reference signal of the first reference signal terminal Ref1 is provided to the driving signal output terminal Gout through the conductive fourth transistor M4.

[0080] The above is only an example of the specific structure of the reset circuit 104 provided by the embodiments of the present disclosure, and in specific implementation, the specific structure of the reset circuit 104 is not limited to the above structure provided by the embodiments of the present disclosure, but can also be other structures known to those skilled in the art, which are not limited herein.

[0081] In some embodiments, in the shift register provided by the embodiments of the present disclosure, as shown in Figures 2 to 10As shown, the driving output circuit 102 can further include at least one control circuit (e.g., 105_1, 105_2, etc.); the control circuit (e.g., 105_1, 105_2, etc.) is configured to control the level of the second node (e.g., Pd_1, Pd_2, etc.) and the level of the first node Pu to be opposite in response to the signal of the input signal end In and the signal of the selection signal end (e.g., VN_1, VN_2, etc.), wherein the selection signal end (e.g., VN_1, VN_2, etc.) and the second node (e.g., Pd_1, Pd_2, etc.) each correspond to the control circuit (e.g., 105_1, 105_2, etc.); the driving output circuit 102 is further configured to provide the second reference signal of the first reference signal end Ref1 to the driving signal output end Gout in response to the signal of the second node (e.g., Pd_1, Pd_2, etc.), the level of the second reference signal being opposite to the level of the first reference signal, so as to perform noise reduction on the driving signal output end Gout. Optionally, in the case of multiple control circuits (e.g., 105_1 or 105_2, etc.), each control circuit (e.g., 105_1 or 105_2, etc.) can work alternately at different times to prolong the service life of the control circuit (e.g., 105_1 or 105_2, etc.). In the drawings of the present disclosure, two control circuits (e.g., 105_1 or 105_2) are taken as examples for illustrative description.

[0082] In some embodiments, in the above-described shift register provided by the embodiments of the present disclosure, as shown, each control circuit (e.g., 105_1 or 105_2, etc.) includes: a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8; the gate of the fifth transistor M5 and the first electrode of the fifth transistor M5 are each coupled to the corresponding selection signal end (e.g., VN_1 or VN_2, etc.), and the second electrode of the fifth transistor M5 is coupled to the second electrode of the sixth transistor M6; the gate of the sixth transistor M6 is coupled to the first node Pu, and the first electrode of the sixth transistor M6 is coupled to the second reference signal end Ref2; the gate of the seventh transistor M7 is coupled to the input signal end In, the first electrode of the seventh transistor M7 is coupled to the second reference signal end Ref2, and the second electrode of the seventh transistor M7 is coupled to the corresponding second node (e.g., Pd_1 or Pd_2, etc.); the gate of the eighth transistor M8 is coupled to the corresponding second node (e.g., Pd_1 or Pd_2, etc.), the first electrode of the eighth transistor M8 is coupled to the second reference signal end Ref2, and the second electrode of the eighth transistor M8 is coupled to the first node Pu. Figures 5 to 12

[0083] ​In implementation, each sixth transistor M6 is in a conductive state in response to the signal of the first node Pu, so that the signal of the second reference signal terminal Ref2 is provided to the corresponding second node (e.g., Pd_1, Pd_2, etc.) through the conductive sixth transistor M6; meanwhile, each seventh transistor M7 is in a conductive state in response to the signal of the input signal terminal In, so that the signal of the second reference signal terminal Ref2 is provided to the corresponding second node (e.g., Pd_1, Pd_2, etc.) through the conductive seventh transistor M7; in response to the signal of the corresponding selection signal terminal (e.g., VN_1 or VN_2, etc.), only one of the fifth transistors M5 is in a conductive state to provide the signal of the corresponding selection signal terminal (e.g., VN_1 or VN_2, etc.) to the corresponding second node (e.g., Pd_1 or Pd_2, etc.), but since the sixth transistor M6 and the seventh transistor M7 simultaneously provide the signal of the second reference signal terminal Ref2 to the second node (e.g., Pd_1 or Pd_2, etc.), the level of the second node (e.g., Pd_1 or Pd_2, etc.) is ultimately determined by the signal of the second reference signal terminal Ref2 and is opposite to the level of the first node Pu. Each eighth transistor M8 is in a cut-off state under the control of the second node (e.g., Pd_1, Pd_2, etc.).

[0084] In addition, in response to the signal of the corresponding selection signal terminal (e.g., VN_1 or VN_2, etc.), only one of the fifth transistors M5 is in a conductive state to provide the signal of the corresponding selection signal terminal (e.g., VN_1 or VN_2, etc.) to the corresponding second node (e.g., Pd_1 or Pd_2, etc.), and when the sixth transistor M6 and the seventh transistor M7 are both in a cut-off state, one of the eighth transistors M8 is in a conductive state under the control of the second node (e.g., Pd_1 or Pd_2, etc.), and the signal of the second reference signal terminal Ref2 is provided to the first node Pu through the conductive eighth transistor M8.

[0085] The above is only an example of the specific structure of the control circuit (e.g., 105_1 or 105_2, etc.) provided by the embodiments of the present disclosure, and in implementation, the specific structure of the control circuit (e.g., 105_1 or 105_2, etc.) is not limited to the above structure provided by the embodiments of the present disclosure, but can also be other structures known to those skilled in the art, which are not limited herein.

[0086] In some embodiments, in the above shift register provided by the embodiments of the present disclosure, as shown in Figures 5 to 12 The driving output circuit 102 can include a second capacitor C2, a ninth transistor M9, and a tenth transistor M10 corresponding to each second node (e.g., Pd_1, Pd_2, etc.). 10In this configuration, the second capacitor C2 is coupled between the first node Pu and the drive signal output terminal Gout; the gate of the ninth transistor M9 is coupled to the first node Pu, the first terminal of the ninth transistor M9 is coupled to the clock signal terminal Clk, and the second terminal of the ninth transistor M9 is coupled to the drive signal output terminal Gout; the tenth transistor M... 10 The gate of the tenth transistor M is coupled to the corresponding second node (e.g., Pd_1, Pd_2, etc.). 10 The first terminal is coupled to the first reference signal terminal Ref1, and the tenth transistor M 10 The second pole is coupled to the drive signal output terminal Gout.

[0087] In practical implementation, the ninth transistor M9 is turned on in response to the signal from the first node Pu, so that the clock signal Clk is provided to the drive signal output Gout through the turned-on ninth transistor M9. During this process, the bootstrap effect of the second capacitor C2 can maintain the level of the first node Pu. In response to the signals of the corresponding second nodes (e.g., Pd_1, Pd_2, etc.), each tenth transistor M... 10 Only one of them is in the conducting state, so that the first reference signal or the second reference signal at the first reference signal terminal Ref1 is passed through the conducting tenth transistor M. 10 Provided to the drive signal output terminal Gout.

[0088] Combination Figures 5 to 13 As can be seen, during the power-off phase T, the first reference signal at the first reference signal terminal Ref1 passes through the tenth transistor M which is turned on. 10 The first transistor M1 provides a driving signal output terminal Gout. Compared to providing a first reference signal to the driving signal output terminal Gout solely through the first transistor M1, this can better release residual charge in the display area, further improving display quality. Furthermore, it should be understood that each tenth transistor M... 10 The second node (e.g., Pd_1, Pd_2, etc.) alternately conducts, therefore, the tenth transistor M 10 The more transistors there are, the more each tenth transistor M can achieve in one frame. 10 The shorter the conduction time, the better it is to maintain the tenth transistor M 10 The stability characteristics reduce the M value of the tenth transistor. 10 The risk of curve characteristic drift. However, more tenth transistors M... 10 It is not conducive to narrow bezel design, therefore, in order to accommodate the tenth transistor M 10 To achieve stable performance and a narrow bezel, this disclosure allows for the inclusion of two or three tenth transistors M. 10 .

[0089] The above is only an example of the specific structure of the driving output circuit 102 provided by the embodiments of the present disclosure, and in specific implementation, the specific structure of the driving output circuit 102 is not limited to the above structure provided by the embodiments of the present disclosure, but can also be other structures known to those skilled in the art, which are not limited herein.

[0090] In some embodiments, in the above shift register provided by the embodiments of the present disclosure, as shown in Figure 2 , Figures 5 to 12 The cascade output circuit 106 is configured to provide the signal of the clock signal end Clk to the cascade signal output end Cout in response to the signal of the first node Pu, and provide the signal of the second reference signal end Ref2 to the cascade signal output end Cout in response to the signal of the second node (for example, Pd_1, Pd_2, etc.). The cascade output circuit 106 can realize the cascade output of the current stage shift register to the next stage shift register.

[0091] In some embodiments, in the above shift register provided by the embodiments of the present disclosure, as shown in Figures 5 to 12 The cascade output circuit 106 can include an eleventh transistor M 11 and a twelfth transistor M 12 corresponding to each of the second nodes (for example, Pd_1, Pd_2, etc.), wherein the gate of the eleventh transistor M 11 is coupled to the first node Pu, the first electrode of the eleventh transistor M 11 is coupled to the clock signal end Clk, and the second electrode of the eleventh transistor M 11 is coupled to the cascade signal output end Cout; the gate of the twelfth transistor M 12 is coupled to the corresponding second node (for example, Pd_1 or Pd_2, etc.), the first electrode of the twelfth transistor M 12 is coupled to the second reference signal end Ref2, and the second electrode of the twelfth transistor M 12 is coupled to the cascade signal output end Cout.

[0092] In specific implementation, the eleventh transistor M 11 is in a conductive state in response to the signal of the first node Pu, and the signal of the clock signal end Clk is provided to the cascade signal output end Cout through the conductive eleventh transistor M 11 to provide an input signal for the next stage shift register; the twelfth transistor M 12 is in a conductive state in response to the signal of the corresponding second node (for example, Pd_1 or Pd_2, etc.), and the signal of the second reference signal end Ref2 is provided to the cascade signal output end Cout through the conductive twelfth transistor M 12 to perform noise reduction on the cascade signal output end Cout.

[0093] The above is merely an example illustrating the specific structure of the cascaded output circuit 106 provided in the embodiments of this disclosure. In specific implementations, the specific structure of the cascaded output circuit 106 is not limited to the structure provided in the embodiments of this disclosure, and may also be other structures known to those skilled in the art, which are not limited here.

[0094] In some embodiments, in the shift registers provided in the present disclosure, such as Figures 5 to 12 As shown, the input circuit 101 includes a thirteenth transistor M. 13 The thirteenth transistor M 13 The gate of the thirteenth transistor M 13 The first electrode of each transistor is coupled to the input signal terminal In. The thirteenth transistor M 13 The second terminal is coupled to the first node Pu. In a specific implementation, the thirteenth transistor M... 13 In response to the signal at the input signal terminal In being in the on state, the signal at the input signal terminal In passes through the on-state thirteenth transistor M. 13 Provided to the first node, Pu.

[0095] The above is merely an example illustrating the specific structure of the input circuit 101 provided in the embodiments of this disclosure. In specific implementations, the specific structure of the input circuit 101 is not limited to the structure provided in the embodiments of this disclosure, and may also be other structures known to those skilled in the art, which are not limited here.

[0096] To reduce the manufacturing process complexity, in the shift register provided in this embodiment, all transistors can be configured as N-type transistors. N-type transistors are turned on by a high-level signal (VGH) and turned off by a low-level signal (VGL). Correspondingly, the first reference signal at the first reference signal terminal Ref1 can be a DC high-level signal (VGH), the second reference signal at the first reference signal terminal Ref1 can be a DC low-level signal (VGL), and the signal at the second reference signal terminal Ref2 can be a DC low-level signal (VGL). In some embodiments, the signal at the second reference signal terminal Ref2 can be less than the second reference signal, which helps to ensure that the transistors in the display area are turned off as completely as possible.

[0097] Of course, in some embodiments, all the transistors provided by the present disclosure can also be P-type transistors, which are turned off under the action of a high-level signal (VGH) and turned on under the action of a low-level signal (VGL). Correspondingly, the first reference signal of the first reference signal terminal Ref1 can be a direct-current low-level signal (VGL), the second reference signal of the first reference signal terminal Ref1 can be a direct-current high-level signal (VGH), and the signal of the second reference signal terminal Ref2 can be a direct-current high-level signal (VGH). In some embodiments, the signal of the second reference signal terminal Ref2 can be greater than the second reference signal, so as to facilitate the transistors in the display area to be turned off as completely as possible.

[0098] It should be noted that the above-mentioned transistors provided by the embodiments of the present disclosure can be thin film transistors (TFTs) or metal oxide semiconductor field effect transistors (MOSs), which are not limited herein. In specific implementation, the gate of the above-mentioned transistor can be a gate, the first pole can be a source, and the second pole can be a drain, or the first pole can be a drain, and the second pole can be a source.

[0099] In specific implementation, taking two selection signal terminals (for example, VN_1 and VN_2) as an example, the signals of the two selection signal terminals (for example, VN_1 and VN_2) can be high-level and low-level switching pulse signals respectively, and the levels of the two selection signal terminals (for example, VN_1 and VN_2) are opposite. In some embodiments, the signals of the two selection signal terminals (for example, VN_1 and VN_2) can also be direct-current signals respectively, and when one of the selection signal terminals is loaded with a high-level direct-current signal, the other selection signal terminal is not loaded with a signal or is loaded with a low-level direct-current signal.

[0100] Next, taking the structure of the shift register shown in Figure 5 as an example, and combining the signal timing diagram shown in Figure 13 , the working process of the above-mentioned shift register provided by the embodiments of the present disclosure is described in detail. In the following description, 1 represents a high-level signal and 0 represents a low-level signal, wherein 1 and 0 represent the logic levels thereof, which are only used to better explain the working process of the above-mentioned shift register provided by the embodiments of the present disclosure, and are not the potentials applied to the gates of the transistors in specific implementation. Specifically, taking the display time t and the shutdown stage T in the working timing diagram shown in Figure 13 as an example, the working process is described in detail. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits the description of the transistors in the off state in each stage.

[0101] In some embodiments, each frame display time t can include a reset phase, an input phase, an output phase and a reset phase.

[0102] In the reset phase, In=0, Clk=0, TRst=1, Rst=0, VN_1=1, VN_2=0, Ref1=0, Ref2=0.

[0103] The first transistor M1 is in a conductive state in response to a high level signal of the initial reset signal end TRst, and provides a low level signal of the first reference signal end Ref1 to the driving signal output end, so as to reset the driving signal output end. The second transistor M2 is in a conductive state in response to a high level signal of the initial reset signal end TRst, and provides a low level signal of the first signal end VGL to the first node Pu through the conductive second transistor M2, so as to reset the pull-up node Pu. A fifth transistor M5 is in a conductive state in response to a high level signal of the selection signal end (for example, VN_1), and provides a high level signal of the corresponding selection signal end (for example, VN_1) to the corresponding second node (for example, Pd_1), so as to control the corresponding eighth transistor M8 to be in a conductive state. A low level signal of the second reference signal end Ref2 is provided to the first node Pu through the conductive eighth transistor M8, so as to reset the first node Pu.

[0104] In the input phase, In=1, Clk=0, TRst=0, Rst=0, VN_1=1, VN_2=0, Ref1=0, Ref2=0.

[0105] The thirteenth transistor M 13 In response to the high level signal of the input signal end In being in a conductive state, the high level signal of the input signal end In is provided to the first node Pu through the conductive thirteenth transistor M 13The first node Pu is provided with a high level signal, and each sixth transistor M6 is in a conductive state in response to the high level signal of the first node Pu, so that the low level signal of the second reference signal end Ref2 is provided to the corresponding second node (for example, Pd_1, Pd_2, etc.) through the conductive sixth transistor M6; meanwhile, each seventh transistor M7 is in a conductive state in response to the high level signal of the input signal end In, so that the low level signal of the second reference signal end Ref2 is provided to the corresponding second node (for example, Pd_1, Pd_2, etc.) through the conductive seventh transistor M7; in response to the high level signal of the corresponding selection signal end (for example, VN_1), the corresponding fifth transistor M5 is in a conductive state, and the high level signal of the selection signal end (for example, VN_1) is provided to the corresponding second node (for example, Pd_1, etc.), but because the sixth transistor M6 and the seventh transistor M7 provide the low level signal of the second reference signal end Ref2 to the second node (for example, Pd_1, Pd_2, etc.), therefore, the level of the second node (for example, Pd_1, Pd_2, etc.) ultimately depends on the low level signal of the second reference signal end Ref2.

[0106] In the output phase, In = 0, Clk = 1, TRst = 0, Rst = 0, VN_1 = 1, VN_2 = 0, Ref1 = 0, and Ref2 = 0.

[0107] The ninth transistor M9 is in a conductive state in response to the high level signal of the first node Pu, so that the high level signal of the clock signal end Clk is provided to the driving signal output end Gout through the conductive ninth transistor M9 as the gate driving signal of the corresponding gate line of the current stage shift register, and in this process, the bootstrap function of the second capacitor C2 can maintain the high level of the first node Pu. The eleventh transistor M 11 The high level signal of the clock signal end Clk is provided to the driving signal output end Gout through the conductive eleventh transistor M 11 The high level signal of the clock signal end Clk is provided to the driving signal output end Gout through the conductive eleventh transistor M

[0108] In the reset phase, In = 0, TRst = 0, Rst = 1, Ref1 = 0, Ref2 = 0, the two selection signal ends (for example, VN_1 and VN_2) are alternately 1, and Clk is alternately 1 and 0.

[0109] The third transistor M3 is in a conductive state in response to a high level signal of the reset signal end Rst, and a low level signal of the first signal end VGL is provided to the first node Pu through the conductive third transistor M3. In response to a high level signal of the selection signal end (for example, VN_1 or VN_2), a fifth transistor M5 is in a conductive state, and a high level signal of the corresponding selection signal end (for example, VN_1 or VN_2) is provided to the corresponding second node (for example, Pd_1 or Pd_2), to control the corresponding eighth transistor M8 to be in a conductive state, and a low level signal of the second reference signal end Ref2 is provided to the first node Pu through the conductive eighth transistor M8; at the same time, the corresponding tenth transistor M 10 is controlled to be in a conductive state, and a low level signal of the second reference signal end Ref2 is provided to the driving signal output end Gout through the conductive tenth transistor M 10 . In addition, the corresponding twelfth transistor M 12 is controlled to be in a conductive state, and a low level signal of the second reference signal end Ref2 is provided to the cascade signal output end Cout through the conductive twelfth transistor M 12 . The fourth transistor M4 is in a conductive state in response to a high level signal of the reset signal end Rst, and a low level signal of the first reference signal end Ref1 is provided to the driving signal output end Gout through the conductive fourth transistor M4.

[0110] In the shutdown stage T, In=1, Clk=1, TRst=1, Rst=0, Ref1=1, Ref2=0, VN_1=1, and VN_2=1.

[0111] The first transistor M1 is in a conductive state in response to a high level signal of the sub-discharge signal end (for example, V_1, which is multiplexed with the initial reset signal end TRst), and a high level signal of the first reference signal end Ref1 is provided to the driving signal output end Gout through the conductive first transistor M1, to control the transistors in the display area to be turned on and release the residual charge. The thirteenth transistor M 13 is in a conductive state in response to a high level signal of the input signal end In, and the high level signal of the input signal end In is provided to the first node Pu through the conductive thirteenth transistor M 13The first node Pu is provided with the low-level signal of the first signal terminal VGL, but the second transistor M2 is in the conductive state in response to the high-level signal of the initial reset signal terminal TRst, the low-level signal of the first signal terminal VGL is provided to the first node Pu through the conductive second transistor M2, so that the first node Pu cannot be at a high potential. In response to the high-level signal of the input signal terminal In and the selection signal terminal (for example, VN_1, VN_2), each fifth transistor M5 is in the conductive state, and the high-level signal of the corresponding selection signal terminal (for example, VN_1, VN_2) is provided to the corresponding second node (for example, Pd_1, Pd_2, etc.), but each seventh transistor M7 is in the conductive state in response to the high-level signal of the input signal terminal In, so that the low-level signal of the second reference signal terminal Ref2 is provided to the corresponding second node (for example, Pd_1, Pd_2, etc.) through the conductive seventh transistor M7, so that the second node (for example, Pd_1, Pd_2, etc.) cannot be at a high potential.

[0112] It should be noted that after the shutdown stage T, the input signal terminal In, the clock signal terminal Clk, the initial reset signal terminal TRst, the reset signal terminal Rst, the first reference signal terminal Ref1, the second reference signal terminal Ref2, and the selection signal terminal (for example, VN_1, VN_2, etc.) remain as the ground signal GND.

[0113] As can be seen from the above description, the sub-discharge signal terminal (for example, V_1) multiplexed with the initial reset signal terminal TRst is a low-level signal in the input stage, the output stage, and the reset stage, and the first transistor M1 is in the cut-off state, so the first transistor M1 will not affect the display quality. In addition, in the reset stage, the initial reset signal terminal TRst is a high-level signal, and the first transistor M1 is in the conductive state, which can reduce the noise of the driving output signal terminal Gout, thereby improving the display quality. In addition, since the gate potential of the first transistor M1 is a low-level signal for most of the time of each frame display time t, the characteristic curve of the first transistor M1 is not prone to drift, thereby the threshold voltage (V th ) of the first transistor M1 can be maintained, and the problem that the threshold voltage of the first transistor M1 increases and cannot provide sufficient potential for the driving signal output terminal Gout, which may affect the release of residual charges in the display area, is solved.

[0114] In some embodiments, the present disclosure also provides Figures 6 to 12 The working process of the shift register is shown in the description below, and only the Figures 6 to 12 The working process of the shift register shown in Figure 5 The differences between the working processes of the shift registers shown in

[0115] For example, in Figure 6 , Figure 11 and Figure 12In the first transistor M1 is in the on state in response to the signal of the initialization signal end TRst, the first capacitor C1 coupled between the gate and the first electrode of the first transistor M1 can increase the gate potential of the first transistor M1 due to the bootstrap effect, so that the first transistor M1 opens more fully.

[0116] In Figure 7 , Figure 8 and Figure 10 , the sub-discharge signal end (for example, V_1 or V_2) can be provided with a signal or not loaded with a signal by the chip alone, and in order not to affect the display, the signal of the sub-discharge signal end (for example, V_1 or V_2) needs to be less than the low-level signal of the first reference signal end Ref1 within each frame time t.

[0117] In addition, in Figure 8 and Figure 11 , a first capacitor C1 is coupled between the gate and the first electrode of the first transistor M1 corresponding to the sub-discharge signal end (for example, V_1 or V_2) provided with a signal by the chip alone. When the first transistor M1 is in the on state, the gate potential of the first transistor M1 can be increased due to the bootstrap effect of the first capacitor C1, so that the first transistor M1 opens more fully.

[0118] In Figure 9 and Figure 12 , the sub-discharge signal end (for example, V_1 or V_2) is multiplexed with the first reference signal end Ref1, so that the corresponding first transistor M1 can provide the first reference signal of the first reference signal end Ref1 to the driving signal output end Gout in response to the first reference signal end Ref1 being in the on state in the shutdown stage T, and release the residual charge of the display area; and because the first reference signal end Ref1 always outputs a low-level signal within each frame display time t, the first transistor M1 is in the off state within each frame display time t, and does not affect the display effect.

[0119] Based on the same inventive concept, the disclosure also provides a driving method of the shift register, as shown in Figure 14 , comprising the following steps:

[0120] S1401, input stage, the input circuit responds to the signal of the input signal end to provide the signal of the input signal end to the first node;

[0121] S1402, output stage, the cascaded output circuit at least responds to the signal of the first node to provide the signal of the clock signal end as the gate driving signal to the driving signal output end;

[0122] S1403, in the shutdown stage, the residual charge release circuit provides the first reference signal of the first reference signal terminal to the driving signal output terminal in response to the signal of the discharge signal terminal, and the level of the first reference signal is the same as the level of the gate driving signal.

[0123] Based on the same inventive concept, the embodiment of the present disclosure provides a gate driving circuit, comprising: a plurality of shift registers cascaded;

[0124] The input signal terminal of the first shift register is coupled with the frame trigger signal terminal;

[0125] In addition to the first shift register, the input signal terminals of the remaining shift registers are respectively coupled with the cascaded signal output terminals of the adjacent upper shift registers;

[0126] The driving signal output terminals of the shift registers are connected with the gate lines of the corresponding rows.

[0127] In some embodiments, to simplify the circuit design, the structure of the shift registers in the gate driving circuit provided by the present disclosure is the same, and the connection relationship of the shift registers with the signal terminals is also the same, which can be referred to the above content, and the repeated parts will not be described here.

[0128] In some embodiments, in the gate driving circuit provided by the embodiment of the present disclosure, four clock signal lines can be used to provide clock signals for the gate driving circuit, and optionally, k is a positive integer, the clock signal terminals Clk of the (4k-3)th shift register unit are electrically connected with the first clock signal line clk1, the clock signal terminals Clk of the (4k-2)th shift register unit are electrically connected with the second clock signal line clk2, the clock signal terminals Clk of the (4k-1)th shift register unit are electrically connected with the third clock signal line clk3, and the clock signal terminals Clk of the 4kth shift register unit are electrically connected with the fourth clock signal line clk4. Optionally, the clock signal provided by the first clock signal line clk1, the clock signal provided by the second clock signal line clk2, the clock signal provided by the third clock signal line clk3, and the clock signal provided by the fourth clock signal line clk4 can be sequentially different by 1 / 2 phase.

[0129] In some embodiments, in the gate driving circuit provided by the embodiment of the present disclosure, the first reference signal terminals Ref1 of each shift register are electrically connected with the same first reference line, the second reference signal terminals Ref2 of each shift register are electrically connected with the same second reference line, and the initial reset signal terminals TRst of each shift register are electrically connected with the same initial reset line.

[0130] Based on the same inventive concept, the display device provided by the embodiments of the present disclosure also includes the above-mentioned gate drive circuit. In some embodiments, the display device can be any product or component with display function, such as mobile phone, tablet computer, television, display, notebook computer, digital photo frame, navigator, smart watch, fitness wristband, personal digital assistant, etc. The display device includes but is not limited to the following components: radio frequency unit, network module, audio output & input unit, sensor, display unit, user input unit, interface unit, memory, processor, power supply, etc. In addition, those skilled in the art can understand that the above structure does not constitute a limitation on the above-mentioned display device provided by the embodiments of the present disclosure, in other words, the above-mentioned display device provided by the embodiments of the present disclosure can include more or less components, or combine certain components, or different component arrangements. Although the present disclosure has described the preferred embodiments, it should be understood that those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if these modifications and variations of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalent technologies, the present disclosure also intends to include these modifications and variations.

Claims

1. A shift register, characterized by, The input circuit is configured to provide a signal of an input signal terminal to a first node in response to a signal of the input signal terminal; The driving output circuit is configured to provide a signal of a clock signal terminal to a driving signal output terminal as a gate driving signal in response to a signal of the first node; The residual charge release circuit is configured to provide a first reference signal of a first reference signal terminal to the driving signal output terminal in response to a signal of a discharge signal terminal, a level of the first reference signal being the same as a level of the gate driving signal; The discharge signal terminal includes at least one sub-discharge signal terminal, and the residual charge release circuit includes a sub-discharge circuit corresponding to each sub-discharge signal terminal, the sub-discharge circuit being configured to provide the first reference signal to the driving signal output terminal in response to a signal of the corresponding sub-discharge signal terminal; The shift register further includes a reset circuit configured to provide a signal of a second reference signal terminal to the first node in response to a signal of an initial reset signal terminal; At least part of the sub-discharge signal terminals are multiplexed with the initial reset signal terminal and / or the first reference signal terminal, or all of the sub-discharge signal terminals are independently provided with the initial reset signal terminal and the first reference signal terminal; The reset circuit is further configured to provide a signal of the second reference signal terminal to the first node and to provide a second reference signal of the first reference signal terminal to the driving signal output terminal in response to a signal of a reset signal terminal, a level of the signal of the second reference signal terminal and a level of the second reference signal being opposite to the level of the first reference signal. The sub-discharge circuit includes a first transistor, a gate of the first transistor being coupled to the corresponding sub-discharge signal terminal, a first pole of the first transistor being coupled to the first reference signal terminal, and a second pole of the first transistor being coupled to the driving signal output terminal.

2. The shift register of claim 1, wherein, At least part of the sub-discharge circuits further include a first capacitor, the first capacitor being coupled between the gate of the first transistor and the first reference signal terminal in the same sub-discharge circuit.

3. The shift register of claim 2, wherein, The reset circuit includes a second transistor, a third transistor, and a fourth transistor, wherein 4. The shift register of claim 1, wherein, A gate of the second transistor is coupled to the initial reset signal terminal, a first pole of the second transistor is coupled to the second reference signal terminal, and a second pole of the second transistor is coupled to the first node; A gate of the third transistor is coupled to the reset signal terminal, a first pole of the third transistor is coupled to the second reference signal terminal, and a second pole of the third transistor is coupled to the first node; A gate of the fourth transistor is coupled to the reset signal terminal, a first pole of the fourth transistor is coupled to the first reference signal terminal, and a second pole of the fourth transistor is coupled to the driving signal output terminal. Further including at least one control circuit; 5. The shift register according to any one of claims 1 to 4, wherein ​ The control circuit is configured to control the level of the second node and the level of the first node to be opposite in response to the signal of the input signal end and the signal of the selection signal end, wherein the selection signal end and the second node each correspond to the control circuit one by one; The driving output circuit is further configured to provide the second reference signal of the first reference signal end to the driving signal output end in response to the signal of the second node, and the level of the second reference signal is opposite to the level of the first reference signal.

6. The shift register of claim 5, wherein, The control circuit comprises a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor; The gate of the fifth transistor and the first electrode of the fifth transistor are coupled with the corresponding selection signal end, and the second electrode of the fifth transistor is coupled with the second electrode of the sixth transistor; The gate of the sixth transistor is coupled with the first node, and the first electrode of the sixth transistor is coupled with the second reference signal end; The gate of the seventh transistor is coupled with the input signal end, the first electrode of the seventh transistor is coupled with the second reference signal end, and the second electrode of the seventh transistor is coupled with the corresponding second node; The gate of the eighth transistor is coupled with the corresponding second node, the first electrode of the eighth transistor is coupled with the second reference signal end, and the second electrode of the eighth transistor is coupled with the first node.

7. The shift register of claim 5, wherein, The driving output circuit comprises a second capacitor, a ninth transistor, and a tenth transistor corresponding to the second node one by one, wherein The second capacitor is coupled between the first node and the driving signal output end; The gate of the ninth transistor is coupled with the first node, the first electrode of the ninth transistor is coupled with the clock signal end, and the second electrode of the ninth transistor is coupled with the driving signal output end; The gate of the tenth transistor is coupled with the corresponding second node, the first electrode of the tenth transistor is coupled with the first reference signal end, and the second electrode of the tenth transistor is coupled with the driving signal output end.

8. The shift register of claim 5, wherein, The cascade output circuit is further configured to provide the signal of the clock signal end to the cascade signal output end in response to the signal of the first node, and provide the signal of the second reference signal end to the cascade signal output end in response to the signal of the second node.

9. The shift register of claim 8, wherein, The cascade output circuit comprises an eleventh transistor and a twelfth transistor corresponding to the second node one by one, wherein The gate of the eleventh transistor is coupled with the first node, the first electrode of the eleventh transistor is coupled with the clock signal end, and the second electrode of the eleventh transistor is coupled with the cascade signal output end; The gate of the twelfth transistor is coupled with the corresponding second node, the first electrode of the twelfth transistor is coupled with the second reference signal end, and the second electrode of the twelfth transistor is coupled with the cascade signal output end.

10. The shift register according to any one of claims 1 to 4, 6 to 9, wherein The input circuit comprises a thirteenth transistor, the gate of the thirteenth transistor and the first electrode of the thirteenth transistor are coupled with the input signal end, and the second electrode of the thirteenth transistor is coupled with the first node.

11. A gate drive circuit, characterized by comprising: The gate drive circuit comprises: a plurality of shift registers connected in cascade, each shift register being as claimed in any one of claims 1 to 10; an input signal terminal of a first shift register is coupled to a frame trigger signal terminal; an input signal terminal of each shift register other than the first shift register is coupled to a cascade signal output terminal of a shift register of an immediately preceding stage; a drive signal output terminal of each shift register is connected to a gate line of a corresponding row.

12. A display device, characterized by comprising: The gate drive circuit as claimed in claim 11.

13. A driving method of a shift register as claimed in any one of claims 1 to 10, characterized by, The gate drive circuit comprises: an input stage in which an input circuit provides a signal at a first node in response to a signal at an input signal terminal; an output stage in which a drive output circuit provides a signal at a drive signal output terminal as a gate drive signal in response to a signal at the first node and a signal at a clock signal terminal; a shutdown stage in which a residual charge release circuit provides a first reference signal at the drive signal output terminal in response to a signal at a discharge signal terminal, the first reference signal having a same level as the gate drive signal; wherein the discharge signal terminal comprises at least one sub-discharge signal terminal, and the residual charge release circuit comprises a sub-discharge circuit corresponding to each sub-discharge signal terminal, the sub-discharge circuit being configured to provide the first reference signal at the drive signal output terminal in response to a signal at the corresponding sub-discharge signal terminal; wherein the input stage, a reset circuit provides a signal at the first node in response to a signal at an initial reset signal terminal; at least part of the sub-discharge signal terminals are multiplexed with the initial reset signal terminal and / or the first reference signal terminal, or all of the sub-discharge signal terminals are provided independently of the initial reset signal terminal and the first reference signal terminal; the reset circuit further provides a signal at the first node and a second reference signal at the drive signal output terminal in response to a signal at a reset signal terminal, the signal at the second reference signal terminal having a level opposite to the first reference signal.

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