Gate driving circuit and display panel

Abstract

The present invention provides a gate driving circuit and a display panel. The nth stage shift register circuit of the gate driving circuit includes a light emitting signal generating circuit, a light emitting signal control circuit, a reset signal generating circuit and a reset signal control circuit. The light emitting signal generating circuit has a node to output a light emitting signal to a pixel array. The light emitting signal control circuit and the reset signal generating circuit are coupled to the node. During a first reset phase, the reset signal generating circuit responds to the light emitting signal to generate an enabled reset signal. During a second reset phase, the reset signal control circuit responds to the light emitting signal to disable the reset signal.

Description

Technical Field

[0001] The present invention relates to a gate driving circuit and a display panel, and in particular to a gate driving circuit and a display panel capable of reducing occupied space. Background Art

[0002] Generally speaking, the gate drive circuit in the display panel outputs a light-emitting signal to drive the pixel. At the same time, the light-emitting signal cooperates with the reset signal to make the pixel emit light or not emit light. However, the circuit used to generate the reset signal and the gate drive circuit are currently controlled by different control signals. Therefore, when multiple pixels are set to balance the variable light-emitting efficiency, multiple control circuits are also required to control the reset signal and the light-emitting signal accordingly, which reduces the configurable circuit space of the display panel and is not conducive to the display panel with zero border design. Summary of the invention

[0003] An embodiment of the present invention provides a gate driving circuit, which can increase the circuit space that can be configured on a display panel.

[0004] The gate driving circuit of the embodiment of the present invention has a multi-stage shift register circuit. The n-th stage shift register circuit includes a light emitting signal generating circuit, a light emitting signal control circuit, a reset signal generating circuit and a reset signal control circuit. The light emitting signal generating circuit has a first node to output a light emitting signal to a pixel array. During the period from the first light emitting stage to the second light emitting stage, the light emitting signal generating circuit enables the light emitting signal. The light emitting signal control circuit is coupled to the first node. During the period from the first reset stage to the second reset stage, the light emitting signal control circuit maintains the voltage level of the light emitting signal at a disabled voltage level. The reset signal generating circuit is coupled to the first node. During the first reset stage, the reset signal generating circuit responds to the light emitting signal to generate an enabled reset signal. The reset signal control circuit is coupled to the light emitting signal control circuit and the reset signal generating circuit. During the second reset stage, the reset signal control circuit responds to the light emitting signal to disable the reset signal.

[0005] Another embodiment of the present invention provides a display panel, which includes a pixel array and the gate driving circuit of the above embodiment, and is coupled to the pixel array.

[0006] Based on the above, the gate driving circuit and the display panel of the embodiment of the present invention generate a reset signal according to the light emitting signal. In this way, the circuit for generating the light emitting signal and the circuit for generating the reset signal are integrated together, and the gate driving circuit and the display panel do not need to be provided with a control circuit to generate the reset signal, so as to reduce the circuit space occupied by the gate driving circuit itself and increase the circuit space that can be configured on the display panel.

[0007] In order to make the above features and advantages of the present invention more obvious and easy to understand, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1A is a block diagram of a display panel according to an embodiment of the present invention.

[0009] Figure 1B According to the present invention Figure 1A A block diagram of an n-th stage shift register circuit shown in an embodiment.

[0010] Figure 2 According to the present invention Figure 1B A circuit diagram of an n-th stage shift register circuit shown in an embodiment.

[0011] Figure 3 According to the present invention Figure 2 The operation diagram of the n-th stage shift register circuit shown in the embodiment is shown.

[0012] 4A to 4D According to the present invention Figure 3 The operation diagram of the n-th stage shift register circuit shown in the embodiment is shown.

[0013] Figure 5 is a block diagram of a display panel according to another embodiment of the present invention.

[0014] Description of reference numerals:

[0015] 100, 500: Display panel

[0016] 110, 210: Luminous signal generating circuit

[0017] 120, 220: Light signal control circuit

[0018] 130, 230: Reset signal generating circuit

[0019] 140, 240: Reset signal control circuit

[0020] C1, C2: capacitors

[0021] CK: clock signal

[0022] EM(n+1): post-stage luminous signal

[0023] EM(n-1): Front stage luminous signal

[0024] EM(1), EM(2), EM(n): luminous signal

[0025] GC: Gate drive circuit

[0026] GC_1, GC_2, GC_n: shift register circuit

[0027] ND1, ND2, ND3, ND4: Node

[0028] P(n): first control signal

[0029] P(n+1): The first control signal of the next stage

[0030] P(n-1): The first control signal of the previous stage

[0031] PEM1, PEM2, PRT1, PRT2: Period

[0032] PXL: Pixel Array

[0033] PXL_1, PXL_2: Sub-pixel array

[0034] Q(n): Second control signal

[0035] R: Resistor

[0036] RST(1), RST(2), RST(n): reset signal

[0037] T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13: Transistors

[0038] VGH1, VPH: Disable voltage level

[0039] VGL, VGH: voltage signal

[0040] VGL1, VGL2, VPL: Enable voltage level DETAILED DESCRIPTION

[0041] Some embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. The referenced element symbols in the following description will be regarded as the same or similar elements when the same element symbols appear in different drawings. These embodiments are only part of the present invention and do not disclose all possible implementation methods of the present invention. More specifically, these embodiments are only examples within the scope of the patent application of the present invention.

[0042] Please refer to Figure 1A , Figure 1A1 is a block diagram of a display panel according to an embodiment of the present invention. In this embodiment, the display panel 100 includes a pixel array PXL and a gate driving circuit GC. The gate driving circuit GC has a plurality of shift register circuits GC_1, GC_2, ..., GC_n. The plurality of shift register circuits GC_1 to GC_n are coupled together in sequence. The shift register circuits GC_1 to GC_n of each stage are coupled to the pixel array PXL. Specifically, the shift register circuit GC_1 of the first stage outputs the luminous signal EM(1) and the reset signal RST(1) of the first stage to the first pixel column in the pixel array PXL. The shift register circuit GC_2 of the second stage outputs the luminous signal EM(2) and the reset signal RST(2) of the second stage to the second pixel column in the pixel array PXL, and so on. The shift register circuit GC_n of the nth stage outputs the luminous signal EM(n) and the reset signal RST(n) of the nth stage to the corresponding pixel column in the pixel array PXL.

[0043] In this embodiment, the shift register circuits GC_1 ˜GC_n of each stage may have the same circuit architecture.

[0044] Please refer to Figure 1B , Figure 1B According to the present invention Figure 1A The block diagram of the n-th shift register circuit shown in the embodiment. In the present embodiment, the n-th shift register circuit GC_n includes a light emitting signal generating circuit 110, a light emitting signal control circuit 120, a reset signal generating circuit 130 and a reset signal control circuit 140. The light emitting signal generating circuit 110 has a node ND1. The node ND1 of the light emitting signal generating circuit 110 outputs a light emitting signal EM(n) to the pixel array PXL. In the present embodiment, the light emitting signal generating circuit 110 is used to enable the light emitting signal EM(n) to drive the pixel array PXL during the corresponding light emitting phase.

[0045] The light emitting signal control circuit 120 is coupled to the node ND1. In this embodiment, during the reset phase, the light emitting signal control circuit 120 maintains the light emitting signal EM(n) at a disabled voltage level.

[0046] The reset signal generating circuit 130 is coupled to the node ND1. The reset signal generating circuit 130 has an output terminal for outputting a reset signal RST(n) to the pixel array PXL. In the present embodiment, in the early stage of the reset phase, the reset signal generating circuit 130 generates an enabled reset signal RST(n) in response to the luminous signal EM(n) to reset the pixel array PXL.

[0047] The reset signal control circuit 140 is coupled to the light emitting signal control circuit 120. The reset signal control circuit 140 is coupled to the output terminal of the reset signal generating circuit 130. The reset signal control circuit 140 has an input terminal for receiving the light emitting signal EM(n). In the present embodiment, in the later period during the reset phase, the reset signal control circuit 140 responds to the light emitting signal EM(n) to disable the reset signal RST(n) to stop resetting the pixel array PXL.

[0048] In this embodiment, the light emitting phase occurs before the resetting phase.

[0049] It is worth mentioning that the reset signal generating circuit 130 and the reset signal control circuit 140 enable or disable the reset signal RST(n) according to the luminous signal EM(n). In this way, the n-th shift register circuit GC_n does not need to set up an additional circuit to generate the reset signal RST(n). Therefore, the circuit for generating the luminous signal EM(n) and the circuit for generating the reset signal RST(n) are integrated in the same n-th shift register circuit GC_n to reduce the circuit space occupied by the n-th shift register circuit GC_n and increase the circuit space that can be configured on the display panel 100 to facilitate the design of a zero-frame display panel 100.

[0050] Please refer to Figure 2 , Figure 2 According to the present invention Figure 1B Circuit diagram of the n-th shift register circuit shown in the embodiment. In this embodiment, the n-th shift register circuit GC_n includes a light emitting signal generating circuit 210 , a light emitting signal control circuit 220 , a reset signal generating circuit 230 and a reset signal control circuit 240 .

[0051] In the present embodiment, the reset signal generating circuit 230 includes transistors T1, T2 and a capacitor C1. The control end of the transistor T1 is coupled to the node ND1. The transistor T1 is controlled by the signal on the node ND1 (i.e., the light emitting signal EM(n)) to perform a switching operation. The first end of the transistor T1 receives the first control signal P(n-1) of the previous stage. The second end of the transistor T1 is coupled to the reset signal control circuit 240 at the node ND2. The control end of the transistor T2 is coupled to the node ND2. The transistor T2 is controlled by the signal on the node ND2 to perform a switching operation. The first end of the transistor T2 receives the clock signal CK. The second end of the transistor T2 outputs the reset signal RST(n). The first end of the capacitor C1 is coupled to the node ND2. The second end of the capacitor C1 is coupled to the second end of the transistor T2. In the present embodiment, the second end of the capacitor C1 and the second end of the transistor T2 serve as the output end of the reset signal generating circuit 230 to output the reset signal RST(n).

[0052] In the present embodiment, the reset signal control circuit 240 includes transistors T3, T4 and T5. The control end of transistor T3 receives the first control signal P(n+1) of the subsequent stage. The first end of transistor T3 is coupled to node ND2. The second end of transistor T3 receives the voltage signal VGH. In the present embodiment, the voltage signal VGH can be referred to as the first voltage signal VGH. The control end of transistor T4 is coupled to the control end of transistor T3. Transistors T3 and T4 are controlled by the first control signal P(n+1) of the subsequent stage to perform switching operation. The first end of transistor T4 is coupled to the second end of transistor T2 and the second end of capacitor C1 (i.e., the output end of reset signal generating circuit 230). The second end of transistor T4 receives the voltage signal VGH. The control end of transistor T5 receives the light emitting signal EM(n). Transistor T5 is controlled by the light emitting signal EM(n) to perform switching operation. In the present embodiment, the control end of transistor T5 serves as the input end of the reset signal control circuit 240. The first end of transistor T5 is coupled to the second end of transistor T2 and the second end of capacitor C1. The second terminal of the transistor T5 receives the voltage signal VGH.

[0053] In the present embodiment, the light emitting signal generating circuit 210 includes transistors T6, T7 and capacitor C2. The control end of transistor T6 receives a clock signal CK. Transistor T6 is controlled by the clock signal CK to perform a switching operation. The first end of transistor T6 receives a previous stage light emitting signal EM(n-1). The second end of transistor T6 is coupled to node ND3. The first end of capacitor C2 receives a subsequent stage light emitting signal EM(n+1). The second end of capacitor C2 is coupled to node ND3. The control end of transistor T7 is coupled to node ND3. Transistor T7 is controlled by a signal on node ND3 (i.e., a second control signal Q(n)) to perform a switching operation. The first end of transistor T7 receives a voltage signal VGL. In the present embodiment, the voltage signal VGL may be referred to as a second voltage signal VGL. The second end of transistor T7 is coupled to node ND1. In the present embodiment, the second end of transistor T7 serves as an output end of the light emitting signal generating circuit 210 to output a light emitting signal EM(n).

[0054] In the present embodiment, the light signal control circuit 220 includes transistors T8, T9, T10, T11, T12, T13 and a resistor R. The control end of transistor T8 is coupled to the first end of transistor T8. The control end and the first end of transistor T8 receive the clock signal CK. Transistor T8 is coupled in a diode configuration and receives the clock signal CK. The control end of transistor T9 receives the previous stage light signal EM(n-1). Transistor T9 is controlled by the previous stage light signal EM(n-1) to perform a switching operation. The first end of transistor T9 is coupled to the second end of transistor T8. The second end of transistor T9 receives the voltage signal VGH. The control end of transistor T10 is coupled to the second end of transistor T8 and the first end of transistor T9. The first end of transistor T10 is coupled to the control end and the first end of transistor T8. The second end of transistor T10 is coupled to the first end of resistor R. The second end of resistor R is coupled to node ND4. The control end of transistor T11 receives the second control signal Q(n). The transistor T11 is controlled by the second control signal Q(n) to perform a switching operation. The first end of the transistor T11 is coupled to the node ND4. The second end of the transistor T11 receives the voltage signal VGH. The control end of the transistor T12 is coupled to the node ND4. The first end of the transistor T12 is coupled to the node ND3. The second end of the transistor T12 receives the voltage signal VGH. The control end of the transistor T13 is coupled to the control end of the transistor T12 (i.e., the node ND4). The transistors T12 and T13 are controlled by the signal on the node ND4 (i.e., the first control signal P(n)) to perform a switching operation. The first end of the transistor T13 is coupled to the node ND1. The second end of the transistor T13 receives the voltage signal VGH.

[0055] In this embodiment, the voltage signals VGH and VGL are different constant voltage signals. In this embodiment, the voltage signal VGH has a disabled voltage level to disable any one of the transistors T1 to T13. The voltage signal VGL has an enabled voltage level to enable any one of the transistors T1 to T13. The voltage signal VGH may have a relatively high voltage level, and the voltage signal VGL may have a relatively low voltage level.

[0056] Please refer to Figure 3 as well as 4A to 4D , Figure 3 According to the present invention Figure 2 The operation diagram of the n-th stage shift register circuit shown in the embodiment is shown. 4A to 4D According to the present invention Figure 3 The operation diagram of the n-th stage shift register circuit shown in the embodiment. Figure 3 In FIG. 5 , the horizontal axis is the operation time of the n-th stage shift register circuit GC_n, and the vertical axis is the voltage value.

[0057] For details on the operation of the n-th stage shift register circuit GC_n in the PEM1 during the first light-emitting phase, please also refer to Figure 3 as well as Figure 4A During the first light emitting stage PEM1, the light emitting signal EM(n) has an enabling voltage level VGL2. In this embodiment, the enabling voltage level VGL2 is expressed by the following formula (1):

[0058] VGL2=VGL1+2×|VTH|……Formula (1)

[0059] In formula (1), VGL1 represents the voltage level of the voltage signal VGL (ie, the enable voltage level VGL1 ). VTH represents the threshold voltage level of any one of the transistors T1 - T13 . In this embodiment, the voltage signal VGH has a disable voltage level VGH1 .

[0060] The enabled luminous signal EM(n) turns on the transistors T1 and T5. The turned-on transistor T1 outputs the previous first control signal P(n-1) to the control terminal of the transistor T2. The previous first control signal P(n-1) has a disable voltage level VPH. The disabled previous first control signal P(n-1) turns off the transistor T2. The next first control signal P(n+1) has an enable voltage level VPL. The enabled next first control signal P(n+1) turns on the transistors T3 and T4. The turned-on transistors T3 and T4 respectively pull the signals at both ends of the capacitor C1 to the voltage signal VGH (i.e., the disable voltage level VGH1) to disable the reset signal RST(n).

[0061] On the other hand, during the first light emitting stage PEM1, the previous stage light emitting signal EM(n-1) has an enable voltage level VGL1. The enabled previous stage light emitting signal EM(n-1) turns on the transistor T9. The turned-on transistor T9 pulls the signal on the control terminal of the transistor T10 to the voltage signal VGH (i.e., the disable voltage level VGH1) to turn off the transistor T10. The clock signal CK has an enable voltage level VGL1. The clock signal CK can turn on the transistors T6 and T8. The turned-on transistor T6 pulls the second control signal Q(n) on the node ND3 to the enabled previous stage light emitting signal EM(n-1) (i.e., the enable voltage level VGL1) to turn on the transistor T7. The enabled second control signal Q(n) turns on the transistor T11. The turned-on transistor T11 pulls the first control signal P(n) on the node ND4 to the voltage signal VGH (i.e., the disable voltage level VGH1) to turn off the transistors T12 and T13. The turned-on transistor T7 pulls the light emitting signal EM(n) to the voltage signal VGL (ie, the enabling voltage level VGL1 ) and outputs the enabled light emitting signal EM(n).

[0062] For details on the operation of the n-th stage shift register circuit GC_n in the PEM2 during the second light-emitting phase, please also refer to Figure 3 as well as Figure 4B . During the second light emitting stage PEM2, the rear-stage first control signal P(n+1) has a disable voltage level VPH. The disabled rear-stage first control signal P(n+1) turns off transistors T3 and T4. The light emitting signal EM(n) has an enable voltage level VGL1. The enabled light emitting signal EM(n) turns on transistors T1 and T5. The turned-on transistor T1 outputs the front-stage first control signal P(n-1) to the node ND2. The front-stage first control signal P(n-1) has an enable voltage level VPL. The enabled front-stage first control signal P(n-1) turns on transistor T2. The clock signal CK has a disable voltage level VGH1 so that the turned-on transistor T2 outputs a disabled reset signal RST(n).

[0063] On the other hand, during the second light-emitting stage PEM2, the front-stage light-emitting signal EM(n-1) has a disable voltage level VGH1. The disabled front-stage light-emitting signal EM(n-1) turns off the transistor T9. The transistor T10 remains turned off. The clock signal CK has a disable voltage level VGH1. The clock signal CK can turn off the transistors T6 and T8. The turned-off transistor T6 makes the node ND3 float. In this way, the capacitor C2 can couple the change of the rear-stage light-emitting signal EM(n+1) to the node ND3 to change the signal on the node ND3. At this time, the rear-stage light-emitting signal EM(n+1) has an enable voltage level VGL2. Through the capacitor C2, the enabled rear-stage light-emitting signal EM(n+1) can pull down the second control signal Q(n) on the node ND3 to turn on the transistor T7. The enabled second control signal Q(n) turns on the transistor T11. The turned-on transistor T11 pulls the first control signal P(n) on the node ND4 to the voltage signal VGH (i.e., the disable voltage level VGH1) to turn off the transistors T12 and T13. The turned-on transistor T7 pulls the luminous signal EM(n) to the voltage signal VGL (i.e., the enable voltage level VGL1) to output the enabled luminous signal EM(n).

[0064] For details on the operation of the n-th stage shift register circuit GC_n during the first reset phase PRT1, please also refer to Figure 3 as well as Figure 4C. During the period PRT1 of the first reset stage, the light emitting signal EM(n) has a disable voltage level VGH1. The disabled light emitting signal EM(n) turns off the transistors T1 and T5. The subsequent first control signal P(n+1) has a disable voltage level VPH. The disabled subsequent first control signal P(n+1) turns off the transistors T3 and T4. The turned-off transistors T1 and T3 make the node ND2 float. In this way, the capacitor C1 can couple the change of the reset signal RST(n) to the node ND2 to change the signal on the node ND2. At this time, the reset signal RST(n) can have an enable voltage level VGL1. The enabled reset signal RST(n) can turn on the transistor T2. At this time, the clock signal CK has an enable voltage level VGL1, which can cause the turned-on transistor T2 to output the enabled reset signal RST(n).

[0065] On the other hand, during the period PRT1 of the first reset stage, the previous stage light emitting signal EM(n-1) has a disable voltage level VGH1. The disabled previous stage light emitting signal EM(n-1) can turn off the transistor T9. At this time, the clock signal CK has an enable voltage level VGL1. The clock signal CK can turn on the transistors T6 and T8. The turned-on transistor T6 pulls the second control signal Q(n) on the node ND3 to the previous stage light emitting signal EM(n-1) (i.e., the disable voltage level VGH1) and thereby turns off the transistors T7 and T11. The turned-on transistor T8 pulls the signal on the control terminal of the transistor T10 to the clock signal CK (i.e., the enable voltage level VGL1) to turn on the transistor T10. The turned-on transistor T10 pulls the first control signal P(n) on the node ND4 to the clock signal CK to turn on the transistors T12 and T13. The turned-on transistor T12 pulls the second control signal Q(n) on the node ND3 to the voltage signal VGH (i.e., the disable voltage level VGH1) so that the second control signal Q(n) on the node ND3 is maintained at the disable voltage level VGH1. The turned-on transistor T13 pulls the light emitting signal EM(n) on the node ND1 to the voltage signal VGH (i.e., the disable voltage level VGH1) so that the light emitting signal EM(n) is disabled.

[0066] For details on the operation of the n-th stage shift register circuit GC_n during the second reset phase PRT2, please also refer to Figure 3 as well as Figure 4DDuring the second reset phase PRT2, the light emitting signal EM(n) has a disable voltage level VGH1. The disabled light emitting signal EM(n) turns off the transistors T1 and T5. The post-stage first control signal P(n+1) has an enable voltage level VPL. The enabled post-stage first control signal P(n+1) turns on the transistors T3 and T4. The turned-on transistors T3 and T4 pull the signals at both ends of the capacitor C1 to the voltage signal VGH (i.e., the disable voltage level VGH1) to turn off the transistor T2 and disable the reset signal RST(n).

[0067] On the other hand, during the period PRT2 of the second reset stage, the previous stage light emitting signal EM(n-1) has the disable voltage level VGH1. The disabled previous stage light emitting signal EM(n-1) turns off the transistor T9. The clock signal CK has the disable voltage level VGH1. At this time, the clock signal CK can turn off the transistors T6 and T8. The transistor T10 remains turned off. The first control signal P(n) on the node ND4 is maintained as the signal of the previous period PRT1 (i.e., the clock signal CK having the enable voltage level VGL1), and the transistors T12 and T13 remain turned on. The turned-on transistor T12 pulls the second control signal Q(n) on the node ND3 to the voltage signal VGH (i.e., the disable voltage level VGH1) so that the signal on the node ND3 is maintained at the disable voltage level VGH1 to turn off the transistors T7 and T11. The turned-on transistor T13 pulls the light emitting signal EM(n) on the node ND1 to the voltage signal VGH (ie, the disable voltage level VGH1 ) so that the light emitting signal EM(n) is disabled.

[0068] In this embodiment, transistors T1 to T13 are implemented as p-type metal-oxide-semiconductor field-effect transistors (PMOSFET). In other embodiments, transistors T1 to T13 are implemented as N-type metal-oxide-semiconductor field-effect transistors (NMOSFET). In other embodiments, the signal is inverse to the corresponding signal in this embodiment.

[0069] Please refer to Figure 5 , Figure 5 5 is a block diagram of a display panel according to another embodiment of the present invention. In this embodiment, the display panel 500 includes a pixel array PXL and a gate drive circuit GC. The pixel array PXL includes sub-pixel arrays PXL_1 and PXL_2. In the top view, the gate drive circuit GC is disposed between the sub-pixel arrays PXL_1 and PXL_2. The implementation details of the gate drive circuit GC have been described in detail in the aforementioned embodiment and will not be repeated here.

[0070] In summary, the gate drive circuit and the display panel of the embodiment of the present invention are integrated into the same shift register circuit for generating the luminous signal and the circuit for generating the reset signal. In addition, the gate drive circuit and the display panel can generate the reset signal according to the luminous signal. In this way, the gate drive circuit and the display panel can save the additional circuit for controlling the reset signal. Therefore, each level of the shift register circuit has an integrated circuit architecture to increase the configurable circuit space on the display panel and help design a zero-border display panel. In some embodiments, the gate drive circuit is arranged between adjacent sub-pixel arrays.

[0071] Although the present invention has been disclosed as above by way of embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some changes and modifications without departing from the concept and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the claims.

Claims

1. A gate drive circuit having a multi-stage shift register circuit, wherein the n-th stage shift register circuit comprises: A light emitting signal generating circuit has a first node outputting a light emitting signal to a pixel array, wherein the light emitting signal generating circuit enables the light emitting signal during a period from a first light emitting stage to a second light emitting stage; a light emitting signal control circuit coupled to the first node, wherein during a period from a first reset stage to a second reset stage, the light emitting signal control circuit maintains the voltage level of the light emitting signal at a disabled voltage level; a reset signal generating circuit coupled to the first node, wherein during the first reset phase, the reset signal generating circuit generates an enabled reset signal in response to the light emitting signal; and A reset signal control circuit is coupled to the light emitting signal control circuit and the reset signal generating circuit, wherein during the second reset phase, the reset signal control circuit disables the reset signal in response to the light emitting signal.

2. The gate driving circuit as claimed in claim 1, wherein the reset signal generating circuit comprises: A first transistor having a control terminal coupled to the first node, the first terminal of the first transistor receiving a previous first control signal, and the second terminal of the first transistor coupled to the reset signal control circuit at a second node; a second transistor having a control terminal coupled to the second node, a first terminal of the second transistor receiving a clock signal, and a second terminal of the second transistor outputting the reset signal; as well as A first capacitor has a first terminal coupled to the second node, and a second terminal of the first capacitor is coupled to the second terminal of the second transistor.

3. The gate driving circuit as claimed in claim 2, wherein the reset signal control circuit comprises: A third transistor having a control terminal for receiving a first control signal of a subsequent stage, a first terminal of the third transistor being coupled to the second node, and a second terminal of the third transistor receiving a first voltage signal; a fourth transistor having a control end coupled to the control end of the third transistor, a first end of the fourth transistor coupled to the second end of the second transistor, and a second end of the fourth transistor receiving the first voltage signal; as well as A fifth transistor has a control terminal for receiving the light emitting signal, a first terminal of the fifth transistor is coupled to the second terminal of the second transistor, and a second terminal of the fifth transistor receives the first voltage signal.

4. The gate driving circuit as described in claim 3, wherein during the first reset stage, the light emitting signal is disabled to turn off the first transistor and the fifth transistor, the post-stage first control signal is disabled to turn off the third transistor and the fourth transistor to make the second node floating, the first capacitor changes the signal on the second node to turn on the second transistor, and the clock signal is enabled to enable the second transistor to output the enabled reset signal.

5. The gate driving circuit as described in claim 3, wherein during the second reset stage, the light emitting signal is disabled to turn off the first transistor and the fifth transistor, and the post-stage first control signal is enabled to turn on the third transistor and the fourth transistor to pull the signal at both ends of the first capacitor to the first voltage signal so that the reset signal is disabled.

6. The gate driving circuit as described in claim 3, wherein during the first light-emitting stage, the light-emitting signal is enabled to turn on the first transistor and the fifth transistor, the front-stage first control signal is disabled to turn off the second transistor, and the rear-stage first control signal is enabled to turn on the third transistor and the fourth transistor to pull the signal at both ends of the first capacitor to the first voltage signal so that the reset signal is disabled.

7. The gate drive circuit as described in claim 3, wherein during the second light-emitting stage, the rear-stage first control signal is disabled to turn off the third transistor and the fourth transistor, the light-emitting signal is enabled to turn on the first transistor and the fifth transistor, the front-stage first control signal is enabled to turn on the second transistor, and the clock signal is disabled so that the second transistor outputs the disabled reset signal.

8. The gate driving circuit as claimed in claim 1, wherein the light emitting signal generating circuit comprises: A sixth transistor having a control terminal for receiving a clock signal, a first terminal for receiving a previous light emitting signal, and a second terminal of the sixth transistor coupled to a third node; A second capacitor having a first end for receiving a post-stage light-emitting signal, and a second end of the second capacitor coupled to the third node; as well as A seventh transistor has a control terminal coupled to the third node, a first terminal of the seventh transistor receives a second voltage signal, and a second terminal of the seventh transistor is coupled to the first node.

9. The gate driving circuit as claimed in claim 8, wherein the light emitting signal control circuit comprises: an eighth transistor having a control terminal and a first terminal for receiving the clock signal; a ninth transistor having a control end for receiving the previous light emitting signal, a first end of the ninth transistor coupled to the second end of the eighth transistor, and a second end of the ninth transistor for receiving a first voltage signal; a tenth transistor having a control terminal coupled to the second terminal of the eighth transistor, and a first terminal of the tenth transistor coupled to the control terminal and the first terminal of the eighth transistor; a resistor having a first end coupled to the second end of the tenth transistor, and a second end of the resistor coupled to a fourth node; an eleventh transistor having a control terminal receiving a second control signal, a first terminal of the eleventh transistor coupled to the fourth node, and a second terminal of the eleventh transistor receiving the first voltage signal; a twelfth transistor, having a control terminal coupled to the fourth node, a first terminal of the twelfth transistor coupled to the third node, and a second terminal of the twelfth transistor receiving the first voltage signal; as well as A thirteenth transistor has a control terminal coupled to the fourth node, a first terminal of the thirteenth transistor coupled to the first node, and a second terminal of the thirteenth transistor receiving the first voltage signal.

10. The gate driving circuit as described in claim 9, wherein during the first reset phase, the previous stage light emitting signal is disabled to turn off the ninth transistor, the clock signal is enabled to turn on the sixth transistor and the eighth transistor to turn off the seventh transistor and the eleventh transistor and turn on the tenth transistor, and the signal on the fourth node is enabled to turn on the twelfth transistor and the thirteenth transistor to pull the light emitting signal to the first voltage signal so that the light emitting signal is disabled.

11. The gate driving circuit as described in claim 9, wherein during the second reset phase, the previous stage light emitting signal is disabled to turn off the ninth transistor, the clock signal is disabled to turn off the sixth transistor and the eighth transistor, the tenth transistor, the seventh transistor and the eleventh transistor are turned off, and the twelfth transistor and the thirteenth transistor are turned on to pull the light emitting signal to the first voltage signal so that the light emitting signal is disabled.

12. The gate driving circuit as described in claim 9, wherein during the first light-emitting stage, the previous light-emitting signal is enabled to turn on the ninth transistor to turn off the tenth transistor, the clock signal is enabled to turn on the sixth transistor and the eighth transistor, the second control signal is enabled to turn on the eleventh transistor to pull the signal on the fourth node to the first voltage signal to turn off the twelfth transistor and the thirteenth transistor, and the seventh transistor is turned on to pull the light-emitting signal to the second voltage signal to output the enabled light-emitting signal.

13. The gate driving circuit as described in claim 9, wherein during the second light-emitting stage, the previous stage light-emitting signal is disabled to turn off the ninth transistor, the tenth transistor is turned off, the clock signal is disabled to turn off the sixth transistor and the eighth transistor to make the third node floating, the second capacitor changes the signal on the third node to turn on the seventh transistor and enable the second control signal, the eleventh transistor is turned on to pull the signal on the fourth node to the first voltage signal to turn off the twelfth transistor and the thirteenth transistor, and the seventh transistor pulls the light-emitting signal to the second voltage signal to output the enabled light-emitting signal.

14. A display panel, comprising: a pixel array; as well as The gate driving circuit as claimed in claim 1 is coupled to the pixel array. 15 . The display panel as claimed in claim 14 , wherein the pixel array comprises a first sub-pixel array and a second sub-pixel array, and the gate driving circuit is disposed between the first sub-pixel array and the second sub-pixel array.

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