Semiconductor process method and semiconductor device system

Abstract

The application provides a semiconductor process method, which comprises the following steps: performing a semiconductor process, the semiconductor process comprising the following steps: manufacturing a first mandrel pattern on a predetermined substrate, manufacturing a first sidewall on both sides of each first mandrel, removing the first mandrel, and processing the predetermined substrate by using the first sidewall to form a plurality of fin structures; and adjusting the width value of the first mandrel in the next semiconductor process according to the width value of the first mandrel and the interval between the corresponding fin structures in the plurality of times of performing the semiconductor process, so that the interval between the fin structures tends to be consistent. The semiconductor process method provided by the application can feed back and adjust the width value of the first mandrel in the next process according to the process result of the previous process in the mass production process, thereby stably maintaining the uniformity of the fin interval in real time, ensuring the product performance and improving the product yield. The application further provides a semiconductor device system.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor process, in particular, to a semiconductor process method and a semiconductor device system for performing the semiconductor process method. BACKGROUND

[0002] With the semiconductor process entering 14nm and below, semiconductor logic devices adopt Fin Field-Effect Transistor (FinFET) technology, and the critical dimension (CD) and pitch of the fin (Fin) pattern are microscaled to 20nm and below, respectively. Due to the limitation of ArF-immersion photolithography technology, the desired critical dimension and pitch cannot be obtained by one-time photolithography, so the industry generally uses self-aligned double patterning (SADP) and self-aligned quadruple patterning (SAQP) technology to obtain the desired size and pitch.

[0003] Taking the self-aligned double patterning technology as an example, as shown in Figures 1 to 7 The self-aligned double patterning technology generally includes seven steps: 1) core shaft photolithography; 2) core shaft etching; 3) atomic layer sidewall deposition; 4) sidewall etching; 5) core shaft removal; 6) fin mask etching; and 7) fin etching. In the self-aligned double patterning and quadruple patterning, each process in the process will affect the pitch of the final fin, including the size of the core shaft photolithography, the size after the core shaft etching, the thickness of the atomic layer sidewall deposition, the size and the angle of the atomic layer sidewall after etching, the size after the fin mask etching, and the size of the final fin, which will affect the pitch uniformity of the final fin, making the pitch uniformity between fins poor.

[0004] Therefore, how to ensure the uniformity of the fin pitch has become a technical problem to be solved in the field. SUMMARY

[0005] The present application aims to provide a semiconductor process method and a semiconductor device system for performing the semiconductor process method, which can realize stable maintenance of the uniformity of the fin pitch.

[0006] To achieve the above-mentioned purpose, as one aspect of the present application, a semiconductor process method is provided for processing a predetermined substrate, the predetermined substrate including a substrate and at least one core shaft layer on the substrate, the semiconductor process method comprising:

[0007] etching the core shaft layer located at the top layer to form a plurality of first core shafts under first process conditions;

[0008] obtaining a width value of each of the first core shafts;

[0009] forming a first sidewall on both sides of each of the first core shafts;

[0010] etching the predetermined substrate with the first sidewall as a mask to form a plurality of fin structures on the substrate;

[0011] obtaining a spacing between the plurality of fin structures;

[0012] judging whether the spacing between the plurality of fin structures is consistent based on the width value of the first core shaft and the spacing between the corresponding fin structures, and if not, adjusting the first process conditions to second process conditions to adjust the width value of the first core shaft when the semiconductor process is performed later to make the spacing between the plurality of fin structures tend to be consistent.

[0013] Optionally, the core shaft layer is a single-layer structure.

[0014] The judging whether the spacing between the plurality of fin structures is consistent based on the width value of the first core shaft and the spacing between the corresponding fin structures includes:

[0015] calculating a first difference value between an average value of the spacing between each pair of the fin structures corresponding to the plurality of first core shafts and an average value of the spacing between the pairs of adjacent fin structures corresponding to different first core shafts;

[0016] judging whether the first difference value is within a preset range;

[0017] If the first difference value is out of the preset range, the spacing between the plurality of fin structures is inconsistent.

[0018] Optionally, the adjusting the first process conditions to the second process conditions to adjust the width value of the first core shaft when the semiconductor process is performed later includes:

[0019] corresponding the width value of the first core shaft and the first difference value and fitting to find a target width value of the first core shaft within the preset range;

[0020] adjusting the first process conditions to the second process conditions to make the width value of the first core shaft formed later satisfy the target width value.

[0021] Optionally, the predetermined substrate comprises a second mandrel layer and a first mandrel layer which are sequentially stacked from bottom to top on a substrate;

[0022] The etching of the predetermined substrate to form a plurality of fin structures on the substrate comprises:

[0023] Etching the second mandrel layer with the first sidewall as a mask to obtain a plurality of second mandrels;

[0024] A second sidewall is formed on both sides of each of the second mandrels;

[0025] Etching the substrate with the second sidewall as a mask to form a plurality of the fin structures on the substrate;

[0026] The judging of the spacing between the plurality of fin structures based on the width value of the first mandrel and the spacing between the corresponding fin structures comprises:

[0027] Calculating a first average value of the spacing between two pairs of the fin structures corresponding to two of the second mandrels in a plurality of groups of the fin structures corresponding to the first mandrel and a second average value of the spacing between a plurality of pairs of adjacent fin structures corresponding to different groups of the fin structures;

[0028] Judging whether a second difference value between the first average value and the second average value is within a preset range, and if the second difference value is outside the preset range, the spacing between the plurality of fin structures is inconsistent.

[0029] Optionally, the adjusting of the first process condition to a second process condition comprises:

[0030] Correlating the width value of the first mandrel and the second difference value and fitting them to find a target width value of the first mandrel within the preset range;

[0031] Adjusting the first process condition to a second process condition so that the width value of the first mandrel formed later satisfies the target width value.

[0032] Optionally, the forming of the first sidewall on both sides of each of the first mandrels comprises:

[0033] Depositing a first sidewall layer on the surface of the first mandrel under a third process condition;

[0034] Etching the first sidewall layer to form the first mandrel with a top surface exposed and the first sidewall vertically;

[0035] The semiconductor process method further comprises:

[0036] obtaining a thickness value of the first sidewall layer;

[0037] calculating a third average value of the spacing between each pair of the fin structures corresponding to a plurality of the second mandrels, and a fourth average value between the first average value and the second average value, to obtain a third difference value between the fourth average value and the third average value;

[0038] establishing a corresponding relationship between the thickness value of the first sidewall layer and the third difference value;

[0039] determining whether the third difference value between the fourth average value and the third average value is within a preset range, and if the third difference value exceeds the preset range, adjusting the first process condition to a second process condition to adjust the width value of the first mandrel in subsequent semiconductor process.

[0040] Optionally, according to the re-determined target thickness of the first sidewall layer, adjusting deposition parameters for depositing the first mandrel layer, the deposition parameters including at least one of deposition time, deposition gas flow, and temperature.

[0041] Optionally, the preset range is greater than or equal to -0.5 nm and less than or equal to 0.5 nm.

[0042] Optionally, the adjusting the first process condition to a second process condition to adjust the width value of the first mandrel in subsequent semiconductor process includes:

[0043] adjusting etching parameters in the step of etching the first mandrel layer according to the re-determined target width value of the first mandrel to form the second process condition, wherein the etching parameters include at least one of etching time, etching gas flow, and temperature.

[0044] As a second aspect of the present application, a semiconductor device system is provided for performing the semiconductor process method as described above.

[0045] Optionally, the semiconductor device system includes a semiconductor process equipment for forming the fin structures, a gap detection device for detecting the spacing between the fin structures, and a controller for determining whether the spacing between the plurality of fin structures tends to be consistent based on the width value of the first mandrel and the spacing between the corresponding fin structures, and if not, adjusting the first process condition to a second process condition to adjust the width value of the first mandrel in subsequent semiconductor process.

[0046] Optionally, a film thickness detection device is further included for detecting a thickness value of the first sidewall layer deposited on the first mandrel.

[0047] In the semiconductor process method and semiconductor device system provided by the present application, the semiconductor device system can adjust the width value of the first mandrel in the next semiconductor process according to the corresponding relationship between the width value of the first mandrel and the fin pitch in the previous semiconductor process, so as to make the pitches between the plurality of fin structures tend to be uniform, thereby being able to perform feedback adjustment on the width value of the first mandrel in the next process according to the process results of the previous multiple processes in the mass production process, and further to stabilize and maintain the uniformity of the fin pitch in real time, thereby ensuring the product performance and improving the product yield. BRIEF DESCRIPTION OF DRAWINGS

[0048] The accompanying drawings are included to provide a further understanding of the present application, and constitute a part of the specification, illustrate the present application and explain the principles of the present application together with the specific embodiments described below, but are not intended to limit the present application. In the drawings:

[0049] Figures 1 to 7 is a process flow diagram of the self-aligned double patterning technology;

[0050] Figure 8 is a diagram showing the corresponding relationship between the patterns of the film layers in the self-aligned double patterning technology;

[0051] Figure 9 is a diagram showing the pitch between the fin structures when the width value of the mandrel is too small;

[0052] Figure 10 is a diagram showing the pitch between the fin structures when the width value of the mandrel is too large;

[0053] Figure 11 is a flow diagram of the semiconductor process method provided by the embodiment of the present application;

[0054] Figure 12 is a top view diagram of the fin structure obtained by the semiconductor process method provided by the embodiment of the present application;

[0055] Figure 13 is a diagram showing the curve obtained by fitting the plurality of first differences with the corresponding width values of the first mandrel using the semiconductor process method provided by the embodiment of the present application;

[0056] Figures 14 to 25 is a process flow diagram of the self-aligned four patterning technology;

[0057] Figure 26 is a diagram showing the corresponding relationship between the patterns of the film layers in the self-aligned four patterning technology;

[0058] Figure 27 is a top view schematic diagram of a fin structure obtained by a semiconductor process method provided by an embodiment of the present application;

[0059] Figure 28 is a schematic diagram of the effect of the width value of the first mandrel on the fin pitch in a quadruple patterning process;

[0060] Figure 29 is a schematic diagram of the pitch between fin structures corresponding to different width values of the first mandrel in a quadruple patterning process.

[0061] Legend of reference signs:

[0062] 100: substrate 210: first mask layer

[0063] 211: first mask structure 310: first mandrel layer

[0064] 311: first mandrel 220: second mask layer

[0065] 221: second mask structure 320: second mandrel layer

[0066] 321: second mandrel 410: carbon coating layer

[0067] 420: anti-reflection layer 430: photoresist layer

[0068] 510: first sidewall layer 511: first sidewall

[0069] 520: second sidewall layer 521: second sidewall

[0070] 10: fin structure 110: substrate fin DETAILED DESCRIPTION

[0071] The specific embodiments of the present application are described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely intended to illustrate and explain the present application, and are not intended to limit the present application.

[0072] The inventors of the present application found in research that in the self-aligned double patterning and quadruple patterning technologies, the accuracy of the mandrel width value has a great influence on the uniformity of the fin structure 10. Taking the self-aligned double patterning technology as an example, as shown in Figures 1 to 7 the steps include:

[0073] Prepare a predetermined substrate, for example, Figure 1As shown, the predetermined substrate includes a substrate 100 and a first mask layer 210 and a first mandrel layer 310 located on the substrate 100 and stacked in sequence from bottom to top. Then, the predetermined substrate is subjected to mandrel photolithography and mandrel etching steps, that is, a carbon coating 410 (spin-on-carbon, i.e., SOC layer), an anti-reflection layer 420, and a photoresist layer 430 are sequentially formed on the first mandrel layer 310, and then the photoresist layer 430 is exposed to obtain a pattern corresponding to the desired first mandrel 311, and then the first mandrel layer 310 is etched using the exposed resist layer 430 as a mask to form a plurality of first mandrels 311, as shown in FIG. Figure 2 shown.

[0074] Then the atomic layer sidewall deposition and sidewall etching steps are performed, i.e., Figures 2 to 3 As shown, a first sidewall layer 510 is deposited on the first mask layer 210 and a plurality of first mandrels 311 thereon, and then, as shown in FIG. Figures 3 to 4 As shown, the structure is etched to remove the first sidewall layer 510 material on the first mask layer 210 and the tops of the plurality of first core shafts 311 , leaving only the first sidewalls 511 on both sides of each first core shaft 311 ;

[0075] Then, the mandrel removal step is performed, such as Figures 4 to 5 As shown, the first core shaft 311 is removed; and then the fin mask etching step is performed, as shown in FIG. Figures 5 to 6 As shown, the first sidewall 511 is used as a mask to etch the first mask layer 210 to obtain a plurality of first mask structures 211; finally, a fin etching step is performed, as shown in FIG. Figures 6 to 7 As shown, the substrate 100 is etched using the first sidewall 511 as a mask to obtain a plurality of fin structures 10. Figure 7 As shown, the fin structure 10 may include substrate fins 110 formed of the substrate 100 material, and may also include residual material of the film layer above each substrate fin 110 (eg, the first mask structure 211 , a portion of the first sidewall 511 , etc.).

[0076] During the self-aligned patterning process, each process will affect the final fin spacing, including the size of the core shaft lithography, the size after the core shaft etching, the thickness of the atomic layer sidewall (first sidewall 511) deposition, the size after the atomic layer sidewall etching and the tilt angle after etching, the size after the fin mask etching, and the final fin size. These parameters will affect the spacing between the final fin structures 10, making the spacing uniformity between the fin structures 10 poor.

[0077] For example, Figure 8 As shown, in the self-aligned double patterning process, the first sidewalls 511 formed on both sides of each first mandrel 311 correspond to a pair of fin structures 10 that are finally formed. Figure 9As shown, when the mandrel width value is too small, it will result in a smaller spacing α between a pair of fin structures 10 corresponding to each first mandrel 311, and a larger spacing β between two fin structures 10 adjacent to each other but not belonging to the same pair; as Figure 10 As shown, when the mandrel width value is too large, it will result in a larger spacing α between a pair of fin structures 10 corresponding to each first mandrel 311, and a smaller spacing β between two fin structures 10 adjacent to each other but not belonging to the same pair.

[0078] Therefore, how to ensure the accuracy of the mandrel width value is the key to solve the problem of inconsistent fin spacing.

[0079] To solve the above technical problems, as one aspect of the present application, a semiconductor process method is provided for processing a predetermined substrate, as shown in Figure 1 , Figure 14 As shown, the predetermined substrate includes a substrate 100 and at least one mandrel layer (for example, including a first mandrel layer 310 (i.e. Figure 1 As shown) or including a first mandrel layer 310 and a second mandrel layer 320 (i.e. Figure 14 As shown), as shown in Figure 11 The semiconductor process method includes:

[0080] Step S1, etching the mandrel layer located on the top layer under a first process condition to form a plurality of first mandrels 311 (as shown in Figures 1 to 2 , Figures 14 to 15 );

[0081] Step S2, obtaining the width value of each first mandrel 311;

[0082] Step S3, forming a first side wall 511 on both sides of each first mandrel 311 (as shown in Figures 2 to 5 , Figures 15 to 18 );

[0083] Step S4, etching the predetermined substrate with the first side wall 511 as a mask to form a plurality of fin structures 10 on the substrate 100 (as shown in Figures 5 to 7 , Figures 18 to 25 );

[0084] Step S5, obtaining the spacing between the plurality of fin structures 10;

[0085] Step S6, based on the width value of the first mandrel 311 and the spacing between the corresponding fin structures 10, judging whether the spacing between the plurality of fin structures 10 is consistent, if not, adjusting the first process condition to a second process condition, and adjusting the width value of the first mandrel 311 through the second process condition when performing the semiconductor process later, so as to make the spacing between the plurality of fin structures 10 tend to be consistent.

[0086] The semiconductor process method provided by the present application can adjust the width value of the first mandrel 311 in the next semiconductor process according to the corresponding relationship between the width value of the first mandrel 311 and the fin pitch (i.e. the pitch between the structures 10) in the previous semiconductor process, so that the pitch between the plurality of fin structures 10 tends to be consistent. Therefore, the width value of the first mandrel 311 in the next process can be adjusted in real time according to the process result of the previous process, and the uniformity of the fin pitch can be stably maintained in real time, thereby ensuring the product performance and improving the product yield.

[0087] As an optional embodiment of the present application, the semiconductor process method is realized by a controller of a semiconductor process equipment. Optionally, the semiconductor process equipment comprises a gap detection device, for example, a critical dimension scanning electron microscope (CDSEM) or an optical critical dimension (OCD) machine, which is used to detect the line width of the wafer surface pattern (for example, the width value of the first mandrel 311 or the pitch between the finally obtained fin structures 10) in the current semiconductor process equipment.

[0088] As an optional embodiment of the present application, the plurality of first mandrels 311 are obtained by etching the mandrel layer on the top layer through a photolithography process. Specifically, as shown in Figure 1 、 Figure 14 The predetermined substrate further comprises a carbon coating layer 410, an anti-reflection layer 420 and a photoresist layer 430 which are sequentially stacked from bottom to top on the mandrel layer on the top layer. The step S1 specifically comprises:

[0089] The photoresist layer 430 is exposed and patterned to obtain a pattern corresponding to the required first mandrel 311. Then, the anti-reflection layer 420, the carbon coating layer 410 and the first mandrel layer 310 are etched with the exposed photoresist layer 430 as a mask to form a plurality of first mandrels 311. Finally, the residual film layer material above the first mandrel 311 is removed to obtain a structure as shown in Figure 2 、 Figure 15 .

[0090] As an optional embodiment of the present application, the mandrel layer is a single-layer structure (only comprising the first mandrel layer 310), i.e. the semiconductor process method provided by the present application is a self-aligned double patterning process, as shown in Figures 1 to 7 Correspondingly, the step S6 of judging whether the pitch between the plurality of fin structures 10 is consistent based on the width value of the first mandrel 311 and the pitch between the corresponding fin structures 10 specifically comprises:

[0091] Step S611: Calculate the average value of the spacing α between each pair of fin structures 10 in the plurality of pairs of fin structures 10 corresponding to the plurality of first core axes 311. The average value of the spacing β between multiple pairs of adjacent fin structures 10 corresponding to different first core axes 311 is The first difference between (i.e., the average value of the fin spacing drift (α-β));

[0092] Step S612: Determine the first difference Whether it is within the preset range;

[0093] Step S613: If the first difference If the distance exceeds the preset range, the spacing between the plurality of fin structures 10 will be inconsistent.

[0094] Accordingly, in the subsequent step, the first process condition is adjusted to the second process condition, and the width value of the first core axis 311 is adjusted by the second process condition when the semiconductor process is performed later, so that the first difference tends to zero, that is, the intervals between the plurality of fin structures 10 tend to be uniform.

[0095] Under ideal conditions, the spacing α and the spacing β should be consistent, such as Figure 12 As shown, the first preset threshold should be zero. However, considering that there are certain errors in actual detection and adjustment of etching parameters, in order to avoid frequent adjustment of process conditions (such as etching process parameters) to ensure production efficiency, as a preferred embodiment of the present invention, the preset range is greater than or equal to -0.5nm (nanometers) and less than or equal to 0.5nm, that is, the average value of the spacing α The average value of the spacing β When the difference is within 0.5 nm, it is considered that the spacing between the fin structures 10 is generally uniform, and there is no need to adjust the process conditions.

[0096] It should be noted that the specific principle of adjusting the process conditions according to the width value of the first core axis 311 and the corresponding spacing of the fin structure 10 in the embodiment of the present invention is to establish a linear correspondence between the different first core axis 311 width values ​​and the uniformity of the spacing of the fin structure 10, and re-determine the required first core axis 311 width value based on the determined linear correspondence, and adjust the process conditions accordingly.

[0097] Specifically, the step of adjusting the first process condition to the second process condition and adjusting the width of the first mandrel 311 when the semiconductor process is subsequently performed using the second process condition specifically includes:

[0098] The width value of the first core shaft 311 and the first difference value A one-to-one correspondence relationship is established and fitting is performed to find the target width value of the first core shaft 311 within a preset range.

[0099] The first process condition is adjusted to the second process condition so that the width value of the first core shaft 311 formed later satisfies the target width value.

[0100] For example, as Figure 13 The first difference value The curve obtained after fitting the width value of the corresponding first core shaft 311 is shown in the schematic diagram. The abscissa range corresponding to the region where the first difference value is zero, that is, the range of the target width value, so that the adjustment range of the width value of the first core shaft 311 can be determined, and the process condition is adjusted in the response direction.

[0101] To avoid etching through the substrate 100 when forming the plurality of first core shafts 311 in step S1, as a preferred embodiment of the present application, as shown in Figure 1 , Figure 14 The predetermined substrate further includes a first mask layer 210 stacked between the substrate 100 and the first core shaft layer 310, that is, the etching in step S1 is only performed to the first mask layer 210, and the substrate 100 is etched in sequence with the first mask layer 210 in the predetermined substrate as a mask in step S4, and finally the fin structure 10 including the substrate fin 110 and the first mask structure 211 is obtained as shown in Figure 7 .

[0102] As an optional embodiment of the present application, the controller of the semiconductor process equipment can be an advanced process control (APC) system. The advanced process control system automatically collects the width value of the first core shaft 311 detected by the scanning electron microscope or the optical line width measuring machine and the data of different types of fin pitch obtained finally in real time during each semiconductor process, and performs fitting on the corresponding relationship between the width value of the first core shaft 311 and the fin pitch measurement value (such as pitch drift α-β), as shown in Figure 13 , that is, the optimal width value of the first core shaft 311 corresponding to the most uniform fin pitch (pitch drift α-β approaching zero) can be obtained in real time.

[0103] As an optional embodiment of the present application, adjusting the first process condition to the second process condition to adjust the width value of the first core shaft 311 during the subsequent semiconductor process by the second process condition specifically includes:

[0104] According to the re-determined target width value of the first mandrel 311, the etching parameters in the step of etching the first mandrel layer 310 are adjusted to form a second process condition, wherein the etching parameters include at least one of etching time, etching gas flow rate, and temperature.

[0105] In other embodiments of the present application, the semiconductor process can also be a self-aligned quadruple pattern process, specifically, as shown in Figure 14 The predetermined substrate includes, on the substrate 100, a second mandrel layer 320 and a first mandrel layer 310 stacked in sequence from bottom to top;

[0106] The step S4 of etching the predetermined substrate to form a plurality of fin structures 10 on the substrate includes:

[0107] The step S41 includes etching the second mandrel layer 320 with the first sidewall 511 as a mask to obtain a plurality of second mandrels 321 (as shown in Figures 18 to 20 );

[0108] The step S42 includes fabricating a second sidewall 521 on both sides of each second mandrel 321 (as shown in Figures 20 to 23 );

[0109] The step S43 includes etching the substrate 100 with the second sidewall 521 as a mask to form a plurality of fin structures 10 on the substrate 100 (as shown in Figures 23 to 25 ).

[0110] In this case, as shown in Figure 26 , Figure 27 Each of the two first sidewalls 511 formed on both sides of each first mandrel 311 corresponds to two second mandrels 321, and each of the second sidewalls 521 formed on both sides of each second mandrel 321 corresponds to a pair of fin structures 10 finally formed, that is, each first mandrel 311 corresponds to two pairs of fin structures 10 (hereinafter referred to as a group of fin structures 10). At this time, there are three types of spacing between the fin structures 10, one is the spacing β between the two pairs of fin structures 10 corresponding to the two second mandrels 321 in each group of fin structures 10, one is the spacing γ between the adjacent two fin structures 10 of different groups, and the other is the spacing α between the pair of fin structures 10 corresponding to each second mandrel 321.

[0111] The pitch β and the pitch γ are both related to the width value of the first mandrel 311. If the width value of the first mandrel 311 is too small, the pitch β between the two pairs of second mandrels 321 corresponding to each first mandrel 311 will be small, and the pitch γ between the two pairs of fin structures 10 corresponding to each group of fin structures 10 will be small. In addition, the pitch γ between the two adjacent second mandrels 321 corresponding to different first mandrels 311 will be large, and the pitch γ between the two adjacent groups of fin structures 10 will be large (i.e., the left side of FIG. 6). Figure 29 If the width value of the first mandrel 311 is too large, the pitch β will be large and the pitch γ will be small (i.e., the right side of FIG. 6). Ideally, the pitch β and the pitch γ are the same (i.e., the middle of FIG. 6). Therefore, the uniformity of the pitch of the fin structures 10 can be measured by the difference β-γ between the pitch β and the pitch γ, and the width value of the first mandrel 311 can be adjusted according to the difference β-γ. Figure 29 Figure 29 Therefore, the step of determining that the pitches between the plurality of fin structures 10 tend to be uniform can specifically include:

[0112] Therefore, the step of determining that the pitches between the plurality of fin structures 10 tend to be uniform can specifically include:

[0113] Step S621, calculating a first average value of the pitch β between the two pairs of fin structures 10 corresponding to the two second mandrels 321 in the plurality of groups of fin structures 10 corresponding to the plurality of first mandrels 311 and a second average value of the pitch γ between the plurality of pairs of adjacent fin structures 10 corresponding to different groups

[0114] Step S622, determining whether a second difference between the first average value and the second average value is within a preset range. If the second difference is outside the preset range, the pitches between the plurality of fin structures 10 are not uniform.

[0115] In addition, the step of adjusting the first process condition to the second process condition to adjust the width value of the first mandrel 311 in the subsequent semiconductor process can specifically include:

[0116] corresponding relationship between the width value of the first mandrel 311 and the second difference and fitting the corresponding relationship to find a target width value of the first mandrel 311 within the preset range;

[0117] adjusting the first process condition to the second process condition so that the width value of the first mandrel 311 formed later satisfies the target width value.

[0118] ​​In view of the actual detection and the error in adjusting the etching parameters, to avoid frequent adjustment of the etching parameters and ensure the production efficiency, as a preferred embodiment of the present application, the second preset range is greater than or equal to -0.5 nm and less than or equal to 0.5 nm, that is, when the second difference between the second average value of the interval γ and the first average value of the interval β is within 0.5 nm, it is considered that the interval between the fin structures 10 corresponding to the first mandrel 311 width value is generally uniform, and there is no need to adjust the etching parameters when etching the first mandrel 311.

[0119] To avoid the etching in step S1 to form a plurality of first mandrels 311 and the etching in step S41 to form a plurality of second mandrels 321 to penetrate the substrate 100, as a preferred embodiment of the present application, as shown in Figure 14 , the predetermined substrate further includes a first mask layer 210 which is stacked between the second mandrel layer 320 and the first mandrel layer 310, and a second mask layer 220 which is stacked between the substrate 100 and the second mandrel layer 320.

[0120] That is, only the first mask layer 210 is etched in step S1, and the first mask layer 210 and the second mandrel layer 320 in the predetermined substrate are etched in sequence with the first side wall 511 as a mask in step S41, to obtain a structure as shown in Figure 19 ; in step S43, the second mask layer 220 and the substrate 100 in the predetermined substrate are etched in sequence with the second side wall 521 as a mask, to finally obtain a fin structure 10 including a substrate fin 110 and a second mask structure 221 as shown in Figure 25 .

[0121] That is, the step S43 of etching the substrate 100 with the second side wall 521 as a mask specifically includes:

[0122] etching the second mask layer 220 with the second side wall 521 as a mask to obtain a plurality of second mask structures 221 as shown in Figures 23 to 24 ;

[0123] etching the substrate 100 with the second side wall 521 as a mask to obtain a plurality of fin structures 10 as shown in Figures 24 to 25 .

[0124] As an optional embodiment of the present application, the first side wall 511 can be obtained by an etching process, that is, a complete film layer is first made on the first mandrel 311, and then the film layer is etched to obtain the first mandrel 311, specifically: as shown in Figures 2 to 4 , Figures 15 to 17 ​As shown, the step of forming the first sidewall 511 on both sides of each first mandrel 311 in step S1 specifically comprises:

[0125] depositing a first sidewall layer 510 on the surface of the first mandrel 311 (as shown in Figures 2 to 3 、 Figures 15 to 16 );

[0126] etching the first sidewall layer 510 to form the first mandrel 311 with a top surface exposed and the vertical first sidewall 511 (as shown in Figures 3 to 4 、 Figures 16 to 17 ).

[0127] As an optional embodiment of the present application, the semiconductor process method further comprises, after the first mandrel 311 and the second mandrel 321 are etched, removing the residual film layer above the mandrel structure (the first mandrel 311 or the second mandrel 321) so as to avoid the influence of the residual structure on the top of the mandrel structure on the normal deposition of the sidewall layer (the first sidewall layer 510 or the second sidewall layer 520).

[0128] The inventors of the present application have also found in research that, in the self-aligned quadruple pattern process, the uniformity of the pitch of the fin structures 10 is also related to the thickness of the first sidewall layer 510. Specifically, as shown in Figure 26 、 Figure 27 , the thickness of the first sidewall layer 510 determines the width value of the first sidewall 511 formed on both sides of each first mandrel 311, and further determines the width value of each second mandrel 321.

[0129] Therefore, if the thickness of the first sidewall layer 510 is too small, the width value of each second mandrel 321 will be too small, which will cause the pitch α between the pair of fin structures 10 corresponding to each second mandrel 321 to be too small, and will cause the pitch between the two fin structures 10 corresponding to different second mandrels 321 to be too large, i.e., the pitch β between the two pairs of fin structures 10 corresponding to the two second mandrels 321 in each group of fin structures 10 and the pitch γ between the adjacent fin structures 10 in different groups will be too large. Conversely, if the thickness of the first sidewall layer 510 is too large, the pitch α will be too large, and the pitches β and γ will be too small.

[0130] Therefore, in order to further improve the uniformity of the pitch of the fin structures 10, as a preferred embodiment of the present application, the uniformity of the pitch of the fin structures 10 can be measured by the difference between the pitch α and other types of pitches (e.g., the pitch β and the pitch γ), and the thickness of the first sidewall layer 510 can be adjusted in feedback according to the difference.

[0131] Specifically, the semiconductor process method further comprises:

[0132] obtaining a thickness value of the first sidewall layer 510;

[0133] establishing a corresponding relationship between the thickness value of the first sidewall layer 510 and a third average value of the interval a between each pair of fin structures 10 corresponding to the plurality of second mandrels 321;

[0134] calculating a third average value of the interval a between each pair of fin structures 10 corresponding to the plurality of second mandrels 321; and a first average value and a second average value to obtain a fourth average value between the third average value and the third average value

[0135] establishing a corresponding relationship between the thickness value of the first sidewall layer 510 and the third difference value

[0136] judging whether the third difference value between the fourth average value and the third average value is within a preset range, if the third difference value is beyond the preset range, adjusting the third process condition to a fourth process condition, and adjusting the width value of the first sidewall 511 when performing the semiconductor process later by the fourth process condition, so that the third difference value tends to zero.

[0137] Considering that there is a certain error in actual detection and adjustment of the parameters for depositing the first sidewall layer 510, in order to avoid frequent adjustment of the process parameters and ensure production efficiency, as a preferred embodiment of the present application, the third preset range is greater than or equal to -0.5 nm and less than or equal to 0.5 nm, that is, when the third difference value is within 0.5 nm, it is considered that the interval between the fin structures 10 corresponding to the thickness of the first sidewall layer 510 is generally uniform, and there is no need to adjust the process parameters when depositing the first sidewall layer 510.

[0138] As an optional embodiment of the present application, adjusting the third process condition to the fourth process condition specifically includes: adjusting the deposition parameters for depositing the first mandrel layer 310 according to the re-determined target thickness of the first sidewall layer 510 to form the fourth process condition, wherein the deposition parameters include at least one of deposition time, deposition gas flow, and temperature.

[0139] ​​​​As a preferred embodiment of the present application, step S6 is performed once every predetermined number of times of step S1, that is, the process parameters of the semiconductor process equipment are calibrated once based on the uniformity of the fin pitch after processing a plurality of wafers, so as to avoid frequent adjustment of the process parameters and improve the efficiency of the semiconductor process.

[0140] As an optional embodiment of the present application, the second side wall 521 can also be obtained through an etching process, that is, a complete film layer is first made on the second mandrel 321, and then the film layer is etched to obtain the first mandrel 311. Specifically, as shown in Figures 2 to 4 、 Figures 15 to 17 In step S1, the step of forming the first side wall 511 on both sides of each first mandrel 311 specifically includes:

[0141] depositing a second side wall layer 520 on the surface of the second mandrel 321 (as shown in Figures 20 to 21 );

[0142] etching the second side wall layer 520 to form the second mandrel 321 with the top surface exposed and the vertical second side wall 521 (as shown in Figures 21 to 22 )。

[0143] As a second aspect of the present application, a semiconductor device system is provided for performing the semiconductor process method provided by the embodiments of the present application.

[0144] The semiconductor device system provided by the present application can adjust the width value of the first mandrel 311 in the next semiconductor process according to the corresponding relationship between the width value of the first mandrel 311 and the fin pitch (i.e. the pitch between the structures 10) in the previous semiconductor process, so as to make the pitch between the plurality of fin structures 10 consistent, thereby being able to feedback adjust the width value of the first mandrel 311 in the next process according to the process results of the previous multiple processes in the mass production process, and further to stabilize and maintain the uniformity of the fin pitch in real time, thereby ensuring the product performance and improving the product yield.

[0145] As an optional embodiment of the present application, the semiconductor device system includes a semiconductor process equipment, a gap detection device and a controller, the semiconductor process equipment is used to form the fin structure 10, the gap detection device is used to detect the pitch between the fin structures 10, and the controller is used to judge whether the pitch between the plurality of fin structures 10 is consistent based on the width value of the first mandrel 311 and the corresponding pitch between the fin structures 10, and if not, adjust the first process condition to the second process condition, and adjust the width value of the first mandrel 311 in the subsequent semiconductor process through the second process condition.

[0146] As an optional embodiment of the present application, the gap detection device can be a scanning electron microscope or an optical line width measurement machine, and the controller can be an advanced process control system. The advanced process control system automatically receives the width value of the first mandrel 311 and the data of the different types of fin pitches obtained finally from the scanning electron microscope or the optical line width measurement machine in real time during each semiconductor process, and establishes the corresponding relationship between the width value of the first mandrel 311 and the value of the fin pitch.

[0147] For example, in the case of a self-aligned quadruple pattern process, the advanced process control system can establish the corresponding relationship between the different width values of the first mandrel 311 (CD1, CD2, CD3) and the three types of fin pitches (the pitch β between the two pairs of fin structures 10 corresponding to the two second mandrels 321 in each group of fin structures 10, the pitch γ between the adjacent two fin structures 10 of different groups, and the pitch α between the pair of fin structures 10 corresponding to each second mandrel 321). As shown in FIG. 4B, based on the foregoing analysis, the width value of the first mandrel 311 mainly affects the pitch β and the pitch γ in the quadruple pattern process, and therefore, as can be seen from the figure, when the width value of the first mandrel 311 is CD3, the pitch β and the pitch γ are closest to each other, and therefore CD3 can be determined as the optimal size of the first mandrel 311, so as to realize feedback control. Figure 28

[0148] It should be noted that the case shown in FIG. 4B is only a schematic embodiment provided for the purpose of understanding, and in actual analysis, the controller needs to record a large amount of data and perform fitting analysis on these data in the manner shown in FIG. 4C, so as to ensure the accuracy of the adjustment of the process parameters (for example, the etching parameters corresponding to the width value of the first mandrel 311 or the process parameters of the deposition process corresponding to the thickness of the first side wall layer 510). Figure 28 Figure 13 It should be noted that the case shown in FIG. 4B is only a schematic embodiment provided for the purpose of understanding, and in actual analysis, the controller needs to record a large amount of data and perform fitting analysis on these data in the manner shown in FIG. 4C, so as to ensure the accuracy of the adjustment of the process parameters (for example, the etching parameters corresponding to the width value of the first mandrel 311 or the process parameters of the deposition process corresponding to the thickness of the first side wall layer 510).

[0149] As an optional embodiment of the present application, the semiconductor device system further comprises a film thickness detection device for detecting the thickness value of the first side wall layer 510 deposited on the first mandrel 311.

[0150] It can be understood that the above embodiments are only exemplary embodiments adopted for the purpose of illustrating the principles of the present application, and the present application is not limited thereto. Various modifications and improvements can be made by those of ordinary skill in the art without departing from the spirit and essence of the present application, and these modifications and improvements are also considered to be within the protection scope of the present application.​​

Claims

1. A semiconductor process method for processing a predetermined substrate, wherein the predetermined substrate comprises a substrate and at least one mandrel layer located on the substrate, characterized in that: The semiconductor process method comprises: Under a first process condition, etching the mandrel layer located at the top layer to form a plurality of first mandrels; Obtaining a width value of each of the first mandrels; forming first side walls on both sides of each of the first core shafts; Etching the predetermined substrate using the first sidewall as a mask to form a plurality of fin structures on the substrate; Obtaining the spacing between the plurality of fin structures; Based on the width value of the first core axis and the corresponding spacing between the fin structures, it is determined whether the spacing between the plurality of fin structures is consistent. If not, the first process condition is adjusted to a second process condition, and the width value of the first core axis is adjusted by the second process condition when the semiconductor process is subsequently performed, so that the spacing between the plurality of fin structures tends to be consistent. Wherein, the core shaft layer is a single-layer structure; The determining whether the spacings between the plurality of fin structures are consistent based on the width of the first core axis and the corresponding spacings between the fin structures includes: Calculating a first difference between an average value of the spacing between each pair of the fin structures in a plurality of pairs of the fin structures corresponding to a plurality of the first core axes and an average value of the spacing between a plurality of adjacent pairs of the fin structures corresponding to different first core axes; Determining whether the first difference is within a preset range; If the first difference exceeds the preset range, the spacings between the plurality of fin structures are inconsistent; The adjusting the first process condition to a second process condition, and adjusting the width of the first mandrel when the semiconductor process is subsequently performed using the second process condition, includes: Establish a one-to-one correspondence between the width value of the first mandrel and the first difference value and perform fitting to find a target width value of the first mandrel within the preset range; The first process condition is adjusted to a second process condition so that a width value of the first mandrel formed later meets a target width value.

2. The semiconductor process method according to claim 1, wherein: The preset range is greater than or equal to -0.5 nm and less than or equal to 0.5 nm.

3. The semiconductor process method according to claim 1 , wherein adjusting the first process condition to a second process condition, and adjusting the width of the first mandrel when the semiconductor process is subsequently performed using the second process condition, comprises: According to the re-determined target width value of the first mandrel, the etching parameters in the step of etching the first mandrel layer are adjusted to form the second process conditions, wherein the etching parameters include at least one of etching time, etching gas flow rate, and temperature.

4. A semiconductor process method for processing a predetermined substrate, wherein the predetermined substrate comprises a substrate and at least one mandrel layer located on the substrate, characterized in that: The semiconductor process method comprises: Under a first process condition, etching the mandrel layer located at the top layer to form a plurality of first mandrels; Obtaining a width value of each of the first mandrels; forming first side walls on both sides of each of the first core shafts; Etching the predetermined substrate using the first sidewall as a mask to form a plurality of fin structures on the substrate; Obtaining the spacing between the plurality of fin structures; Based on the width value of the first core axis and the corresponding spacing between the fin structures, it is determined whether the spacing between the plurality of fin structures is consistent. If not, the first process condition is adjusted to a second process condition, and the width value of the first core axis is adjusted by the second process condition when the semiconductor process is subsequently performed, so that the spacing between the plurality of fin structures tends to be consistent. The predetermined substrate includes a second mandrel layer and a first mandrel layer which are located on the substrate and are stacked in sequence from bottom to top; The etching of the predetermined substrate to form a plurality of fin structures on the substrate includes: etching the second mandrel layer using the first sidewall as a mask to obtain a plurality of second mandrels; forming second side walls on both sides of each of the second mandrels; Etching the substrate using the second sidewall as a mask to form a plurality of fin structures on the substrate; The determining, based on the width of the first core axis and the corresponding spacing between the fin structures, that the spacing between the plurality of fin structures tends to be consistent includes: Calculating a first average value of the spacings between two pairs of the fin structures corresponding to two of the second mandrels in the plurality of groups of the fin structures corresponding to the plurality of first mandrels and a second average value of the spacings between a plurality of pairs of adjacent fin structures corresponding to different groups; determining whether a second difference between the first average value and the second average value is within a preset range, and if the second difference exceeds the preset range, the spacings between the plurality of fin structures are inconsistent; The adjusting the first process condition to a second process condition, and adjusting the width of the first mandrel when the semiconductor process is subsequently performed using the second process condition, includes: Establish a one-to-one correspondence between the width value of the first mandrel and the second difference value and perform fitting to find a target width value of the first mandrel within the preset range; The first process condition is adjusted to a second process condition so that a width value of the first mandrel formed later meets a target width value.

5. The semiconductor process method according to claim 4, wherein: The first sidewalls are formed on both sides of each of the first core shafts, comprising: depositing a first sidewall layer on the surface of the first mandrel under a third process condition; Etching the first sidewall layer to form the first core shaft with an exposed top surface and the first vertical sidewall; The semiconductor process method further includes: Obtaining a thickness value of the first sidewall layer; Calculating a third average value of the spacing between each pair of the fin structures corresponding to the plurality of second core axes, and a fourth average value between the first average value and the second average value, to obtain a third difference between the fourth average value and the third average value; Establishing a corresponding relationship between the thickness value of the first sidewall layer and the third difference; Determine whether the third difference is within a preset range. If the third difference exceeds the preset range, adjust the third process condition to a fourth process condition, and adjust the width value of the first sidewall when the semiconductor process is subsequently performed using the fourth process condition.

6. The semiconductor process method according to claim 5, wherein: According to the re-determined target thickness of the first sidewall layer, deposition parameters for depositing the first mandrel layer are adjusted, where the deposition parameters include at least one of deposition time, deposition gas flow rate, and temperature.

7. The semiconductor process method according to any one of claims 4 or 5, characterized in that: The preset range is greater than or equal to -0.5 nm and less than or equal to 0.5 nm.

8. The semiconductor process method according to claim 4, wherein adjusting the first process condition to a second process condition, and adjusting the width of the first mandrel when the semiconductor process is subsequently performed using the second process condition, comprises: According to the re-determined target width value of the first mandrel, the etching parameters in the step of etching the first mandrel layer are adjusted to form the second process conditions, wherein the etching parameters include at least one of etching time, etching gas flow rate, and temperature.

9. A semiconductor device system, characterized in that: The semiconductor device system is used to perform the semiconductor process method described in any one of 1-8.

10. The semiconductor device system according to claim 9, wherein: The semiconductor device system includes semiconductor process equipment, a gap detection device and a controller. The semiconductor process equipment is used to form the fin structure. The gap detection device is used to detect the spacing between the fin structures. The controller is used to determine whether the spacing between multiple fin structures tends to be consistent based on the width value of the first core axis and the corresponding spacing between the fin structures. If not, the first process condition is adjusted to the second process condition, and the width value of the first core axis is adjusted by the second process condition when the semiconductor process is subsequently performed.

11. The semiconductor device system according to claim 10, wherein: It also includes a film thickness detection device, which is used to detect the thickness of the first sidewall layer deposited on the first core shaft.

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