Driving backplane and manufacturing method thereof, and display panel

Abstract

The present application discloses a driving backplane, a preparation method thereof, and a display panel. The driving backplane includes a substrate, an oxide semiconductor layer, an aluminum oxide layer, a silicon oxide layer, a source electrode, a drain electrode, and a gate electrode. The oxide semiconductor layer is arranged on the substrate and includes a channel and a source contact portion and a drain contact portion located on opposite sides of the channel; the aluminum oxide layer covers the surface of the oxide semiconductor layer, and an opening is provided in the aluminum oxide layer, exposing the channel; the silicon oxide layer is arranged on the side of the aluminum oxide layer away from the oxide semiconductor layer, the silicon oxide layer fills the opening, and contacts with the surface of the channel; the source electrode and the drain electrode are arranged on the side of the silicon oxide layer away from the aluminum oxide layer; the gate electrode is arranged on the side of the oxide semiconductor layer close to the substrate or the side of the silicon oxide layer close to the source electrode. The present application improves the short channel effect in the existing driving backplane and realizes the miniaturized design of thin film transistors.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a driving backplane and a preparation method thereof, and a display panel. Background Art

[0002] With the development of OLED (Organic Light-Emitting Diode) display technology, the application of IGZO (Indium Gallium Zinc Oxide) in OLED backplanes has been in a hot stage in the display industry.

[0003] IGZO has lower leakage current and better mobility than amorphous silicon (a-Si), so it can be used as a semiconductor layer material in thin film transistor devices. However, in the conductorization process of the prior art, the two sides of the channel of the semiconductor layer are usually subjected to conductorization treatment separately. Specifically, plasma surface treatment is performed under an inert gas to capture oxygen in the portion of the semiconductor layer located on both sides of the channel, or hydrogen in the existing film layer is used to diffuse into the portion of the semiconductor layer located on both sides of the channel, thereby achieving conductorization on both sides of the channel. However, in the above process route, the inert gas or hydrogen used in the conductorization process easily diffuses into the channel, resulting in the region where the channel is located being partially conductorized, wherein the conductor length of the channel can be close to 2 microns, which makes it impossible to make the channel length smaller. As the channel length decreases, the short channel effect becomes more obvious, thereby limiting the miniaturization design of thin film transistors. Summary of the Invention

[0004] The embodiments of the present application provide a driving backplane and a method for manufacturing the same, and a display panel to improve the short channel effect in the existing driving backplane and achieve a miniaturized design of thin film transistors.

[0005] The embodiment of the present application provides a driving backplane, which includes:

[0006] substrate;

[0007] an oxide semiconductor layer disposed on one side of the substrate, the oxide semiconductor layer comprising a channel and a source contact portion and a drain contact portion located on opposite sides of the channel;

[0008] an aluminum oxide layer covering a surface of the oxide semiconductor layer, wherein the aluminum oxide layer has an opening, and the opening exposes the channel;

[0009] a silicon oxide layer, disposed on a side of the aluminum oxide layer away from the oxide semiconductor layer, the silicon oxide layer filling the opening and contacting a surface of the channel; and

[0010] a source electrode and a drain electrode, which are arranged on a side of the silicon oxide layer away from the aluminum oxide layer, the source electrode being connected to the source contact portion, and the drain electrode being connected to the drain contact portion; and

[0011] The gate is arranged on a side of the oxide semiconductor layer close to the substrate or a side of the silicon oxide layer close to the source.

[0012] Optionally, in some embodiments of the present application, the length of the channel in the direction from the source contact toward the drain contact is greater than or equal to the opening length of the opening.

[0013] Optionally, in some embodiments of the present application, the length of the channel is in the range of 2 microns to 3 microns.

[0014] Optionally, in some embodiments of the present application, the gate is arranged on a side of the silicon oxide layer close to the source, the orthographic projection of the gate on the plane where the substrate is located covers the orthographic projection of the channel on the plane where the substrate is located, and the line width of the gate is less than or equal to 4 microns.

[0015] Optionally, in some embodiments of the present application, the driving backplane further includes a metal oxide barrier layer, and the metal oxide barrier layer is arranged between the silicon oxide layer and the source electrode.

[0016] Optionally, in some embodiments of the present application, the driving backplane further includes an etch stop layer, wherein the etch stop layer is arranged between the metal oxide barrier layer and the source electrode, and the orthographic projection of the etch stop layer on the plane where the substrate is located covers the orthographic projection of the metal oxide barrier layer on the plane where the substrate is located.

[0017] Optionally, in some embodiments of the present application, the material of the metal oxide barrier layer includes aluminum oxide, and the material of the etch stop layer includes silicon oxide.

[0018] An embodiment of the present application provides a display panel, which includes the driving backplane as described in any of the aforementioned embodiments.

[0019] The present invention also provides a method for preparing a driving backplane, which includes the following steps:

[0020] providing a substrate;

[0021] forming an oxide semiconductor layer on one side of the substrate, the oxide semiconductor layer comprising a channel region and a source region and a drain region located on opposite sides of the channel region;

[0022] forming an aluminum layer on a side of the oxide semiconductor layer away from the substrate, wherein the aluminum layer covers the channel region, the source region, and the drain region;

[0023] performing a thermal oxidation treatment on the aluminum layer to form an aluminum oxide layer, wherein aluminum in the aluminum layer deprives oxygen from the oxide semiconductor layer to make the oxide semiconductor layer conductive, and a portion of the oxide semiconductor layer located in the source region forms a source contact, and a portion of the oxide semiconductor layer located in the drain region forms a drain contact;

[0024] performing patterning on the aluminum oxide layer to form an opening exposing the channel region;

[0025] forming a silicon oxide layer on a side of the aluminum oxide layer away from the oxide semiconductor layer, wherein the silicon oxide layer fills the opening; and

[0026] forming a source electrode and a drain electrode on a side of the silicon oxide layer away from the aluminum oxide layer, wherein the source electrode is connected to the source contact portion, and the drain electrode is connected to the drain contact portion;

[0027] Before or after the step of forming a source and a drain on the side of the silicon oxide layer away from the aluminum oxide layer, the silicon oxide layer is annealed, and oxygen in the silicon oxide layer diffuses into the oxide semiconductor layer to semiconductorize the oxide semiconductor layer, and the portion of the oxide semiconductor layer located in the channel region is formed into a channel.

[0028] Optionally, in some embodiments of the present application, the length of the channel in the direction from the source contact toward the drain contact is greater than or equal to the opening length of the opening, and the length of the channel is in the range of 2 microns to 3 microns.

[0029] The present application provides a driving backplane, a method for preparing the same, and a display panel. The driving backplane provided by the present application forms an aluminum oxide layer on the surface of an oxide semiconductor layer. On the one hand, the oxide semiconductor layer can be made conductive while the aluminum oxide layer is formed, thereby obtaining a source contact and a drain contact. On the other hand, during the process of locally semiconductorizing the oxide semiconductor layer, since the aluminum oxide layer covers the source contact and the drain contact, the barrier effect of the aluminum oxide layer ensures that oxygen in the silicon oxide layer diffuses only into the channel, thereby preventing oxygen from diffusing into the source contact and the drain contact. This prevents the occurrence of a short channel effect, and, under a certain exposure machine precision, reduces the channel length, thereby facilitating a reduction in the size of thin-film transistors, achieving a miniaturized design of thin-film transistors, and improving the resolution of display products. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. The drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0031] Figure 1 This is a schematic structural diagram of the driving backplane provided in the first embodiment of the present application.

[0032] Figure 2 This is a schematic structural diagram of the driving backplane provided in the second embodiment of the present application.

[0033] Figure 3 This is a schematic structural diagram of the driving backplane provided in the third embodiment of the present application.

[0034] Figure 4 This is a schematic structural diagram of the driving backplane provided in the fourth embodiment of the present application.

[0035] Figure 5 1 is a graph showing a change in the diffusion amount of hydrogen in a silicon nitride layer with temperature in a pair of ratios and an embodiment provided in this application.

[0036] Figure 6 This is a schematic structural diagram of the driving backplane provided in the fifth embodiment of the present application.

[0037] Figure 7 This is a schematic structural diagram of the driving backplane provided in the sixth embodiment of the present application.

[0038] Figure 8 It is a structural schematic diagram of the display panel provided in this application.

[0039] Figure 9 It is a flow chart of the method for preparing the driving backplane provided in an embodiment of the present application.

[0040] Figures 10A to 10H yes Figure 9 The schematic diagram of the structure obtained in sequence in each step of the preparation method of the driving backplane shown. DETAILED DESCRIPTION

[0041] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise specified, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the accompanying drawings; and "inside" and "outside" refer to the outline of the device.

[0042] This application provides a driving backplane and a method for manufacturing the same, as well as a display panel. These are described in detail below. It should be noted that the order in which the following embodiments are described does not limit the preferred order of the embodiments.

[0043] Please refer to Figure 1 The first embodiment of the present application provides a driving backplane 100, which includes a substrate 10, an oxide semiconductor layer 11, an aluminum oxide layer 12, a gate insulating layer 13, a gate 14, a dielectric insulating layer 15, a source electrode 16, and a drain electrode 17. The oxide semiconductor layer 11, the gate 14, the source electrode 16, and the drain electrode 17 constitute a thin film transistor (not shown in the figure).

[0044] Specifically, the substrate 10 may be a rigid substrate, such as a glass substrate; or, the substrate 10 may be a flexible substrate, such as a polyimide substrate. The present application does not specifically limit the material of the substrate 10.

[0045] An oxide semiconductor layer 11 is disposed on one side of the substrate 10. Specifically, the material of the oxide semiconductor layer 11 includes one or more of IGZO, IGZTO, IGTO, IZTO, ITO, and IZO. In this embodiment, the material of the oxide semiconductor layer 11 is IGZO. The oxide semiconductor layer 11 includes a channel 111 and a source contact 112 and a drain contact 113 located on opposite sides of the channel 111.

[0046] The aluminum oxide layer 12 covers the surface of the oxide semiconductor layer 11. The aluminum oxide layer 12 is provided with an opening 121, a first via 122, and a second via 123. The opening 121 exposes the channel 111. The first via 122 exposes the source contact 112. The second via 123 exposes the drain contact 113. In this embodiment, the aluminum oxide layer 12 is provided on the entire surface. Because the aluminum oxide layer 12 has good density, the above-mentioned configuration can maximize the water and oxygen barrier effect of the aluminum oxide layer 12, preventing hydrogen from the outside or other film layers from diffusing into the oxide semiconductor layer 11, thereby improving the stability of the thin film transistor.

[0047] The thickness of the aluminum oxide layer 12 may be 10 micrometers to 50 micrometers. In some specific embodiments, the thickness of the aluminum oxide layer 12 may be 10 micrometers, 20 micrometers, 25 micrometers, 30 micrometers, 40 micrometers, 45 micrometers, or 50 micrometers.

[0048] In this embodiment, the preparation process of the aluminum oxide layer 12 and the oxide semiconductor layer 11 may include the following steps: first, an aluminum layer is formed on the surface of the oxide semiconductor layer 11, and then, the aluminum layer is thermally oxidized to oxidize the aluminum in the aluminum layer to form aluminum oxide, thereby forming the aluminum oxide layer 12. At the same time, since the aluminum in the aluminum layer will capture the oxygen in the oxide semiconductor layer 11, the oxide semiconductor layer 11 can be conductive, thereby forming a conductive source contact portion 112 and a conductive drain contact portion 113.

[0049] The gate insulating layer 13 is arranged on the side of the aluminum oxide layer 12 away from the oxide semiconductor layer 11. In this embodiment, the gate insulating layer 13 is a silicon oxide layer. The silicon oxide layer fills the opening 121 and contacts the surface of the channel 111. Under the above setting, in the preparation process of the driving backplane 100, when the system where the film layers such as the silicon oxide layer and the oxide semiconductor layer 11 are located is annealed, the oxygen in the silicon oxide layer will diffuse into the oxide semiconductor layer 11, thereby realizing the local semiconductorization of the oxide semiconductor layer 11, thereby forming a semiconductorized channel 111. Among them, the silicon oxide layer extends from the periphery of the opening 121 to the inside of the opening 121 to improve the diffusion efficiency of oxygen.

[0050] In this embodiment, an aluminum oxide layer 12 is formed on the surface of the oxide semiconductor layer 11. On the one hand, the oxide semiconductor layer 11 can be made conductive while the aluminum oxide layer 12 is formed, thereby obtaining a source contact 112 and a drain contact 113. On the other hand, in the process of locally semiconductorizing the oxide semiconductor layer 11, since the aluminum oxide layer 12 covers the source contact 112 and the drain contact 113, the barrier effect of the aluminum oxide layer 12 can ensure that oxygen in the silicon oxide layer diffuses only into the channel 111, and oxygen does not diffuse into the source contact 112 and the drain contact 113, thereby avoiding the occurrence of the short channel 111 effect. Under a certain exposure machine accuracy, the length of the channel 111 can be reduced, which is beneficial to reducing the size of the thin film transistor and realizing the miniaturization design of the thin film transistor, thereby improving the resolution of the display product.

[0051] The length of the channel 111 from the source contact 112 toward the drain contact 113 is greater than or equal to the length of the opening 121. In this embodiment, the length of the channel 111 from the source contact 112 toward the drain contact 113 is equal to the length of the opening 121. Under the above configuration, when the exposure machine has a certain accuracy, the length of the channel 111 can be controlled by controlling the length of the opening 121, thereby achieving controllability of the length of the channel 111.

[0052] Specifically, in this embodiment, the length of the channel 111 can be reduced to less than 4 microns. Specifically, the length of the channel 111 is in the range of 2 microns to 3 microns. In some embodiments, the length of the channel 111 can be 2 microns, 2.1 microns, 2.2 microns, 2.3 microns, 2.4 microns, 2.5 microns, 2.6 microns, 2.7 microns, 2.8 microns, 2.9 microns, or 3 microns.

[0053] The gate 14 is disposed on the side of the gate insulating layer 13 away from the aluminum oxide layer 12. In this embodiment, the orthographic projection of the gate 14 on the plane of the substrate 10 overlaps the orthographic projection of the channel 111 on the plane of the substrate 10. The line width of the gate 14 is less than or equal to 4 microns. Since the length of the channel 111 is reduced in this embodiment, the line width of the gate 14 can be correspondingly reduced in the design of the line width of the gate 14, thereby further reducing the size of the thin film transistor, saving the space occupied by the thin film transistor, and thus facilitating an increase in the aperture ratio of the display product, thereby further improving the resolution of the display product.

[0054] The gate 14 may be made of a metal such as molybdenum, titanium, or copper, or an alloy of at least two of the above metals. It should be noted that the gate 14 may be a single-layer structure, a double-layer structure, or a multi-layer structure. This embodiment only illustrates a single-layer structure for the gate 14, and this should not be construed as limiting the present application.

[0055] A dielectric insulating layer 15 is disposed on a side of the gate 14 away from the gate insulating layer 13. The dielectric insulating layer 15 covers the gate 14 and the aluminum oxide layer 12. The material of the dielectric insulating layer 15 may include one or more of silicon oxide, silicon nitride, and silicon oxynitride. In this embodiment, the material of the dielectric insulating layer 15 is silicon oxide to avoid the introduction of hydrogen when using silicon nitride or silicon oxynitride, which may affect the stability of the thin film transistor.

[0056] The source electrode 16 and the drain electrode 17 are disposed on a side of the dielectric insulating layer 15 away from the gate electrode 14. The source electrode 16 is connected to the source contact portion 112 through a via hole (not labeled in the figure) and a first via hole 122 in the dielectric insulating layer 15. The drain electrode 17 is connected to the drain contact portion 113 through a via hole (not labeled in the figure) and a second via hole 123 in the dielectric insulating layer 15.

[0057] Furthermore, in this embodiment, the driving backplane 100 further includes a light shielding electrode 18 , a buffer layer 19 , a passivation layer 20 , a connecting electrode 21 and a planarization layer 22 .

[0058] Specifically, the buffer layer 19 is located on a side of the oxide semiconductor layer 11 close to the substrate 10. The material of the buffer layer 19 may include one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0059] The light-shielding electrode 18 is disposed between the substrate 10 and the buffer layer 19. The material of the light-shielding electrode 18 may include a metal such as molybdenum, titanium, or copper, or may include an alloy composed of at least two of the above metals. It should be noted that the light-shielding electrode 18 may have a single-layer structure, a double-layer structure, or a multi-layer structure. This embodiment only illustrates the case where the light-shielding electrode 18 has a single-layer structure, and this is not to be construed as limiting the present application.

[0060] The passivation layer 20 is disposed on a side of the drain electrode 17 away from the dielectric insulating layer 15. The material of the passivation layer 20 may include one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0061] The connecting electrode 21 is disposed on a side of the passivation layer 20 away from the drain electrode 17. The connecting electrode 21 is connected to the drain electrode 17 through a via (not shown) in the passivation layer 20. The material of the connecting electrode 21 can be a transparent conductive oxide such as indium tin oxide or indium zinc oxide.

[0062] The planarization layer 22 is disposed on a side of the connection electrode 21 away from the passivation layer 20. The planarization layer 22 is provided with an opening 121 (not marked in the figure) exposing the connection electrode 21.

[0063] Please refer to Figure 2 The second embodiment of the present application provides a driving backplane 200. The driving backplane 200 provided in the second embodiment of the present application differs from the first embodiment in that: the gate electrode 14 is disposed on the side of the oxide semiconductor layer 11 close to the substrate 10; the dielectric insulating layer 15 is a silicon oxide layer, and the entire silicon oxide layer is disposed on the surface of the aluminum oxide layer 12; and the light shielding electrode 18 and the buffer layer 19 are omitted from the driving backplane 200. That is, in this embodiment, the thin film transistor is a bottom-gate thin film transistor.

[0064] Please refer to Figure 3 The third embodiment of the present application provides a driving backplane 300. The driving backplane 300 provided in the third embodiment of the present application differs from the first embodiment in that the aluminum oxide layer 12 is only provided in the region where the thin film transistors are located. Specifically, the aluminum oxide layer 12 covers the upper surface of the source contact 112 and the upper surface of the drain contact 113 and only covers the side surfaces of the source contact 112 and the side surfaces of the drain contact 113.

[0065] Please refer to Figure 4 The fourth embodiment of the present application provides a driving backplane 400. The driving backplane 400 provided in the fourth embodiment of the present application differs from the first embodiment in that the driving backplane 400 further includes a metal oxide barrier layer 23 disposed between the dielectric insulating layer 15 and the source electrode 16.

[0066] In this embodiment, the metal oxide barrier layer 23 is used to block hydrogen and oxygen. Specifically, on the one hand, the provision of the metal oxide barrier layer 23 can prevent hydrogen in the environment or in other film layers from diffusing into the channel 111, thereby improving the stability of the thin film transistor. On the other hand, during the preparation process of the driving backplane 400, when the relevant film layers in the driving backplane 400, such as the gate insulating layer 13 and the dielectric insulating layer 15, are annealed, the metal oxide barrier layer 23 can prevent oxygen in the gate insulating layer 13 and the dielectric insulating layer 15 from diffusing away from the channel 111. Therefore, when the oxygen content in the gate insulating layer 13 and the dielectric insulating layer 15 is constant, the diffusion probability of oxygen away from the channel 111 can be increased, thereby increasing the diffusion probability of oxygen toward the channel 111, thereby helping to improve the semiconductor efficiency of the channel 111, thereby increasing the resistance of the channel 111 and reducing the carrier concentration, thereby improving the electrical performance of the thin film transistor.

[0067] The metal oxide barrier layer 23 is provided over the entire surface to maximize its barrier effect. Specifically, the material of the metal oxide barrier layer 23 may include one or more of aluminum oxide, molybdenum oxide, or zirconium oxide. In this embodiment, the metal oxide barrier layer 23 is made of aluminum oxide. Leveraging the excellent compactness of aluminum oxide, the metal oxide barrier layer 23 significantly enhances its barrier effect against hydrogen and oxygen.

[0068] When the material of the metal oxide barrier layer 23 is aluminum oxide, in order to prove the barrier performance of the metal oxide barrier layer 23 to hydrogen, as shown in FIG. Figure 5 As shown, the present application measures the diffusion amount of hydrogen before and after the metal oxide barrier layer 23 is provided. Specifically, the present application provides a comparative example and an embodiment. In the comparative example, a glass substrate and a silicon nitride layer provided on the glass substrate are provided. The curve A showing the change of the diffusion amount of hydrogen with temperature when there is no metal oxide barrier layer 23 on the silicon nitride layer is measured. In the embodiment, a glass substrate and a silicon nitride layer and a metal oxide barrier layer 23 provided on the glass substrate in sequence are provided. The curve B showing the change of the diffusion amount of hydrogen with temperature when there is a metal oxide barrier layer 23 on the silicon nitride layer is measured. By Figure 5 It can be seen that after the metal oxide barrier layer 23 is provided, the diffusion amount of hydrogen decreases significantly as the temperature increases. That is, the metal oxide barrier layer 23 in this embodiment can effectively block hydrogen.

[0069] Please refer to Figure 6 The fifth embodiment of the present application provides a driving backplane 500. The driving backplane 500 provided in the fifth embodiment of the present application differs from the fourth embodiment in that the driving backplane 500 further includes an etch stop layer 24, which is disposed between the metal oxide barrier layer 23 and the source electrode 16. The orthographic projection of the etch stop layer 24 on the plane where the substrate 10 is located covers the orthographic projection of the metal oxide barrier layer 23 on the plane where the substrate 10 is located.

[0070] It is understood that, in the process of preparing the source electrode 16 and the drain electrode 17, an etching process is usually required to achieve patterning of the source electrode 16 and the drain electrode 17. In this embodiment, an etching stop layer 24 is provided between the metal oxide barrier layer 23 and the source electrode 16. By utilizing the protective effect of the etching stop layer 24, it is possible to prevent the etching solution used in the etching process from damaging the metal oxide barrier layer 23, thereby further improving the barrier effect of the metal oxide barrier layer 23.

[0071] In this embodiment, the etch stop layer 24 is disposed entirely on the surface of the metal oxide barrier layer 23 to maximize the protective effect of the etch stop layer 24. Specifically, the material of the etch stop layer 24 may include one or more of silicon oxide, silicon nitride, and silicon oxynitride. In this embodiment, the material of the etch stop layer 24 is silicon oxide to avoid the introduction of hydrogen when using silicon nitride or silicon oxynitride, which may affect the stability of the thin film transistor.

[0072] Please refer to Figure 7 The sixth embodiment of the present application provides a driving backplane 600. The driving backplane 600 provided in the sixth embodiment of the present application differs from the first embodiment in that the driving backplane 600 further includes a metal oxide barrier layer 23 disposed between the passivation layer 20 and the planarization layer 22.

[0073] In this embodiment, the material of the passivation layer 20 is silicon oxide to avoid the introduction of hydrogen when using silicon nitride or silicon oxynitride, which may affect the stability of the thin film transistor.

[0074] The metal oxide barrier layer 23 is used to block hydrogen and oxygen. Specifically, on the one hand, the provision of the metal oxide barrier layer 23 can prevent hydrogen in the environment or hydrogen in other film layers from diffusing into the channel 111, thereby improving the stability of the thin film transistor. On the other hand, during the preparation process of the driving backplane 600, when the relevant film layers in the driving backplane 600, such as the gate insulating layer 13, the dielectric insulating layer 15, and the passivation layer 20, are annealed, the metal oxide barrier layer 23 can prevent oxygen in the above three film layers from diffusing away from the channel 111. Therefore, when the oxygen content is constant, by reducing the diffusion probability of oxygen away from the channel 111, the diffusion probability of oxygen toward the channel 111 can be increased, thereby helping to improve the semiconductor efficiency of the channel 111, thereby increasing the resistance of the channel 111 and reducing the carrier concentration, thereby improving the electrical performance of the thin film transistor.

[0075] The metal oxide barrier layer 23 is provided over the entire surface to maximize its barrier effect. Specifically, the material of the metal oxide barrier layer 23 may include one or more of aluminum oxide, molybdenum oxide, or zirconium oxide. In this embodiment, the metal oxide barrier layer 23 is made of aluminum oxide. Leveraging the excellent compactness of aluminum oxide, the metal oxide barrier layer 23 significantly enhances its barrier effect against hydrogen and oxygen.

[0076] Please refer to Figure 8The present application also provides a display panel 1000. The display panel 1000 includes a driving backplane 101 and a light-emitting layer 102 disposed on the driving backplane 101. Specifically, the display panel 1000 can be a liquid crystal display panel, an organic light-emitting diode display panel, a mini light-emitting diode display panel, or a micro light-emitting diode display panel. When the display panel 1000 is a liquid crystal display panel, the driving substrate 101 can be an array substrate, and / or the driving substrate 101 can be directly used in a backlight module to drive the backlight source to emit light.

[0077] The driving backplane 101 may be the driving backplane described in any of the aforementioned embodiments. The specific structure of the driving backplane may refer to the description of the aforementioned embodiments and will not be repeated here.

[0078] Please refer to Figure 9 The present application provides a method for preparing a driving backplane, which comprises the following steps:

[0079] 101: providing a substrate;

[0080] 102: forming an oxide semiconductor layer on one side of the substrate, the oxide semiconductor layer including a channel region and a source region and a drain region located on opposite sides of the channel region;

[0081] 103: forming an aluminum layer on a side of the oxide semiconductor layer away from the substrate, wherein the aluminum layer covers the channel region, the source region, and the drain region;

[0082] 104: thermally oxidizing the aluminum layer to form an aluminum oxide layer. The aluminum in the aluminum layer removes oxygen from the oxide semiconductor layer to make the oxide semiconductor layer conductive. The portion of the oxide semiconductor layer located in the source region forms a source contact, and the portion of the oxide semiconductor layer located in the drain region forms a drain contact.

[0083] 105: Patterning the aluminum oxide layer to form an opening exposing the channel region;

[0084] 106: forming a silicon oxide layer on a side of the aluminum oxide layer away from the oxide semiconductor layer, wherein the silicon oxide layer fills the opening; and

[0085] 107: forming a source electrode and a drain electrode on a side of the silicon oxide layer away from the aluminum oxide layer, wherein the source electrode is connected to the source contact portion, and the drain electrode is connected to the drain contact portion;

[0086] Before or after the step of forming the source and drain on the side of the silicon oxide layer away from the aluminum oxide layer, the silicon oxide layer is annealed, and the oxygen in the silicon oxide layer diffuses into the oxide semiconductor layer to semiconductorize the oxide semiconductor layer, and the portion of the oxide semiconductor layer located in the channel region is formed into a channel.

[0087] Therefore, in the method for preparing the driving backplane provided in this embodiment, after forming an aluminum layer on the side of the oxide semiconductor layer away from the substrate, the aluminum layer is first subjected to a thermal oxidation treatment to simultaneously form the aluminum oxide layer and make the oxide semiconductor layer conductive, thereby obtaining a source contact and a drain contact. Then, the silicon oxide layer is annealed to diffuse oxygen in the silicon oxide layer into the oxide semiconductor layer, thereby locally semiconducting the oxide semiconductor layer and forming a channel. In the process of locally semiconducting the oxide semiconductor layer, since the aluminum oxide layer covers the source contact and the drain contact, the barrier effect of the aluminum oxide layer can ensure that oxygen in the silicon oxide layer diffuses only into the channel, thereby preventing oxygen from diffusing into the source contact and the drain contact, thereby avoiding the occurrence of a short channel effect. Furthermore, under the condition of a certain exposure machine accuracy, the channel length can be reduced, which is conducive to reducing the size of the thin film transistor, realizing a miniaturized design of the thin film transistor, and improving the resolution of the display product.

[0088] Please refer to Figure 9 、 Figures 10A to 10H The following is a detailed description of the manufacturing method of the driver backplane provided by this application through a specific example. It should be noted that this application example only uses the manufacturing method of the driver backplane 500 provided in the aforementioned fifth embodiment as an example, but it should not be understood as a limitation of this application.

[0089] 201: Provide a substrate 10, such as Figure 10A shown.

[0090] Specifically, the substrate 10 may be a rigid substrate, such as a glass substrate; or, the substrate 10 may be a flexible substrate, such as a polyimide substrate. The present application does not specifically limit the material of the substrate 10.

[0091] It should be noted that step 201 also includes the steps of sequentially forming a light-shielding electrode 18 and a buffer layer 19 on the substrate 10 , which will not be described in detail here.

[0092] 202: An oxide semiconductor layer 11 is formed on one side of the substrate 10. The oxide semiconductor layer 11 includes a channel region 11a and a source region 11b and a drain region 11c located on opposite sides of the channel region 11a. Figure 10B shown.

[0093] Specifically, the material of the oxide semiconductor layer 11 includes one or more of IGZO, IGZTO, IGTO, IZTO, ITO, and IZO. In this embodiment, the material of the oxide semiconductor layer 11 is IGZO, and the oxide semiconductor layer 11 is formed by a physical vapor deposition process.

[0094] 203: An aluminum layer 12a is formed on the side of the oxide semiconductor layer 11 away from the substrate 10. The aluminum layer 12a covers the channel region 11a, the source region 11b and the drain region 11c. Figure 10C shown.

[0095] Specifically, the aluminum layer 12a is formed by a physical vapor deposition process.

[0096] 204: The aluminum layer 12a is subjected to a thermal oxidation treatment to form the aluminum layer 12a into an aluminum oxide layer 12. The aluminum in the aluminum layer 12a removes oxygen from the oxide semiconductor layer 11 to make the oxide semiconductor layer 11 conductive. The portion of the oxide semiconductor layer 11 located in the source region 11b is formed as a source contact portion 112, and the portion of the oxide semiconductor layer 11 located in the drain region 11c is formed as a drain contact portion 113. Figure 10D shown.

[0097] 205: Patterning the aluminum oxide layer 12 to form an opening 121 exposing the channel region 11a. Figure 10E shown.

[0098] 206: Form a gate insulating layer 13 on the side of the aluminum oxide layer 12 away from the oxide semiconductor layer 11. The gate insulating layer 13 fills the opening 121. Figure 10F shown.

[0099] The gate insulating layer 13 is a silicon oxide layer. After step 206, the process further includes forming a gate 14, a dielectric insulating layer 15, a metal oxide barrier layer 23 and an etching stop layer 24 on the gate insulating layer 13 in sequence, which will not be described in detail here.

[0100] 207: Annealing the gate insulating layer 13, so that oxygen in the gate insulating layer 13 diffuses into the oxide semiconductor layer 11, so that the oxide semiconductor layer 11 is semiconducted, and the portion of the oxide semiconductor layer 11 located in the channel region 11a is formed into a channel 111, as shown in FIG. Figure 10G shown.

[0101] Specifically, the system comprising the structure formed in the aforementioned steps is annealed, and oxygen in the gate insulating layer 13 diffuses into the channel region 11a, thereby increasing the resistance of the portion of the oxide semiconductor layer 11 located in the channel region 11a, thereby achieving semiconductorization of the channel region 11a, thereby forming the channel 111. The annealing process is performed in clean, dry air at a temperature of 250°C to 350°C for 1 hour.

[0102] 208: A source electrode 16 and a drain electrode 17 are formed on the side of the gate insulating layer 13 away from the aluminum oxide layer 12. The source electrode 16 is connected to the source contact portion 112, and the drain electrode 17 is connected to the drain contact portion 113. Figure 10H shown.

[0103] It should be noted that, in some embodiments, step 207 may also be formed after the steps of forming the source 16 and the drain 17 , which will not be described in detail here.

[0104] After step 208, the passivation layer 20, the connection electrode 21 and the planarization layer 22 are sequentially formed on the source electrode 16 and the drain electrode 17 to form a Figure 10H The structure shown and the related preparation methods are all prior art and will not be described in detail here.

[0105] The above is a detailed introduction to a driving backplane and its preparation method, and a display panel provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea; at the same time, for technical personnel in this field, based on the ideas of the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A driving backplane, characterized in that: include: substrate; an oxide semiconductor layer disposed on one side of the substrate, the oxide semiconductor layer comprising a channel and a source contact portion and a drain contact portion located on opposite sides of the channel; an aluminum oxide layer covering a surface of the oxide semiconductor layer, wherein the aluminum oxide layer has an opening, and the opening exposes the channel; a silicon oxide layer, disposed on a side of the aluminum oxide layer away from the oxide semiconductor layer, the silicon oxide layer filling the opening and contacting the surface of the channel, the silicon oxide layer extending from the periphery of the opening into the opening; as well as A source electrode and a drain electrode are arranged on a side of the silicon oxide layer away from the aluminum oxide layer, the source electrode is connected to the source contact portion, and the drain electrode is connected to the drain contact portion; as well as The gate is arranged on a side of the oxide semiconductor layer close to the substrate or a side of the silicon oxide layer close to the source.

2. The driving backplane according to claim 1, characterized in that: In a direction from the source contact portion toward the drain contact portion, a length of the channel is greater than or equal to an opening length of the opening.

3. The driving backplane according to claim 2, characterized in that: The length of the channel is in the range of 2 micrometers to 3 micrometers.

4. The driving backplane according to claim 3, characterized in that: The gate is arranged on a side of the silicon oxide layer close to the source, the orthographic projection of the gate on the plane where the substrate is located covers the orthographic projection of the channel on the plane where the substrate is located, and the line width of the gate is less than or equal to 4 microns.

5. The driving backplane according to claim 2, characterized in that: The driving backplane further includes a metal oxide barrier layer, and the metal oxide barrier layer is arranged between the silicon oxide layer and the source electrode.

6. The driving backplane according to claim 5, characterized in that: The driving backplane further includes an etch stop layer, which is arranged between the metal oxide barrier layer and the source electrode, and the orthographic projection of the etch stop layer on the plane where the substrate is located covers the orthographic projection of the metal oxide barrier layer on the plane where the substrate is located.

7. The driving backplane according to claim 6, characterized in that: The material of the metal oxide barrier layer includes aluminum oxide, and the material of the etch stop layer includes silicon oxide.

8. A display panel, characterized in that: The driver backplane comprises the driver backplane according to any one of claims 1 to 7.

9. A method for preparing a driving backplane, characterized in that: The following steps are involved: providing a substrate; forming an oxide semiconductor layer on one side of the substrate, the oxide semiconductor layer comprising a channel region and a source region and a drain region located on opposite sides of the channel region; forming an aluminum layer on a side of the oxide semiconductor layer away from the substrate, wherein the aluminum layer covers the channel region, the source region, and the drain region; performing a thermal oxidation treatment on the aluminum layer to form an aluminum oxide layer, wherein aluminum in the aluminum layer deprives oxygen from the oxide semiconductor layer to make the oxide semiconductor layer conductive, and a portion of the oxide semiconductor layer located in the source region forms a source contact, and a portion of the oxide semiconductor layer located in the drain region forms a drain contact; performing patterning on the aluminum oxide layer to form an opening exposing the channel region; forming a silicon oxide layer on a side of the aluminum oxide layer away from the oxide semiconductor layer, wherein the silicon oxide layer fills the opening; as well as forming a source electrode and a drain electrode on a side of the silicon oxide layer away from the aluminum oxide layer, wherein the source electrode is connected to the source contact portion, and the drain electrode is connected to the drain contact portion; Before or after the step of forming a source and a drain on the side of the silicon oxide layer away from the aluminum oxide layer, the silicon oxide layer is annealed, and oxygen in the silicon oxide layer diffuses into the oxide semiconductor layer to semiconductorize the oxide semiconductor layer, and the portion of the oxide semiconductor layer located in the channel region is formed into a channel.

10. The method for preparing a driving backplane according to claim 9, characterized in that: In a direction from the source contact portion toward the drain contact portion, the length of the channel is greater than or equal to the opening length of the opening, and the length of the channel is in a range from 2 micrometers to 3 micrometers.

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