An image sensor and a manufacturing method thereof

Abstract

The application discloses an image sensor and a manufacturing method thereof, and belongs to the technical field of semiconductor manufacturing. The manufacturing method comprises the following steps: providing a substrate; forming a plurality of shallow trench isolation structures on the substrate, and the shallow trench isolation structures divide the substrate into a plurality of light-sensitive areas; injecting ions into the light-sensitive areas multiple times to form a pre-doped area of a photodiode; annealing the light-sensitive areas to form a doped area of the photodiode, wherein the depth of the doped area of the photodiode is greater than the depth of the shallow trench isolation structure; and depositing a polysilicon layer on the substrate, and etching the polysilicon layer to form a control structure. The image sensor and the manufacturing method thereof can reduce the crosstalk between adjacent photodiodes.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor manufacturing technology, and specifically relates to an image sensor and its manufacturing method. Background Technology

[0002] Image sensors are devices that convert light signals into electrical signals and are widely used in fields such as photography, security systems, smart phones, fax machines, scanners, and medical electronics.

[0003] With the continuous development of integrated circuits, the size of photodiodes (PDs) in image sensors is getting smaller and smaller, and the spacing between each photodiode is also getting smaller. When the light intensity of the photodiode is too high, the photoelectrons generated by the pixel overflow into the adjacent pixel unit, making the image too bright, causing blurring, and forming crosstalk. Summary of the Invention

[0004] The purpose of this invention is to provide an image sensor and its manufacturing method, which can reduce crosstalk between adjacent photodiodes.

[0005] To solve the above-mentioned technical problems, the present invention is achieved through the following technical solution:

[0006] This invention provides a method for manufacturing an image sensor, comprising:

[0007] Provide a substrate;

[0008] Multiple shallow trench isolation structures are formed on the substrate, and the shallow trench isolation structures divide the substrate into multiple photosensitive areas;

[0009] Ions are injected multiple times into the photosensitive region to form a pre-doped region of the photodiode;

[0010] The photosensitive area is annealed to form a doped region of the photodiode, wherein the depth of the doped region of the photodiode is greater than the depth of the shallow trench isolation structure; and

[0011] A polysilicon layer is deposited on the substrate and then etched to form a control structure.

[0012] In one embodiment of the present invention, when ions are injected into the photosensitive area, the injection angle of the injected ions is in the range of 15° to 165°.

[0013] In one embodiment of the present invention, when annealing the photosensitive area, the annealing temperature range is 800℃~1200℃.

[0014] The present invention also provides an image sensor, wherein the image sensor comprises:

[0015] Substrate;

[0016] Multiple shallow trench isolation structures are disposed on the substrate, and the shallow trench isolation structures divide the substrate into multiple photosensitive areas;

[0017] The doped region of the photodiode is disposed within the photosensitive region, and the depth of the doped region of the photodiode is greater than the depth of the shallow trench isolation structure; and

[0018] A control structure is disposed on the substrate.

[0019] In one embodiment of the present invention, the substrate further includes a first region, the first region being located on one side of the photosensitive region, and one end of the first region being connected to the photosensitive region.

[0020] In one embodiment of the present invention, the first region is L-shaped.

[0021] In one embodiment of the present invention, the substrate further includes a second region, which is located on the other side of the photosensitive region and is perpendicular to the other end of the first region.

[0022] In one embodiment of the present invention, the doped region of the photodiode fills the photosensitive region, and the doped region has a predetermined distance from the bottom of the substrate.

[0023] In one embodiment of the present invention, the control structure includes a charge integration switch, which is disposed on the doped region of the photodiode and located at the connection between the photosensitive region and the first region.

[0024] In one embodiment of the present invention, the control structure includes a signal amplification switch, and the signal amplification switch is disposed on the first region.

[0025] As described above, the image sensor and its manufacturing method provided by this invention form multiple shallow trench isolation structures on a substrate, dividing the substrate into multiple photosensitive regions, and doped regions of photodiodes are disposed in these photosensitive regions. Furthermore, the doped regions of the photodiodes provided by this invention can prevent crosstalk during photodiode operation. Multiple reset transistors and signal amplifiers are also disposed on the substrate, which can improve the output of the image sensor. The image sensor and its manufacturing method provided by this invention can maximize substrate utilization while avoiding crosstalk between adjacent photodiodes.

[0026] Of course, any product implementing this invention does not necessarily need to achieve all of the advantages described above at the same time. Attached Figure Description

[0027] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a flowchart of a manufacturing method for an image sensor.

[0029] Figure 2 This is a schematic diagram of an image sensor array.

[0030] Figure 3 This is a schematic diagram of the structure of the pad oxide layer and the pad nitride layer in this embodiment.

[0031] Figure 4 For this embodiment Figure 2 A schematic diagram of the shallow trench along the A-A' direction.

[0032] Figure 5 This is a top view of the image sensor array forming the trench isolation structure in this embodiment.

[0033] Figure 6 For this embodiment Figure 5 A schematic diagram of the trench isolation structure along the A-A' direction.

[0034] Figure 7 This is a schematic diagram of the pre-doped region of the photodiode in this embodiment.

[0035] Figure 8 This is a schematic diagram of the doped region of the photodiode in this embodiment.

[0036] Figure 9 This is a top view of the image sensor array control structure in this embodiment.

[0037] Figure 10 For this embodiment Figure 9 A schematic diagram of the control structure in the A-A' direction.

[0038] Figure 11 This is a schematic diagram of the electrical connection of the image sensor in this embodiment.

[0039] Label Explanation:

[0040] 10 Image sensor; 11 Pixel unit; 100 Substrate; 100a Epitaxial structure; 101 Pad oxide layer; 102 Pad nitride layer; 103 Shallow trench; 104 Shallow trench isolation structure; 105 Photosensitive area; 106 First region; 107 Second region; 108 Pre-doped region of photodiode; 109 Doped region of photodiode; 110 Charge integration switch; 111 Signal amplification switch; 112 Reset switch; B Injection angle; M1 Reset transistor; M2 Signal amplifier; M3 Selector; VDD power supply. Detailed Implementation

[0041] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0042] Please see Figure 2 and Figure 9 As shown, in one embodiment of the present invention, an image sensor 10 is provided with a plurality of pixel units 11, each pixel unit 11 containing a photodiode, forming a pixel. The plurality of pixel units 11 form a two-dimensional pixel array. An image is focused onto the pixel array of the image sensor 10 through an imaging lens. Each photodiode converts the light intensity on its surface into an electrical signal, and a control circuit electrically connected to the photodiode selects the pixel to be used, reading out the electrical signal from the pixel. After amplification and noise reduction processing, the signal is output. Each pixel unit 11 may also be provided with a control structure, such as a charge integration switch 110, a reset switch 112, and a signal amplification switch 111. During the operation of the pixel unit 11, the reset switch 112 is first controlled to open the reset tube, resetting the photodiode. Then, sampling is performed; the reset switch 112 is closed, and the charge integration switch 110 is opened, causing the photodiode to work, generating charge and forming an electrical signal output. When the signal amplification switch 111 is opened, the electrical signal on the pixel is amplified.

[0043] Please see Figure 1 and Figure 3 As shown, in one embodiment of the present invention, the method for manufacturing the image sensor includes step S11, providing a substrate.

[0044] Please see Figure 3As shown, in one embodiment of the present invention, the substrate 100 can be any applicable semiconductor material, such as silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), silicon germanium (GeSi), sapphire, or silicon wafers, etc., and also includes stacked structures composed of these semiconductors, or silicon-on-insulator, silicon-on-insulator stacked, silicon-on-insulator stacked, silicon-on-insulator, and germanium-on-insulator, etc., which can be selected according to the fabrication requirements of the image sensor 10. In this embodiment, the substrate 100 is, for example, a silicon wafer semiconductor substrate with an epitaxial structure 100a, and the epitaxial structure 100a is, for example, a homoepitaxial layer. The substrate 100 can be an undoped substrate or a doped substrate. In this embodiment, the substrate 100 is, for example, a P-type substrate.

[0045] Please see Figure 1 and Figure 3 As shown, in one embodiment of the present invention, after obtaining the substrate 100, a shallow trench isolation structure 104 may be formed on the substrate 100. In this embodiment, for example, step S12 may also be included, which involves forming a pad oxide layer and a pad nitride layer on the substrate.

[0046] Please see Figure 3 As shown, in one embodiment of the present invention, the surface of the substrate 100 is first cleaned to remove impurities, and then a pad oxide layer 101 is formed on the substrate 100. The pad oxide layer 101 is, for example, a dense silicon oxide material, and can be formed on the substrate 100 by methods such as thermal oxidation, in-situ water vapor growth, or chemical vapor deposition. In this embodiment, the cleaned substrate 100 is placed in a furnace tube at a temperature of, for example, 900°C to 1150°C, and oxygen is introduced into the furnace tube. The substrate 100 reacts with the oxygen at a high temperature to generate a dense pad oxide layer 101. The thickness of the pad oxide layer 101 is, for example, 5nm to 15nm, specifically, 6nm, 8nm, 10nm, or 14nm.

[0047] Please see Figure 3As shown, in one embodiment of the present invention, after the pad oxide layer 101 is formed, a pad nitride layer 102 is formed on the pad oxide layer 101. The pad nitride layer 102 is, for example, silicon nitride or a mixture of silicon nitride and silicon oxide. In this embodiment, the pad nitride layer 102 is, for example, silicon nitride. The pad oxide layer 101, as a buffer layer, can improve the stress between the substrate 100 and the pad nitride layer 102. In the present invention, the pad nitride layer 102 can be formed on the pad oxide layer 101 by methods such as low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD). Specifically, a substrate 100 with a pad oxide layer 101 is placed in a furnace tube filled with dichlorosilane and ammonia gas, and reacted at a pressure of, for example, 2 Torr to 10 Torr and a temperature of, for example, 700°C to 800°C to deposit a pad nitride layer 102. The thickness of the pad nitride layer 102 can be adjusted by controlling the annealing time. In some embodiments, the thickness of the pad nitride layer 102 is, for example, 40 nm to 120 nm, specifically, 60 nm, 80 nm, 100 nm, or 120 nm. The pad nitride layer 102 can protect the substrate 100 from damage during the etching process.

[0048] Please see as follows Figure 1 , Figure 3 and Figure 4 As shown, in one embodiment of the present invention, after forming the pad oxide layer 101 and the pad nitride layer 102, step S13 is performed to form a shallow trench isolation structure on the substrate.

[0049] Please see Figure 3 , Figure 4 and Figure 6 As shown, in one embodiment of the present invention, after forming the pad nitride layer 102, a plurality of shallow trench isolation structures 104 are formed on the substrate 100. Specifically, a photoresist layer (not shown in the figure) can be formed on the pad nitride layer 102, and a patterned photoresist layer is formed by processes such as exposure and development to define the positions of the shallow trench isolation structures 104. Using the patterned photoresist layer as a mask, the pad nitride layer 102, the pad oxide layer 101, and part of the substrate 100 located under the patterned photoresist layer are quantitatively removed by etching methods such as dry etching, wet etching, or a combination of dry and wet etching to obtain shallow trenches 103. In this embodiment, for example, dry etching is used to form the shallow trenches 103, and the etching gas is, for example, one or a combination of several of the following: chlorine (Cl2), fluoromethane (CF3), difluoromethane (CF2), nitrogen trifluoride (NF3), sulfur hexafluoride (SF6), hydrogen bromide (HBr), or oxygen (O2).

[0050] Please see Figures 4 to 6 As shown, in one embodiment of the present invention, after forming the shallow trench 103, an isolation medium can be deposited in the shallow trench 103, for example, by high-density plasma chemical vapor deposition (HDP-CVD) or high-aspect-ratio process chemical vapor deposition (HARP-CVD), and the isolation medium is, for example, an insulating material such as silicon oxide. The step of forming the isolation medium may include: placing the substrate 100 in a cavity, then introducing a silicon-containing precursor and an oxygen-containing precursor into the cavity, then annealing to form a plasma from the silicon-containing precursor and the oxygen-containing precursor, and then reacting to form the isolation medium in the shallow trench. In this embodiment, the silicon-containing precursor may be tetraethyl orthosilicate, the oxygen-containing precursor may be ozone, and the flow ratio of the oxygen-containing precursor to the silicon-containing precursor may be greater than 20:1.

[0051] Please see Figures 4 to 6 As shown, in one embodiment of the present invention, after the isolation medium is deposited, the isolation medium, the pad nitride layer 102, and the pad oxide layer 101 can be etched first. Then, planarization processes such as Chemical Mechanical Polishing (CMP) are used to bring the top of the isolation medium and the substrate 100 to the same plane, thereby forming multiple shallow trench isolation structures 104, which are flush with the surface of the substrate 100. However, it should be noted that because the pad nitride layer 102 and the pad oxide layer 101 are made of different materials, the removal of the pad nitride layer 102 and the pad oxide layer 101 can be performed in one or two steps. In this embodiment, dry etching can be used, and a mixed gas of CF4 and CHF3 can be used to remove the pad nitride layer 102 and the pad oxide layer 101 in a single etching process. In other embodiments, wet etching can be performed in two stages, for example, using a thermal phosphoric acid etch pad nitride layer 102 with a temperature range of 140°C to 200°C, and a hydrofluoric acid etch pad oxide layer 101 with a concentration between 1% and 10%. By setting multiple shallow trench isolation structures 104, adjacent photodiodes in the image sensor 10, as well as photodiodes and other semiconductor devices, can be isolated, reducing mutual interference between semiconductor devices and improving the performance of the image sensor 10.

[0052] Please see Figure 5 and Figure 6As shown, in one embodiment of the present invention, the formed shallow trench isolation divides the substrate 100 into a plurality of photosensitive regions 105 to form a photodiode. Furthermore, the shallow trench isolation structure 104 also distinguishes a reset transistor and a signal amplifier formation region on one side of each photosensitive region 105. The present invention does not limit the shape of the photosensitive regions 105, nor the formation regions of the reset transistor and signal amplifier. In this embodiment, the substrate 100 includes, for example, the photosensitive region 105, a first region 106 forming the signal amplifier, and a second region 107 forming the reset transistor. The photosensitive region 105 is hexagonal. The first region 106 is disposed on one side of the photosensitive region 105, the first region 106 is L-shaped, and one end of the first region 106 is connected to the photosensitive region 105. The second region 107 is disposed on the other side of the photosensitive region 105, the second region 107 is strip-shaped, and is perpendicular to the other end of the first region 106. In this application, the photodiode in each pixel unit 11 can be controlled independently, and the first region 106 and the second region 107 minimize the distance between adjacent photodiodes without affecting the light-sensing efficiency of adjacent photodiodes.

[0053] Please see Figure 1 and Figure 7 As shown, in one embodiment of the present invention, after forming the shallow trench isolation structure 104, step S14 is performed to implant ions in the photosensitive area to form a pre-doped region of the photodiode.

[0054] Please see Figure 6 and Figure 7 As shown, in one embodiment of the present invention, ions are first implanted into the photosensitive region 105 to form a pre-doped region 108 of the photodiode. This application does not limit the type of ions implanted in each photosensitive region 105, as long as the desired device is formed. In this embodiment, when the substrate 100 is P-type, the ions implanted in each photosensitive region 105 are, for example, N-type ions. Specifically, the implanted ions can be ions with five valence electrons, such as phosphorus ions or arsenic ions. When phosphorus ions replace silicon atoms, they provide a negatively charged electron to the valence band of the crystal, thereby forming the pre-doped region 108 of the N-type photodiode.

[0055] Please see Figure 7 As shown, in one embodiment of the present invention, when ion implantation is performed on the photosensitive region 105, multiple ion implantations at different angles can be performed to ensure the quality and shape of the photodiode formed after ion implantation. In this embodiment, 3 to 5 ion implantations are performed on each photosensitive region 105, and the implantation angle B during ion implantation is, for example, 15° to 165°. Wherein, the implantation angle B is the ion implantation direction (…). Figure 7The angle between the arrow in the diagram and the substrate 100 on the same side relative to the ion implantation direction. During ion doping, the pre-doped region 108 of the photodiode can be extended to the bottom of the shallow trench isolation structure 104 to facilitate ion diffusion to a region with a depth greater than that of the shallow trench isolation structure 104 during annealing.

[0056] Please see Figure 7 As shown, in one embodiment of the present invention, the photosensitive region 105 is subjected to four ion implantations. First, the photosensitive region 105 is subjected to two ion implantations, and the implantation angle B is, for example, 85° to 95°, specifically, 90°, and the ion implantation dose range is, for example, 4 × 10⁻⁶. 12 atoms / cm 2 ~5×10 13 atoms / cm 2 Secondly, ion implantation is performed once, with the implantation angle B being, for example, 35° to 55°, specifically, 45°, and the implantation dose being, for example, 5 × 10⁻⁶. 12 atoms / cm 2 ~5×10 13 atoms / cm 2 Finally, ion implantation is performed once, with the implantation angle B being, for example, 125°–145°, specifically 135°, and the implantation dose being, for example, 5 × 10⁻⁶. 12 atoms / cm 2 ~5×10 13 atoms / cm 2 After multiple ion implantations, such as Figure 7 As shown, a pre-doped region 108 of the photodiode is formed on the photosensitive region 105. The bottom of the pre-doped region 108 is arc-shaped, and the depth of the pre-doped region 108 gradually increases from the side near the shallow trench isolation structure 104 to the center of the photosensitive region 105. During annealing, it can be ensured that ions do not easily diffuse to the bottom of the shallow trench isolation structure 104.

[0057] Please see Figure 1 , Figure 7 and Figure 8 As shown, after ion implantation into the photosensitive region 105, step S15 is performed to anneal the photosensitive region to form the doped region of the photodiode.

[0058] Please see Figure 7 and Figure 8As shown, in one embodiment of the present invention, after ion implantation of the photosensitive region 105 to form a pre-doped region 108 of the photodiode, the photosensitive region 105 is annealed. Ions in the pre-doped region 108 diffuse to a region with a depth greater than that of the shallow trench isolation structure 104, forming a doped region 109 of the photodiode. In this embodiment, the annealing temperature is 800℃~1200℃, and the annealing time is, for example, 60S~120S. After annealing, the depth of the doped region 109 of the photodiode is greater than the depth of the shallow trench isolation structure 104. The doped region 109 of the photodiode does not extend to the bottom of the shallow trench isolation structure 104, and the ions in the doped region 109 of the photodiode after thermal diffusion are uniformly distributed. Furthermore, the doped region 109 of the photodiode fills the photosensitive region 105 between adjacent shallow trench isolation structures 104. This allows the photodiode to convert light into electrons for output as much as possible during operation, avoiding photoelectron saturation overflow and enhancing the isolation between adjacent photosensitive regions 105. The doped region 109 of the photodiode has a predetermined distance from the bottom of the substrate 100. Compared to before annealing, the P-type dopant in the substrate 100 also diffuses upward, which can further enhance the isolation. In this embodiment, by using a method of multiple ion implantation and annealing to enhance the isolation between pixel units 11, it is possible to avoid setting an automatic discharge tube on the pixel unit 11 to remove excess charge, thereby avoiding sacrificing the light-emitting area.

[0059] Please see Figure 7 and Figure 8 As shown, in one embodiment of the present invention, when the photodiode is operating, the P-type region where the substrate 100 is located can be grounded. First, the doped region 109 (heavily doped N-type region) of the photodiode is reset to a positive voltage through a control structure. Then, the photodiode maintains a reverse bias condition and enters an electrically floating state. Due to the built-in electric field, electrons excited by photons tend to accumulate in the doped region 109 of the photodiode, thereby reducing the potential of this region. Simultaneously, holes flow into the ground terminal. In this case, the electrons are the signal charge, which can convert the optical signal into an electrical signal.

[0060] Please see Figure 1 and Figure 9 As shown, in one embodiment of the present invention, after annealing the photosensitive region 105, step S16 is performed to implant ions in the first and second regions to form doped regions for the reset transistor and signal amplifier. The present invention does not limit the specific types of the reset transistor and signal amplifier, nor the shape and position of the implanted ions in the first and second regions 106, as long as the relevant devices can be formed.

[0061] Please see Figure 2 and Figure 9 As shown, in one embodiment of the present invention, the reset transistor and the signal amplifier are, for example, N-type transistors, specifically, NMOS transistors. N-type doped regions are formed in the first region 106 and the second region 107, located on both sides of the reset switch 112 and the signal amplifier switch 111, thus forming an N-type transistor structure. The present invention does not specifically limit the doped regions of the reset switch 112 and the signal amplifier switch 111; an NMOS structure is sufficient.

[0062] Please see Figure 2 and Figure 9 As shown, in one embodiment of the present invention, after forming the doped regions of the photodiode, the reset tube and the signal amplifier, step S17 is performed to form a plurality of control structures on the substrate.

[0063] Please see Figure 9 and Figure 10 As shown, in one embodiment of the present invention, the control structure includes a charge integration switch 110, a reset switch 112, and a signal amplification switch 111. The charge integration switch 110 is disposed on the doped region 109 of the photodiode. The signal amplification switch 111 is disposed on the first region 106, and located between the two N-type doped regions in the first region 106. The reset switch 112 is disposed on the second region 107, and located between the two N-type doped regions in the second region 107.

[0064] For details, please refer to Figure 9 and Figure 10 As shown, in this embodiment, a polysilicon layer can be formed on the substrate 100, and photoresist can be coated on the polysilicon layer. A portion of the photoresist above the polysilicon layer is removed using an alkaline wet process or a dry ashing process to form a patterned photoresist layer. This patterned photoresist layer exposes the locations of the charge integration switch 110, the reset switch 112, and the signal amplification switch 111. Then, using the patterned photoresist layer as a mask, the remaining polysilicon layers except for those at the locations of the charge integration switch 110, the reset switch 112, and the signal amplification switch 111 are removed, thus forming the locations of the charge integration switch 110, the reset switch 112, and the signal amplification switch 111.

[0065] Please see Figure 9 and Figure 10 As shown, in one embodiment of the present invention, a charge integration switch 110 is disposed on the doped region 109 of the photodiode, near the junction of the photosensitive region 105 and the first region 106. A signal amplification switch 111 is disposed on the first region 106, located on the side near the second region 107. A reset switch 112 is disposed on the second region 107, located in the middle of the second region 107, and is on the same straight line as the signal amplification switch 111.

[0066] In some embodiments, after forming multiple control structures, a multilayer metal interconnect structure can be formed on the control structures to electrically connect the control structures to external control circuits.

[0067] Please see Figure 11 As shown, in one embodiment of the present invention, for example, the charge integrating switch 110 is electrically connected to the source of the reset transistor M1, the drain of the reset transistor M1 is electrically connected to the power supply VCC, and the gate of the reset transistor M1 is electrically connected to an external control circuit. The signal amplification switch 111 (the gate of the signal amplifier M2) is electrically connected to the charge integrating switch 110, the drain of the signal amplifier M2 is electrically connected to the power supply VCC, and the source of the signal amplifier M2 is electrically connected to the horizontal selector M3 of the external control circuit. When the image sensor is working, a reset is first performed, that is, a reverse voltage is applied to the PN junction of the photodiode, which activates the reset transistor M1 to reset the PN junction. After the reset is completed, the reset transistor M1 is turned off. Then, the exposure process is performed. Photons hit the doped region 109 of the photodiode and the substrate 100, and after being absorbed, electron-hole pairs are generated. These address holes move through the electric field, reducing the reverse voltage on the PN junction. Then, the readout process is performed. The horizontal selector M3 in the control circuit is activated, and the signal in the PN junction is read out after passing through the signal amplifier M2. Once the conversion is complete, the process of resetting, exposing, and reading out is repeated in a loop.

[0068] In summary, the image sensor and its manufacturing method provided by this invention form multiple patterned shallow trench isolation structures on a substrate, dividing the substrate into a photosensitive region, a first region, and a second region. A photodiode is fabricated within the photosensitive region, a signal amplifier is formed within the first region, and a reset transistor is formed within the second region, thus forming a pixel unit of the image sensor. The image sensor formed by this invention avoids crosstalk between adjacent photodiodes, improving the image sensor's quality.

[0069] Throughout this specification, the terms "one embodiment," "an embodiment," or "a specific embodiment" refer to a particular feature, structure, or characteristic described in connection with an embodiment that is included in at least one embodiment of the invention, but not necessarily in all embodiments. Therefore, the various representations of the phrases "in one embodiment," "in an embodiment," or "in a specific embodiment" in different places throughout the specification do not necessarily refer to the same embodiment. Furthermore, a particular feature, structure, or characteristic of any specific embodiment of the invention may be combined with one or more other embodiments in any suitable manner. It should be understood that other variations and modifications of the embodiments of the invention described and illustrated herein may be based on the teachings herein and will be considered part of the spirit and scope of the invention.

[0070] The embodiments of the present invention disclosed above are merely illustrative of the invention. The embodiments do not exhaustively describe all details, nor do they limit the invention to the specific implementations described. Clearly, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to better understand and utilize the invention. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A method of manufacturing an image sensor, characterized by, Includes the following steps: Provide a substrate; Multiple shallow trench isolation structures are formed on the substrate, and the shallow trench isolation structures divide the substrate into multiple photosensitive areas; Ions are implanted multiple times into the photosensitive region to form a pre-doped region of the photodiode. The bottom of the pre-doped region of the photodiode is arc-shaped, and the depth of the pre-doped region of the photodiode gradually increases from the side near the shallow trench isolation structure to the center of the photosensitive region. The photosensitive area is annealed to form the doped region of the photodiode, and the depth of the doped region of the photodiode is greater than the depth of the shallow trench isolation structure. as well as A polysilicon layer is deposited on the substrate and then etched to form a control structure.

2. The method of manufacturing an image sensor according to claim 1, wherein When ions are injected into the photosensitive area, the injection angle of the injected ions is in the range of 15° to 165°.

3. The method of manufacturing an image sensor according to claim 1, wherein When annealing the photosensitive area, the annealing temperature range is 800℃~1200℃.

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