Lateral Diffused Metal Oxide Semiconductor Device and Its Processing Method

Abstract

The invention relates to a laterally diffused metal oxide semiconductor (LDMOS) device and a processing method thereof. The LDMOS device includes a semiconductor substrate of a first conductivity type, a doped drift region of a second conductivity type formed on at least a part of the substrate, and a body region of the first conductivity type formed in the doped drift region. Source and drain regions of the second conductivity type are respectively formed adjacent to the upper surfaces of the body region and the doped drift region and are laterally spaced from each other. A gate structure is disposed between the source region and the drain region. The gate structure includes a control gate formed above the body region and a field plate formed above the doped drift region. The gate structure is electrically isolated from the body region and the doped drift region by a first insulating layer. An oxide structure is formed on a part of the field plate and a part of the drift region, and the oxide structure overlaps the corner of the field plate.

Description

Technical Field

[0001] The present invention generally relates to electrical, electronic, and computer technologies, and more particularly to devices for use with metal oxide semiconductor field effect transistor devices. Background Art

[0002] Modern wireless communication circuits and systems impose extremely stringent requirements on power and linear performance. For example, such requirements apply to power amplifiers and switching circuits operating at microwave frequencies. These increasing power and linear requirements pose challenges to the design of high-frequency, high-power circuit components. In the past few years, silicon laterally diffused metal oxide semiconductor (LDMOS) power transistors have dominated in such applications. However, as the operability of such devices approaches its limit, other semiconductor materials and / or device structures are needed to meet the high-power and high-linearity requirements of next-generation wireless technologies.

[0003] As is well known, a field plate structure can be employed in LDMOS devices. The field plate is essentially an extension of the gate over the drift region in an LDMOS device. The field plate, typically formed of polysilicon, has been shown to not only increase the breakdown voltage in LDMOS devices but also suppress surface states, which significantly affect the power performance of the device. The large gate polysilicon area also helps to accumulate electrons in the drift region under the field plate during the on-state of the LDMOS device, thereby reducing the on-resistance (R DSon ).

[0004] Unfortunately, although the field plate structure in conventional MOSFET devices helps to increase the breakdown voltage of the device by locally adjusting the electric field, it generates an additional parasitic feedback capacitance from the drain to the gate, also known as the Miller capacitance (C gd ). More specifically, from a circuit perspective, the field plate acts as a gate-drain feedback capacitance, providing additional signal modulation at the input and output terminals of the device. This parasitic feedback capacitance adversely affects the overall high-frequency performance of the device, especially in high-speed switching applications, at least in part due to the additional phase change provided by the feedback path. Summary of the Invention

[0005] As shown in one or more embodiments, the present invention advantageously provides an enhanced field plate structure suitable for integration with LDMOS transistor devices, as well as a method for manufacturing such devices. This field plate structure is advantageously compatible with existing complementary metal oxide semiconductor (CMOS) manufacturing technologies and does not rely on the use of expensive processes and materials (such as dual silicide field plate structures) to achieve a substantial improvement in the high-frequency performance of the device. In addition, embodiments of the present invention advantageously achieve enhanced high-frequency performance, such as by reducing the gate charge (Q g ) and / or reducing the gate-drain capacitance (C gd) without significantly reducing the breakdown voltage and / or on-resistance (R DSon ) in the device.

[0006] According to an embodiment of the present invention, a high-frequency LDMOS device includes: a semiconductor substrate of a first conductivity type; a doped drift region of a second conductivity type, which is formed on at least a part of the substrate, and the polarity of the second conductivity type is opposite to that of the first conductivity type; a body region of the first conductivity type, which is formed in the doped drift region and close to the upper surface of the doped drift region; source and drain regions of the second conductivity type, which are respectively formed near the upper surfaces of the body region and the doped drift region and are laterally spaced from each other; a gate structure including a control gate and a field plate, the control gate is formed above at least a part of the body region, the field plate is formed above at least a part of the doped drift region, the gate structure is disposed between the source region and the drain region and is electrically isolated from the body region and the doped drift region by a first insulating layer, the first insulating layer is formed between the gate structure and the body region and the doped drift region; and an oxide structure, which is formed on a part of the field plate and a part of the doped drift region, and the oxide structure has an angular overlap with the field plate.

[0007] According to an embodiment of the present invention, a method for manufacturing a high-frequency LDMOS device includes the steps of: forming a doped drift region of the first conductivity type, which is formed on at least a part of a semiconductor substrate of the second conductivity type, and the polarity of the second conductivity type is opposite to that of the first conductivity type; forming a body region of the second conductivity type, which is formed in the doped drift region and close to the upper surface of the doped drift region; forming source and drain regions of the first conductivity type, which are respectively formed near the upper surfaces of the body region and the doped drift region and are laterally spaced from each other; forming a gate structure including a control gate and a field plate, the control gate is formed above at least a part of the body region, the field plate is formed above at least a part of the doped drift region, the gate structure is disposed between the source region and the drain region and is electrically isolated from the body region and the doped drift region by a first insulating layer, the first insulating layer is formed between the gate structure and the body region and the doped drift region; and forming an oxide structure, which is formed on a part of the field plate and a part of the doped drift region, and the oxide structure has an angular overlap with the field plate.

[0008] The technology of the present invention can provide substantial beneficial technical effects. The listed embodiments are only examples and should not be construed restrictively. The LDMOS device according to one or more embodiments of the present invention has one or more of the following advantages:

[0009] · Low on-state resistance R DSon ;

[0010] · Reduced parasitic capacitance;

[0011] · Lower switching losses;

[0012] · Higher frequency applications.

[0013] These and other features and advantages of the present invention will become apparent from the following detailed description of exemplary embodiments of the invention and should be read in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The following drawings are provided by way of example only and should not be construed restrictively, where reference numerals (as shown in the figures) indicate corresponding elements in each view, where:

[0015] Figure 1A is a perspective view depicting at least a portion of a laterally diffused metal oxide semiconductor (LDMOS) device having a field plate;

[0016] Figure 1B is a cross-sectional view taken along line A-A' of at least a portion of the LDMOS device as shown in Figure 1A ; Figure 1A in;

[0017] Figure 2 is a perspective view depicting at least a portion of an exemplary LDMOS device according to an embodiment of the present invention, the exemplary LDMOS device including a field plate structure having reduced parasitic capacitance;

[0018] Figure 3 is a cross-sectional view taken along line B-B' of at least a portion of the exemplary LDMOS device of an embodiment of the present invention as shown in Figure 2 ;

[0019] Figure 4 is a cross-sectional view taken along line C-C' of at least a portion of the exemplary LDMOS device of an embodiment of the present invention as shown in Figure 2 ;

[0020] Figure 5 is a perspective view depicting at least a portion of an exemplary LDMOS device of an embodiment of the present invention, the field plate structure of the LDMOS device having a plurality of openings formed therein;

[0021] Figures 6A to 6E is a cross-sectional view taken along line of at least a portion of an exemplary manufacturing step of the LDMOS device of an embodiment of the present invention as shown in Figure 3 ;

[0022] Figure 7Ais a perspective view of at least a part of an exemplary LDMOS device according to an embodiment of the present invention, the LDMOS device including a field plate that forms a structure separated from the gate;

[0023] Figure 7B is a description of as Figure 7A shown perspective view of an exemplary LDMOS device, the LDMOS device including a gate drive circuit connected to the outside;

[0024] Figure 8 is a description of as Figure 1A shown cross-sectional view of an exemplary LDMOS device, conceptually describes the associated parasitic capacitance elements;

[0025] Figure 9 is Figure 7A shown cross-sectional view of an exemplary LDMOS device, conceptually describes the associated parasitic capacitance elements;

[0026] Figure 10 is a cross-sectional view of at least a part of an exemplary LDMOS device, the exemplary LDMOS device being consistent with Figures 2 to 7B shown exemplary LDMOS device, in a preferred embodiment of the present invention, the thick insulating layer is replaced by a local oxidation of silicon (LOCOS) isolation structure;

[0027] Figure 11 is a cross-sectional view of at least a part of an exemplary LDMOS device, the exemplary LDMOS device being consistent with Figure 2 to the exemplary LDMOS device shown in FIG. 7, in a preferred embodiment of the present invention, the thick insulating layer is replaced by a shallow trench isolation (STI) structure;

[0028] Figure 12 is a cross-sectional view of an intermediate step of fabricating an exemplary LDMOS device, the device being the same as the exemplary device shown in Figure 1A and 1B ;

[0029] Figure 13 is a description of Figure 12 shown cross-sectional view of the exemplary LDMOS device after subsequent manufacturing steps have been performed;

[0030] Figure 14 is a description of Figure 12 and Figure 13 shown cross-sectional view of the exemplary LDMOS device after reducing the gate width;

[0031] Figure 15 is a cross-sectional view of at least a part of an exemplary LDMOS device, in a preferred embodiment of the present invention, the LDMOS device being consistent withFigure 3 is the same as the exemplary LDMOS device shown, and the LDMOS device includes a gate separated into a control gate and a field plate portion;

[0032] Figure 16 is a cross-sectional view depicting an intermediate manufacturing step of an exemplary LDMOS device. In a preferred embodiment of the present invention, the LDMOS device is formed in a manner similar to that of the exemplary LDMOS device shown Figure 13 but without a thick oxide structure;

[0033] Figure 17 is a cross-sectional view depicting at least a portion of an exemplary LDMOS device. In a preferred embodiment of the present invention, the LDMOS device is the one shown in Figure 16 after silicidation has been performed;

[0034] Figure 18 is a cross-sectional view depicting at least a portion of an exemplary LDMOS device. In a preferred embodiment of the present invention, the LDMOS device is configured to reduce the impact of oxide boundary variations on the rate of change of the gate silicide length;

[0035] Figure 19 is a cross-sectional view of at least a portion of an exemplary LDMOS device. In a preferred embodiment of the present invention, the exemplary LDMOS device combines the novel processing technology for forming the exemplary LDMOS device shown in Figure 18 with the thick oxide structure of the exemplary LDMOS device shown in Figure 15 ;

[0036] Figure 20 is a cross-sectional view of at least a portion of an exemplary LDMOS device. In a preferred embodiment of the present invention, the exemplary LDMOS device combines the novel processing technology for forming the exemplary LDMOS device shown in Figure 18 with the LOCOS technology for forming the exemplary LDMOS device shown in Figure 10 ;

[0037] Figure 21 is a cross-sectional view of at least a portion of an exemplary LDMOS device. In a preferred embodiment of the present invention, the exemplary LDMOS device combines the novel processing technology for forming the exemplary LDMOS device shown in Figure 18 with the STI technology for forming the exemplary LDMOS device shown in Figure 11 ; and

[0038] Figure 22is a flow chart depicting at least a portion of an exemplary method for fabricating an LDMOS device having reduced sensitivity of gate silicide length variations to oxide edge variations;

[0039] It should be understood that the description of the elements in the figures is for simplicity and clarity of presentation. In commercially viable embodiments, some elements that are useful or necessary but are well-known may not be shown in the figures to reduce clutter in the views. Detailed Description

[0040] As shown in one or more embodiments, the principles of the present invention will be described in an exemplary laterally diffused metal oxide semiconductor (LDMOS) device, as well as a method for fabricating the LDMOS device, the LDMOS device having a field plate structure for improving high-frequency performance without significantly degrading the power and linear performance of the device. However, it should be noted that the present invention is not limited to the specific devices and / or methods shown and described in this application. On the contrary, in light of the teachings of this application, those skilled in the art will readily recognize that many modifications can be made to the illustrated embodiments, and all such embodiments are within the scope of the invention claimed. That is, no limitation of the present invention should be inferred from the embodiments described and recited in this application.

[0041] For purposes of describing and claiming embodiments of the invention, the term "MISFET" as used herein is intended to be construed broadly to include any type of metal-insulator-semiconductor field effect transistor. For example, the term "MISFET" is intended to include semiconductor field effect transistors that use an oxide material as the gate dielectric (i.e., MOSFETs), as well as semiconductor field effect transistors that do not use an oxide material as the gate dielectric. Further, although the initials MISFET and MOSFET refer to "metal", the terms MISFET and MOSFET are also intended to include semiconductor field effect transistors having a gate made of a non-metal material (e.g., polysilicon); the terms "MISFET" and "MOSFET" may be used interchangeably in this application.

[0042] Although the overall manufacturing method and structure of the present application are entirely new, according to one or more embodiments of the present invention, certain individual processing steps required to implement part or multiple parts of the method can utilize conventional semiconductor manufacturing techniques and conventional semiconductor manufacturing tools. These techniques and tools are already familiar to those of ordinary skill in the relevant art. In addition, many processing steps and tools for manufacturing semiconductor devices are also described in many readily available publications, such as "Compound Semiconductor Handbook: Formation, Processing, Characterization, and Devices" by P.H. Holloway et al., published by Cambridge University Press in 2008; and "Processing and Characteristics of Compound Semiconductors" by R.K. Willardson et al., published by Academic Press in 2001. The entire contents of the above two books are incorporated into the present application by reference. It should be emphasized that although some individual processing steps are listed here, these steps are merely illustrative, and those skilled in the art may be familiar with several equally suitable alternatives, which also fall within the scope of the present invention.

[0043] It should be understood that the layers and / or regions shown in the drawings are not necessarily drawn to scale. In addition, for ease of description, one or more semiconductor layers of a type commonly used in such integrated circuit devices may not be explicitly shown in a given figure. However, this does not mean that the semiconductor layers not explicitly shown are omitted in the actual integrated circuit device.

[0044] Figure 1A and 1B are a perspective view and a cross-sectional view, respectively, in which at least a part of an exemplary LDMOS device 100 including a field plate structure is described in the perspective view; Figure 1B For Figure 1A is a cross-sectional view of the LDMOS device 100 along the line A-A' in. Specifically, the LDMOS device 100 includes a substrate 102 that can be formed of single-crystalline silicon. Preferably, impurities or dopants (such as boron, phosphorus, arsenic, etc.) are added to the substrate 102 to change the conductivity type of the material (such as n-type or p-type polarity). In this example, since the LDMOS device 100 is an n-channel transistor and the substrate 102 has a p-type conductivity type, it can be referred to as a p-substrate (P-SUB).

[0045] In this embodiment, a body region 104 (P-BODY) having a p-type conductivity type is formed near the upper surface of the substrate 102, which extends laterally from the source side to the drain side of the device. A lightly doped drift (LDD) region 106 is formed near the upper surface of the substrate 102 and is adjacent to the body region 104 laterally. The LDD region 106 has a conductivity type opposite to that of the body region 104, which is an n-type conductivity type in this embodiment, and is therefore referred to as an n-type drain drift (NDD) region.

[0046] The LDMOS transistor 100 includes a source region 108, a drain region 110, and a gate 112. The source region 108 and the drain region 110 are respectively formed near the upper surface of the substrate 102 and are laterally spaced from each other. Preferably, the source region 108 and the drain region 110 are doped with impurities, for example, through a conventional implantation step, using a known concentration level of impurities, and selectively changing the conductivity type of the material as needed. In this example, the source region 108 and the drain region 110 have an n-type conductivity type.

[0047] The source region 108 is formed in at least a part of the body region 104, and the drain region 110 is formed in at least a part of the NDD region 106. A heavily doped region 114 having the same conductivity type as the body region 104 (p-type in this embodiment) is formed near the upper surface of the substrate 102, is laterally adjacent to the source region 108 and is within the body region, and has physical contact with the LDMOS device 100. The source region 108 is electrically connected to the body contact region 114.

[0048] The gate 112 is formed between the source region 108 and the drain region 110 and is formed on at least a part of the body region. Although not explicitly stated, a thin oxide layer (e.g., silicon dioxide (S i O2)) is formed under the gate 112 to electrically isolate the gate, the source region 108, and the drain region 110 in the LDMOS device 100. As is understood by those skilled in the art, the bias voltage applied to the gate forms a channel in the body region 104 under the gate to control the current between the source region 108 and the drain region 110.

[0049] As Figure 1A and 1B shown, the gate 112 is configured to have a gate extension portion 116 that laterally extends through the NDD region 106 and extends in front of the drain region 110. The gate extension portion 116 is formed on a dielectric layer 118 whose thickness is greater than the thickness of the gate oxide, and the gate extension portion 116 is generally referred to as a field plate. In this example, the field plate 116 is a continuous extension of the gate 112, and its function is to modulate the electric field in the LDMOS device 100, and this function increases the breakdown voltage of the device. The field plate 116 also causes electrons to accumulate near the upper surface of the NDD region 106 at the on-state position of the LDMOS device 100, which reduces the on-resistance (R DS-on ).

[0050] As described above, in the past few years, LDMOS power transistors have dominated in high-power applications, especially in power amplifier applications such as in wireless communication systems. As is well known, in MOSFET devices, a field plate structure is adopted to increase the breakdown voltage of the device by locally modulating the electric field. However, the additional parasitic feedback capacitance generated by the standard field plate structure has an adverse effect on the overall high-frequency performance of the device, making the device simply inapplicable to high-frequency applications without using complex and expensive materials and / or manufacturing processes.

[0051] To meet the frequency performance standards of modern high-frequency applications, a reduction in the parasitic gate-drain capacitance C gd can be adopted. Generally, the capacitance C of a parallel plate capacitor is defined by the following formula:

[0052]

[0053] where ε0 is the absolute permittivity (i.e., the vacuum permittivity ε0 = 8.854×10 ―12 F / m), ε r is the relative permittivity of the dielectric or dielectric material between the parallel plates, A is the surface area of one end of each parallel plate, and d is the distance between the plates (i.e., the thickness of the dielectric material between the plates). Therefore, in order to reduce the capacitance, the thickness of the dielectric material between the plates can be increased and / or the surface area of one or both plates can be reduced.

[0054] To achieve enhanced high-frequency performance in an LDMOS device without significantly affecting the power and linear performance in the device, as shown in one or more embodiments of the present invention, the present invention provides an LDMOS device having a new field plate structure configured to reduce the overlapping region between the gate and the drain, thereby advantageously reducing the parasitic gate-drain capacitance (C gd ) in the device.

[0055] As an embodiment of the present invention, Figures 2 to 4 shown, at least a part of an exemplary LDMOS device 200 is conceptually described, including a field plate structure with reduced parasitic capacitance; Figure 2 is a perspective view describing at least a part of the exemplary LDMOS device 200, Figure 3 is a cross-sectional view along line B-B′ describing at least a part of the exemplary LDMOS device 200, Figure 4is a cross-sectional view of at least a portion of an exemplary LDMOS device 200 along line C-C'. The LDMOS device 200 includes a semiconductor substrate 202. In one or more embodiments, the substrate 202 is formed of single-crystalline silicon (e.g., having a <100> or <111> crystal orientation), and suitable alternative materials may also be used, such as, but not limited to, germanium, silicon-germanium, silicon carbide, gallium arsenide, gallium nitride, or similar materials. Additionally, in one or more embodiments, the substrate 202 is preferably modified by adding impurities or dopants (such as boron, phosphorus, arsenic, etc.) to change the conductivity type (e.g., n-type or p-type) of the material. In one or more embodiments, the substrate 202 has a p-type conductivity type and may thus be referred to as a p-type substrate (P-SUB). By adding a specified concentration level (e.g., about 10 14 to about 10 18 atoms per cubic centimeter) of a p-type impurity or dopant (e.g., a Group III element, such as boron), a p-type substrate can be formed, for example, by using diffusion or implantation steps to change the conductivity type of the material in the desired manner. In one or more alternative embodiments, an n-type substrate can be formed by adding a specified concentration level of an n-type impurity or dopant (e.g., a Group V element, such as phosphorus) to the substrate material.

[0056] A lightly doped drain drift or drain extension region 206 is formed on at least a portion of the substrate 202 near its upper surface. The drain drift region 206 has a conductivity type opposite to that of the substrate 202. In one or more embodiments, when a p-type substrate 202 is used, the drain drift region 206 has an n-type conductivity type, which can be formed by implanting an n-type impurity (such as phosphorus) into a specific region of the substrate using standard CMOS manufacturing techniques, and is thus referred to herein as an n-type drain drift (NDD) region. The doping concentration of the NDD region 206 is closely related to the breakdown voltage of the LDMOS device 200, and thus, among other factors, by controlling the doping level of the NDD region 206, a desired breakdown voltage can be achieved in the device.

[0057] A local low-resistivity body region 204 is formed in at least a portion of the NDD region 206. The conductivity type of the body region 204 is opposite to that of the drain drift region 206. In one or more embodiments, the body region 204 includes a p-type well (or p-well) disposed near the upper surface of the NDD region 206. In this exemplary embodiment, the body region 204 is formed by implanting p-type impurities (such as boron) into a specific region of the NDD region 206 using standard CMOS manufacturing techniques. Although the body region 204 has the same conductivity type as the substrate 202, preferably, it has a higher doping concentration relative to the substrate, so that the body region has a lower resistivity than the substrate, for example, about 0.01 to 0.3 Ω-cm. In one or more other embodiments employing an n-type substrate 202, the body region 204 may include an n-type well formed using similar CMOS manufacturing techniques.

[0058] First and second heavily doped regions having a conductivity type / polarity opposite to that of the substrate 202 (such as n-type) are formed near the upper surface of the LDMOS device 200, and the source region 208 and the drain region 210 of the LDMOS device are defined; the source region is formed in the body region 204, and the drain region is formed in the NDD region. In one or more embodiments, the source region 208 and the drain region 210 are composed of heavily doped n-type material formed using a standard CMOS implantation process. Specifically, standard CMOS manufacturing techniques can inject n-type material into the source region 208 and the drain region 210 to form a first n+ region corresponding to the source region 208 and a second n+ region corresponding to the drain region 210. The n-type material includes donor-type impurity atoms capable of providing electrons, such as, but not limited to, phosphorus, arsenic, antimony, or the like. Injecting n-type material into the source region 208 and / or the drain region 210 results in the carrier electron density in the source region 208 and / or the drain region 210 exceeding the carrier hole density.

[0059] A heavily doped region 211 is formed in the body region, having the same conductivity type as the body region 204 (i.e., p-type in this embodiment), only having a higher doping concentration than the body region. The heavily doped region 211 is formed within the body region 204, near the upper surface of the body region 204 and adjacent to the source region 208 laterally. The heavily doped region 211 forms the body contact region of the LDMOS device 200. For example, in a subsequent metallization step, the source region 208 is electrically connected to the body contact region 211.

[0060] Continue to refer to Figures 2 to 4, the gate 212 is formed over the body region 204, near the upper surface of the wafer, and between the source region 208 and the drain region 210. The gate 212 is electrically isolated from the body region 204 and the NDD region 206 by a thin insulating layer 214 disposed on the upper surface of the wafer where the gate is formed. In some embodiments, the thin insulating layer 214 may be formed of an oxide (e.g., silicon dioxide) and may thus be referred to herein as a gate oxide layer. Although other materials (such as metals) are similarly contemplated for forming the gate, preferably, the gate 212 is formed of heavily doped polysilicon. As is known to those skilled in the art, when a bias voltage is applied between the gate 212 and the source region 208, an inversion layer or channel is induced in the body region 204 under the gate oxide layer 214 by the field effect principle. The function of the channel is to facilitate current flow between the source region 208 and the drain region 210 of the LDMOS device 200 and to control the magnitude of the current according to the applied voltage.

[0061] In Figures 2 to 4 the illustrative embodiment, the gate 212 includes a shielding structure 216. Preferably, the shielding structure 216 is formed as a coextensive type of the gate 212 and extends laterally over at least a portion of the NDD region 206. The shielding structure 216, also referred to as a Faraday shield or a field plate; in one or more embodiments the shielding structure 216 is configured as a stepped structure having a first end adjacent to the gate 212 and a second end that extends laterally from the first end and is disposed over the NDD region 206. The field plate (i.e., the shielding structure) 216 is electrically isolated from the NDD region 206 by an insulating layer 218. In one or more embodiments, the insulating layer 218 is formed as an extension of the gate oxide layer 214, located between the NDD region 206 and the field plate 216, and has a greater thickness relative to the gate oxide layer. In this example, the field plate 216, as an extension of the gate 212, is formed of the same material as the gate (e.g., doped polysilicon), and other embodiments of the present invention are similarly contemplated, where the gate and the field plate are configured as separate structures formed of the same or different materials. The main function of the field plate 216 is to mitigate the local high electric field at the gate edge on the drain side of the LDMOS device 200, which can cause electron injection (e.g., hot carrier injection) into the gate oxide layer 214, resulting in threshold drift and thus degrading linearity.

[0062] As described above, according to aspects of the present invention, the field plate 216 is configured to reduce the overlapping region between the gate and the drain, thereby advantageously reducing the parasitic gate-drain capacitance in the device. Specifically, in one or more embodiments, the field plate 216 is formed to have at least one opening 220 that exposes at least a portion of the underlying NDD region 206. The opening 220 in the field plate 216 is configured to reduce the number of overlapping regions (i.e., the gate portions overlapping with the NDD region), which advantageously reduces the gate-drain capacitance in the LDMOS device 200. The degree of reduction of the gate-drain capacitance affects the size of the opening 220. The gate-drain capacitance is inversely proportional to the area of the opening 220, i.e., the larger the area of the opening 220, the smaller the gate-drain capacitance.

[0063] Although the shape of the opening 220 is rectangular, embodiments of the present invention are not limited to any specific shape or size. For example, in one or more embodiments, the shape of the opening 220 is substantially elliptical. Additionally, field plates having multiple openings are also considered similarly in embodiments of the present invention. Specifically, refer to the alternative embodiment as shown in Figure 5 The field plate 216 in the LDMOS device 500 is configured to have multiple openings 502, 504, and 506, and the field plate 216 covers the NDD region 206. It should be understood that embodiments of the present invention do not limit any specific number of openings, nor any specific shape and / or size of each of the openings 502, 504, and 506.

[0064] Although omitted in Figure 2 as shown in Figure 3 and 4 Preferably, an insulating spacer 222 is formed on the sidewalls of the gate 212 and the field plate 216. The insulating spacer 222 electrically isolates the gate 212 and the field plate 216 from other elements of the LDMOS device 200. Optionally, referring to Figure 3 , an implant layer 224 is formed in the NDD region 206, which is close to the upper surface of the NDD region and is located below the opening 220 between the gate 212 and the field plate 216. In this exemplary embodiment, the implant layer 224 is doped with an n-type impurity having a specific concentration level (e.g., about 10 15 to about 10 18 atoms per cubic centimeter).

[0065] The implant layer 224 is at least partially used to increase the n-type concentration at the channel end closest to the drain region 210, thereby reducing the on-resistance (R DS-on)。The implanted layer 224 is also used to define the channel region under the gate 212, effectively forming an extension of the self-aligned channel, thereby enabling the use of a shorter gate length and enhancing stability. In high-frequency applications, it is desirable that a smaller gate length corresponds to a smaller gate charge (Q g )。When the gate length is reduced below a certain size (e.g., less than the lateral diffusion length of the p-type body region), the p-type body region 204 extends beyond the gate 212, and it becomes difficult for the LDMOS device to conduct. By adding the n-type implanted layer 224, the p-type body region 204 extending beyond the gate 212 will be counter-doped to the n-type conductivity type (as in this exemplary embodiment), thereby making the LDMOS device 200 easier to conduct and less affected by the unstable lateral diffusion of the body region 206.

[0066] In one or more embodiments, a silicide 226 (an alloy of a metal and silicon) layer is formed on at least a portion of the upper surface of the gate 212 and the field plate structure 216 to reduce the resistivity of the gate and the field plate structure. Although not explicitly shown, the silicide layer may also be formed on at least a portion of the upper surface of the source region 208 and the drain region 210 to form low-resistance interconnections between the source region and the corresponding source contact region, and between the drain region and the corresponding drain contact region. The source and drain contact regions (not explicitly shown in the drawings but implied) provide electrical connections to the source region 208 and the drain region 210 of the LDMOS device 200, respectively.

[0067] Using standard CMOS manufacturing steps, once the front-end process for forming the LDMOS device 200 is completed, the LDMOS device can be interconnected with one or more components fabricated on the same wafer to form the desired circuit. This is applied in a series of wafer processing steps, which are collectively referred to as back-end-of-line (BEOL) processing. BEOL processing mainly involves creating metal interconnections isolated by insulating layers (i.e., dielectrics). The insulating material used to form the dielectric layer has traditionally been silicon dioxide (S i O2), and embodiments of the present invention also contemplate the use of other materials (such as silicate glass, etc.).

[0068] As shown in one embodiment of the present invention, this embodiment is only an example and not a restrictive description. For example, Figures 6A to 6E is a cross-sectional view of at least a portion of the intermediate process processing step 600 of the exemplary LDMOS device 200 according to an embodiment of the present invention. Referring to Figure 3 Figure 6A ​, The exemplary processing step 600 starts with a substrate 202 which, in one or more embodiments, includes single-crystalline silicon or alternatively other semiconductor materials such as, but not limited to, germanium, silicon-germanium, silicon carbide, gallium arsenide, gallium nitride, or the like. In the present embodiment, the substrate 202 is doped with a p-type impurity or dopant (e.g., boron, phosphorus, arsenic, etc.) to form a p-type conductive substrate or p-type substrate (P-SUB). Embodiments of the present invention also contemplate the use of an n-type conductive substrate. An NDD region 206 is formed on the upper surface of at least a portion of the substrate 202. In one or more embodiments, the NDD region 206 is preferably formed using an implantation process, e.g., ion implantation.

[0069] As Figure 6B shown, a thick (high-voltage) insulating layer 218 is formed on at least a portion of the upper surface of the NDD region 206. In one or more embodiments, the insulating layer 218 includes an oxide (e.g., silicon dioxide (S i O2)) formed using a standard oxidation process, and other suitable insulating materials may also be considered. A deposition process may also be used to form the high-voltage insulating layer 218. Then the high-voltage insulating layer 218 is patterned using standard lithography and etching, and the resulting structure is as Figure 6B shown.

[0070] In Figure 6C it, a thin insulating (gate oxide) layer 214 is formed, such as by oxidizing the wafer. As previously mentioned, the thickness of the gate oxide layer 214 is less than the thickness of the high-voltage insulating layer 218. The S i O2 used to form the high-voltage insulating layer 218 and the gate oxide layer 214 is generally formed by a chemical reaction driven by oxygen and silicon in a high-temperature environment (e.g., about 800 degrees Celsius to 1200 degrees Celsius); however, even at room temperature, a thin natural oxide layer (e.g., about 1 nanometer (nm) thick) can be formed in an air environment. To grow a thicker oxide in a controllable environment, several known methods can be used, e.g., plasma-enhanced chemical vapor deposition (PECVD).

[0071] Then a polysilicon layer is deposited on at least a portion of the upper surface of the wafer, particularly above the high-voltage insulating layer 218 and the gate oxide layer 214. After the polysilicon layer is patterned and etched, the gate 212 and field plate 216 structures of the LDMOS device 200 are formed. As previously mentioned, in the present exemplary embodiment, the field plate 216 is substantially an extension of the gate 212 and is configured with at least one opening 220 therein for reducing the parasitic gate-drain overlap capacitance C gd .

[0072] Continuing to refer to Figure 6C, a doped body region 204 is formed in a portion of the NDD region 206 and is near the upper surface of the NDD region. In this example, the body region 204 is doped with an impurity having a conductivity type opposite to that of the NDD region (i.e., a p-type impurity), thereby forming the p-type body region of the LDMOS device 200. The body region 204 is preferably formed using an implantation process, e.g., ion implantation, typically followed by annealing at a specified temperature to drive and distribute the impurity in the NDD region 206. By applying a specific bias voltage (e.g., at least equal to the threshold voltage V Figure 2 between the gate and the source region (212 and 208 respectively in t ), an inversion layer or channel is established in the body region 204 under the gate oxide layer 214 of the LDMOS device 200. The function of this channel is to facilitate the current flow between the source region and the drain region in the LDMOS device 200 according to the applied bias voltage.

[0073] Optionally, an implanted layer 224 is formed in the NDD region 206, near the upper surface of the NDD region, under the opening 220 between the gate 212 and the field plate 216. During implantation, the gate 212 and the field plate 216 are preferably used as masks. As described above, the implanted layer 224 in this exemplary embodiment is an n-type implanted layer, which is used to increase the n-type doping concentration level at the channel edge closest to the drain region 210, thereby reducing the on-resistance of the LDMOS device. The implanted layer 224 is also used to confine the channel region under the gate 212 to improve the high-frequency performance.

[0074] In Figure 6D , insulating spacers 222 are formed on the sidewalls of the gate 212 and the field plate 216. In addition, the source region 208 and the drain region 210 are formed, e.g., by using an implantation process (e.g., ion implantation) to generate impurity with a specified concentration level and type, and then a diffusion step is used to promote the distribution of the dopant. Preferably, the source region 208 and the drain region 210 are formed near the upper surfaces of the body region 204 and the NDD region 206 respectively, and are laterally spaced from each other. Preferably, a heavily doped region 211 is formed near the source region 208 using an implantation process, and in the preferred example, this region 211 has a p-type conductivity type and is used as a body contact region.

[0075] As Figure 6EAs shown, a silicide layer 226 is formed on the upper surfaces of the gate 212 and the field plate 216, thereby reducing the resistance of this structure. As is known to those skilled in the art, silicides are typically formed by depositing a metal on the upper surface of a silicon structure and then performing a high-temperature annealing (e.g., about 900 degrees Celsius) to convert the deposited metal into a silicide layer. The silicide layer 226 is formed only in the regions where the deposited metal (the metal component that becomes a silicide after annealing) is in direct contact with silicon, so the process is self-aligned. As is known to those skilled in the art, after the silicide formation is completed, the BEOL process is preferably used to interconnect individual devices (such as transistors, capacitors, resistors, etc.) with the wiring and metallization layers on the wafer.

[0076] Figure 7A FIG. 4 is a perspective view showing at least a portion of an exemplary LDMOS device 700 including an enhanced field plate structure according to an alternative embodiment of the present invention. Specifically, the LDMOS device 700 is configured in a manner consistent with the exemplary LDMOS device 200 shown in Figure 2 . Different from that, the LDMOS device 700 does not have a field plate ( Figure 2 labeled 216) formed as an extension of the gate 212, but includes a shielding structure 702, which is a structure separated from the gate 212. Compared with the field plate structure shown in Figure 2 , the separation of the shielding structure 702 from the gate 212 further reduces the parasitic gate-drain capacitance in the LDMOS device 700. In addition, since the shielding structure 702 is configured as a structure separated from the gate 212, the shielding structure does not have to be formed of the same material as the gate.

[0077] In the present exemplary embodiment, the shielding structure 702 is electrically connected to the gate 212 through a gate electrode 704 and a corresponding conductive via 706. The conductive via 706 is configured to provide a direct electrical connection between the gate electrode 704 and the respective ends of the gate 212 and the shielding structure 702. In one or more embodiments, the ends of the gate 212 and the shielding structure 702 located at the distal end of the conductive via 706 are kept electrically open (i.e., not connected). In addition, the conductive via 706 is adapted to vertically separate the gate electrode 704 from the NDD region 206, thereby further reducing the parasitic gate-drain capacitance. The gate electrode 704 and the conductive via 706 can be formed of a metal (such as an aluminum gate electrode and a tungsten via), and the embodiments of the present invention are not limited to any specific conductive material. In addition, the gate electrode 704 and the conductive via 706 do not have to be formed of the same material.

[0078] Preferably, in one or more embodiments, the gate electrode 704 and / or the conductive via 706 are formed of a high-impedance material. Forming the gate electrode 704 and / or the conductive via 706 with a high-impedance material can minimize the drain electrode voltage spikes coupled to the gate 212 at high switching frequencies, thereby helping to reduce the likelihood of breakdown due to false gate turn-on, which often occurs in high-frequency power switching applications.

[0079] In this embodiment, the gate and shield structure are configured as parallel, independent finger-like structures. Since the shield structure 702 is electrically connected to the gate 212 only at the finger-like ends of the gate and shield structure through the gate electrode 704 and the conductive via 706, the number of electrical couplings of the gate over the NDD region 206 and the parasitic gate-drain capacitance are significantly reduced.

[0080] In an alternative embodiment, the gate 212 and the shield structure 702 are electrically connected together through an external circuit. Specifically, Figure 7B is a perspective view depicting an exemplary LDMOS device 700 as shown in Figure 7A and, according to an embodiment of the present invention, includes being connected to an external gate drive circuit 708. In this exemplary embodiment, the gate electrode ( Figure 7A labeled 704 therein) is divided into a gate electrode 710 and a shield structure electrode 712 that are physically and electrically separated from each other. The gate electrode 708, similar to the gate electrode 704 shown in Figure 7A , is electrically connected to the gate 212 through a corresponding conductive via 706. Similarly, the shield structure electrode 712 is electrically connected to the shield structure 702 through its corresponding conductive via 714.

[0081] Continuing as shown in Figure 7B , the external gate drive circuit 708 is coupled between the gate electrode 710 and the shield structure electrode 712. In one or more embodiments, in addition to providing control signals for independently driving the gate 212 and the shield structure 702, the gate drive circuit 708 also provides a high-impedance (e.g., about 1000 ohms) electrical connection between the gate 212 and the shield structure 702. As previously mentioned, one of the benefits of this high-impedance connection arrangement is to minimize the drain voltage spikes that may be coupled to the gate 212 at high switching frequencies, thereby causing false gate turn-on; this helps to reduce the likelihood of breakdown; that is, when both devices are turned on, the high-voltage power supply is short-circuited to ground through the high-side and low-side MOSFETs.

[0082] Figure 8 is Figure 1A a cross-sectional view of the LDMOS device 100 shown in. Conceptually depicts the parasitic capacitance elements associated with the gate 112 and the field plate 116. For comparison purposes only, Figure 9Yes Figure 7A Cross-sectional view of the LDMOS device 700 shown therein. Parasitic capacitance elements associated with the gate 212 and the shielding structure 702 are conceptually described.

[0083] More specifically, referring to Figure 8 , the LDMOS device 100 includes parasitic gate-drain capacitance elements C gd1 , C gd2 and C gd3 resulting from the extension of the gate 112 and the field plate 116 over the NDD region 106. The capacitance of C gd3 is less than that of C gd2 , at least in part due to the thicker dielectric layer 118 formed on the field plate 116. The distributed parallel capacitance elements C gd1 , C gd2 and C gd3 are added together as the total gate-drain capacitance 100 in the LDMOS device. By comparison, compared with the new configuration of the shielding structure 702 shown in Figure 9 , the elements of the parasitic gate-drain capacitance present in the LDMOS device 700 are C gd1 , C gd2 and C gd3 , where C gd1 is attributed to the slight electrical coupling at the edge of the gate 212 over the NDD region 206, C gd2 is attributed to the slight overlap at the edge of the shielding structure 702 over the NDD region, and C gd3 is attributed to the extension of the shielding structure over the NDD region. However, since a large part of the gate extension over the NDD region in the LDMOS device 700 has been removed, these parasitic gate-drain capacitance elements in the LDMOS device 700 are much smaller compared to the corresponding parasitic capacitance elements in the LDMOS device 100 in FIG. 1A. In addition, since the gate-drain capacitance is the main source of switch-induced false gate turn-on in the LDMOS device, compared with the LDMOS device 100, the LDMOS device 700 will beneficially achieve enhanced device reliability at higher switching frequencies.

[0084] As previously mentioned, to reduce the parasitic capacitance resulting from the extension of the field plate 216 (as shown in Figure 2 ), the thickness of the insulating layer 218 between the field plate (i.e., the shielding structure 702 in Figure 7A and 7B ) and the NDD region is increased. The insulating layer 218 is as shown in Figures 2 to 7B , and preferably, as shown in the embodiments of the present invention, is formed using an oxidation process or an oxide deposition process. To better be compatible with the current semiconductor processing platform, Figure 10 and Figure 11An alternative embodiment is shown in which a high-voltage insulating layer is formed under the field plate 216.

[0085] Specifically, Figure 10 at least a partial cross-sectional view of an exemplary LDMOS device 1000 is described, which is formed in a consistent manner with the exemplary LDMOS device 1000 shown in Figures 2 to 7B . According to an embodiment of the present invention, the high-voltage insulating layer (such as Figure 2 , 7A and the 218 labeled in 7B) is replaced by a local oxidation of silicon (LOCOS) structure 1002. As is known to those skilled in the art, during the LOCOS process, the regions on the wafer that are not to be oxidized are coated with a material (such as silicon nitride) that prevents oxygen diffusion at high temperatures (e.g., about 800 to 1200 °C). In one or more embodiments, the LOCOS structure 1002 is formed by thermally oxidizing silicon in the NDD region 206. During this high-temperature process, the silicon wafer is "consumed" and "replaced" by silicon oxide. Then, a field plate 216 is formed on at least a portion of the LOCOS structure 1002 in a manner consistent with the formation of the field plate 216 on the high-voltage insulating layer 218 shown in Figure 2 .

[0086] Similarly, Figure 11 at least a partial cross-sectional view of an exemplary LDMOS device 1100 is described, which is formed in a manner consistent with the exemplary LDMOS device shown in Figures 2 to 7B . According to an embodiment of the present invention, the high-voltage insulating layer (such as Figure 2 , 7A and the 218 labeled in 7B) is replaced by a shallow trench isolation (STI) structure 1102. As is known to those skilled in the art, the STI structure 1102 is formed early in the semiconductor device manufacturing process, before transistors and other active elements are formed. In one or more embodiments, the STI structure 1102 is formed by etching trenches in a portion of the NDD region 206 (between the implant layer 224 and the drain region 210), depositing one or more dielectric materials (such as silicon dioxide) to fill the trenches, and using a planarization technique such as CMP to remove the excess dielectric material. Then, a field plate 216 is formed on at least a portion of the STI structure 1102 in a manner consistent with the formation of the field plate 216 on the high-voltage insulating layer 218 shown in Figure 2 . However, since the STI structure 1102 is substantially flush with the upper surface of the wafer, the field plate 216 is formed on the NDD region 206 so that it is substantially flush with the gate 212; that is, the field plate is not a stepped structure similar to the field plates shown in Figure 2 , 7A or 7.

[0087] Figure 12is a cross-sectional view depicting an intermediate processing step of an exemplary LDMOS device 1200, which is consistent with the exemplary device 100 shown in Figure 1A and Figure 1B The LDMOS device 1200 includes a substrate 1202 and a doped drain region 1204. The substrate 1202 is preferably of p-type conductivity (P-SUB) in this embodiment, and the doped drain region 1204 is preferably an n-type drain drift (NDD) region in this embodiment. The doped drain region 1204 is formed in the substrate, close to the upper surface of the substrate. When forming the LDMOS device 1200, a photolithographic patterning process is preferably used to define a photoresist layer 1206, which is disposed on the upper surface of an oxide layer formed at the upper end of the wafer. After etching, a thick oxide structure 1208 will remain below the patterned photoresist layer 1206. It should be understood that the thick oxide structure 1208 may include an insulating material or a material other than an oxide. The thick oxide structure 1208 is used to block the drain silicide and maintain the drain voltage in the LDMOS device 1200.

[0088] Now referring to Figure 13 , an LDMOS device 1200 after performing subsequent manufacturing steps is shown. More specifically, in one or more embodiments, the LDMOS device 1200 further includes a drain region 1210 having n-type conductivity (N+), which is formed in the NDD region 1204 close to the upper surface of the NDD region. A body region 1212 is formed in the NDD region 1204 (or in some embodiments, adjacent to the NDD region) close to the upper surface of the NDD region and extends laterally from the source side to the drain side of the LDMOS device 1200. The body region 1212 has a conductivity type opposite to that of the NDD region 1204, which is p-type conductivity (P-BODY) in this embodiment.

[0089] The LDMOS device 1200 includes a source region 1214, which is formed on the upper surface adjacent to the body region 1212 and is laterally spaced apart from the drain region 1210. In a preferred embodiment, the source region and the drain region 1214, 1210 are doped with impurities at a known concentration level through a conventional implantation step and the conductivity of the material can be selectively changed as needed. In this example, the source region and the drain region 1214, 1210 have n-type conductivity, but other embodiments of the present invention are not limited to n-type conductivity.

[0090] A thin oxide layer 1216 is formed on the upper surfaces of at least a portion of the body region 1212 and the NDD region 1204. The thin oxide layer 1216 is used to prevent a direct electrical connection between the gate 1218 and the NDD and body regions 1204, 1212. In this exemplary embodiment, the gate 1218 is formed on the upper surface of the thin oxide layer 1216 and at least a portion of the thick oxide structure 1208. In one or more embodiments, the gate 1218 includes a polysilicon material that may or may not be silicided.

[0091] The gate charge Q associated with the gate 1218 g is proportional to the width of the polysilicon gate. As Figure 14 shown, for some applications where it is desired to reduce the gate charge, such as in most high-frequency and / or high-speed applications, preferably, the width of the polysilicon gate 1218 is reduced (e.g., proportionally). When the width of the gate 1218 is reduced too much, the length L of the gate over the channel in the body region 1212 on the thin oxide layer 1216 becomes very small. Due to the variations inherent in the lithography process and other factors, the boundary position of the thick oxide structure 1208 will change by ΔX. This thick oxide boundary change ΔX remains substantially constant and is independent of the gate width reduction. Thus, as the gate length L becomes smaller, the change ratio ΔX / L becomes unacceptably large, resulting in instability of the LDMOS device. To ensure that the change ratio ΔX / L does not exceed a specified threshold, process guard bands are typically configured to limit the proximity of the thick oxide boundary to the device channel. However, these guard bands limit the amount by which the gate width can be reduced, thus undesirably limiting the high-frequency performance of the LDMOS device.

[0092] According to one or more embodiments of the present invention, the polysilicon gate 1218 is divided into a control gate portion and a field plate portion that are laterally spaced apart from each other. According to one or more embodiments of the present invention, as Figure 15 shown, a cross-sectional view of at least a portion of an exemplary LDMOS device 1500 including a gate 1502 separated into a control gate and a field plate portion. More specifically, in the LDMOS device 1500, the gate 1502 is divided into a control gate 1503 formed on the thin oxide layer 1216 and a field plate 1504 formed on at least a portion of the thick oxide structure 1208. The control gate 1503 and the field plate 1504 are laterally separated and electrically isolated from each other by an isolation structure 1506 formed over the NDD region 1204 between the control gate and the field plate. Arranged in this way, the control gate 1503 will not be affected by the thick oxide boundary change ΔX. In addition, the control gate 1503 can be fully silicided to advantageously provide a reduced and stable gate charge Q g .

[0093] Figure 16 is described in a similar manner toFigure 12 A cross-sectional view of an intermediate processing step of an exemplary LDMOS device 1600 formed in the manner of the exemplary LDMOS device 1200 shown. According to one or more embodiments of the present invention, as Figure 13 shown, there is no thick oxide structure provided. Referring to FIG. 6, the LDMOS device 1600 includes a gate 1602 formed on a thin insulating layer 1604, preferably a polysilicon gate; the thin insulating layer 1604 may include an oxide (e.g., silicon dioxide), disposed on the upper surfaces of at least a portion of the NDD region 1204 and the body region 1212. As shown, the gate 1602 may optionally be defined by insulating sidewall spacers at either end.

[0094] Using photolithographic patterning and etching, an oxide structure 1606 is formed on at least a portion of the upper surfaces of the gate 1602 and the NDD region 1204, leaving an exposed drain region 1210 and a portion of the gate for subsequent silicidation. Thus, at least a portion of the oxide structure 1606 is used to block the drain silicide above the NDD region 1204. As Figure 12 and 13 in the example of the thick oxide structure 1208 shown, due to variations inherent in the photolithography process and other factors, there will be a variation Δx in the position of the edge boundary of the oxide structure 1606. This oxide boundary variation Δx remains substantially constant and is independent of the polysilicon gate width.

[0095] According to one or more embodiments of the present invention, Figure 17 a cross-sectional view of at least a portion of the illustrative LDMOS device 1600 shown in Figure 16 after performing silicidation is described. In this embodiment, the width of the polysilicon gate 1602 is scaled down, thereby reducing the gate charge Q g . The overlapping portion of the oxide structure 1606 on the upper surface of the gate 1602 remains substantially unchanged after the gate width is reduced, leaving only a very small gate silicide length l on the gate upper surface, which is undesirable. Additionally, similar to the previously described gate length change ratio ΔX / L, the LDMOS device 1600 will experience an unacceptably large gate silicide length change ratio Δx / l because the boundary change Δx remains approximately constant and will become the dominant factor in the change ratio as the silicide length l shrinks. This will make the gate resistance R of the LDMOS device 1600 g too unstable to be practically useful. To ensure that the change ratio Δx / l does not exceed a specified threshold, guard bands are provided for the distance between the edge of the oxide structure 1606 and the opposite edge of the gate 1602. These guard bands undesirably limit the amount by which the gate width can be reduced.

[0096] Figure 18is a cross-sectional view depicting at least a portion of an exemplary LDMOS device 1800, which, according to one or more embodiments of the present invention, is configured to reduce the effect of oxide boundary variations on the rate of change of the gate silicide length. Similar to Figure 15 the exemplary LDMOS device 1500 shown in g the LDMOS device 1800 includes a gate 1802 and a field plate 1804. The gate 1802 includes a control gate 1803 formed on a thin oxide layer 1216 proximate to the body region 1212, and the field plate 1804 is formed on the thin oxide layer 1216 on the upper surface of at least a portion of the NDD region 1204. The control gate 1803 and the field plate 1804 are laterally spaced apart by an isolation structure 1806 above the NDD region 1204 between the control gate and the field plate and are electrically isolated from each other. Arranged in this way, the control gate 1803 is not affected by the oxide boundary variation Δx of the oxide structure 1606 that blocks the silicide. In addition, the control gate 1803 can be fully silicided to advantageously provide a reduced gate charge Q g and a reduced and stable gate resistance R

[0097] As can be seen from Figure 18 in the LDMOS device 1800, the silicide-blocking oxide structure 1606 is used in place of Figure 6E the high-voltage insulating layer 218 in the exemplary LDMOS device shown. In one or more embodiments, the oxide structure 1606 is formed as a stepped structure that is provided on a portion of the upper surface of the field plate 1804, the sidewalls of the field plate (which may include sidewall spacers), and a portion of the upper surface of the NDD region 1204 so as to overlap the corners of the field plate. One advantage of fabricating the LDMOS device 1800 in this way is that it provides a beneficial reduction in the number of required process steps. More specifically, for a low-voltage LDMOS, the thick oxide layer ( Figure 6E 218 in

[0098] is not necessary to maintain the drain voltage, and thus the oxide structure 1606 can replace the thick oxide layer 218 in the device of FIG. 6. This oxide structure 1606 is also used to block the silicide layer that might otherwise undesirably form on the upper surface of the NDD region 1204 (between the field plate 1804 and the drain region), and no additional thick oxide process is required to prevent silicidation of the undesired NDD region. Figures 19 - 21 The feature techniques of the present invention can be extended for use in combination with other isolation structures, as exemplified by Figure 19is a cross-sectional view depicting at least a portion of an exemplary LDMOS device 1900 that will be used to form Figure 18 a novel processing technique for an LDMOS device 1800 with that of a thick oxide structure 1208 of an LDMOS device 1500 as shown in Figure 15 . Referring to Figure 19 , LDMOS device 1900 includes a gate 1902 and a field plate 1904. The gate 1902 includes a control gate 1903 formed on a thin oxide layer 1216, and a field plate 1904 formed on at least a portion of the thick oxide structure 1208. The control gate 1903 and the field plate 1904 are laterally separated and electrically isolated from each other by an isolation structure 1906 formed above an NDD region 1204 between the control gate and the field plate.

[0099] As previously described, when configured in the above manner, the control gate 1903 will not be affected by variations in the thick oxide boundary inherent in the processing. Using photolithographic patterning and etching, an oxide structure 1606 is formed on at least a portion of the upper surface of the field plate 1904 and the thick oxide structure 1208, leaving an exposed drain region 1210 and a portion of the field plate for subsequent formation of a silicide layer 1908 thereon. The oxide structure 1606 prevents at least a portion of the field plate 1904 from being silicided, while allowing the control gate 1903 to be fully silicided to provide a reduced and stable gate charge Q g and gate resistance R g . Forming the LDMOS device 1900 in this manner advantageously provides a more relaxed processing window. Specifically, by insulating the left boundary of the oxide structure 1606 without directly setting it on the thick oxide structure 1208 (which can lead to process defects), the yield can be advantageously increased.

[0100] Similarly, according to one or more embodiments of the present invention, Figure 20 a cross-sectional view of at least a portion of an exemplary LDMOS device 2000 is described, which will be used to form Figure 18 a novel processing technique for an LDMOS device 1800 as shown in with that of a LOCOS technique for an LDMOS device 1000 as shown in Figure 10 . Referring to Figure 20 , the LDMOS device 2000 is substantially the same as the LDMOS device 1900 depicted in Figure 19 , except that the thick oxide structure 1208 is replaced by a LOCOS structure 2002.

[0101] As previously combined with Figure 10As described, during LOCOS processing, regions of the wafer that are not to be oxidized are coated with a material that prevents oxygen diffusion at high temperatures (e.g., approximately 800 to 1200 °C). In one or more embodiments, the LOCOS structure 2002 is formed by thermally oxidizing silicon in the NDD region 1204. During this high-temperature processing, the silicon wafer is "consumed" and "replaced" by silicon oxide. Then, a field plate 1904 is formed on at least a portion of the LOCOS structure 2002 in a manner consistent with Figure 19 the manner of forming a field plate on the thick oxide structure 1208 as shown therein.

[0102] Similarly, in one or more embodiments of the present invention, Figure 21 a cross-sectional view of at least a portion of an exemplary LDMOS device 2100 is described, which exemplary LDMOS device 2100 will be used to form Figure 18 a novel processing technique for the exemplary LDMOS device 1800 as shown is combined with the STI technique for forming the exemplary LDMOS device 1100 as shown in Figure 11 . Referring to Figure 21 , the LDMOS device 2100 is substantially the same as the LDMOS device 1900 described in Figure 19 , except that the thick oxide structure 1208 is replaced by the STI structure 2102.

[0103] The STI structure 2102 is typically formed early in the semiconductor device processing; specifically, before transistors and other active elements are formed. In one or more embodiments, the STI structure 2102 is formed by etching a trench in a portion of the NDD region 1204 between the body region 1212 and the drain region 1210, depositing one or more dielectric materials (e.g., silicon dioxide) to fill the trench, and removing the excess dielectric material using a planarization process (e.g., CMP). Then, a field plate 1904 is formed on at least a portion of the upper surface of the STI structure 2102 in a manner consistent with Figure 19 the manner of forming a field plate on the thick oxide structure 1208 as shown. However, since the STI structure 2102 is substantially coplanar with the upper surface of the wafer, the field plate 1904 will be formed above the NDD region 1204 such that it is substantially coplanar with the control gate 1903; that is, the field plate 1904 will not be formed as a stepped structure as in Figure 19 and 20 , but will be formed in the same plane as the control gate 1903.

[0104] In one or more embodiments of the present invention, Figure 22 a flowchart of at least a portion of an exemplary method 2200 for manufacturing an LDMOS device is described, which LDMOS device has reduced sensitivity to the ratio of gate silicide length change to oxide boundary change. Referring toFigure 22 Method 2200 begins at step 2202 by using oxide diffusion (OD), STI, or other processes to determine the active region in the semiconductor structure. The LDMOS device will ultimately be formed in this active region. In step 2204, an implantation process (such as ion implantation) is used to form the NDD or well region of the LDMOS device.

[0105] After forming a polysilicon layer on the oxide layer on the upper surface of the structure, in step 2206, the polysilicon layer is patterned, for example, using standard lithography processes to form the gate of the LDMOS device. In one or more embodiments, the gate is formed as a multi-segment structure, including a control gate and a field plate portion (e.g., 1503 and 1504 in Figure 15 respectively), as previously described. In step 2208, an epitaxial implantation process is implemented to form a channel in the LDMOS device. Then, in step 2210, an insulating (e.g., dielectric) spacer is formed at least on the sidewalls of the gate and the field plate portion, and / or between the control gate and the field plate portion (e.g., the isolation structure 1506 in Figure 15 ). Then an implantation process (such as ion implantation, etc.) is used in step 2210 to form the source region and the drain region in the LDMOS device. The source region and / or the drain region are preferably self-aligned with the insulating spacer.

[0106] Next, in step 2212, a layer of oxide is formed on the upper surface of the device, followed by photolithographic patterning and etching to form a silicide-blocking oxide structure (e.g., 1606 in Figure 16 ). The silicide-blocking oxide structure, as the name implies, is preferably used to block the formation of a silicide layer on the upper surface of the NDD region in the LDMOS device and can also be used to prevent the field plate portion of the gate from being fully silicided. The silicide-blocking oxide structure is used to replace the high-voltage insulating layer in the LDMOS device (e.g., 218 in Figure 2 ). Compared with other LDMOS device manufacturing techniques, the formation of the silicide-blocking oxide structure beneficially reduces the number of process steps required. In step 2214, contacts, vias, and / or other backend metals (such as M1, M2, etc.) are formed, for example, using standard metallization techniques.

[0107] At least a portion of the techniques of the present invention may be implemented in an integrated circuit. During the formation of an integrated circuit, identical chips are typically fabricated in a repetitive manner on the surface of a semiconductor wafer. Each wafer includes the devices described in this application and may also include other structures and / or circuits. Individual chips are cut or diced from the wafer and then packaged into an integrated circuit. Those skilled in the art should know how to cut and package wafers to produce integrated circuits. Any exemplary structure or device or portion thereof shown in the drawings may be part of an integrated circuit. Accordingly, an integrated circuit fabricated using the technical solution of the present invention is considered part of the present invention.

[0108] Those skilled in the art know that the above-described exemplary structures may be distributed in an unprocessed form (i.e., a single wafer with multiple unpackaged chips), a bare die, a packaged form, or incorporated as part of an intermediate or final product that benefits from LDMOS devices formed in accordance with one or more embodiments of the present invention, such as a power management IC, a radio frequency power amplifier, etc.

[0109] The integrated circuits disclosed in accordance with the present invention can be used, in general, in any high-frequency, high-power applications and / or electronic systems. Systems suitable for the embodiments of the present invention include, but are not limited to, DC-DC converters. A system incorporating such an integrated circuit is considered part of the present invention. Given the teachings provided by the present disclosure, those skilled in the art will be able to conceive of other embodiments and applications of the embodiments of the present invention.

[0110] The illustrations of the embodiments of the invention described in this application are intended to provide an overall understanding of the various embodiments and are not intended as a complete description of all elements and features of the devices and systems that may use the circuits and techniques described in this application. Given the teachings herein, many other embodiments will become apparent to those skilled in the art; other embodiments can be utilized and derived therefrom, and structural and logical substitutions and changes can be made without departing from the scope of the present disclosure. The drawings are also merely representative and are not drawn to scale. Accordingly, their specifications and images should be regarded as explanatory and not restrictive.

[0111] The term "embodiments" as used singly and / or collectively in this agreement for the embodiments of the present invention is for convenience only and is not intended to limit the scope of this application to any one embodiment or inventive concept if this application actually recites more than one embodiment or inventive concept. Accordingly, although specific embodiments have been illustrated and described in this agreement, it should be understood that other embodiments that achieve the same purpose may replace the specific embodiments shown; that is, the present disclosure is intended to cover any and all adaptations or variations of the various embodiments. Combinations of the above embodiments, as well as other embodiments not specifically described herein, will become apparent to those skilled in the art from the teachings of this application.

[0112] The terms used in this agreement are only for describing specific embodiments and are not intended to limit the present invention. Unless the context clearly indicates otherwise, the singular forms "a", "the", and "said" used in this agreement also include their plural forms. It should be further understood that when the terms "comprise" and / or "comprising" are used in this application, only the presence of the described features, steps, operations, elements, and / or components is stipulated, but the presence or addition of one or more other features, steps, operations, elements, components, and / or their groups is not excluded. Terms such as "above", "below", "on top", and "beneath" are used to indicate the relative positional relationship between elements or structures, rather than the absolute position.

[0113] In the claims, the corresponding structures, materials, steps, and equivalents of all method or act-plus-function elements are intended to include any structure, material, or act for performing the recited function in combination with other elements in the claim. The description of various embodiments is provided for purposes of illustration and description only and is not intended to be exhaustive or limited to the disclosed forms. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiments selected for description herein are chosen to best explain the principles of the invention and its practical application and to enable those of ordinary skill in the art to understand the invention with various modifications as are suited to the particular use contemplated.

[0114] The abstract is provided to comply with the requirements of 37 C.F.R. § 1.72(b), which requires the abstract to enable the reader to quickly ascertain the nature of the technical disclosure. The submission of the abstract is on the premise that it will not be used to interpret or limit the scope or meaning of the claims. Additionally, in the above description, it can be seen that for the purpose of simplifying the disclosure, various features are combined in one embodiment. This manner of disclosure should not be construed as requiring more features in the claimed embodiments than are expressly recited in each claim. On the contrary, as reflected in the appended claims, the inventive subject matter does not lie in all the features of a single embodiment. Accordingly, the following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate claim.

[0115] In view of the description of the embodiments of the present invention provided herein, those of ordinary skill in the art will be able to conceive of other implementation methods and applications of the technology of the embodiments of the present invention. Although the exemplary embodiments of the present invention have been described with reference to the accompanying drawings, it should be understood that the embodiments of the present invention are not limited to such exact embodiments, and those skilled in the art can make various other changes and modifications without departing from the scope of the appended claims.

Claims

1. A laterally diffused metal oxide semiconductor (LDMOS) device, comprising: A semiconductor substrate of a first conductivity type; A doped drift region of a second conductivity type, which is formed on at least a part of the substrate, and the polarity of the second conductivity type is opposite to that of the first conductivity type; A body region of the first conductivity type, which is formed in the doped drift region and close to the upper surface of the doped drift region; Source and drain regions of the second conductivity type, which are respectively formed near the upper surfaces of the body region and the doped drift region and are laterally spaced from each other; A gate structure, including a control gate and a field plate, the control gate is formed above at least a part of the body region, the field plate is formed above at least a part of the doped drift region, the gate structure is disposed between the source region and the drain region and is electrically isolated from the body region and the doped drift region by a first insulating layer, and the first insulating layer is formed between the gate structure and the body region and the doped drift region; And An oxide structure, which is formed on a part of the field plate and a part of the doped drift region, and the oxide structure overlaps with the corner of the field plate.

2. The LDMOS device according to claim 1, wherein It further includes a silicide layer, which is formed on the upper surface of the control gate, the upper surface of the part of the field plate not covered by the oxide structure, and the upper surfaces of the source region and the drain region.

3. The LDMOS device according to claim 2, wherein The control gate is fully silicided.

4. The LDMOS device according to claim 1, wherein It further includes an isolation structure, which is formed on the doped drift region between the control gate and the field plate.

5. The LDMOS device according to claim 4, wherein The isolation structure is formed on at least one sidewall of each of the control gate and the field plate.

6. The LDMOS device according to claim 1, wherein It further includes a plurality of insulating spacers, which are at least formed on the sidewalls of the control gate and the field plate.

7. The LDMOS device according to claim 1, wherein, The control gate and the field plate are formed to be substantially in the same plane relative to each other.

8. The LDMOS device according to claim 1, characterized in that, It further includes a thick oxide structure, which is formed on the upper surface of the doped drift region, at least a part of the field plate is formed on the upper surface of the thick oxide structure, at least a part of the oxide structure is formed on the thick oxide structure, and the thick oxide structure extends laterally across the doped drift region to the drain region.

9. The LDMOS device according to claim 1, wherein It further includes a local oxidation of silicon (LOCOS) structure, which is formed in the doped drift region adjacent to the upper surface of the doped drift region, at least a part of the field plate is formed on the upper surface of the LOCOS structure, at least a part of the oxide structure is formed on the LOCOS structure, and the LOCOS structure extends laterally in the doped drift region to the drain region.

10. The LDMOS device according to claim 1, characterized in that, It further includes a shallow trench isolation (STI) structure, which is formed in the doped drift region and adjacent to the upper surface of the doped drift region, at least a part of the field plate is formed on the upper surface of the STI structure, so that the field plate is substantially in the same plane as the control gate, at least a part of the oxide structure is formed on the STI structure, and the STI structure extends laterally in the doped drift region to the drain region.

11. A method for fabricating a laterally diffused metal oxide semiconductor (LDMOS) device, the method comprising the following steps: Forming a doped drift region of a second conductivity type, the doped drift region being formed on at least a portion of a semiconductor substrate of a first conductivity type, the polarity of the second conductivity type being opposite to that of the first conductivity type; Forming a body region of a first conductivity type, the body region being formed in the doped drift region and near the upper surface of the doped drift region; Forming a source region and a drain region of a second conductivity type, respectively formed near the upper surfaces of the body region and the doped drift region and laterally spaced from each other; Forming a gate structure including a control gate and a field plate, the control gate being formed above at least a portion of the body region, the field plate being formed above at least a portion of the doped drift region, the gate structure being disposed between the source region and the drain region and being electrically isolated from the body region and the doped drift region by a first insulating layer, the first insulating layer being formed between the gate structure and the body region and the doped drift region; And Forming an oxide structure, the oxide structure being formed on a portion of the field plate and a portion of the doped drift region, the oxide structure overlapping the corner of the field plate.

12. The method according to claim 11, wherein Further comprising forming a silicide layer, the silicide layer being formed on the upper surface of the control gate, the upper surface of the portion of the field plate not covered by the oxide structure, and the upper surfaces of the source region and the drain region.

13. The method according to claim 12, further comprising fully siliciding the control gate.

14. The method according to claim 11, wherein Further comprising forming an isolation structure, the isolation structure being formed on the doped drift region between the control gate and the field plate.

15. The method according to claim 14, wherein The isolation structure is formed on at least one sidewall of each of the control gate and the field plate.

16. The method according to claim 11, wherein Further comprising forming a plurality of insulating spacers, the insulating spacers being formed at least on the sidewalls of the control gate and the field plate.

17. The method according to claim 11, wherein Further comprising forming a thick oxide structure, the thick oxide structure being formed on the upper surface of the doped drift region, at least a portion of the field plate being formed on the upper surface of the thick oxide structure, at least a portion of the oxide structure being formed on the thick oxide structure, the thick oxide structure extending laterally across the doped drift region to the drain region.

18. The method according to claim 11, wherein Further comprising forming a local oxidation of silicon (LOCOS) structure, the LOCOS structure being formed in the doped drift region near the upper surface of the doped drift region, at least a portion of the field plate being formed on the upper surface of the LOCOS structure, at least a portion of the oxide structure being formed on the LOCOS structure, the LOCOS structure extending laterally in the doped drift region to the drain region.

19. The method according to claim 11, wherein Further included is forming a Shallow Trench Isolation (STI) structure, which is formed in the doped drift region and adjacent to the upper surface of the doped drift region, at least a part of the field plate is formed on the upper surface of the STI structure, such that the field plate and the control gate are substantially in the same plane, at least a part of the oxide structure is formed on the STI structure, and the STI structure laterally extends in the doped drift region to the drain region.

20. The method according to claim 11, wherein The control gate and the field plate are formed to be substantially in the same plane relative to each other.

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