Clock circuit, data operation unit

Abstract

Embodiments of the present application provide a clock circuit and a data operation unit. The clock circuit comprises a function unit, a first output unit, a second output unit and a feedback loop. The first input end of the function unit receives a clock source signal, the output end is connected with the first output unit and the second output unit, and the output end is connected with the second input end of the function unit to form the feedback loop. The feedback loop is used to generate a feedback signal according to the output signal of the function unit. The function unit is used to generate a pulse clock signal according to the clock source signal, generate a delay feedback signal according to the pulse clock signal based on the feedback signal, and generate an output signal according to the delay feedback signal and the clock source signal. The first output unit is used to generate a first pulse trigger signal according to the output signal. The second output unit is used to generate a second pulse trigger signal according to the output signal. The time difference between the first pulse trigger signal and the second pulse trigger signal is a specified time length.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of semiconductor devices, and in particular to a clock circuit and a data operation unit. BACKGROUND

[0002] Clock circuits are widely used, such as clock circuits of computers and electronic watches, etc. The clock circuit for generating a clock can also be referred to as a clock generator. In the prior art, the clock width (duty cycle) of the clock generator is specified by the clock source, in other words, is limited by the pulse width of the clock source signal. The fixed pulse width of the clock source may change after being processed by several stages of the clock generator, resulting in the inability to meet the requirements in certain specific scenarios. SUMMARY

[0003] The purpose of the present application is to provide a clock circuit, a data operation unit and a chip to at least partially solve the above problems.

[0004] In a first aspect of the embodiments of the present application, a clock circuit is provided, comprising: a functional unit, a first output unit, a second output unit and a feedback loop.

[0005] A first input end of the functional unit receives a clock source signal, and an output end is connected with the first output unit and the second output unit, and the output end is also connected with a second input end of the functional unit to form the feedback loop.

[0006] The feedback loop is configured to generate a feedback signal according to an output signal of the functional unit.

[0007] The functional unit is configured to generate a pulse clock signal according to the clock source signal, generate a delay feedback signal according to the pulse clock signal based on the feedback signal, and generate the output signal according to the delay feedback signal and the clock source signal.

[0008] The first output unit is configured to generate a first pulse trigger signal according to the output signal.

[0009] The second output unit is configured to generate a second pulse trigger signal according to the output signal, and the time difference between the first pulse trigger signal and the second pulse trigger signal is a specified time length.

[0010] Optionally, the clock circuit is applied to a two-stage shift register, the specified time length is greater than or equal to the time length of the holding time of the latter stage shift register in the two-stage shift register, the first clock pulse signal is used to control the former stage shift register in the two-stage shift register, and the second clock pulse signal is used to control the latter stage shift register in the two-stage shift register.

[0011] Optionally, the functional unit comprises a logic flip module, the logic flip module comprises a plurality of inverters connected in series, wherein an input end of a first inverter is used as a first input end of the functional unit, and the plurality of inverters are used for sequentially flipping the clock source signal to generate a pulse clock signal.

[0012] Optionally, the functional unit further comprises a delay module connected with the logic flip module; the delay module comprises a selector and a plurality of delay sub-units.

[0013] Each of the delay sub-units corresponds to a different delay time, and is used for delaying the received pulse clock signal by a corresponding preset time length based on the feedback signal;

[0014] The selector is used for selecting a delay sub-unit, so that the delay sub-unit delays the pulse clock signal by a preset time length based on the feedback signal to generate a delayed feedback signal.

[0015] Optionally, the functional unit further comprises an NAND gate module connected with the delay module, the NAND gate module respectively receives the clock source signal and the delayed feedback signal, and is used for performing NAND logic processing on the clock source signal and the delayed feedback signal to obtain the output signal.

[0016] Optionally, the logic flip module comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor.

[0017] The gate of the first PMOS transistor is connected with the gate of the first NMOS transistor, and the first input end of the functional unit is obtained; the gate of the second NMOS transistor is the second input end of the functional unit.

[0018] Optionally, the NAND gate module comprises a sixth PMOS transistor, a seventh PMOS transistor, a sixth NMOS transistor, and a seventh NMOS transistor, the gates of the sixth PMOS transistor and the sixth NMOS transistor are connected with the clock source signal, the gates of the seventh NMOS transistor and the seventh PMOS transistor are connected with the delayed feedback signal, the drain of the sixth PMOS transistor is connected with the source of the sixth NMOS transistor, and is connected with the output end, the drain of the seventh NMOS transistor is grounded, and the drain of the seventh NMOS transistor is connected with the output end.

[0019] Optionally, the first output unit comprises a cascade of M inverters, for odd times flipping the output signal and for even times inverting the output signal, to generate the first pulse trigger signal, M being an integer greater than or equal to 1.

[0020] Optionally, the second output unit comprises a cascade of N inverters, for odd times flipping the output signal and for even times inverting the output signal, to generate the second pulse trigger signal, N being an integer greater than or equal to 1, and N being greater than M.

[0021] In a second aspect, a data operation unit is provided, comprising a control circuit, an operation circuit and a clock circuit connected in intercommunication, the clock circuit being any of the clock circuits described in the embodiments.

[0022] In a third aspect, a chip is provided, comprising at least one data operation unit as described.

[0023] According to the clock circuit provided in the embodiments of the present application, the clock circuit comprises a functional unit, a first output unit, a second output unit and a feedback loop; a first input end of the functional unit receives a clock source signal, an output end of the functional unit is connected with the first output unit and the second output unit, and the output end is also connected with a second input end of the functional unit to form the feedback loop; the feedback loop is used to generate a feedback signal according to an output signal of the functional unit; the functional unit is used to generate a pulse clock signal according to the clock source signal, to generate a delay feedback signal according to the pulse clock signal based on the feedback signal, and to generate the output signal according to the delay feedback signal and the clock source signal; the first output unit is used to generate a first pulse trigger signal according to the output signal; the second output unit is used to generate a second pulse trigger signal according to the output signal, and a time difference between the first pulse trigger signal and the second pulse trigger signal is a specified time length, so that a pulse trigger signal with a pulse width meeting the requirements of a specific scenario can be generated. BRIEF DESCRIPTION OF DRAWINGS

[0024] Other features, objects and advantages of the present application will become more apparent from the following detailed description of non-limiting embodiments thereof as read in conjunction with the accompanying drawings:

[0025] Figure 1 FIG. 1 is a circuit structure schematic diagram of a clock circuit provided for an embodiment of the present application.

[0026] Figure 2 FIG. 2 is a circuit structure schematic diagram of a clock circuit provided for an embodiment of the present application.

[0027] Figure 3 FIG. 3 is a schematic diagram of an application of an embodiment of the present application to a two-stage shift register.

[0028] Figure 4 The circuit structure schematic diagram of the clock circuit provided for the fourth embodiment of the present application is shown in the figure.

[0029] Figure 5A The structure schematic diagram of the delay module provided for the present application is shown in the figure.

[0030] Figure 5B The structure schematic diagram of the U-shaped delay chain provided for the present application is shown in the figure.

[0031] Figure 6 The structure schematic diagram of the data operation unit in the embodiment of the present application is shown in the figure.

[0032] Figure 7 The structure schematic diagram of the chip in the embodiment of the present application is shown in the figure. DETAILED DESCRIPTION

[0033] The present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely configured to explain the related application, but not to limit the application. In addition, it should be noted that only the parts related to the application are shown in the drawings for the convenience of description.

[0034] It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict. The present application will be described in detail below with reference to the accompanying drawings and embodiments.

[0035] Embodiment one

[0036] Reference is made to Figure 1 , Figure 1 The circuit structure schematic diagram of a clock circuit provided for the first embodiment of the present application is shown in the figure. The clock circuit comprises a functional unit 1, a first output unit 2, a second output unit 3 and a feedback loop 4.

[0037] The first input end of the functional unit 1 receives a clock source signal, and the output end is connected with the first output unit 2 and the second output unit 3, and the output end is also connected with the second input end of the functional unit 1 to form the feedback loop.

[0038] The feedback loop is used to generate a feedback signal according to the output signal of the functional unit 1.

[0039] The functional unit 1 is used to generate a pulse clock signal according to the clock source signal, and generate a delay feedback signal (as described below X) based on the feedback signal according to the pulse clock signal, so as to generate the output signal according to the delay feedback signal and the clock source signal.

[0040] The first output unit 2 is used to generate a first pulse trigger signal according to the output signal.

[0041] The second output unit 3 is configured to generate a second pulse trigger signal according to the output signal, and a time difference between the first pulse trigger signal and the second pulse trigger signal is a specified time length.

[0042] In the embodiment, the time difference between the first pulse trigger signal and the second pulse trigger signal can be a time length specified according to actual requirements. For example, when the clock circuit is applied to a two-stage shift register, the first clock pulse signal is used to control a front-stage shift register in the two-stage shift register, the second clock pulse signal is used to control a rear-stage shift register in the two-stage shift register, and the specified time length is greater than or equal to a time length of a holding time of the rear-stage shift register in the two-stage shift register.

[0043] Embodiment two

[0044] Figure 2 A circuit structure schematic diagram of a clock circuit provided by the embodiment two of the application is shown in FIG. 2. Figure 2 As shown in FIG. 2, the functional unit 1 includes a logic inversion module 10, a delay module 11, and a NAND gate module 12. The logic inversion module 10 includes a plurality of stages of inverters connected in series, wherein an input end of a first-stage inverter is used as a first input end of the functional unit, and an output end of a last-stage inverter is used as an output end of the functional unit; the plurality of stages of inverters are used to sequentially invert the clock source signal to generate a pulse clock signal (S3 as described below).

[0045] The delay module 11 is connected with the logic inversion module 10. The delay module 11 includes a selector and a plurality of delay sub-units. Each delay sub-unit corresponds to a different delay time, and is used to generate a delay feedback signal (X as described below) by delaying the received pulse clock signal by a preset time length based on the feedback signal; the selector is used to select a delay sub-unit, so that the delay sub-unit generates a delay feedback signal (FB as described below) by delaying the pulse clock signal by a preset time length based on the feedback signal.

[0046] The NAND gate module 12 is connected with the delay module 11. The NAND gate module 12 receives the clock source signal and the delay feedback signal respectively, and is used to perform NAND logic processing on the clock source signal and the delay feedback signal to obtain the output signal (OUT as described below).

[0047] Embodiment three

[0048] Figure 3 A schematic diagram of the application applied to a two-stage shift register is shown in FIG. 3. Figure 3In the embodiment, the first pulse trigger signal is denoted as (CKN2, CKP2), and the second pulse trigger signal is denoted as (CKN1, CKP1).

[0049] As shown in Figure 3 the working principle is briefly described as follows: for example, data Dn is transmitted into a previous stage shift register, and when the clock rising edge of CLKP1 arrives, the previous stage shift register outputs the data Dn; when the clock rising edge of CLKP2 arrives, the next stage shift register starts to latch the data Dn output by the previous stage shift register, and the next stage shift register starts to latch the data. During the time period from the start of latching the data to the completion of latching the data, if the previous stage shift register transmits another data to the next stage shift register before the holding time, it is possible that the data Dn is not stored in the next stage shift register.

[0050] Therefore, the clock circuit provided by the embodiment of the present application can generate the first pulse trigger signal and the second pulse trigger signal based on the delay feedback signal, the time difference between the first pulse trigger signal and the second pulse trigger signal is the specified time length, the specified time length is greater than or equal to the time length of the holding time of the next stage shift register in the two-stage shift register, so that it can be ensured that the previous stage shift register transmits another data to the next stage shift register after the holding time can meet the holding time of the shift register, and then accurate storage of data is realized.

[0051] Embodiment four

[0052] Figure 4 The circuit structure schematic diagram of the clock circuit provided by the embodiment four of the present application is shown. For example, the clock circuit can be applied to a two-stage shift register, and the specified time length is greater than or equal to the time length of the holding time of the next stage shift register in the two-stage shift register.

[0053] As shown in Figure 4 the logic flip module 10 includes a first PMOS transistor P1, a third PMOS transistor P3, a fourth PMOS transistor P4, a first NMOS transistor N1, a third NMOS transistor N3, and a fourth NMOS transistor N4, which can be used for logic flipping of the clock source signal. Among them, the first PMOS transistor P1 and the first NMOS transistor N1 constitute a first stage inverter, the third PMOS transistor P3 and the third NMOS transistor N3 constitute a second stage inverter, and the fourth PMOS transistor P4 and the fourth NMOS transistor N4 constitute a second stage inverter, that is, the logic flip module 10 includes three-stage inverters, the output signal of the first stage inverter is denoted as S1, the output signal of the second stage inverter is denoted as S2, and the output signal of the third stage inverter is denoted as S3, which is the pulse clock signal output by the logic flip module.

[0054] The gates of the first PMOS transistor P1 and the first NMOS transistor N1 are both connected to the clock source signal CLK. The source of the first PMOS transistor P1 is connected to the power supply, and the drain of the first PMOS transistor P1 is connected to the drain of the first NMOS transistor N1. The gates of the third PMOS transistor P3 and the third NMOS transistor N3 are connected to S1. The drains of the third PMOS transistor P3 and the third NMOS transistor N3 are connected to each other, and the source of the third NMOS transistor N3 is grounded. The gates of the fourth PMOS transistor P4 and the fourth NMOS transistor N4 are connected to S2. The drains of the fourth PMOS transistor P4 and the fourth NMOS transistor N4 are connected to each other and connected to S3. The source of the fourth PMOS transistor P4 is connected to the power supply, and the source of the fourth NMOS transistor N4 is grounded.

[0055] The signal obtained by S3 after processing by delay module 11 is denoted as X, that is, X represents the delayed feedback signal.

[0056] It should be noted that in other embodiments, the number of inverters included in the logic flip module 10 is determined according to the application scenario and is not limited to three stages.

[0057] like Figure 4 As shown, the delay module 11 includes a selector and multiple delay sub-units; each delay sub-unit corresponds to a different delay time, used to delay the received pulse clock signal for a corresponding preset duration based on the feedback signal to generate a delayed feedback signal; the selector is used to select a delay sub-unit so that the delay sub-unit delays the pulse clock signal for a preset duration based on the feedback signal to generate a delayed feedback signal.

[0058] Figure 4 Taking four delay sub-units (referred to as delay 1, delay 2, delay 3, and delay 4 in sequence) as an example, it can be understood that in practical applications, those skilled in the art can set any appropriate number of delay sub-units according to their needs.

[0059] The NOR gate module includes a sixth PMOS transistor P6, a seventh PMOS transistor P7, a sixth NMOS transistor N6, and a seventh NMOS transistor N7. The gates of the sixth PMOS transistor and the sixth NMOS transistor are connected to the clock source signal. The gates of the seventh NMOS transistor and the seventh PMOS transistor are connected to the delay feedback signal. The drain of the sixth PMOS transistor is connected to the source of the sixth NMOS transistor and the output of the functional unit. The source of the seventh NMOS transistor is grounded. The drain of the seventh PMOS transistor is connected to the output. The sources of the sixth PMOS transistor P6 and the seventh PMOS transistor P7 are connected to the power supply. The source of the seventh NMOS transistor is grounded. The drain of the seventh PMOS transistor N7 is connected to the output of the functional unit 1.

[0060] Further, the gates of the sixth PMOS transistor P6 and the sixth NMOS transistor N6 are connected to each other and to the gates of the first PMOS transistor P1 and the first NMOS transistor N1, serving as the first input of the functional unit 1.

[0061] Referring to Figure 4 The feedback loop 4 includes an inverter, a pull-down module, and a pull-up module. The input of the inverter is connected to the output of the functional unit. The input of the pull-down module is connected to the output of the inverter. The output of the pull-down module is connected to the input of the pull-up module. The output of the pull-up module is connected to the second-stage inverter in the logic flip module 10, specifically to the source of the third PMOS transistor P3.

[0062] Specifically, the inverter included in the feedback loop 4 includes an eighth PMOS transistor P8 and an eighth NMOS transistor N8. The gates of the eighth PMOS transistor P8 and the eighth NMOS transistor N8 are connected to the output of the functional unit 1. The source of the eighth PMOS transistor P8 is connected to the power supply. The drain of the eighth PMOS transistor P8 is connected to the drain of the eighth NMOS transistor N8. The source of the eighth NMOS transistor N8 is grounded. The output signal of the inverter is denoted as FB, which is the delay feedback signal.

[0063] Specifically, the pull-down module includes a second PMOS transistor N2. The drain of the second PMOS transistor N2 is connected to the drain of the first NMOS transistor N1. The source of the second PMOS transistor N2 is grounded. The gate of the second PMOS transistor N2 is connected to the output of the inverter (consisting of P8 and N8) to receive the feedback signal FB.

[0064] Specifically, the pull-up module comprises a second PMOS transistor P2, a fifth PMOS transistor P5, and a fifth NMOS transistor N5. The gate of the fifth PMOS transistor P5 and the gate of the fifth NMOS transistor N5 are connected to the output of the inverter (consisting of P8 and N8) to receive the feedback signal FB. The source of the fifth PMOS transistor P5 is connected to a power supply, the source of the fifth NMOS transistor N5 is connected to ground, the drain of the fifth PMOS transistor P5 is connected to the drain of the fifth NMOS transistor N5, and the gate of the second PMOS transistor P2 is connected to the drain of the fifth PMOS transistor P5 and the drain of the fifth NMOS transistor N5. The source of the second PMOS transistor P2 is connected to the power supply, and the drain of the second PMOS transistor P2 is connected to the source of the third PMOS transistor P3.

[0065] It should be noted that the specific circuit structure of the inverter, the pull-down module, and the pull-up module included in the feedback loop 4 described above is only an example and is not the only one.

[0066] For ease of understanding, the clock pulse signal generation process of the clock circuit shown in the above detailed embodiments will be explained and described as follows: Figure 4 The clock source signal CLK = 0, the clock source signal CLK is a rising edge signal (0↑1), and CLK = 1 are described respectively.

[0067] (1) When the clock source signal CLK = 0, the circuit is in a stable state, at this time, the delay time has arrived, and the delay module does not perform delay processing on S3:

[0068] When the clock source signal CLK = 0, the first PMOS transistor P1 is turned on, and N1 is turned off. At this time, S1 is 1, the third NMOS transistor N3 is turned on, P3 is turned off, S2 is 0, the fourth PMOS transistor P4 is turned on, N4 is turned off, S3 is 1, and at this time, S3 will not be delayed due to the delay time of the delay module 11, so that the signal at S3 reaches X directly, and therefore X = 1.

[0069] In addition, when the clock source signal CLK = 0, the sixth PMOS transistor P6 is turned on, the sixth NMOS transistor N6 is turned off, X = 1, the seventh PMOS transistor P7 is turned off, the seventh NMOS transistor N7 is turned on, OUT = 1, and the eighth NMOS transistor N8 is turned on, so that FB = 0. Among them, the sixth PMOS transistor P6, the sixth NMOS transistor N6, the seventh PMOS transistor P7, and the seventh NMOS transistor N7 constitute an NAND gate.

[0070] In addition, since FB=0, the second NMOS transistor N2 is ensured to be off (equivalent to the pull-down module being off, no pull-down effect), the fifth NMOS transistor N5 is off and the second PMOS transistor P2 is off (equivalent to the pull-up module being off, no pull-up effect), so that CLK is equivalent to directly passing through three levels of inversion processing (P1 and N1 constitute the first level of inversion to generate the signal at S1, which is 1 at this time, P3 and N3 constitute the second level of inversion to generate the signal at S2, which is 0 at this time, and P4 and N4 constitute the third level of inversion to generate the signal at S3, which is 1 at this time), thereby generating OUT, which is 1 at this time.

[0071] Since OUT=1, at this time, after the processing of the first output unit 2, CKN2=1 and CKP2=0; after the processing of the second output unit 3, CKN1=1 and CKP1=0.

[0072] (2) When the clock source signal CLK is a rising edge signal (0↑1), the delay module delays S3, realizes that X remains 1 before the delay time is reached, and makes OUT generate a falling edge:

[0073] When the clock source signal CLK is a rising edge signal (0↑1), the sixth PMOS transistor P6 is off and the sixth NMOS transistor N6 is on, but since OUT remains 1, N8 is on, so that FB remains 0, and N2, N5, and P2 remain off, so that S1 remains 1, S2 remains 0, and S3 remains 1, which is equivalent to CKL being a rising edge signal, which will not cause S1, S2, and S3 to change, and thus will not cause X to change, i.e., X remains 1, and thus OUT remains 1.

[0074] Since X remains 1 and CLK is a rising edge signal, after the processing of the NAND gate composed of the sixth PMOS transistor P6, the sixth NMOS transistor, the seventh PMOS transistor P7, and the seventh NMOS transistor N7, OUT is inverted. At this time, after the processing of the first output unit 2, CKN2↓ (i.e., a falling edge is generated) and CKP2↑ (i.e., a rising edge is generated); after the processing of the second output unit 3, CKN1↓ (i.e., a falling edge is generated) and CKP1↑ (i.e., a rising edge is generated).

[0075] (3) When the clock source signal CLK=1:

[0076] As mentioned above, since OUT is inverted to OUT=0, at this time, P8 is on, so that FB↑, and when the clock source signal CLK=1, FB↑ to FB=1;

[0077] FB=1, ensures N2 conduction (pull-down module conduction, pull-down effect), N5 conduction and P2 also conduction (pull-up module conduction, pull-up effect), thus causing S1 to flip (symbolized as ↓) to S1=0, S2 to flip (symbolized as ↑) to S2=1, S3 to flip (symbolized as ↓) to S3=0, which is equivalent to CKL being a rising edge signal, causing S1, S2, S3 to change.

[0078] Due to OUT=0, after processing by the first output unit 2, CKN2=0, CKP2=1; after processing by the second output unit 3, CKN1=0, CKP1=1.

[0079] When the delay time is reached, S3=0, causing X to change from 1 to 0, and since the preset time length is less than the time length corresponding to the pulse width of the clock source signal, CLK still remains 1 at this time, thus after processing by the NAND gate, OUT forms a rising edge until OUT=1.

[0080] When OUT=1, P8 is turned on, thus causing FB to become 0 again, re-disconnecting the second NMOS transistor N2, disconnecting the fifth NMOS transistor N5, and disconnecting the second PMOS transistor P2.

[0081] When CLK flips to 0, similar to the case of (1) above, S1↑ until 1, S2↓ until 0; S2↑ causes the fourth NMOS transistor N4 to conduct, the fourth PMOS transistor P4 to disconnect, S3↓ until 0, thus ensuring that OUT=1, further causing CKN2↑ (i.e. generating a rising edge) to 1, CKP2↓ (i.e. generating a falling edge) to 0, CKN1↑ (i.e. generating a rising edge) to 1, CKP1↓ (i.e. generating a falling edge) to 0, thus re-entering the stable state.

[0082] Referring to the circuit Figure 4 , the first output unit 2 can include a first inverter and a second inverter, two clock pulse signals outputted by the first inverter and the second inverter being opposite in phase, the second output unit 3 including four inverters in series, the second output unit 3 also outputting CKN1 and CKP1 opposite in phase. The signal at OUT outputted by the functional unit (the same as the signal at FB) can be delayed by a first time length by the inverter in the first output unit 2, and then a first clock pulse signal CKP2 is outputted; the signal at OUT outputted by the functional unit can be delayed by a second time length by the inverter in the second output unit 3, and a second clock pulse signal CKP1 is outputted. In this embodiment, the time difference between the first time length and the second time length is greater than or equal to the holding time of the last stage of the two-stage shift register shown in the figure. Figure 3 The holding time of the last stage of the two-stage shift register shown in the figure.

[0083] It can be understood that the more inverters contained in the circuit unit, the longer the delay time; in the embodiment, or Figure 4 In the embodiment, the second output unit 3 has a longer delay time (second time length) than the first output unit 2 (first time length).

[0084] In the application scenario of the embodiment, that is, the embodiment can be applied to Figure 3 The time difference between the second time length and the first time length is greater than or equal to the holding time of the second-stage shift register in the two-stage shift register shown in FIG. 2. Figure 3 The time difference between the second time length and the first time length is greater than or equal to the holding time of the second-stage shift register in the two-stage shift register shown in FIG. 2.

[0085] Figure 5A The structure diagram of the delay module in the embodiment of the application is shown in FIG. 3. Figure 5A Optionally, in a specific embodiment, the delay module includes a plurality of U-shaped delay chains in a chain, each U-shaped delay chain including a selector and a delay selection switch (also referred to as a delay unit), the selector being configured to control the delay time of the current U-shaped delay chain or the delay time of the next U-shaped delay chain, so as to sequentially open the plurality of U-shaped delay chains to form delay chains with different delay times.

[0086] Figure 5B The structure diagram of the U-shaped delay chain in the embodiment of the application is shown in FIG. 4. Figure 5BOptionally, in a specific embodiment, the structure of the delay chain can include: n+1 delay selection switches (Delay Mux, also known as delay), one delay selection switch participates in forming a one-stage U-shaped delay chain, n is an integer greater than or equal to 1, the n+1 delay selection switches form an n+1-stage U-shaped delay chain, in addition, the one-stage U-shaped delay chain further includes a selector for generating a gating signal, and each delay selection switch works or suspends work under the control of the corresponding gating signal. Specifically, the corresponding gating signals of the n+1 delay selection switches are EN(0), EN(1), …, EN(n-1), and EN(n) in turn. When EN(i) = 1, 0 ≤ i ≤ y, the corresponding delay selection switch is effective and can play a delay role, and EN(0)-EN(i-1) corresponding delay selection switches are also effective; otherwise, when EN = 0, the corresponding delay selection switch does not work and does not play a delay role. When EN = 1, it indicates that the U-shaped delay chain of this stage is in series, and In will be in Out_Ext, and Out_Ext is actually connected to the In of the next-stage U-shaped delay chain. In this way, the delay unit is equivalent to passing through two-stage delay units, that is, the delay is doubled.

[0087] EN(0), EN(1), …, EN(n-1), and EN(n) are specifically generated by a selector, and the selector specifically performs logical operation on the hot code (also known as one hot) generated by a decoder, thereby generating EN(0), EN(1), …, EN(n-1), and EN(n). The specific principle is: when EN[i] = 1, the control circuit ensures that EN[x] = 1 (0 <= x < i), and since EN[n] is a one-bit hot code structure and EN[y] = 0 (i < y < n), therefore, assuming that EN[i] = 1 is selected, the Out of the selected stage and the stages before the selection will be connected in series from In_Ext, thereby forming a return path of the U-shaped loop chain, and EN[i+1] = 0, In-DelayCell-AND2-Out forms a return path, and Out_Ext = 0, and the stages of EN[y] = 0 (y > i+1) are selected, because In = 0, all output nodes become 0, and therefore the In_Ext of the EN[i+1] stage = 0, thereby making Out = the output of AND2, that is, forming a U-shaped loop.

[0088] It is assumed that the delay of each delay selection switch is 50ps / stage, that is, the corresponding delay time is 50ps.

[0089] For example, taking EN[0]=1, EN[1]=1, EN[2]=0 as an example, since EN[2]=0, the third U-type delay chain is the last stage of this time delay, and the delay time is 150ps; by analogy, when EN(0:n-1)=1, EN(n)=0, the nth U-type delay chain is the last stage of this time delay, and the delay time is (n+1)*50ps.

[0090] In Figure 5B , the In terminal is used for receiving the second output signal, and the Out terminal is used for outputting the delay signal.

[0091] Referring to Figure 5B , in a specific embodiment, the structure of the delay selection switch (Delay Mux) includes a delay unit (Delay Cell), two AND gates (AND1, AND2), an OR gate, and a NOT gate. The connection relationship of these logic circuit components is shown in Figure 5B , which constitutes a U-shaped structure as a whole. The delay unit can specifically include a buffer and a multiplexer. The buffer is used to buffer S3 and output to the input terminals of the two AND gates through the multiplexer. The low or high level in S3 is input to the input terminals of the two AND gates through the multiplexer for delay processing by the working multiple or one delay selection switch to delay S3.

[0092] In combination with Figure 5A , Figure 5B , the principle of making the delay time 150ps when EN[0]=1, EN[1]=1, EN[2]=0 is described in detail as follows:

[0093] When EN[2]=0, EN[1]=1, EN[0]=1, S3 will be transmitted from the U-type delay chain enabled by EN[0] to be delayed by 50ps, then to the U-type delay chain unit enabled by EN[1], and then from the U-type delay chain unit enabled by EN[1] to EN[2], and then through the AND gate (AND2) in the U-type delay chain enabled by EN[2], and then after the OR gate processing, it is returned in reverse, passes through the Out of the U-type delay chain enabled by EN[2], the Out of the U-type delay chain enabled by EN[1], the Out of the U-type delay chain enabled by EN[0], and finally to the output.

[0094] Referring to the above Figure 5BIn the above process, EN[0] = 1, the output of the NOT gate in its corresponding U-type delay chain is 0, then the output of AND2 is 0, and the output of AND1 is 1, that is, S3 is input to the In end of the U-type delay chain corresponding to EN[1]. However, at this time, when the output of AND2 is 0 and in_Ext is 0, then the output of the OR gate is 0; EN[1] = 1, the output of the NOT gate in its corresponding U-type delay chain is 0, then the output of AND2 is 0, and the output of AND1 is 1, but at this time, in_Ext is also 0, then the output of the OR gate is 0; EN[2] = 0, the output of the NOT gate in its corresponding U-type delay chain is 1, then the output of AND2 is 1, and the output of AND1 is 0, that is, the delayed S3 will not be input to the U-type delay chain corresponding to EN[3]. However, at this time, the OR gate is equivalent to a buffer, thus making Out = AND2. The output of the U-type delay chain corresponding to EN[2] is 1, and is input to the output Out of the U-type delay chains corresponding to EN[1] and EN[0] in sequence. Referring to the above process, in each U-shaped delay chain, since there is a delay unit, S3 will be delayed by 50ps. Therefore, the U-shaped delay chains corresponding to EN[0], EN[1], and EN[2] will be delayed a total of 3 times, for a total of 3*50ps=150ps.

[0095] In the clock circuit of this embodiment, exemplarily, after receiving the rising edge signal of the clock source signal, functional unit 1 flips it through a branch and outputs it. Then, after being flipped by the first output unit and / or the second output unit, it becomes the rising edge of the newly generated clock pulse signal. The flipped falling edge signal is then input to functional unit 1 through feedback loop 4 to start the delay module 11 to perform a delay of a preset duration (wherein, the preset duration is less than the duration corresponding to the pulse width of the clock source signal). Then, based on the feedback signal, functional unit 1 uses NAND gate module 12 to perform NAND logic operation on the clock source signal and the delay feedback signal, thereby realizing the trailing edge clipping operation of the clock source signal to obtain the falling edge of the newly generated clock pulse signal, and thus obtaining a new clock pulse signal. That is to say, the pulse width of the newly generated clock pulse signal can be preset by the delay subunit, thereby obtaining a clock pulse signal that is arbitrarily smaller than the pulse width of the clock source signal. Further, when the delay duration of the first output unit 2 is less than the delay duration of the second output unit 3, and the time difference between the two is greater than or equal to the delay duration of the second output unit 3, the clock pulse signal can be obtained. Figure 4 The hold time of the second-stage shift register in the two-stage shift register setup ensures that the next data is input only after the current data in the second-stage shift register has been latched, thus ensuring accurate storage of the current data. In other words, it can generate a clock signal with a pulse width that meets the requirements of specific scenarios.

[0096] The clock circuit provided in this embodiment of the invention can serve as a customized standard unit, such as a clock signal generator to provide clock pulse signals for scenarios requiring pulse signals. For example, it can function as a clock generator for pulse latches, a shift register misalignment clock generator, or a multi-directional non-overlapping clock generator. Furthermore, it can be used as a clock generation unit in a CPU / CPU for generating clock pulse signals in ultra-large-scale computing scenarios; it can also be used as a clock generation unit in an AI (Artificial Intelligence) chip for generating clock pulse signals in high-density computing scenarios; and it can also be used as a system-level clock generation unit in a System on Chip (SOC) / Field Programmable Gate Array (FPGA) for generating clock pulse signals in low-power computing scenarios.

[0097] This invention also provides a data processing unit. Figure 6 This is a schematic diagram of the data processing unit in an embodiment of the present invention. Figure 6 As shown, the data processing unit 500 includes a control circuit 501, a processing circuit 502, and multiple clock circuits 503. The control circuit 501 controls the clock circuits 503 to generate clock pulse signals with a preset pulse width, and the processing circuits 502 perform processing on the data according to the clock pulse signals. The clock circuits 503 are the clock circuits in any of the above embodiments.

[0098] This invention also provides a chip. Figure 7 This is a schematic diagram of the chip structure in an embodiment of the present invention. Figure 7 As shown, chip 600 includes a control unit 601 and one or more data processing units 500. The control unit 601 inputs data to the data processing units 500 and processes the data output by the data processing units 500.

[0099] This invention also provides an electronic terminal, which includes at least one chip as described in the embodiments of this application.

[0100] The terms "first," "second," "first," or "second" used in the various embodiments of this disclosure may modify various components regardless of their order and / or importance, but these terms do not limit the corresponding components. The above terms are configured only for the purpose of distinguishing an element from other elements. For example, "first user equipment" and "second user equipment" refer to different user equipments, although both are user equipment. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0101] When an element (e.g., a first element) is referred to as being “(operatively or communicatively) coupled with” or “(operatively or communicatively) coupled to” another element (e.g., a second element), or “connected to” another element (e.g., a second element), it should be understood that the one element is directly connected to the other element or the one element is indirectly connected to the other element via yet another element (e.g., a third element). In contrast, it will be understood that when an element (e.g., a first element) is referred to as being “directly connected” or “directly coupled” to another element (a second element), then no element (e.g., a third element) intervenes between them.

[0102] The above description is only preferred embodiments of the present application and the technical principles used. Those skilled in the art should understand that the scope of the application involved in the present application is not limited to the technical solutions formed by the specific combinations of the above technical features, and should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the above inventive concept. For example, the above features are replaced with each other to form technical solutions with similar functions disclosed in the present application (but not limited to).

Claims

1. A clock circuit, characterized in that, The clock circuit includes: a functional unit, a first output unit, a second output unit, and a feedback loop; The first input terminal of the functional unit receives a clock source signal, and the output terminal is connected to the first output unit and the second output unit. The output terminal is also connected to the second input terminal of the functional unit to form the feedback loop. The feedback loop is used to generate a feedback signal based on the output signal of the functional unit; The functional unit is used to generate a pulse clock signal based on the clock source signal, generate a delay feedback signal based on the feedback signal and the pulse clock signal, and generate the output signal based on the delay feedback signal and the clock source signal. The first output unit is configured to generate a first pulse trigger signal based on the output signal; The second output unit is used to generate a second pulse trigger signal based on the output signal, wherein the time difference between the first pulse trigger signal and the second pulse trigger signal is a specified duration; The functional unit includes: A logic flip module, comprising several inverters connected in series, wherein the input terminal of the first inverter serves as the first input terminal of the functional unit, and the several inverters are used to sequentially flip the clock source signal to generate a pulse clock signal. A delay module is connected to a logic flip module. The delay module includes a selector and multiple delay sub-units. Each delay sub-unit corresponds to a different delay time and is used to delay the received pulse clock signal for a corresponding preset duration based on the feedback signal. The selector is used to, according to the delay sub-unit, cause the delay sub-unit to delay the pulse clock signal for a preset duration based on the feedback signal to generate a delayed feedback signal. The logic switching module includes a second PMOS transistor, a fifth PMOS transistor, a second NMOS transistor, and a fifth NMOS transistor. The gate of the second NMOS transistor is the second input terminal of the functional unit, its drain is connected to the drain of the first NMOS transistor, and its source is grounded. The source of the fifth PMOS transistor is connected to the power supply, its gate is connected to the gate of the fifth NMOS transistor, its source is grounded, its drain is connected to the drain of the fifth NMOS transistor and to the gate of the second PMOS transistor, its source is connected to the power supply, and its drain is connected to the source of a third PMOS transistor. The drain of the second NMOS transistor is connected to the drain of the first NMOS transistor, and the source of the second NMOS transistor is grounded; the gates of the fifth PMOS transistor and the fifth NMOS transistor N5 are connected to the output of the inverter to receive feedback signals, and the drain of the second PMOS transistor is connected to the source of the third PMOS transistor.

2. The clock circuit according to claim 1, characterized in that, The clock circuit is applied to a two-stage shift register, the specified duration is greater than or equal to the hold time of the latter shift register in the two-stage shift register, the first pulse trigger signal is used to control the former shift register in the two-stage shift register, and the second pulse trigger signal is used to control the latter shift register in the two-stage shift register.

3. The clock circuit according to claim 1, characterized in that, The functional unit further includes: a NAND gate module, which is connected to the delay module. The NAND gate module receives the clock source signal and the delay feedback signal respectively, and performs NAND logic processing on the clock source signal and the delay feedback signal to obtain the output signal.

4. The clock circuit according to claim 3, characterized in that, The NAND gate module includes a sixth PMOS transistor, a seventh PMOS transistor, a sixth NMOS transistor, and a seventh NMOS transistor. The gates of the sixth PMOS transistor and the sixth NMOS transistor are both connected to the clock source signal. The gates of the seventh NMOS transistor and the seventh PMOS transistor are both connected to the delay feedback signal. The drain of the sixth PMOS transistor is connected to the source of the sixth NMOS transistor and is also connected to the output terminal. The drain of the seventh NMOS transistor is grounded and is connected to the output terminal.

5. The clock circuit according to claim 1, characterized in that, The first output unit includes cascaded M-stage inverters for performing odd-numbered flips and even-numbered inversions on the output signal to generate the first pulse trigger signal, where M is an integer.

6. The clock circuit according to claim 5, characterized in that, The second output unit includes N cascaded inverters for performing an odd number of flips and an even number of inversions on the output signal to generate the second pulse trigger signal, where N is an integer and N is greater than M.

7. A data processing unit, comprising an interconnected control circuit, a processing circuit, and a clock circuit, wherein the clock circuit is the clock circuit according to any one of claims 1-6.

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