LED driver integrated circuit and LED driver system

Abstract

An LED driver integrated circuit and an LED driver system. The LED driver integrated circuit can sequentially enable multiple LED enable circuits to sequentially excite multiple LED light strings. After all of the multiple LED enable circuits are enabled, the downstream enable circuit is enabled to enable a downstream enable signal. The LED driver system is used to synchronize two LED driver integrated circuits to drive LED light strings. The LED driver system sequentially excites the LED light strings driven by a first LED driver integrated circuit, then outputs a downstream enable signal from the first LED driver integrated circuit to a second LED driver integrated circuit to excite the LED light strings driven by the second LED driver integrated circuit.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to electronic circuits, and more particularly, to light emitting diode (LED) driving circuits. Background Art

[0002] For both aesthetic and functional reasons, the rear end of today's vehicles utilizes sequential LED lighting. In this process, numerous LED strings are illuminated sequentially. Because a typical LED driver integrated circuit (IC) can only drive a limited number of LED strings, more than one IC is typically used to power the required number of LED strings. Consequently, there is a need to address the issue of synchronizing the time difference between when one IC illuminates the last LED string it drives and when the next IC illuminates the first LED string it drives. Summary of the Invention

[0003] To achieve the above and other objectives, an LED driver integrated circuit for driving multiple LED light strings is provided according to one embodiment of the present invention, comprising an enable pin, multiple LED enable circuits, a downstream enable circuit, a control circuit, and a downstream enable pin. The enable pin is used to provide an enable signal. The multiple LED enable circuits correspond one-to-one to the multiple LED light strings, wherein each LED enable circuit is coupled to a corresponding LED light string and is used to activate the corresponding LED light string when the LED enable circuit is enabled. The downstream enable circuit is used to provide a downstream enable signal, wherein when the downstream enable circuit is enabled, the downstream enable signal is in an enabled state. The control circuit is coupled to the enable pin to receive the enable signal, wherein the control circuit sequentially enables the multiple LED enable circuits in response to the enable signal and enables the downstream enable circuit control circuit after all the LED enable circuits are enabled. The downstream enable pin is coupled to the downstream enable circuit and is used to output the downstream enable signal.

[0004] According to one embodiment of the present invention, an LED driver integrated circuit for driving multiple LED light strings is also provided, comprising an enable pin, a control circuit, multiple LED enable circuits, a downstream enable switch, and a downstream enable pin. The enable pin is used to receive an enable signal. The control circuit is coupled to the enable pin to receive the enable signal and is used to generate multiple LED enable control signals and downstream enable control signals based on the enable signal. The multiple LED enable circuits correspond one-to-one to the multiple LED light strings and the multiple LED enable control signals, wherein each LED enable circuit is coupled to the control circuit to receive a corresponding LED enable control signal, and each LED enable circuit is coupled to a corresponding LED light string and is used to activate or deactivate the corresponding LED light string in response to the corresponding LED enable control signal. The downstream enable switch is coupled to the control circuit to receive the downstream enable signal and is used to provide a downstream enable signal based on the downstream enable control signal. The downstream enable pin is coupled to the downstream enable switch and is used to output the downstream enable signal.

[0005] According to one embodiment of the present invention, an LED driver system is provided, comprising a first LED driver integrated circuit and a second LED driver integrated circuit, each configured to drive two LED arrays, each LED array comprising multiple LED light strings. The first LED driver integrated circuit and the second LED driver integrated circuit each include an enable pin, multiple LED enable circuits, a downstream enable circuit, a control circuit, and a downstream enable pin. The enable pin is configured to receive an enable signal. Each LED enable circuit corresponds one-to-one to an LED light string, wherein each LED enable circuit is coupled to a corresponding LED light string and configured to activate the corresponding LED light string when the LED enable circuit is enabled. The downstream enable circuit is configured to provide a downstream enable signal, wherein the downstream enable signal is in an enabled state when the downstream enable circuit is enabled. The control circuit is coupled to the enable pin to receive the enable signal. In response to the enable signal, the control circuit sequentially enables the multiple LED enable circuits and enables the downstream enable circuit control circuit after the LED enable circuits are enabled. The downstream enable pin is coupled to the downstream enable circuit and configured to output the downstream enable signal. The enable pin of the second LED driver integrated circuit is coupled to the downstream enable pin of the first LED driver integrated circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present invention may be further understood with reference to the following detailed description and accompanying drawings, in which like components have like reference numerals. The following drawings are for illustration purposes only and therefore may only show a portion of the device and are not necessarily drawn to scale.

[0007] Figure 1 FIG. 1 is a schematic diagram of an LED driver integrated circuit 100 according to an embodiment of the present invention.

[0008] Figure 2A FIG. 2 is a schematic diagram of an enable detection circuit 200 according to an embodiment of the present invention.

[0009] Figure 2B FIG. 2 is a schematic diagram of an enable detection circuit 210 according to another embodiment of the present invention.

[0010] Figure 3 FIG. 1 is a waveform diagram of an exemplary enabling circuit 113W according to an embodiment of the present invention.

[0011] Figure 4 FIG. 4 is a schematic diagram of an LED driver integrated circuit 400 according to an embodiment of the present invention.

[0012] Figure 5 FIG. 1 is a waveform diagram of an LED driver integrated circuit 400 according to an embodiment of the present invention.

[0013] Figure 6 FIG. 6 is a schematic diagram of an LED driving system 600 according to an embodiment of the present invention.

[0014] Figure 7 FIG. 4 is a schematic diagram of another downstream enabling circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0015] Some embodiments of the present invention will be described in detail below. In the following description, some specific details, such as the specific circuit structures and specific parameters of these circuit components in the embodiments and the figures, are used to provide a better understanding of the embodiments of the present invention and do not necessarily limit the present invention. After reading the description herein, it will be apparent that the present invention can be modified in various ways. In addition, the present invention can be implemented in the form of devices, methods, software, etc. Accordingly, the present invention can be implemented in the form of pure hardware, pure software, or software combined with hardware. Therefore, the following description should not be used to limit the present invention.

[0016] Throughout the specification and claims, plural forms such as "a plurality" or "the" do not exclude singular references unless the context clearly limits the reference to the plural. For example, "a plurality of LED light strings" or "these LED light strings" may also include only one LED light string. For another example, "a plurality of LEDs" or "these LEDs" may also include only one LED. Furthermore, the terms "a," "an," and "the" include plural references.

[0017] Figure 1 FIG. 1 is a schematic diagram of an LED driver integrated circuit 100 according to an embodiment of the present invention. Figure 1As shown, an LED driver integrated circuit 100 is used to drive an LED array ALED. The LED array ALED includes a plurality of LED strings SLED1, ..., SLEDi, ..., SLEDN, where i represents an integer ranging from 1 to N, and N is an integer greater than or equal to 1. The LED string SLEDi (i=1, 2, ..., N) includes a plurality of LEDs (LEDi1, ..., LEDij, ..., LEDiM), each of which has a first terminal (e.g., an anode) and a second terminal (e.g., a cathode), where j represents an integer ranging from 1 to M, and M is an integer greater than or equal to 1. As shown, the first terminals of the plurality of LEDs (LEDi2, ..., LEDiM) are coupled one-to-one to the second terminals of the plurality of LEDs (LEDi1, ..., LEDi(M-1)). The first terminal of LEDi1 is used to receive a bias voltage VBIAS as an input power supply.

[0018] like Figure 1 As shown, the LED driver integrated circuit 100 includes an enable pin RDYIN for receiving an enable signal SEN and a downstream enable pin RDYOUT. The LED driver integrated circuit 100 may further include a plurality of LED enable circuits CHL1, ..., CHLi, ..., CHLN, each corresponding one-to-one to the plurality of LED light strings SLED1, ..., SLEDi, ..., SLEDN. More specifically, the LED enable circuit CHLi is coupled to the LED light string SLEDi and is configured to activate the LED light string SLEDi when the LED enable circuit CHLi is enabled, or to deactivate the LED light string SLEDi when the LED enable circuit CHLi is disabled.

[0019] In one embodiment, “exciting” the LED light string means allowing sufficient current to flow through the LED light string to illuminate the LED light string and output a light source. Conversely, “stopping exciting” the LED light string means inhibiting sufficient current from flowing through the LED light string so that the LED light string is not illuminated and does not output a light source.

[0020] In one embodiment, when the LED enabling circuit CHLi (i=1, 2, ..., or N) is enabled, a current path is established to allow sufficient current to flow through the LED enabling circuit CHLi and, therefore, through the LED string SLEDi. Conversely, when the LED enabling circuit CHLi is disabled, no current path is established, resulting in insufficient current flowing through the LED enabling circuit CHLi and the LED string SLEDi.

[0021] In one embodiment, the LED enabling circuit CHLi (i=1, 2, ..., or N) may include: Figure 4The LED enable switch Si is shown. The LED enable switch Si has a first terminal, a second terminal, and a control terminal. The first terminal of the LED enable switch Si is coupled to the second terminal of the corresponding LED light string SLEDi, and the second terminal of the LED enable switch Si is coupled to a reference ground (e.g., via a resistor). The LED enable switch Si is configured to receive an LED enable control signal SSi at its control terminal and selectively turn on ("enable") or turn off ("disable") the LED enable switch Si in response to the LED enable control signal SSi. More specifically, when the LED enable control signal SSi is in an activated state (e.g., a logic "1"), the LED enable switch Si is turned on, and when the LED enable control signal SSi is in a deactivated state (e.g., a logic "0"), the LED enable switch Si is turned off. In one embodiment, the LED enable switch Si can be implemented using a metal oxide semiconductor field effect transistor (MOSFET). In another embodiment, the MOSFET can be N-type.

[0022] like Figure 1 As shown, the LED driver integrated circuit 100 can further include a downstream enable circuit CHD for providing a downstream enable signal SOUT. When the downstream enable circuit CHD is enabled, the downstream enable signal SOUT is in an enabled state (e.g., a logic "1"). When the downstream enable circuit CHD is disabled, the downstream enable signal SOUT is in a disabled state (e.g., a logic "0"). A downstream enable pin RDYOUT is coupled to the downstream enable circuit CHD and is configured to output the downstream enable signal SOUT.

[0023] In one embodiment, the enable signal SEN represents operation information for sequentially activating the plurality of LED light strings SLED1, ..., SLEDi, ..., SLEDN. For example, in automotive applications, the enable signal SEN may represent a user instruction to sequentially light up the taillights.

[0024] In one embodiment, the downstream enabling circuit CHD may include: Figure 4 The inverter INV and the downstream enable switch SD are shown. The inverter INV has an input terminal and an output terminal. The input terminal of the inverter INV is coupled to the enable circuit 113 to receive the downstream enable control signal SSD, and the inverter INV inverts the downstream enable control signal SSD and outputs the inverted downstream enable control signal SSD1 at the output terminal of the inverter INV. The downstream enable switch SD has a first terminal, a second terminal and a control terminal. The first terminal of the downstream enable switch SD is coupled to the power supply voltage VCC and is used to provide the downstream enable signal SOUT. In the example Figure 4In the illustrated embodiment, a first terminal of the downstream enable switch SD is coupled to the supply voltage VCC via a resistor RPUP. A second terminal of the downstream enable switch SD is coupled to a reference ground. The downstream enable switch SD is configured to receive an inverted downstream enable control signal SSD1 at its control terminal and selectively turn on ("enable") or off ("disable") the downstream enable switch SD in response to the downstream enable control signal SSD (or the inverted downstream enable control signal SSD1). Specifically, when the downstream enable control signal SSD is in an active state (e.g., a logic "1") and the inverted downstream enable control signal SSD1 is in an inactive state (e.g., a logic "0"), the downstream enable switch SD is turned off. Consequently, the downstream enable signal SOUT is at a high voltage level, indicating an enabled state. On the other hand, when the downstream enable control signal SSD is in an inactive state (e.g., a logic "0") and the inverted downstream enable control signal SSD1 is in an active state (e.g., a logic "1"), the downstream enable switch SD is turned on. Therefore, the downstream enable signal SOUT is at a low voltage level and is in a disabled state. In one embodiment, the downstream enable switch SD is an N-type MOSFET.

[0025] In another embodiment, Figure 7As shown, the downstream enabling circuit CHD may include an inverter INV, a first downstream enabling switch SD1, and a second downstream enabling switch SD2. The inverter INV has an input terminal and an output terminal. The input terminal of the inverter INV is coupled to the enabling circuit 113 to receive the downstream enabling control signal SSD. The inverter INV inverts the downstream enabling control signal SSD and outputs the inverted downstream enabling control signal SSD1 at the output terminal of the inverter INV. The first downstream enabling switch SD1 and the second downstream enabling switch SD2 each have a first terminal, a second terminal, and a control terminal. The first terminal of the first downstream enabling switch SD1 is coupled to the supply voltage VCC, the first terminal of the second downstream enabling switch SD2 is coupled to the first terminal of the first downstream enabling switch SD1 and is used to provide the downstream enabling signal SOUT, and the second terminal of the second downstream enabling switch SD2 is coupled to the reference ground. The control terminals of the first downstream enabling switch SD1 and the second downstream enabling switch SD2 are each configured to receive an inverted downstream enabling control signal SSD1 and selectively turn on ("enable") or off ("disable") the first downstream enabling switch SD1 and the second downstream enabling switch SD2 in response to the downstream enabling control signal SSD (or the inverted downstream enabling control signal SSD1). Specifically, when the downstream enabling control signal SSD is in an active state (e.g., a logic "1") and the inverted downstream enabling control signal SSD1 is in a deactivated state (e.g., a logic "0"), the first downstream enabling switch SD1 is turned on and the second downstream enabling switch SD2 is turned off. Therefore, the downstream enabling signal SOUT is at a high voltage level and is in an enabled state. On the other hand, when the downstream enabling control signal SSD is in an inactive state (e.g., a logic "0") and the inverted downstream enabling control signal SSD1 is in an active state (e.g., a logic "1"), the first downstream enabling switch SD1 is turned off and the second downstream enabling switch SD2 is turned on. Therefore, the downstream enable signal SOUT is at a low voltage level and is in a disabled state. In one embodiment, the first downstream enable switch SD1 is a P-type MOSFET and the second downstream enable switch SD2 is an N-type MOSFET.

[0026] Refer again Figure 1 , the LED driver integrated circuit 100 may further include a control circuit 101, which is coupled to the enable pin RDYIN to receive the enable signal SEN. The control circuit 101 is used to generate a plurality of LED enable control signals SS1, ..., SSi, ..., SSN and a downstream enable control signal SSD in response to the enable signal SEN. The control circuit 101 is used to use the plurality of LED enable control signals SS1, ..., SSi, ..., SSN to sequentially enable the plurality of LED enable circuits CHL1, ..., CHLi, ..., CHLN, and use the downstream enable control signal SSD to enable the downstream enable circuit CHD. In one embodiment, as Figure 3As shown, the downstream enabling circuit CHD is enabled after the multiple LED enabling circuits CHL1, ..., CHLi, ..., CHLN are all enabled. That is, the control circuit 101 sequentially enables the LED enabling circuit CHL1, the LED enabling circuit CHL2, ... until the LED enabling circuit CHLN is enabled. After that, the control circuit 101 enables the downstream enabling circuit CHD.

[0027] In one embodiment, if Figure 3 As shown, the control circuit 101 initiates a sequential enable operation, sequentially enabling the plurality of LED enable circuits CHL1, ..., CHLi, ..., CHLN and the downstream enable circuit CHD in response to the enable state of the enable signal SEN. In one embodiment, the control circuit 101 initiates the sequential enable operation after the enable signal SEN transitions to the enable state. In another embodiment, the control circuit 101 initiates the sequential enable operation when one or more conditions are satisfied after the enable signal SEN transitions to the enable state.

[0028] In one embodiment, the control circuit 101 enables the plurality of LED enabling circuits CHL1, ..., CHLi, ..., CHLN and the downstream enabling circuit CHD at a plurality of enabling times t1, ..., ti, ..., tN, and tD, with a predetermined time interval td between each two consecutive enabling times. That is, the control circuit 101 enables the plurality of LED enabling circuits CHL1, ..., CHLi, ..., CHLN in a one-to-one correspondence at each enabling time t1, ..., ti, ..., tN, and enables the downstream enabling circuit CHD at enabling time tD. Furthermore, a predetermined time interval td is present between each two consecutive enabling times of the plurality of enabling times t1, ..., ti, ..., tN, and a predetermined time interval td is present between the enabling time tN for enabling the LED enabling circuit CHLN and the enabling time tD for enabling the downstream enabling circuit CHD.

[0029] Those skilled in the art will appreciate that, in the above embodiment, the preset time interval between each two consecutive enabling moments of the plurality of enabling moments t1, ..., ti, ..., tN is equal and is equal to the preset time interval between enabling moment tN and enabling moment tD. However, in another embodiment, the preset time interval between enabling moment tN and enabling moment tD and the preset time interval between each two consecutive enabling moments of the plurality of enabling moments t1, ..., ti, ..., tN may be different.

[0030] Refer again Figure 1The control circuit 101 includes an enable detection circuit 111, a counting circuit 112, and an enable circuit 113. The enable detection circuit 111 receives an enable signal SEN to generate a trigger signal STR. In one embodiment, the enable detection circuit 111 receives the enable signal SEN and an enable threshold signal STH1 and generates the trigger signal STR based on a comparison between the enable signal SEN and the enable threshold signal STH1.

[0031] Figure 2A FIG. 2 shows a schematic diagram of an enable detection circuit 200 according to an embodiment of the present invention. The enable detection circuit 200 can be used as Figure 1 The enable detection circuit 111 in the embodiment of the present invention. The enable detection circuit 200 may include a comparator CMP having a first terminal, a second terminal, and an output terminal, wherein the first terminal is used to receive the enable signal SEN, and the second terminal is used to receive the enable threshold signal STH1. In one embodiment, the first terminal of the comparator CMP is a non-inverting input terminal, and the second terminal of the comparator CMP is an inverting input terminal. The comparator CMP compares the enable signal SEN with the enable threshold signal STH1 and generates a trigger signal STR at the output terminal based on the comparison result. When the level of the enable signal SEN is higher than the level of the enable threshold signal STH1, the trigger signal STR is in an excited state (e.g., a logic "1"). When the level of the enable signal SEN is not higher than the level of the enable threshold signal STH1, the trigger signal STR is in a non-excited state (e.g., a logic "0").

[0032] In another embodiment, Figure 2B As shown, the enable detection circuit 210 may include a comparator CMP, and the comparator CMP may further include a third input terminal for receiving another enable threshold signal STH2. In this embodiment, the comparator CMP compares the enable signal SEN with the enable threshold signal STH1 and the enable threshold signal STH2, and generates a trigger signal STR at the output terminal based on the comparison result, wherein when the level of the enable signal SEN is higher than the level of the enable threshold signal STH1, the trigger signal STR is in an excited state (for example, a logic "1"), and when the level of the enable signal SEN is lower than the level of the enable threshold signal STH2, the trigger signal STR is in a non-excited state (for example, a logic "0").

[0033] The counting circuit 112 is configured to receive the trigger signal STR and generate a counting signal SCT having a count value. The counting circuit 112 is configured to increment the count value of the counting signal SCT at each predetermined time interval td in response to the active state (e.g., logic "1") of the trigger signal STR. In other words, the counting circuit 112 increments the count value of the counting signal SCT every predetermined time interval td after the trigger signal STR transitions to the active state.

[0034] In one embodiment, for example, further reference may be made to Figure 5 For further understanding, the counting circuit 112 is configured to receive a clock signal CLK having a clock period equal to the predetermined time interval td. The counting circuit 112 increments the count value of the counting signal SCT in response to each period of the clock signal CLK. In another embodiment, the clock signal CLK has multiple rising edges, each of which is generated when the clock signal CLK transitions from an inactive state (e.g., a logic "0") to an active state (e.g., a logic "1"), and the predetermined time interval td is between each two consecutive rising edges. In this embodiment, the counting circuit 112 increments the count value of the counting signal SCT in response to each rising edge of the clock signal CLK. In another embodiment, the counting circuit 112 increments the count value of the counting signal SCT from an initial count value L0 to a predetermined maximum count value LM.

[0035] Table 1 shows the operation of the exemplary counting circuit 112T according to an embodiment of the present invention. The counting circuit 112T can be implemented as follows: Figure 1 Counting circuit 112. In one embodiment, as Figure 4As shown, the counting circuit 112T is configured to receive a trigger signal STR and a clock signal CLK. Based on the trigger signal STR and the clock signal CLK, the counting circuit 112T outputs a counting signal SCT. The counting signal SCT has a count value, represented by L consecutive digital bits D[L-1], ..., D[0] as shown in Table 1, where L is an integer greater than 0. Specifically, when the trigger signal STR is in a deactivated state (e.g., logic "0"), the count value of the counting signal SCT is an initial value L0. After the trigger signal STR transitions from a deactivated state (e.g., logic "0") to an activated state (e.g., logic "1"), the counting circuit 112T increments the count value of the counting signal SCT by one at each rising edge of the clock signal CLK until the count value of the counting signal SCT increases from the initial count value L0 to a predetermined maximum count value LM. For example, in Table 1, where L = 4, the counting circuit 112T has 64 states S1, ..., S64. Assume that the initial count value of the counting circuit 112T is 00000 when the trigger signal STR is in the non-excited state (for example, logic "0"), when the first rising edge of the clock signal CLK arrives after the trigger signal STR is converted to the excited state (for example, logic "1"), the count value of the counting circuit 112T increases from the initial count value 00000 to 00001. Similarly, when the next rising edge of the clock signal CLK arrives, the count value of the counting circuit 112T then increases from 00001 to 00010. The counting circuit 112T repeats the above operation until the count value of the counting signal SCT reaches the preset maximum count value LM. In one embodiment, the preset maximum count value LM can be determined by the number of LED light strings. For example, when the LED driver integrated circuit 100 drives 16 LED light strings, the preset maximum count value LM can be set to 10001. In another embodiment, the number of digital bits L is set so that 2 L ≥LM.

[0036] Table 1

[0037] state D[4] D[3] D[2] D[1] D[0] S1 0 0 0 0 0 S2 0 0 0 0 1 S3 0 0 0 1 0 S4 0 0 0 1 1 S5 0 0 1 0 0 S6 0 0 1 0 1 S7 0 0 1 1 0 S8 0 0 1 1 1 S9 0 1 0 0 0 S10 0 1 0 0 1 S11 0 1 0 1 0 S12 0 1 0 1 1 S13 0 1 1 0 0 S14 0 1 1 0 1 S15 0 1 1 1 0 S16 0 1 1 1 1 S17 1 0 0 0 0 S18 1 0 0 0 1 … … … … … … S64 1 1 1 1 1

[0038] The enable circuit 113 is configured to generate a plurality of LED enable control signals SS1, ..., SSi, ..., SSN and a downstream enable control signal SOUT based on a count signal SCT. The plurality of LED enable control signals SS1, ..., SSi, ..., SSN correspond one-to-one to the plurality of LED enable circuits CHL1, ..., CHLi, ..., CHLN and are respectively configured to selectively enable or disable the plurality of LED enable circuits CHL1, ..., CHLi, ..., CHLN. The downstream enable circuit SOUT is configured to selectively enable or disable the downstream enable circuit CHD. Specifically, for each i from 1 to N, when the LED enable control signal SSi is in an active state (e.g., a logic "1"), the corresponding LED enable circuit CHLi is enabled, and when the LED enable control signal SSi is in a non-active state (e.g., a logic "0"), the corresponding LED enable circuit CHLi is disabled. Similarly, when the downstream enable control signal SOUT is in an activated state (eg, logic “1”), the downstream enable circuit CHD is enabled, and when the downstream enable control signal SOUT is in a deactivated state (eg, logic “0”), the downstream enable circuit CHD is disabled.

[0039] Figure 3 FIG. 1 is a waveform diagram of an exemplary enabling circuit 113W according to an embodiment of the present invention. The enabling circuit 113W can be implemented as follows: Figure 1The enable circuit 113 is shown. For convenience, the following description assumes that the LED driver integrated circuit 100 is used to drive 16 LED enable circuits. The enable circuit 113W is configured to convert a digital count signal SCT into a plurality of analog LED enable control signals SS1, ..., SSi, ..., SSN, and an analog downstream enable control signal SSD. Specifically, the enable circuit 113W receives the count signal SCT. When the count value of the count signal SCT transitions from 00000 to 00001, the LED enable control signal SS1 transitions from a deactivated state (e.g., a logic "0") to an activated state (e.g., a logic "1") to enable the LED enable circuit CHL1. Similarly, when the count value of the count signal SCT transitions from 00001 to 00010, the LED enable control signal SS2 transitions from a deactivated state (e.g., a logic "0") to an activated state (e.g., a logic "1") to enable the LED enable circuit CHL2. The enabling circuit 113W repeats the above operation until the LED enabling circuit CHL16 is enabled when the count value of the counting signal SCT changes from 01111 to 10000. Thereafter, when the count value of the counting signal SCT changes from 10000 to 10001, the downstream enabling control signal SSD changes from a non-activated state (e.g., logic "0") to an activated state (e.g., logic "1") to enable the downstream enabling circuit CHD.

[0040] Figure 4 FIG. 4 is a schematic diagram of an LED driver integrated circuit 400 according to an embodiment of the present invention. In the LED driver integrated circuit 400, the enable detection circuit may be Figure 2A In another embodiment, the comparator CMP may be implemented as Figure 2B The counting circuit may be implemented by the aforementioned counting circuit 112T, the enabling circuit may be implemented by the enabling circuit 113W, the LED enabling circuit CHLi (i=1, 2, ..., or N) may be implemented by the LED enabling switch Si, and the downstream enabling circuit CHD may be implemented by the inverter INV and the downstream enabling switch SD.

[0041] Figure 5 is a waveform diagram of the LED driver integrated circuit 400. Figure 5The operation of the LED driver integrated circuit 400 is described. For convenience, the following description will assume that the LED driver integrated circuit 100 is used to drive 16 LED enable circuits to illustrate the operation of the enable circuit 113. When the level of the enable signal SEN is higher than the level of the enable threshold signal STH1 (for example, 2V), at time point t0, the trigger signal STR output by the comparator CMP is converted to an excited state (for example, a logic "1"), so that the counting circuit 112 increases the count value of the count signal SCT from the initial value (for example, Figure 5 As shown in the figure 00000) starts to increase the count. Figure 5 As shown, after the trigger signal STR transitions to the activated state, the first rising edge of the clock signal CLK arrives. At time t1, the count signal SCT increases from 00000 to 00001, causing the LED enable control signal SS1 output by the enable circuit 113 to be activated (e.g., a logic "1"). Consequently, the activated LED enable control signal SS1 turns on the LED enable switch S1, thereby activating the corresponding LED light string SLED1. Then, after a predetermined time interval td, at time t2, the second rising edge of the clock signal CLK arrives, causing the count signal SCT to increase from 00001 to 00010. This causes the LED enable control signal SS2 output by the enable circuit 113 to be activated (e.g., a logic "1"). This activated LED enable control signal SS2 turns on the LED enable switch S2, thereby activating the corresponding LED light string SLED2. The above operation is repeatedly performed until the counting signal SCT increases from 01111 to 10000, the last LED string SLED16 is activated at time t16, and the LED enable control signal SS16 is therefore converted to an activated state (eg, logic “1”).

[0042] Next, at time t17, when the next rising edge of the clock signal CLK arrives, the count signal SCT increases from 10000 to 10001, causing the downstream enable control signal SSD output by the enable circuit 113 to be in an activated state (e.g., logic "1"), and the inverted downstream enable control signal SSD1 output by the inverter INV to be in a deactivated state (e.g., logic "0"). Therefore, the deactivated inverted downstream enable control signal SSD1 turns off the downstream enable switch SD, causing the downstream enable signal SOUT to be at a high voltage level and in an enabled state (e.g., logic "1").

[0043] Figure 6FIG. 6 is a schematic diagram of an LED driving system 600 according to an embodiment of the present invention. The LED driving system 600 includes a first LED driving integrated circuit IC1 and a second LED driving integrated circuit IC2. The first LED driving integrated circuit IC1 is used to drive an LED array ALED1. The LED array ALED1 has the following features: Figure 1 The LED array ALED is configured as shown. The second LED driver integrated circuit IC2 is used to drive the LED array ALED2. The LED array ALED2 has the following features: Figure 1 The LED array ALED is set as shown. The first LED driver integrated circuit IC1 and the second LED driver integrated circuit IC2 can be the LED driver integrated circuits described in the above embodiment. In one embodiment, the first LED driver integrated circuit IC1 and the second LED driver integrated circuit IC2 can be as follows Figure 1 In another embodiment, the first LED driver integrated circuit IC1 and the second LED driver integrated circuit IC2 may be as follows: Figure 4 The LED driver integrated circuit 400 is shown. The enable pin RDYIN of the second LED driver integrated circuit IC2 is coupled to the downstream enable pin of the first LED driver integrated circuit IC1 to receive the downstream enable signal SOUT from the first LED driver integrated circuit IC1 as the enable signal SEN of the second LED driver integrated circuit IC2.

[0044] Next, the operation of the LED driving system 600 will be described. When the level of the enable signal SEN received from the first LED driver integrated circuit IC1 is higher than the level of the enable threshold signal STH1 (e.g., 2V), at time point t0, the trigger signal STR output by the comparator CMP is converted to an excited state (e.g., logic "1"), so that the counting circuit 112 increases the count value of the counting signal SCT from the initial value (e.g., Figure 5 As shown in the figure 00000) starts to increase the count. Figure 5As shown, after the trigger signal STR transitions to the activated state, the first rising edge of the clock signal CLK arrives. At time t1, the count value of the count signal SCT increases from 00000 to 00001, causing the LED enable control signal SS1 output by the enable circuit 113 to be in the activated state (e.g., a logic "1"). Therefore, the activated LED enable control signal SS1 turns on the LED enable switch S1, thereby activating the corresponding LED light string SLED1. Then, after a predetermined time interval td, at time t2, the second rising edge of the clock signal CLK arrives, causing the count value of the count signal SCT to increase from 00001 to 00010. This causes the LED enable control signal SS2 output by the enable circuit 113 to be in the activated state (e.g., a logic "1"). The activated LED enable control signal SS2 turns on the LED enable switch S2, thereby activating the corresponding LED light string SLED2. The above operation is repeatedly performed until the count value of the counting signal SCT increases from 01111 to 10000, the last LED string SLED16 is activated at time t16, and the LED enable control signal SS16 is therefore converted to an activated state (eg, logic "1").

[0045] Next, at time t17, when the next rising edge of the clock signal CLK arrives, the count value of the count signal SCT increases from 10000 to 10001, causing the downstream enable control signal SSD output by the enable circuit 113 to be in an activated state (e.g., logic "1"), and the inverted downstream enable control signal SSD1 output by the inverter INV to be in a deactivated state (e.g., logic "0"). Therefore, the deactivated inverted downstream enable control signal SSD1 turns off the downstream enable switch SD, causing the downstream enable signal SOUT to be at a high voltage level and in an enabled state (e.g., logic "1"). Since the second LED driver integrated circuit IC2 receives the downstream enable signal SOUT from the first driver integrated circuit IC1 as the enable signal SEN of the second LED driver integrated circuit IC2, the level of the downstream enable signal SOUT in the excited state output by the first driver integrated circuit IC will be higher than the level of the enable threshold signal STH1 of the second LED driver integrated circuit IC2 (for example, 2V). Therefore, the second LED driver integrated circuit IC2 will repeatedly perform the above-mentioned operation of the first driver integrated circuit IC to activate the multiple LED light strings SLED1, SLEDi, ..., SLED16 driven by the second LED driver integrated circuit IC2.

[0046] As can be seen from the operation of LED driver system 600 described above, the first LED driver integrated circuit IC1 can output a downstream enable signal SOUT from its downstream enable pin RDYOUT to the second LED driver integrated circuit IC2. This supports the communication of delay information between the time when the first LED driver integrated circuit IC1 activates the last LED string SLED 16 in its driven LED array ALED1 and the time when the second LED driver integrated circuit IC2 activates the first LED string SLED 1 in its driven LED array ALED2. This significantly simplifies the architecture for synchronizing the timing of illuminating LED strings between two adjacent LED driver integrated circuits. In particular, compared to conventional differential interface solutions where all integrated circuits receive enable signals from a microcontroller unit, the LED driver integrated circuit of the present invention frees up resources from the microcontroller unit.

[0047] Those skilled in the art will appreciate that the present invention is not limited to the specific details and specifications described above. Rather, the scope of the present invention is defined by the claims and includes any combination and subcombination of the various features described above, as well as variations and modifications based on these combinations and subcombinations that are apparent to those skilled in the art after reading the above description and that do not fall within the prior art.

Claims

1. An LED driver integrated circuit for driving multiple LED light strings, comprising: Enable pin, used to provide an enable signal; a plurality of LED enabling circuits corresponding one-to-one to the plurality of LED light strings, wherein each LED enabling circuit is coupled to a corresponding LED light string and is configured to activate the corresponding LED light string when enabled; a downstream enabling circuit, configured to provide a downstream enabling signal, wherein when the downstream enabling circuit is enabled, the downstream enabling signal is in an enabled state; a control circuit coupled to the enable pin to receive the enable signal, wherein the control circuit sequentially enables the plurality of LED enable circuits in response to the enable signal and enables the downstream enable circuit after all of the plurality of LED enable circuits are enabled; as well as The downstream enable pin is coupled to the downstream enable circuit and is used to output the downstream enable signal.

2. The LED driver integrated circuit according to claim 1, wherein the control circuit comprises: an enable detection circuit, configured to receive the enable signal and the enable threshold signal, and generate a trigger signal based on a comparison between the enable signal and the enable threshold signal; a counting circuit for generating a counting signal having a counting value, wherein the counting circuit is configured to increase the counting value at each predetermined time interval in response to the trigger signal; as well as an enabling circuit for generating a plurality of LED enable control signals and a downstream enable control signal based on the counting signal, wherein the plurality of LED enable control signals correspond one-to-one to the plurality of LED enabling circuits, and each LED enable control signal is used to selectively enable or disable the corresponding LED enabling circuit, and the downstream enable control signal is used to selectively enable or disable the downstream enabling circuit.

3. The LED driver integrated circuit of claim 2 , wherein the counting circuit is further configured to receive a clock signal, the clock signal having a plurality of rising edges with the predetermined time interval between each two consecutively adjacent rising edges, and the counting circuit increments the count value from an initial count value to a predetermined maximum count value in response to each rising edge of the clock signal.

4. The LED driver integrated circuit of claim 2 , wherein the counting signal is in digital form including at least one digital bit, and the enabling circuit is configured to convert the counting signal in digital form into analog forms for the plurality of LED enable control signals and the downstream enable control signal.

5. The LED driver integrated circuit of claim 1 , wherein the downstream enable circuit comprises a downstream enable switch, the downstream enable switch including a first terminal, a second terminal, and a control terminal, wherein the first terminal of the downstream enable switch is coupled to a supply voltage and is used to provide the downstream enable signal, the second terminal of the downstream enable switch is coupled to a reference ground, and wherein the downstream enable switch is configured to receive a downstream enable control signal at the control terminal, and the downstream enable switch is selectively turned on or off in response to the downstream enable control signal.

6. The LED driver integrated circuit of claim 1, wherein the control circuit is configured to sequentially enable the plurality of LED enabling circuits and the downstream enabling circuit at a plurality of enabling times, wherein a predetermined time interval exists between each two adjacent enabling times.

7. The LED driver integrated circuit of claim 1 , wherein each LED enable circuit comprises an LED enable switch, wherein the LED enable switch comprises a first terminal, a second terminal, and a control terminal, the first terminal of the LED enable switch being coupled to the corresponding LED light string, the second terminal of the LED enable switch being coupled to a reference ground, and wherein the LED enable switch is configured to receive an LED enable control signal at the control terminal, and the LED enable switch is selectively turned on or off in response to the LED enable control signal.

8. An LED driver integrated circuit for driving a plurality of LED light strings, comprising: Enable pin, used to receive an enable signal; a control circuit coupled to the enable pin to receive the enable signal and configured to generate a plurality of LED enable control signals and a downstream enable control signal based on the enable signal; a plurality of LED enable circuits corresponding one-to-one to the plurality of LED light strings and the plurality of LED enable control signals, wherein each LED enable circuit is coupled to the control circuit to receive a corresponding LED enable control signal, and each LED enable circuit is coupled to a corresponding LED light string and is configured to activate or deactivate the corresponding LED light string in response to the corresponding LED enable control signal; a downstream enable switch coupled to the control circuit to receive the downstream enable control signal and configured to provide a downstream enable signal based on the downstream enable control signal; as well as a downstream enable pin, coupled to the downstream enable switch and configured to output the downstream enable signal; The control circuit enables the plurality of LED enable circuits in sequence in response to the enable signal, and provides the downstream enable signal in an enabled state after all of the plurality of LED enable circuits are enabled.

9. The LED driver integrated circuit according to claim 8, wherein the control circuit comprises: an enable detection circuit, configured to receive the enable signal and the enable threshold signal, and generate a trigger signal based on a comparison between the enable signal and the enable threshold signal; a counting circuit for generating a counting signal having a counting value, wherein the counting circuit is configured to increase the counting value at each predetermined time interval in response to an excited state of the trigger signal; as well as an enabling circuit for generating a plurality of LED enable control signals and the downstream enable control signal based on the counting signal, wherein the plurality of LED enable control signals correspond one-to-one to the plurality of LED enable circuits, and each LED enable control signal is used to selectively enable or disable the corresponding LED enable circuit, and the downstream enable control signal is used to selectively enable or disable the downstream enable switch.

10. The LED driver integrated circuit of claim 9 , wherein the counting circuit is further configured to receive a clock signal, the clock signal having a plurality of rising edges with the predetermined time interval between each two consecutively adjacent rising edges, and the counting circuit increases the count value from an initial count value to a predetermined maximum count value in response to each rising edge of the clock signal.

11. The LED driver integrated circuit of claim 9 , wherein the counting signal is in digital form including at least one digital bit, and the enabling circuit is configured to convert the counting signal in digital form into the plurality of LED enable control signals and the downstream enable control signal in analog form.

12. The LED driver integrated circuit of claim 8 , wherein the downstream enable switch comprises a first terminal, a second terminal, and a control terminal, wherein the first terminal of the downstream enable switch is coupled to a downstream enable resistor to receive a supply voltage and to provide the downstream enable signal, the second terminal of the downstream enable switch is coupled to a reference ground, and wherein the downstream enable switch is configured to receive the downstream enable control signal at the control terminal, and the downstream enable switch is selectively turned on or off in response to the downstream enable control signal.

13. The LED driver integrated circuit according to claim 8, wherein the control circuit is configured to sequentially enable the plurality of LED enabling circuits and the downstream enabling switch at a plurality of enabling times, wherein a predetermined time interval exists between each two adjacent enabling times.

14. The LED driver integrated circuit of claim 8 , wherein each LED enable circuit comprises an LED enable switch, wherein the LED enable switch comprises a first terminal, a second terminal, and a control terminal, the first terminal of the LED enable switch being coupled to the corresponding LED light string, the second terminal of the LED enable switch being coupled to a reference ground, and wherein the LED enable switch is configured to receive an LED enable control signal at the control terminal, and the LED enable switch is selectively turned on or off in response to the LED enable control signal.

15. An LED driving system, characterized in that: include: The first LED driver integrated circuit and the second LED driver integrated circuit are respectively used to drive two sets of LED arrays, each set of LED arrays including a plurality of LED light strings, wherein the first LED driver integrated circuit and the second LED driver integrated circuit each include: Enable pin, used to receive an enable signal; a plurality of LED enabling circuits corresponding one-to-one to the plurality of LED light strings, wherein each LED enabling circuit is coupled to a corresponding LED light string and configured to activate the corresponding LED light string when the LED enabling circuit is enabled; a downstream enabling circuit, configured to provide a downstream enabling signal, wherein when the downstream enabling circuit is enabled, the downstream enabling signal is in an enabled state; a control circuit coupled to the enable pin to receive the enable signal, wherein the control circuit sequentially enables the plurality of LED enable circuits in response to the enable signal and enables the downstream enable circuit after the LED enable circuit is enabled; and a downstream enable pin, coupled to the downstream enable circuit and configured to output the downstream enable signal; The enable pin of the second LED driver integrated circuit is coupled to the downstream enable pin of the first LED driver integrated circuit.

16. The LED driving system according to claim 15, wherein the control circuit comprises: an enable detection circuit, configured to receive the enable signal and the enable threshold signal, and generate a trigger signal based on a comparison between the enable signal and the enable threshold signal; a counting circuit for generating a counting signal having a counting value, wherein the counting circuit is configured to increase the counting value at each predetermined time interval in response to an excited state of the trigger signal; as well as an enabling circuit for generating a plurality of LED enable control signals and a downstream enable control signal based on the counting signal, wherein the plurality of LED enable control signals correspond one-to-one to the plurality of LED enabling circuits, and each LED enable control signal is used to selectively enable or disable the corresponding LED enabling circuit, and the downstream enable control signal is used to selectively enable or disable the downstream enabling circuit.

17. The LED driving system of claim 16 , wherein the counting circuit is further configured to receive a clock signal, the clock signal having a plurality of rising edges with the predetermined time interval between each two consecutively adjacent rising edges, and the counting circuit increases the count value from an initial count value to a predetermined maximum count value in response to each rising edge of the clock signal.

18. The LED driving system according to claim 16, wherein the counting signal is in digital form including at least one digital bit, and the enabling circuit is used to convert the counting signal in digital form into the plurality of LED enabling control signals and the downstream enabling control signal in analog form.

19. The LED driving system of claim 15 , wherein the downstream enabling circuit comprises a downstream enabling switch, the downstream enabling switch including a first terminal, a second terminal, and a control terminal, wherein the first terminal of the downstream enabling switch is coupled to a downstream enabling resistor to receive a supply voltage and to provide the downstream enabling signal, the second terminal of the downstream enabling switch is coupled to a reference ground, and wherein the downstream enabling switch is configured to receive a downstream enabling control signal at the control terminal, and the downstream enabling switch is selectively turned on or off in response to the downstream enabling control signal. 20 . The LED driving system of claim 15 , wherein the control circuit is configured to sequentially enable the plurality of LED enabling circuits and the downstream enabling circuit at a plurality of enabling times, wherein a predetermined time interval exists between each two adjacent enabling times.

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