Electrical test structure and electrical test method

Abstract

The present application relates to an electrical test structure and an electrical test method. The electrical test structure comprises: a plurality of test components, each of which comprises a test structure and a protection structure electrically connected to the test structure; and a plurality of pads, each of which is connected to two test components and each of which can be connected to two test components at the same time, and the protection structure in each test component is used to control whether the test structure and the pad are conductive. The present application can effectively save the number of pads, improve the anti-interference of the test components themselves, and reduce the interference between the test structures.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to an electrical testing structure and an electrical testing method. Background Technology

[0002] With the development of planar flash memory, semiconductor manufacturing processes have made tremendous progress. However, in recent years, the development of planar flash memory has encountered various challenges: physical limits, limitations of existing development technologies, and limits of storage electron density. Against this backdrop, in order to solve the difficulties encountered by planar flash memory and to pursue lower production costs per unit of storage cell, various three-dimensional (3D) flash memory structures have emerged, such as 3D NOR (3D NAND) flash memory and 3D NAND (3D NAND) flash memory.

[0003] To ensure the performance of semiconductor devices such as 3D NAND, electrical test structures involving multiple structures under test (DUTs) and multiple bonding pads are required for electrical testing. However, current electrical test structures are prone to interfering with other DUTs (such as those adjacent to the one being tested) during the electrical testing of one DUT, thus affecting subsequent electrical testing of other DUTs.

[0004] Therefore, how to reduce the interference between the structures under test during electrical testing and ensure that the electrical test is carried out smoothly and stably is a technical problem that urgently needs to be solved. Summary of the Invention

[0005] This invention provides an electrical testing structure and method to solve the problem of mutual interference between structures under test during electrical testing, thereby ensuring that the electrical testing process is carried out smoothly and stably.

[0006] To address the above problems, the present invention provides an electrical testing structure, comprising:

[0007] Multiple components under test, each component under test including a structure under test and a protection structure electrically connected to the structure under test;

[0008] Multiple solder pads are provided, each component under test is connected to two solder pads, and each solder pad can connect to two components under test simultaneously. The protection structure within each component under test is used to control whether there is electrical connection between the component under test and the solder pads.

[0009] Optional, also includes:

[0010] The test component includes a test structure, which is electrically connected to a plurality of the solder pads and is used to apply test signals to the solder pads.

[0011] Optionally, the protection structure includes a unidirectional current conduction element.

[0012] Optionally, the current-conducting element is a transistor.

[0013] Optionally, the current-conducting element is a diode.

[0014] Optionally, in the same component under test, the structure under test and the protection structure are connected in series.

[0015] Optionally, in one of the components under test connected to the two pads, the input terminal of the structure under test is connected to one of the pads, the first end of the protection structure is connected to the output terminal of the structure under test, the second end of the protection structure is connected to the other pad, and the protection structure is forward biased when current is input from the first end and reverse biased when current is input from the second end.

[0016] Optionally, in two components under test connected to the same pad, the second end of the protection structure in one component under test is connected to the input end of the protection structure in that component under test, and the first end of the protection structure in the other component under test is connected to the output end of the protection structure in that component under test. The protection structure is forward biased when current is input from the first end and reverse biased when current is input from the second end.

[0017] Optionally, the structure under test is a dielectric breakdown voltage test structure, and the sum of the reverse-bias breakdown voltage of the protection structure in each component under test and the estimated breakdown voltage of the structure under test is greater than the maximum estimated breakdown voltage in each structure under test.

[0018] Optionally, the structure under test is a gate oxide capacitor structure, a metal-insulator-metal capacitor structure, or a metal-oxide-metal capacitor structure.

[0019] Optionally, the current-conducting element is a transistor;

[0020] In one of the components under test (DUTs) connected to the two said pads, the input of the DUT is connected to one of the said pads, the output of the DUT is connected through the input of the protection structure, and the output of the protection structure is connected to the other said pad.

[0021] Optionally, the component under test further includes:

[0022] A control circuit, connected to the control terminal of the protection structure, is used to control whether the input terminal and the output terminal of the protection structure are connected.

[0023] Optional, also includes:

[0024] Substrate, the substrate including chip region and dicing region;

[0025] The component under test and the solder pad are located in the chip region; or...

[0026] The component under test and the solder pad are located in the cut track area.

[0027] To address the above problems, the present invention also provides an electrical testing method, comprising the following steps:

[0028] The system is configured with multiple components under test (UDTs) and multiple solder pads connected to the multiple UDTs respectively. Each UDT includes a structure under test (SUT) and a protection structure electrically connected to the SUT. Each UDT is connected to two solder pads, and each solder pad can connect to two UDTs simultaneously.

[0029] Connect multiple of the solder pads to a test component, and select a component under test as the target component under test;

[0030] The test component applies a test signal to one of the pads connected to the target component under test, controls the protection structure in the target component under test to be turned on, and controls the protection structure in at least one other component under test connected to the same pad to be turned off.

[0031] Optionally, the protection structure includes a unidirectional current conduction element.

[0032] Optionally, the specific steps of configuring multiple components under test (UDT) and multiple solder pads respectively connected to the multiple UDTs include:

[0033] Multiple components under test and multiple solder pads are formed;

[0034] The structure under test and the protection structure in each of the components under test are connected in series, and multiple components under test are connected to multiple solder pads respectively.

[0035] Optionally, the plurality of components under test (DUTs) and the plurality of solder pads are arranged in a configuration order. In one DUT connected to two solder pads, the input terminal of the DUT is connected to one solder pad, the first terminal of the protection structure is connected to the output terminal of the DUT, and the second terminal of the protection structure is connected to the other solder pad. The protection structure is forward biased when current is input from the first terminal and reverse biased when current is input from the second terminal. The electrical testing method further includes the following steps:

[0036] The component under test is selected sequentially according to the configuration order as the target component under test, and when a test voltage is applied to a pad connected to the target component under test, the protection structure in the target component under test is controlled to be turned on, and the protection structure in the component under test located after the target component under test according to the configuration order is controlled to be turned off.

[0037] Optionally, in two components under test connected to the same solder pad, the second end of the protection structure in one component under test is connected to the input terminal of the protection structure in that component under test, and the first end of the protection structure in the other component under test is connected to the output terminal of the protection structure in that component under test. The protection structure is forward biased when current is input from the first end and reverse biased when current is input from the second end. The electrical testing method further includes:

[0038] Arbitrarily select one of the components under test as the target component under test, and when a test voltage is applied to one of the pads connected to the target component under test, control the protection structure in the target component under test to be turned on, and control the protection structure in another component under test connected to the same pad as the target component under test to be turned off.

[0039] Optionally, the current-conducting element is a diode.

[0040] Optionally, the test signal is a dielectric breakdown test signal.

[0041] The electrical testing structure and method provided by this invention enable pad sharing among multiple components under test (DUTs) and multiple solder pads within the electrical testing structure. Each DUT is connected to two solder pads, and each solder pad can simultaneously connect to two DUTs, thereby effectively saving the number of solder pads required. Furthermore, the DUTs provided by this invention include a structure under test (SUT) and a protection structure. The protection structure controls the continuity between the solder pads and the SUT, preventing the test signal from flowing to a non-selected SUT when a test signal is applied to a shared solder pad. This improves the DUT's own anti-interference capability and reduces interference between SUTs. Attached Figure Description

[0042] Appendix Figure 1 This is a schematic diagram of the electrical testing structure in a specific embodiment of the present invention;

[0043] Appendix Figure 2 This is a circuit connection diagram of an electrical testing structure in a specific embodiment of the present invention;

[0044] Appendix Figure 3This is another circuit connection diagram of the electrical test structure in a specific embodiment of the present invention;

[0045] Appendix Figure 4 This is a top view schematic diagram of the electrical testing structure in a specific embodiment of the present invention;

[0046] Appendix Figure 5 This is a flowchart of the electrical testing method in a specific embodiment of the present invention. Detailed Implementation

[0047] The specific implementation methods of the electrical testing structure and electrical testing method provided by the present invention will be described in detail below with reference to the accompanying drawings.

[0048] In integrated circuit wafers, electrical test structures are placed in the dicing area and connected to pads via metal wires. During electrical testing, signal lines from the test instrument contact the pads through probes to apply test signals to the electrical test structures. Multiple electrical test structures are typically placed in the dicing area of ​​an integrated circuit wafer, and during testing, the signal endpoints of each electrical test structure need to be connected to a pad. As the number of electrical test structures increases, the number of pads required also increases. With the increasing complexity of integrated circuit processes, the number of electrical test structures that need to be placed in the dicing area increases significantly, while the number of pads in the dicing area remains relatively constant. This makes it difficult to meet the needs of all electrical test structures with the available pads. To solve this problem, multiple electrical test structures can share a single pad, for example, two electrical test structures can share one pad. However, the shared pad testing method can easily affect other electrical test structures during the testing of one electrical test structure. For example, when performing dielectric breakdown testing on one electrical test structure, it can easily cause breakdown of other electrical test structures, thereby affecting the normal electrical testing of other electrical test structures.

[0049] To improve the anti-interference capability of the structure under test and thus reduce interference between structures under test, this specific embodiment provides an electrical test structure, attached... Figure 1 This is a schematic diagram of the electrical testing structure in a specific embodiment of the present invention. The electrical testing structure includes:

[0050] Multiple components under test, each component under test including a structure under test and a protection structure electrically connected to the structure under test;

[0051] Multiple solder pads are provided, each component under test is connected to two solder pads, and each solder pad can connect to two components under test simultaneously. The protection structure within each component under test is used to control whether there is electrical connection between the component under test and the solder pads.

[0052] In this specific embodiment, "multiple" refers to two or more. This specific embodiment, by configuring each component under test (DUT) to connect to two solder pads, and each solder pad simultaneously connecting to two DUTs, allows any two DUTs in the electrical test structure to share one solder pad, effectively reducing the number of solder pads required to satisfy all DUTs in the electrical test structure. The two solder pads connected to one DUT can be adjacent or non-adjacent; the two DUTs simultaneously connected to one solder pad can also be adjacent or non-adjacent. In one embodiment, the two solder pads connected to one DUT are adjacent, and the DUTs simultaneously connected to one solder pad are also adjacent, thereby simplifying the internal wiring of the electrical test structure, shortening the connection length between the solder pad and the DUT, and reducing circuit loss.

[0053] Optionally, the electrical test structure further includes:

[0054] The test assembly includes a test structure 12 distributed across a plurality of the solder pad electrical connections for applying test signals to the solder pads.

[0055] Specifically, such as Figures 1-3 As shown, the test structure 12 is electrically connected to the first solder pad 111, the second solder pad 112, the third solder pad 113, and the fourth solder pad 114 via multiple probes 13. The test signal emitted by the test structure 12 is transmitted to the solder pads via the probes 13.

[0056] Appendix Figure 2 This is a circuit connection diagram of an electrical testing structure according to a specific embodiment of the present invention, attached. Figure 3 This is another circuit connection diagram of the electrical testing structure in a specific embodiment of the present invention. For example, such as... Figures 1-3As shown, the electrical test structure includes a first component under test (DUT) 101, a second DUT 102, a third DUT 103, a first solder pad 111, a second solder pad 112, a third solder pad 113, and a fourth solder pad 114. The first DUT 101 is connected to the first solder pad 111 and the second solder pad 112 at both ends. The second DUT 102 is connected to the second solder pad 112 and the third solder pad 113 at both ends. The third DUT 103 is connected to the third solder pad 113 and the fourth solder pad 114 at both ends. The first DUT 101 and the second DUT 102 share the second solder pad 112, and the second DUT 102 and the third DUT 103 share the third solder pad 113, thus requiring only three solder pads for both DUTs, thereby reducing the number of solder pads. The first component under test 101 includes a first structure under test 1011 and a first protection structure 1012, the second component under test 102 includes a second structure under test 1021 and a second protection structure 1022, and the third component under test 103 includes a third structure under test 1031 and a third protection structure 1032. The first protection structure 1012 is used to control whether the first structure under test 1011 is connected to the first solder pad 111 or the second solder pad 112 (i.e., to control whether the first solder pad 111 is connected to the second solder pad 112). The second protection structure 1022 is used to control whether the second structure under test 1021 is connected to the second solder pad 112 or the third solder pad 113 (i.e., to control whether the second solder pad 112 is connected to the third solder pad 113). The third protection structure 1032 is used to control whether the third structure under test 1031 is connected to the third solder pad 113 or the fourth solder pad 114 (i.e., to control whether the third solder pad 113 is connected to the fourth solder pad 114).

[0057] This specific embodiment incorporates a protective structure connected to the structure under test (DUT) within the component under test (DUT). This protective structure controls the continuity between the DUT and the solder pads. Consequently, when a test signal is transmitted from one solder pad to the DUT within one DUT, even if other probes applying the test signal to other solder pads or the signal lines connecting other probes to the test structure are not in a floating state (i.e., neither the probes nor the signal lines are in contact with the solder pads), this embodiment prevents the test signal from flowing to other DUTs through the shared solder pads. This improves the DUT's anti-interference capability, reduces or even eliminates mutual interference between DUTs, and ensures that all DUTs in the electrical test structure can undergo electrical testing smoothly.

[0058] Optionally, the protection structure includes a unidirectional current conduction element.

[0059] Specifically, since the current unidirectional conduction element is directly and actively controlled by the direction of current input, there is no need to set up other control circuit structures, which helps to simplify the overall structure of the electrical test structure and the operation steps of the electrical test method.

[0060] Optionally, the unidirectional current-conducting element is a transistor. Since diodes are relatively simple to manufacture and occupy a relatively small area, in one embodiment, the unidirectional current-conducting element is a diode.

[0061] Optionally, in the same component under test, the structure under test and the protection structure are connected in series.

[0062] Optionally, the structure under test is a dielectric breakdown voltage test structure, and the sum of the reverse-bias breakdown voltage of the protection structure in each component under test and the estimated breakdown voltage of the structure under test is greater than the maximum estimated breakdown voltage in each structure under test.

[0063] Optionally, the structure under test is a gate oxide capacitor structure, a metal-insulator-metal capacitor structure, or a metal-oxide-metal capacitor structure.

[0064] Specifically, before performing a dielectric layer breakdown voltage test on a structure under test (SUT), the breakdown voltage of the SUT has an estimated range (i.e., the estimated breakdown voltage). The purpose of the dielectric layer breakdown voltage test is to obtain an accurate dielectric breakdown voltage value. The estimated breakdown voltages of multiple SUTs may be the same or different. To avoid damage to the SUT and to ensure the normal operation of the dielectric breakdown voltage test, this specific embodiment uses the maximum value of the estimated breakdown voltage of each SUT as a benchmark to select the appropriate unidirectional current conducting element. Furthermore, when selecting the unidirectional current conducting element, an appropriate reverse bias breakdown voltage margin is added to adequately protect the SUT connected in series, while considering cost, and to prevent the corresponding SUT from suffering soft damage.

[0065] When the structure under test is a dielectric breakdown voltage test structure, the dielectric in the structure under test can be, for example, any one of: ILD (Inter Layer Dielectric) dielectric, IMD (Inter Metal Dielectric) dielectric, or any one of: gate oxide capacitor, MIM (Metal Insulator Metal) capacitor, or MOM (Metal Oxide Metal) capacitor. In other embodiments, the dielectric can also be other dielectrics known to those skilled in the art.

[0066] In one embodiment, such as Figure 2 As shown, in a component under test connected to two pads, the input terminal of the structure under test is connected to one pad, the first end of the protection structure is connected to the output terminal of the structure under test, the second end of the protection structure is connected to the other pad, and the protection structure is forward biased when current is input from the first end and reverse biased when current is input from the second end.

[0067] The following explanation uses an example where the protection structure is a diode, the first end of the protection structure is the positive terminal of the diode, the second end of the protection structure is the negative terminal of the diode, and the structure under test is a dielectric breakdown voltage test structure. For example, such as... Figure 2 As shown, the first component under test (DUT) 101, the second DUT 102, and the third DUT 103 are arranged sequentially. The input terminal of the first DUT structure in the first DUT 101 is connected to the second solder pad 112, and the output terminal is connected to the first terminal of the first protection structure 1012. The second terminal of the first protection structure 1012 is connected to the first solder pad 111. The input terminal of the second DUT structure 1021 in the second DUT 102 is connected to the third solder pad 113, and the output terminal is connected to the first terminal of the second protection structure 1022. The second terminal of the second protection structure 1022 is connected to the second solder pad 112. The input terminal of the third DUT structure 1031 in the third DUT 103 is connected to the fourth solder pad 114, and the output terminal is connected to the first terminal of the third protection structure 1032. The second terminal of the third protection structure 1032 is connected to the third solder pad 113.

[0068] During electrical testing, each component under test is tested sequentially according to its arrangement. The following explanation uses an example where the protection structure is a diode, the first end of the protection structure is the anode of the diode, the second end of the protection structure is the cathode of the diode, and the structure under test is a dielectric breakdown voltage test structure. For example, such as... Figure 2 As shown, when testing the first structure under test 1011 in the first component under test 101, the test structure 12 applies a test signal to the second pad 112 through a probe 13. The first pad 111 is grounded, and the test signal flows from the second pad 112 to the first structure under test 1011. The first protection structure 1012 is forward biased and conducts, while the second protection structure 1022 in the second component under test 102 connected to the second pad 112 is reverse biased and cut off. This prevents the test signal from flowing to the second structure under test 1021, enhances the anti-interference capability of the second component under test 102, and reduces or even avoids the mutual influence between the first structure under test 1011 and the second structure under test 1021. After the first structure under test 1011 completes the dielectric breakdown voltage test, the test structure 12 applies a test signal to the third pad 113 through another probe 13. The second pad 112 is grounded, and the test signal flows from the third pad 113 to the second structure under test 1021. The second protection structure is forward biased and conducts, while the third protection structure 1032 in the third component under test 103 connected to the third pad 113 is reverse biased and cut off, thereby preventing the test signal from flowing to the third structure under test 1031. Since the first structure under test 1011 has completed the test, no further protection is needed. This process continues until all the components under test in the electrical test structure have completed the test sequentially.

[0069] In another embodiment, such as Figure 3 As shown, in two components under test connected to the same pad, the second end of the protection structure in one component under test is connected to the input end of the protection structure in that component under test, and the first end of the protection structure in the other component under test is connected to the output end of the protection structure in that component under test. The protection structure is forward biased when current is input from the first end and reverse biased when current is input from the second end.

[0070] The following explanation uses an example where the protection structure is a diode, the first end of the protection structure is the positive terminal of the diode, the second end of the protection structure is the negative terminal of the diode, and the structure under test is a dielectric breakdown voltage test structure. For example, such as... Figure 3As shown, in the first component under test 101, the input terminal of the first structure under test 1011 is connected to the second terminal of the first protection structure 1012, and the output terminal is connected to the second pad 112. The first terminal of the first protection structure 1012 is connected to the first pad 111. In the second component under test 102, the output terminal of the second structure under test 1021 is connected to the first terminal of the second protection structure 1022, and the input terminal is connected to the third pad 113. The second terminal of the second protection structure 1022 is connected to the second pad 112.

[0071] During electrical testing, it is not necessary to test multiple components under test sequentially. The following explanation will still use the example of a diode as the protection structure, the first end of the protection structure as the positive terminal of the diode, the second end of the protection structure as the negative terminal of the diode, and the structure under test as a dielectric breakdown voltage test structure. For example, such as... Figure 3 As shown, when testing the first structure under test 1011 in the first component under test 101, the test structure 12 applies a test signal to the first pad 111 through a probe 13. The second pad 112 is grounded. The test signal flows to the first component under test 101 through the first pad 111. The first protection structure 1012 is forward biased and conducts, while the second protection structure 1022 in the second component under test 102 connected to the second pad 112 is reverse biased and cut off. This prevents the test signal from flowing to the second structure under test 1021, enhances the anti-interference capability of the second component under test 102, and reduces or even avoids the mutual influence between the first structure under test 1011 and the second structure under test 1021. When testing the second structure under test 1021 in the second component under test 102, the test structure 12 applies a test signal to the third pad 113 through another probe 13. The second pad 112 is grounded, and the test signal flows to the second component under test 102 through the third pad 113. The second protection structure 1022 is forward biased and turned on, while the first protection structure 1012 in the first component under test 101 connected to the second pad 112 is reverse biased and turned off, thereby enhancing the anti-interference capability of the first component under test 101.

[0072] To improve the flexibility of test selection in the electrical test structure, the current-conducting element may optionally be a transistor;

[0073] In one of the components under test (DUTs) connected to the two said pads, the input of the DUT is connected to one of the said pads, the output of the DUT is connected through the input of the protection structure, and the output of the protection structure is connected to the other said pad.

[0074] Optionally, the component under test further includes:

[0075] A control circuit, connected to the control terminal of the protection structure, is used to control whether the input terminal and the output terminal of the protection structure are connected.

[0076] Appendix Figure 4 This is a top view schematic diagram of the electrical testing structure in a specific embodiment of the present invention. Optionally, such as... Figure 4 As shown, the electrical test structure further includes:

[0077] The substrate includes a chip region 40 and a dicing region 41;

[0078] The component under test and the solder pad are located in the chip region 40; or...

[0079] The component under test and the solder pad are located in the cut track region 41.

[0080] Specifically, the plurality of components under test (DUTs) and the plurality of solder pads can be disposed in the chip region 40 or in the dicing region 41. When the DUTs and the solder pads are both disposed in the dicing region 41, the DUTs and the solder pads should be located in the same dicing channel to simplify the electrical connection operation between the DUTs and the solder pads.

[0081] Furthermore, this specific embodiment also provides an electrical testing method, attached... Figure 5 This is a flowchart of the electrical testing method in a specific embodiment of the present invention. The electrical testing method provided in this specific embodiment can be adopted as follows: Figures 1-4 The electrical test structure shown is implemented. For example... Figures 1-5 As shown, the electrical testing method includes the following steps:

[0082] Step S51: Configure multiple components under test (UTPs) and multiple solder pads connected to the multiple UTPs respectively. Each UTP includes a structure under test (SUT) and a protection structure electrically connected to the SUT. Each UTP is connected to two solder pads, and each solder pad can connect to two UTPs simultaneously.

[0083] Step S52: Connect the plurality of solder pads to a test component and select a component under test as the target component under test;

[0084] Step S53: Apply a test signal to one of the solder pads connected to the target component under test through the test component, and control the protection structure in the target component under test to be turned on, and control the protection structure in at least one other component under test connected to the same solder pad as the target component under test to be turned off.

[0085] Optionally, the protection structure includes a unidirectional current conduction element.

[0086] Optionally, the specific steps of configuring multiple components under test (UDT) and multiple solder pads respectively connected to the multiple UDTs include:

[0087] Multiple components under test and multiple solder pads are formed;

[0088] The structure under test and the protection structure in each of the components under test are connected in series, and multiple components under test are connected to multiple solder pads respectively.

[0089] Optionally, the plurality of components under test (DUTs) and the plurality of solder pads are arranged in a configuration order. In one DUT connected to two solder pads, the input terminal of the DUT is connected to one solder pad, the first terminal of the protection structure is connected to the output terminal of the DUT, and the second terminal of the protection structure is connected to the other solder pad. The protection structure is forward biased when current is input from the first terminal and reverse biased when current is input from the second terminal. The electrical testing method further includes the following steps:

[0090] The component under test is selected sequentially according to the configuration order as the target component under test, and when a test voltage is applied to a pad connected to the target component under test, the protection structure in the target component under test is controlled to be turned on, and the protection structure in the component under test located after the target component under test according to the configuration order is controlled to be turned off.

[0091] Optionally, in two components under test connected to the same solder pad, the second end of the protection structure in one component under test is connected to the input terminal of the protection structure in that component under test, and the first end of the protection structure in the other component under test is connected to the output terminal of the protection structure in that component under test. The protection structure is forward biased when current is input from the first end and reverse biased when current is input from the second end. The electrical testing method further includes:

[0092] Arbitrarily select one of the components under test as the target component under test, and when a test voltage is applied to one of the pads connected to the target component under test, control the protection structure in the target component under test to be turned on, and control the protection structure in another component under test connected to the same pad as the target component under test to be turned off.

[0093] Optionally, the current-conducting element is a diode.

[0094] Optionally, the test signal is a dielectric breakdown test signal.

[0095] The electrical testing structure and method provided in this specific embodiment enable pad sharing among multiple components under test (DUTs) and multiple solder pads within the electrical testing structure. Each DUT is connected to two solder pads, and each solder pad can simultaneously connect to two DUTs, thereby effectively saving the number of solder pads required. Furthermore, the DUTs provided by this invention include a structure under test (SUT) and a protection structure. The protection structure controls the continuity between the solder pads and the SUT, preventing the test signal from flowing to a non-selected SUT when a test signal is applied to a shared solder pad. This improves the DUT's own anti-interference capability and reduces interference between SUTs.

[0096] The above description is merely a specific embodiment of the present invention. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. An electrical testing structure, characterized in that, include: Multiple components under test, each component under test including a structure under test and a protection structure electrically connected to the structure under test, wherein the structure under test and the protection structure are connected in series in the same component under test; Multiple solder pads are provided, each component under test is connected to two solder pads, and each solder pad can connect to two components under test simultaneously. The protection structure within each component under test is used to control whether there is conduction between the component under test and the solder pads. The protection structure includes a diode, the first end of the protection structure is the positive terminal of the diode, the second end of the protection structure is the negative terminal of the diode, and the protection structure is forward biased when current is input from the first end and reverse biased when current is input from the second end. In one component under test (DUT) connected to two pads, the input terminal of the structure under test (SUT) is connected to one pad, the first end of the protection structure is connected to the output terminal of the SUT, and the second end of the protection structure is connected to the other pad; or, in two DUTs connected to the same pad, the second end of the protection structure in one DUT is connected to the input terminal of the SUT in that DUT, and the first end of the protection structure in the other DUT is connected to the output terminal of the SUT in that DUT.

2. The electrical testing structure according to claim 1, characterized in that, Also includes: The test component includes a test structure, which is electrically connected to a plurality of the solder pads and is used to apply test signals to the solder pads.

3. The electrical testing structure according to claim 1, characterized in that, The structure under test is a dielectric breakdown voltage test structure, and the sum of the reverse-bias breakdown voltage of the protection structure in each component under test and the estimated breakdown voltage of the structure under test is greater than the maximum estimated breakdown voltage in each structure under test.

4. The electrical testing structure according to claim 1, characterized in that, The structure under test is a gate oxide capacitor structure, a metal-insulator-metal capacitor structure, or a metal-oxide-metal capacitor structure.

5. The electrical testing structure according to claim 1, characterized in that, The component under test also includes: A control circuit, connected to the control terminal of the protection structure, is used to control whether the input terminal and the output terminal of the protection structure are connected.

6. The electrical testing structure according to claim 1, characterized in that, Also includes: Substrate, the substrate including chip region and dicing region; The component under test and the solder pad are located in the chip area; or, The component under test and the solder pad are located in the cut track area.

7. An electrical testing method, characterized in that, Includes the following steps: The system is configured with multiple components under test (DUTs) and multiple solder pads connected to the DUTs respectively. Each DUT includes a structure under test (SUT) and a protection structure electrically connected to the SUT. Each DUT is connected to two solder pads, and each solder pad can connect to two DUTs simultaneously. In the same DUT, the SUT and the protection structure are connected in series. The protection structure includes a diode, with a first terminal of the protection structure being the anode of the diode and a second terminal of the protection structure being the cathode of the diode. The protection structure is forward biased when current is input from the first terminal and reverse biased when current is input from the second terminal. In one component under test (DUT) connected to two said pads, the input terminal of the structure under test (SUT) is connected to one of the said pads, the first end of the protection structure is connected to the output terminal of the SUT, and the second end of the protection structure is connected to the other said pad; or, in two DUTs connected to the same said pad, the second end of the protection structure in one DUT is connected to the input terminal of the SUT in that DUT, and the first end of the protection structure in the other DUT is connected to the output terminal of the SUT in that DUT. Connect multiple of the solder pads to a test component, and select a component under test as the target component under test; The test component applies a test signal to one of the pads connected to the target component under test, controls the protection structure in the target component under test to be turned on, and controls the protection structure in at least one other component under test connected to the same pad to be turned off.

8. The electrical testing method according to claim 7, characterized in that, The specific steps for configuring multiple components under test (UDTs) and multiple solder pads respectively connected to the multiple UDTs include: Multiple components under test and multiple solder pads are formed; The structure under test and the protection structure in each of the components under test are connected in series, and multiple components under test are connected to multiple solder pads respectively.

9. The electrical testing method according to claim 8, characterized in that, The plurality of components under test (DUTs) and the plurality of solder pads are arranged in a configuration order. In one DUT connected to two solder pads, the input terminal of the DUT is connected to one solder pad, the first end of the protection structure is connected to the output terminal of the DUT, and the second end of the protection structure is connected to the other solder pad. The electrical testing method further includes the following steps: The component under test is selected sequentially according to the configuration order as the target component under test, and when a test voltage is applied to a pad connected to the target component under test, the protection structure in the target component under test is controlled to be turned on, and the protection structure in the component under test located after the target component under test according to the configuration order is controlled to be turned off.

10. The electrical testing method according to claim 8, characterized in that, In two components under test connected to the same pad, the second end of the protective structure in one component under test is connected to the input end of the structure under test in that component under test, and the first end of the protective structure in the other component under test is connected to the output end of the structure under test in that component under test; The electrical testing method further includes: Arbitrarily select one of the components under test as the target component under test, and when a test voltage is applied to one of the pads connected to the target component under test, control the protection structure in the target component under test to be turned on, and control the protection structure in another component under test connected to the same pad as the target component under test to be turned off.

11. The electrical testing method according to claim 7, characterized in that, The test signal is a dielectric breakdown test signal.

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