A liquid crystal writing device and method with voltage switching control function

Abstract

This invention discloses a liquid crystal writing device and method with voltage switching control function, comprising: a processor and a switching switch connected to the processor, wherein the processor receives a communication signal and controls the switching switch to switch the voltage of the TFT and the conductive layer according to the communication signal, so as to realize erasure and / or discharge.

Description

Technical Field

[0001] This invention relates to the field of liquid crystal writing technology, and in particular to a liquid crystal writing device and method with voltage switching control function. Background Technology

[0002] The statements in this section are merely background information related to the present invention and do not necessarily constitute prior art.

[0003] Currently, liquid crystal writing devices include a conductive layer, a bistable liquid crystal layer, and a substrate layer arranged sequentially from top to bottom; several pixel units are arranged in an array on the substrate layer, and each pixel unit is provided with a pixel electrode and a thin film field-effect transistor (TFT) connected to the pixel electrode.

[0004] The voltage control process of the liquid crystal writing device during erasure includes applying a conduction voltage to the TFT gate, applying an input voltage to the TFT source, thereby inputting a set voltage to the corresponding pixel electrode, and then applying a voltage to the conductive layer to form a voltage difference between the conductive layer and the pixel electrode, thereby forming an erasure electric field at the position where the pixel electrode and the conductive layer overlap in space to achieve erasure.

[0005] Alternatively, when the liquid crystal writing device performs partial erasure by illumination, a set control voltage and input voltage are applied to the gate and source of the TFT respectively, so that the TFT is in a critical cutoff state. The light of a set intensity is applied to the erasure area, thereby applying voltage to the corresponding pixel electrode and applying voltage to the conductive layer, so as to form a voltage difference between the conductive layer and the pixel electrode to achieve partial erasure. When the erasure is completed, the applied voltage is removed to complete the discharge.

[0006] It can be seen that voltage selection is required for both the voltage control during erasure and / or the voltage control after erasure to ensure that the voltage of the pixel electrode and the voltage difference between the conductive layers meet the erasure conditions. However, current voltage control during erasure cannot achieve automatic voltage selection and switching. Summary of the Invention

[0007] To address the aforementioned problems, this invention proposes a liquid crystal writing device and method with voltage switching control function, enabling automatic selection and switching control of voltage during erasure.

[0008] To achieve the above objectives, the present invention adopts the following technical solution:

[0009] In a first aspect, the present invention provides a liquid crystal writing device with voltage switching control function, comprising: a processor and a switching switch connected to the processor, wherein the processor receives a communication signal and controls the switching switch to switch the voltage of the TFT and the conductive layer according to the communication signal, so as to realize erasure and / or discharge.

[0010] As an alternative implementation, the switching switch is a high-voltage switching switch.

[0011] As an alternative implementation, when the processor receives the communication signal of the erase command, in the one-key erase state, it applies a conduction voltage to the TFT gate by switching the voltage, and applies corresponding voltages to the TFT source and the conductive layer respectively, so as to form a voltage difference between the conductive layer and the pixel electrode.

[0012] As an alternative implementation, when the processor receives the communication signal for the erase command, in the state of partial erasure using light illumination, it applies a set voltage to all or a set portion of the TFTs by switching the voltage to put them in a critical cutoff state, and at the same time applies a voltage to the conductive layer to form a voltage difference between the conductive layer and the pixel electrode.

[0013] As an alternative implementation, when the processor receives a communication signal for a partial erase command, it controls the discharge of the area to which the voltage is applied by switching the voltage in the state after the optical erase is completed.

[0014] As an alternative implementation, the liquid crystal writing device further includes a wireless signal receiving unit that communicates with the erasing element, the wireless signal receiving unit being used to receive communication signals sent by the erasing element.

[0015] As an alternative implementation, electrode lines are led out from the substrate layer and the conductive layer respectively to connect a voltage drive circuit that provides the required voltage to the substrate layer and the conductive layer.

[0016] As an alternative implementation, the voltage drive circuit is designed based on bipolar transistors, MOSFETs, IGBTs, or integrated circuits.

[0017] As an alternative implementation, the liquid crystal writing device further includes a power supply and a voltage driving circuit connected to the processor; the driving circuit includes a source voltage driving circuit, a gate voltage driving circuit, and a conductive layer voltage driving circuit, each driving circuit including at least two access ports, wherein at least two access ports are connected to the power supply; the processor receives communication signals and controls the conduction of the corresponding communication ports connected to the voltage driving circuits according to the communication signals, so as to trigger the conduction of the corresponding access ports and enable each voltage driving circuit to output the required voltage.

[0018] In a second aspect, the present invention provides a method for operating the liquid crystal writing device with voltage switching control function as described in the first aspect, comprising: controlling a switching switch to switch the corresponding voltages of the TFT and the conductive layer through a received communication signal, so as to realize erasure and / or discharge.

[0019] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0020] This invention proposes a liquid crystal writing device and method with voltage switching control function. By communicating with the erasing element, the device receives communication signals sent by the erasing element and controls the switching switch to switch the corresponding voltages of the TFT and conductive layer according to the communication signals. This realizes the control of the applied voltage during erasure and / or the control of the discharge voltage after erasure, thereby realizing the automatic selection and switching control of the voltage during erasure.

[0021] Advantages of additional aspects of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0022] The accompanying drawings, which form part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an improper limitation of the invention.

[0023] Figure 1 This is a schematic diagram of a liquid crystal writing device with voltage switching control function provided in Embodiment 1 of the present invention;

[0024] Figure 2 This is a schematic diagram of the TFT wiring provided in Embodiment 1 of the present invention;

[0025] Figure 3 This is a schematic diagram of the power supply circuit provided in Embodiment 1 of the present invention;

[0026] Figure 4 This is a schematic diagram of the source voltage driving circuit provided in Embodiment 1 of the present invention;

[0027] Figure 5 This is a schematic diagram of the conductive layer voltage driving circuit provided in Embodiment 1 of the present invention;

[0028] Figure 6 This is a schematic diagram of the gate voltage driving circuit provided in Embodiment 1 of the present invention. Detailed Implementation

[0029] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0030] It should be noted that the following detailed descriptions are exemplary and intended to provide further illustration of the invention. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains.

[0031] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments of the present invention. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. Furthermore, it should be understood that the terms “comprising” and “having”, and any variations thereof, are intended to cover non-exclusive inclusion, for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0032] Where there is no conflict, the embodiments and features in the embodiments of the present invention can be combined with each other.

[0033] Example 1

[0034] like Figure 1 As shown, this embodiment provides a liquid crystal writing device with voltage switching control function. The liquid crystal writing device includes: a conductive layer, a bistable liquid crystal layer and a substrate layer arranged sequentially from top to bottom; wherein, the conductive layer may not be segmented, and a plurality of pixel units are arranged in an array on the substrate layer. Each pixel unit is provided with a pixel electrode and a TFT connected to the pixel electrode. The conduction of the TFT can provide voltage to the pixel electrode connected to it.

[0035] The liquid crystal writing device further includes a processor and a switching switch connected to the processor. The processor receives communication signals and controls the switching switch to switch the voltage of the TFT and the conductive layer according to the communication signals, so as to realize erasure and / or discharge.

[0036] As an alternative implementation, a conduction voltage V is applied to the TFT gate. GON An input voltage is applied to the TFT source electrode, thereby inputting a set voltage to the corresponding pixel electrode. Then, a voltage is applied to the conductive layer to form a voltage difference between the conductive layer and the pixel electrode. An erasing electric field is formed at the position where the pixel electrode and the conductive layer overlap in space, thereby achieving erasure.

[0037] The voltage control for this erasure process is specifically as follows:

[0038] (1) When the processor does not receive the communication signal of the erase instruction, i.e. the initial state, the voltage difference between each pixel unit of the conductive layer and the base layer is zero.

[0039] (2) When the processor receives the erase command, in the one-key erase state, the voltage switching is used to apply the turn-on voltage to the TFT gate and apply the corresponding voltage to the TFT source and the conductive layer respectively, so as to form a voltage difference between the conductive layer and the pixel electrode.

[0040] Specifically, during the first half-cycle of voltage application, a turn-on voltage V is applied to the TFT gate of the pixel cell on the substrate. GON A voltage of 0V is applied to the TFT source, and a voltage of V is applied to the conductive layer. SON This creates a voltage difference V between the conductive layer and the pixel electrode. SON .

[0041] During the latter half of the voltage application cycle, a turn-on voltage V is applied to the TFT gate in the pixel cell on the substrate. GON Apply voltage V to the TFT source SON Applying a voltage of 0V to the conductive layer creates a voltage difference V between the conductive layer and the pixel electrode. SON .

[0042] Therefore, when switching between the two erasure states, the voltage of the TFT source and the conductive layer needs to be selected. Thus, in this embodiment, a switching switch is used to switch the voltage of the TFT source and the conductive layer to meet the current erasure state.

[0043] The voltage switching control described above is applied in the one-key erase state. As another optional implementation method, it can also be applied to partial erasure. The voltage control during the erasure process is specifically as follows:

[0044] (1) When the processor does not receive the communication signal of the erase instruction, the voltage difference between each pixel unit of the conductive layer and the base layer is zero.

[0045] (2) When the processor receives the erase command, a conduction voltage V is applied to the TFT source of the local erase area by voltage switching. GON Appropriate voltages are applied to the TFT source electrode and the conductive layer respectively, so that a voltage difference is formed between the conductive layer and the pixel electrode in the locally erased area, while the voltage difference in the remaining areas remains zero. This voltage switching process is consistent with the above, applying voltages of 0V and V to the TFT source electrode. SON Switching between voltages 0V and V, the conductive layer is subjected to voltages 0V and V. SON Switch between modes to suit the current erasure state.

[0046] As an alternative implementation method, in the process of using light to achieve localized erasure:

[0047] After receiving the communication signal for the erase command, the processor controls the application of a set voltage to all or a selected portion of the TFTs to bring them to a critical cutoff state. Simultaneously, a voltage is applied to the conductive layer to create a voltage difference between the conductive layer and the pixel electrode. Specifically, a voltage of 0V is applied to the TFT gate, and a voltage of V is applied to the TFT source. MINDON Apply voltage V to the conductive layer SONThis creates a voltage difference |V between the conductive layer and the pixel electrode in the area illuminated by the set intensity of light. MINDON -V SON |

[0048] After receiving the communication signal for the discharge command, the processor controls the discharge to be performed using the applied voltage; specifically, a voltage V is applied to the TFT gate. GON Apply voltage V to the TFT source MINDON Alternatively, grounding can be used to apply a voltage V to the conductive layer. MINDON Alternatively, grounding can be used to eliminate the voltage difference between the conductive layer and the pixel electrode.

[0049] Therefore, when switching between the erasure and discharge states in photo-erasing, the voltages of the TFT gate, TFT source, and conductive layer need to be selected; as can be seen from the above process, the TFT gate voltage is 0V, voltage V GON Switching between grounding and voltage, the conductive layer operates at voltage V. MINDON Voltage V SON Switching between erasing and grounding. Therefore, this embodiment uses a switching switch to switch the voltage between the TFT gate and the conductive layer to meet the current erase state and discharge state.

[0050] As an optional implementation, the switching switch is a high-voltage switching switch; this embodiment provides possible models, such as MAX6922, PT6392, etc., but is not limited to these.

[0051] It is understandable that any other possible circuit structure can be used for the switching switch, as long as it can achieve voltage switching of the TFT gate, TFT source and conductive layer. Those skilled in the art can design or select the circuit according to the specific operating conditions, which will not be elaborated here.

[0052] As an optional implementation, the liquid crystal writing device further includes a wireless signal receiving unit that communicates with the erasing element, the wireless signal receiving unit being used to receive communication signals sent by the erasing element.

[0053] As an optional implementation, the erasing device is equipped with a wireless signal transmitting unit, which is activated by a button.

[0054] Alternatively, as another optional implementation, the erasing device is a light erasing device, and the wireless signal transmitting unit is activated after the light unit on the light erasing device meets the triggering conditions or the light unit is triggered to light up.

[0055] The wireless signal transmitting unit transmits a communication signal to the liquid crystal writing device. After receiving the communication signal, the wireless signal receiving unit on the liquid crystal writing device controls the switching switch to switch the corresponding voltage between the TFT and the conductive layer according to the communication signal. During photo erasure, it also receives a second wireless communication signal sent by the photo erasing device to control the removal of the applied voltage.

[0056] As an optional implementation method, such as Figure 2 The diagram shows the wiring schematic of the TFT. The first electrode represents the pixel electrode area where the TFT is connected on the substrate layer, and the second electrode represents the conductive layer. In this embodiment, electrode lines are led out from the substrate layer and the conductive layer respectively to connect a voltage driving circuit that can provide the voltage required by the substrate layer and the conductive layer.

[0057] As an optional implementation, the voltage driving circuit can adopt any other circuit structure that can realize voltage driving, as long as it can achieve the switching of various voltages between the substrate layer and the conductive layer. Those skilled in the art can design or select the circuit according to the specific operating conditions.

[0058] As an optional implementation, the voltage drive circuit can be designed using bipolar transistors, MOSFETs, IGBTs, integrated circuits, etc.; of course, those skilled in the art can also select other switching elements according to actual needs.

[0059] This embodiment uses a bipolar transistor as an example to illustrate the design of a voltage drive circuit, but it is only used as an example and is not intended to be specific.

[0060] Specifically, it includes: a power supply and a voltage driving circuit connected to the processor; the voltage driving circuit includes a source voltage driving circuit, a gate voltage driving circuit, and a conductive layer voltage driving circuit, each voltage driving circuit including at least two access ports, wherein at least two access ports are connected to the power supply; the processor receives communication signals and controls the conduction of the corresponding communication ports connected to the voltage driving circuits according to the communication signals, so as to trigger the conduction of the corresponding access ports and enable each voltage driving circuit to output the required voltage.

[0061] In this embodiment, as Figure 3 As shown, the power supply includes at least one power input port and three power output ports; wherein, the power input port is connected to a communication port of the processor, and the three power output ports are respectively used to connect to the source voltage drive circuit. SON V, used to connect the gate voltage drive circuit GON and medium pressure V MIDON The required voltage can be output from the three power output ports by modulating the voltage using PWM modulation.

[0062] In this embodiment, as Figure 4 As shown, the source voltage driving circuit includes a first access port, a second access port, and a ground port; wherein, the first access port is connected to port V. SON Connection, second access port and V MIDON Connect the grounding port to the ground.

[0063] The source voltage driving circuit includes three communication ports connected to the processor, which are used to trigger the conduction of the three access ports respectively; wherein, communication port P1 is used to trigger the conduction of the first access port, communication port P2 is used to trigger the conduction of the second access port, and communication port P3 is used to trigger the conduction of the ground port; so as to realize the switching of the connection of each access port in the source voltage driving circuit.

[0064] The output terminal of the source voltage driving circuit is connected to the TFT source. By switching the connection of the access port, the voltage input to the TFT source can be adjusted.

[0065] In this embodiment, the source voltage driving circuit includes a first source circuit, a second source circuit, and a third source circuit, all of which are connected to the processor. The first source circuit is used to provide a first voltage to the TFT source, the second source circuit is used to provide a second voltage to the TFT source, and the third source circuit is used to ground the TFT source. In this embodiment, the first voltage is greater than the second voltage.

[0066] In this embodiment, the first source pole circuit includes at least a first communication port P1 and a first access port; the first access port and the power output port V SON The first communication port P1 is connected to the processor.

[0067] The first source circuit includes at least a first transistor Q3A and a second transistor Q1A. The processor's communication port P1 is connected to the base of the first transistor Q3A through at least one first resistor. The base of the first transistor Q3A is grounded through at least one second resistor. The emitter of the first transistor Q3A is grounded.

[0068] The collector of the first transistor Q3A is connected to the base of the second transistor Q1A through at least one third resistor R3. The base of the second transistor Q1A is connected to the emitter of the second transistor Q1A through at least one fourth resistor R1. The emitter of the second transistor Q1A is connected to the power output port V. SON The collector of the second transistor Q1A is connected to the source of the TFT through at least one fifth resistor R6.

[0069] In this embodiment, the second source pole circuit includes at least a second communication port P2 and a second access port, the second access port being connected to the power output port V. MIDONThe second communication port P2 is connected to the processor.

[0070] The second source circuit includes at least a third transistor Q3B and a fourth transistor Q1B. The processor's communication port P2 is connected to the base of the third transistor Q3B through at least one sixth resistor. The base of the third transistor Q3B is grounded through at least one seventh resistor, and the emitter of the third transistor Q3B is grounded.

[0071] The collector of the third transistor Q3B is connected to the base of the fourth transistor Q1B through at least one eighth resistor R16. The base of the fourth transistor Q1B is connected to the emitter of the fourth transistor Q1B through at least one ninth resistor R11. The emitter of the fourth transistor Q1B is connected to the power output port V. MIDON The collector of the fourth transistor Q1B is connected to the input terminal of the first diode, and the output terminal of the first diode is connected to the source of the TFT.

[0072] In this embodiment, the third source electrode circuit includes at least a third communication port P3 and a ground port. The third communication port P3 is connected to the processor, and the ground port is used to ground the TFT source electrode.

[0073] The third source circuit includes at least a sixth transistor Q7. The processor's communication port P3 is connected to the base of the sixth transistor Q7 through at least one tenth resistor R21. The collector of the sixth transistor Q7 is used to connect to the TFT source, and the emitter of the sixth transistor Q7 is grounded.

[0074] In this embodiment, the processor controls the conduction of communication ports P1-P3 according to the received first communication signal, so as to drive the conduction of the corresponding access ports and realize the switching of the first voltage, the second voltage and ground.

[0075] In this embodiment, as Figure 5 As shown, the conductive layer voltage driving circuit includes a first conductive layer sub-circuit, a second conductive layer sub-circuit, and a third conductive layer sub-circuit, all of which are connected to the processor. The first conductive layer sub-circuit is used to provide a first voltage to the conductive layer, the second conductive layer sub-circuit is used to provide a second voltage to the conductive layer, and the third conductive layer sub-circuit is used to ground the conductive layer. In this embodiment, the first voltage is greater than the second voltage.

[0076] The first conductive layer sub-circuit includes at least a fourth communication port P4 and a fourth access port; the fourth access port is connected to the power output port V. SON The fourth communication port P4 is connected to the processor; the output of the first conductive layer sub-circuit is connected to the conductive layer. The other circuit structures are the same as the first source circuit, and will not be described again here.

[0077] The second conductive layer sub-circuit includes at least a fifth communication port P5 and a fifth access port, the fifth access port being connected to the power output port V. MIDON The fifth communication port P5 is connected to the processor, and the output is connected to the conductive layer. The rest of the circuit structure is the same as the second source circuit, and will not be described again here.

[0078] The third conductive layer sub-circuit includes at least a sixth communication port P6 and a ground port. The sixth communication port P6 is connected to the processor, and the ground port is used to ground the conductive layer. The other circuit structures are the same as the third source circuit and will not be described again here.

[0079] In this embodiment, the processor controls the conduction of communication ports P4-P6 according to the received first communication signal, so as to drive the conduction of the corresponding access ports and realize the switching of the first voltage, the second voltage and ground.

[0080] In this embodiment, as Figure 6 As shown, the gate voltage driving circuit includes a first gate sub-circuit, a second gate sub-circuit, and a third gate sub-circuit, all of which are connected to the processor. The first gate sub-circuit is used to provide a first voltage to the TFT gate, the second gate sub-circuit is used to provide a second voltage to the TFT gate, and the third gate sub-circuit is used to ground the TFT gate. In this embodiment, the first voltage is greater than the second voltage.

[0081] The first gate sub-circuit includes at least a seventh communication port P7 and a seventh access port; the seventh access port is connected to the power output port V. GON The seventh communication port P7 is connected to the processor, and the output is connected to the TFT gate. The rest of the circuit structure is the same as the first source circuit, and will not be described again here.

[0082] The second gate sub-circuit includes at least an eighth communication port P8 and an eighth access port, the eighth access port being connected to the power output port V. MIDON The eighth communication port P8 is connected to the processor, and the output is connected to the TFT gate. The rest of the circuit structure is the same as the second source circuit, and will not be described again here.

[0083] The third gate sub-circuit includes at least a ninth communication port P9 and a ground port. The ninth communication port P9 is connected to the processor, and the ground port is used to ground the TFT gate. The other circuit structures are the same as those of the third source sub-circuit and will not be described again here.

[0084] In this embodiment, the processor controls the conduction of communication ports P7-P9 according to the received first communication signal, so as to drive the conduction of the corresponding access ports and realize the switching of the first voltage, the second voltage and ground.

[0085] It is understood that the voltage driving circuit described above can also adopt any other circuit structure that can realize voltage driving, as long as it can realize the switching of various voltages between the base layer and the conductive layer and the switching of various ports. Those skilled in the art can design or select the circuit according to the specific operating conditions.

[0086] In this embodiment, the voltage driving circuit can be connected to the TFT source, TFT gate and conductive layer respectively through connectors; the processor controls the switching switch to switch the corresponding voltage of the TFT and conductive layer according to the received communication signal, so as to control the voltage of the TFT source, gate and conductive layer respectively, and realize erasure and / or discharge.

[0087] For example, during one-click erasure, a 20V turn-on voltage is provided through the gate voltage driving circuit, while a 0V input voltage is provided through the source voltage driving circuit. At this time, the voltage applied to each pixel electrode is 0V. A 25V voltage is applied to the conductive layer through the conductive layer voltage driving circuit. Then, the voltage difference between the conductive layer and the substrate layer is 25V, which achieves the erasure electric field and realizes erasure.

[0088] During optical erasure, a 0V voltage is provided by the gate voltage driving circuit, a 10V voltage is provided by the source voltage driving circuit, and a 35V voltage is applied to the conductive layer by the conductive layer voltage driving circuit. When the TFT in the area illuminated by the set intensity of light is turned on, the voltage on the pixel electrode corresponding to the erasure area is 10V. Then, the voltage difference between the conductive layer and the substrate layer is 25V, which achieves the erasure electric field and realizes the erasure.

[0089] After erasing is complete, discharge is performed by providing a 30V voltage through the gate voltage drive circuit, a 0V input voltage through the source voltage drive circuit, and applying a 0V voltage to the conductive layer through the conductive layer voltage drive circuit to complete the discharge.

[0090] Of course, the voltage values ​​mentioned above are merely examples, and those skilled in the art can reasonably select the applied voltage values ​​according to actual needs and the characteristics of the liquid crystal.

[0091] Understandably, a positioning circuit can also be integrated on the base layer to position the erasing element and control the switching of the voltage at the pixel unit at the corresponding erasing position, so as to realize the position positioning or other positioning functions during local erasure.

[0092] Understandably, the positioning circuit can be implemented using electromagnetic positioning, capacitive positioning, infrared positioning, ultrasonic positioning, or image positioning. These positioning methods are all publicly available in the prior art, and the specific implementation process will not be described in detail.

[0093] Example 2

[0094] This embodiment provides a method for operating the erasure circuit of the liquid crystal writing device described in Embodiment 1, including: controlling a switching switch to switch the corresponding voltages of the TFT and the conductive layer through a received communication signal, so as to realize erasure and / or discharge.

[0095] While the specific embodiments of the present invention have been described above in conjunction with the accompanying drawings, this is not intended to limit the scope of protection of the present invention. Those skilled in the art should understand that various modifications or variations that can be made by those skilled in the art without creative effort based on the technical solutions of the present invention are still within the scope of protection of the present invention.

Claims

1. A liquid crystal writing device with voltage switching control function, characterized in that, The liquid crystal writing device comprises: a processor and a switch connected to the processor, the processor receiving a communication signal for controlling the switch to switch the TFT and the conductive layer to a corresponding voltage to achieve erasing and / or discharging according to the communication signal; in the process of local erasing by using light: when the processor does not receive the communication signal of the erasing instruction, the voltage difference between each pixel unit of the conductive layer and the substrate layer is zero; After receiving the communication signal for the erase command, the processor controls the application of a set voltage to all or a selected portion of the TFTs to bring them to a critical cutoff state. Simultaneously, a voltage is applied to the conductive layer to create a voltage difference between the conductive layer and the pixel electrode. Specifically, a voltage of 0V is applied to the TFT gate, and a voltage of V is applied to the TFT source. MINDON Apply voltage V to the conductive layer SON This creates a voltage difference |V| between the conductive layer and the pixel electrode in the area illuminated by the set intensity of light. MINDON -V SON |; After the processor receives the communication signal of the discharge instruction, the voltage applied is discharged; specifically, the voltage V GON is applied to the TFT gate MINDON or ground, the voltage V MINDON or ground is applied to the conductive layer, so that there is no voltage difference between the conductive layer and the pixel electrode.

2. The liquid crystal writing device having a voltage switching control function according to claim 1, characterized in that, the liquid crystal writing device further comprises a wireless signal receiving unit in communication with the eraser, the wireless signal receiving unit being used to receive the communication signal sent by the eraser.

3. The liquid crystal writing device having a voltage switching control function according to claim 1, wherein By leading out electrode lines on the substrate layer and the conductive layer, the voltage driving circuit providing the required voltage for the substrate layer and the conductive layer is connected.

4. The liquid crystal writing device having a voltage switching control function according to claim 3, wherein The voltage driving circuit is designed based on bipolar transistor, MOS tube, IGBT or integrated circuit.

5. The liquid crystal writing device having a voltage switching control function according to claim 3, wherein The liquid crystal writing device further comprises a power supply and a voltage driving circuit connected to the processor; the driving circuit comprises a source voltage driving circuit, a gate voltage driving circuit and a conductive layer voltage driving circuit, each driving circuit comprising at least two access ports, and at least two access ports being connected to the power supply; the processor receives a communication signal and controls the conduction of the corresponding communication port connected to the voltage driving circuit according to the communication signal to trigger the conduction of the corresponding access port, so that each voltage driving circuit outputs the required voltage.

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