A neural network processor fault unit repair system and method

Abstract

The present invention discloses a system and method for repairing a faulty unit in a neural network processor. A system for repairing a faulty unit in a neural network processor includes: a redundant computing array for performing a first computing and generating a first computing result; a fault detection module for checking whether a second computing result is erroneous based on the first computing result; and if so, obtaining a first position based on the second computing result; an address control module for generating an address and a control signal based on the first position; and a control module for caching the first computing result based on the address and the control signal, and setting a second unit to perform the first computing instead of the first unit. The present invention realizes the timely location and repair of faulty units in the computing array of a neural network processor, improves the reliability of the neural network processor, and can be widely used in the field of chip technology.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to a system and method for repairing a faulty unit in a neural network processor. Background Art

[0002] Neural-network Processing Units (NPUs) typically consist of a large, conventional 2D computing array and a set of on-chip buffers for input features, output features, and weights. The reliability of the 2D computing array affects the reliability of the entire accelerator. Since each processing element (PE) in the computing array can be used to calculate multiple feature values in different network layers, a fault in a single PE may lead to multiple erroneous computational results during the execution of a deep learning model. In order to reduce hardware failures in the 2D computing array of a neural network processor, researchers have proposed fault-tolerant design methods from two main aspects. The first type of fault-tolerant design method mainly performs inherent fault-tolerant processing on the neural network model by training a neural network model for the faulty computing array, without modifying the hardware circuit of the existing neural network processor. However, the neural network model trained for a specific faulty computing array has limitations, and the model needs to be retrained when facing different faults; the core of the second type of fault-tolerant design method is to use redundant PEs to recover the faulty PE. Traditional redundancy design methods such as Dual Modular Redundancy (DMR) and Triple Modular Redundancy (TMR) offer high reliability but require significant hardware resources, increasing costs. Researchers have also proposed row, column, and diagonal redundancy methods, which significantly reduce hardware resource consumption compared to DMR and TMR. These methods can effectively mitigate failures in 2D computing arrays when the number of faulty PEs is small and evenly distributed. However, when faulty PEs are unevenly distributed in the computing array or when the number of faulty PEs exceeds the number of redundant PEs in the corresponding row or column, the faulty PEs cannot be fully repaired. Summary of the Invention

[0003] The purpose of the present invention is to solve one of the technical problems existing in the prior art to at least a certain extent.

[0004] To this end, an object of an embodiment of the present invention is to provide a neural network processor fault unit repair system and method, so as to achieve timely positioning and repair of faulty units in the neural network processor computing array and improve the reliability of the neural network processor.

[0005] In order to achieve the above technical objectives, the technical solutions adopted by the embodiments of the present invention include:

[0006] In a first aspect, an embodiment of the present invention provides a neural network processor fault unit repair system, comprising:

[0007] a redundant computing array, configured to perform a first computing operation to generate a first computing result, wherein the first computing operation is an intermediate computing operation performed by the neural network processor;

[0008] a fault detection module, configured to check whether a second calculation result is erroneous based on the first calculation result, where the second calculation result is a result obtained by a calculation array of a neural network processor performing the first calculation; and, if so, to obtain a first position based on the second calculation result, where the first position is a position of a first unit, where the first unit is a processing element unit in the calculation array performing the first calculation;

[0009] an address control module, configured to generate an address and a control signal according to the first position;

[0010] A control module is used to cache the first calculation result according to the address and control signal, and set a second unit to replace the first unit to perform the first calculation, where the second unit is a processing element unit in the redundant calculation array that performs the first calculation.

[0011] In addition, the neural network processor fault unit repair system according to the above embodiment of the present invention may also have the following additional technical features:

[0012] Furthermore, in a neural network processor fault unit repair system according to an embodiment of the present invention, the redundant computing array and the computing array operate in a dual-core lock-step state.

[0013] Furthermore, in one embodiment of the present invention, the neural network processor fault unit repair system also includes a fault list, and the fault list is used to record the first position.

[0014] Furthermore, in one embodiment of the present invention, the fault detection module compares the first calculation result with the second calculation result to check whether the second calculation result is wrong;

[0015] When the first calculation result and the second calculation result are different, determining that the second calculation result is wrong;

[0016] When the first calculation result and the second calculation result are the same, it is determined that the second calculation result is correct.

[0017] Furthermore, in one embodiment of the present invention, when the second calculation result is not erroneous, the control module caches the second calculation result.

[0018] Furthermore, in one embodiment of the present invention, the neural network processor fault unit repair system also includes an output buffer area, and the output buffer area is used to cache the first calculation result and the second calculation result.

[0019] In a second aspect, an embodiment of the present invention provides a method for repairing a faulty unit in a neural network processor. The method is applied to a system for repairing a faulty unit in a neural network processor. The system includes a redundant computing array, a fault detection module, an address control module, and a control module. The method includes:

[0020] Performing a first calculation by the redundant calculation array to generate a first calculation result, wherein the first calculation is an intermediate calculation when the neural network processor performs the calculation;

[0021] Based on the first calculation result, checking whether a second calculation result is wrong by the fault detection module, the second calculation result being a result obtained by a calculation array of a neural network processor performing the first calculation;

[0022] If yes, obtaining a first position through the fault detection module according to the second calculation result, where the first position is a position of a first unit, and the first unit is a processing element unit in the calculation array that performs the first calculation;

[0023] generating an address and a control signal by the address control module according to the first position;

[0024] According to the address and control signal, the first calculation result is cached by the control module, and a second unit is set to replace the first unit to perform the first calculation, and the second unit is a processing element unit in the redundant computing array that performs the first calculation.

[0025] Furthermore, in one embodiment of the present invention, the neural network processor fault unit repair system further includes a fault list;

[0026] The method for repairing a faulty unit in a neural network processor further includes:

[0027] Recording the first position through the fault list;

[0028] The first position is obtained from the fault list by the address control module.

[0029] Furthermore, in one embodiment of the present invention, checking whether the second calculation result is erroneous by the fault detection module according to the first calculation result includes:

[0030] comparing the first calculation result and the second calculation result;

[0031] When the first calculation result and the second calculation result are different, determining that the second calculation result is wrong;

[0032] When the first calculation result and the second calculation result are the same, it is determined that the second calculation result is correct.

[0033] Furthermore, in one embodiment of the present invention, after the step of checking whether the second calculation result is erroneous by the fault detection module according to the first calculation result, the method further includes:

[0034] If not, the second calculation result is cached by the control module.

[0035] The advantages and benefits of the present invention will be described in part in the following description and will become apparent from the following description or learned through practice of the present application:

[0036] The embodiment of the present invention provides a redundant computing array, performs calculations synchronously with the neural network processor computing array, and compares the calculation results after each intermediate calculation, thereby performing error detection on the intermediate calculation results of the computing array, thereby achieving timely and efficient computing array error detection; by obtaining the position of the faulty unit after an error occurs in the intermediate calculation result of the computing array, and generating an address and control signal according to the position of the faulty unit, the calculation result of the redundant computing array is used to replace the erroneous result, and the corresponding unit in the redundant computing array replaces the faulty unit to perform the corresponding calculation, thereby achieving timely, efficient and accurate computing array repair and improving the reliability of the neural network processor. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following introduction is made to the drawings of the embodiments of the present application or the related technical solutions in the prior art. It should be understood that the drawings introduced below are only for the convenience of clearly describing some embodiments of the technical solutions of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without any creative work.

[0038] Figure 1 This is a structural diagram of a specific embodiment of a neural network processor fault unit repair system of the present invention;

[0039] Figure 2 The figure is a flowchart of a specific embodiment of a method for repairing a faulty unit in a neural network processor according to the present invention. DETAILED DESCRIPTION

[0040] The embodiments of the present invention are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application and are not to be construed as limiting the present application. The step numbers in the following embodiments are provided only for the convenience of explanation and do not limit the order of the steps. The order of execution of the steps in the embodiments can be adaptively adjusted according to the understanding of those skilled in the art.

[0041] The terms "first," "second," "third," and "fourth," etc., in the specification, claims, and accompanying drawings of the present invention are used to distinguish between different items, not to describe a specific order. Furthermore, the terms "including," "having," and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or elements is not limited to the listed steps or elements, but may optionally include steps or elements not listed, or may optionally include other steps or elements inherent to the process, method, product, or apparatus.

[0042] References to "embodiments" in this disclosure mean that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the disclosure. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0043] Neural network processors typically consist of a large, conventional 2D compute array and a set of on-chip buffers for input features, output features, and weights. The reliability of the 2D compute array impacts the reliability of the entire accelerator. Because each PE in the compute array can compute multiple feature values across different network layers, a failure in a single PE can lead to multiple erroneous computational results during the execution of a deep learning model. To mitigate hardware failures in the 2D compute array of a neural network processor, researchers have proposed fault-tolerant design approaches from two perspectives. The first type of fault-tolerant design approach primarily trains a neural network model tailored to the faulty compute array, making the neural network model inherently fault-tolerant without requiring modifications to the existing neural network processor hardware circuitry. However, trained neural network models tailored to a specific faulty compute array have limitations, requiring retraining in the face of different faults. The second type of fault-tolerant design approach focuses on utilizing redundant PEs to recover from faulty PEs. Traditional redundancy design approaches, such as dual-mode redundancy and triple-mode redundancy, offer high reliability but require significant hardware resources, increasing costs. In addition, researchers have proposed row, column, and diagonal redundancy methods, which significantly reduce hardware resource consumption compared to dual-module redundancy and triple-module redundancy. This method effectively mitigates failures in 2D computing arrays when the number of faulty PEs is small and evenly distributed. However, when the faulty PEs are unevenly distributed in the computing array or when the number of faulty PEs exceeds the number of redundant PEs in the corresponding row or column, the faulty PEs cannot be fully repaired.

[0044] To this end, the present invention proposes a neural network processor fault unit repair system and method, which provides a redundant computing array (RCA) to perform synchronous calculations with the neural network processor computing array and compare the calculation results after each intermediate calculation, thereby performing error detection on the intermediate calculation results of the computing array, thereby achieving timely and efficient computing array error detection; by obtaining the position of the faulty unit after an error in the intermediate calculation result of the computing array, and generating an address and control signal according to the position of the faulty unit, so as to replace the erroneous result with the calculation result of the redundant computing array, and making the corresponding unit in the redundant computing array replace the faulty unit to perform the corresponding calculation, thereby achieving timely, efficient and accurate computing array repair, thereby improving the reliability of the neural network processor.

[0045] The following describes in detail a neural network processor fault unit repair system and method proposed in an embodiment of the present invention with reference to the accompanying drawings. First, a neural network processor fault unit repair system proposed in an embodiment of the present invention will be described with reference to the accompanying drawings.

[0046] Reference Figure 1 , an emission control system in an embodiment of the present invention includes:

[0047] a redundant computing array, configured to perform a first computing operation to generate a first computing result, wherein the first computing operation is an intermediate computing operation performed by the neural network processor;

[0048] a fault detection module, configured to check whether a second calculation result is erroneous based on the first calculation result, where the second calculation result is a result obtained by a calculation array of a neural network processor performing the first calculation; and, if so, to obtain a first position based on the second calculation result, where the first position is a position of a first unit, where the first unit is a processing element unit in the calculation array performing the first calculation;

[0049] an address control module, configured to generate an address and a control signal according to the first position;

[0050] A control module is used to cache the first calculation result according to the address and control signal, and set a second unit to replace the first unit to perform the first calculation, where the second unit is a processing element unit in the redundant calculation array that performs the first calculation.

[0051] In an embodiment of the present invention, the redundant computing array and the computing array operate in a dual-core lock-step state.

[0052] In one embodiment of the present invention, fault detection and repair of faulty units in a neural network processor are performed through a combination of software and hardware. Checkpoints are set at the software level and are located after each intermediate computation (the first computation) of the neural network processor. Specifically, after the neural network processor's computation array and redundant computation array perform the first computation, the fault detection module performs error detection on the second computation result at the checkpoint.

[0053] Specifically, in one embodiment of the present invention, when the second calculation result is erroneous, the computation state of the neural network processor rolls back to the previous checkpoint and re-performs the current round of computation. After re-performing the first calculation, the control module caches the first calculation result based on the address and control signal.

[0054] As an optional implementation, the neural network processor fault unit repair system further includes a fault table (FPT), which is used to record the first position.

[0055] Specifically, after the first position is recorded in the fault list, the address control module obtains the first position from the fault list.

[0056] As an optional implementation, the fault detection module compares the first calculation result with the second calculation result to check whether the second calculation result is wrong.

[0057] When the first calculation result and the second calculation result are different, determining that the second calculation result is wrong;

[0058] When the first calculation result and the second calculation result are the same, it is determined that the second calculation result is correct.

[0059] As an optional implementation, when the second calculation result is not wrong, the control module caches the second calculation result.

[0060] Specifically, if the second calculation result is correct (ie, the first calculation result is the same as the second calculation result), the second calculation result is cached by the control module.

[0061] As an optional implementation, the neural network processor fault unit repair system further includes an output buffer area, and the output buffer area is used to cache the first calculation result and the second calculation result.

[0062] Specifically, the correct intermediate calculation results of the calculation array of the neural network processor are cached in the output cache area through the control module, and when the intermediate calculation results of the calculation array are erroneous, the intermediate calculation results of the redundant calculation array are used to replace them and cached in the output cache area, and the final calculation results are output from the output cache area after the neural network processor completes the entire calculation.

[0063] It can be understood that the embodiments of the present invention perform timely error detection and correction on intermediate calculation results without considering the final calculation results, so that the accuracy of the neural network processor in each intermediate calculation is not affected by previous erroneous calculation results and faulty units, and can achieve more efficient, more timely and more accurate repair of neural network processor faulty units.

[0064] In summary, the present invention sets a redundant computing array, performs calculations synchronously with the neural network processor computing array, and compares the calculation results after each intermediate calculation, thereby performing error detection on the intermediate calculation results of the computing array, thereby realizing timely and efficient computing array error detection; by obtaining the position of the faulty unit after an error occurs in the intermediate calculation result of the computing array, and generating an address and a control signal according to the position of the faulty unit, so as to replace the erroneous result with the calculation result of the redundant computing array, and making the corresponding unit in the redundant computing array replace the faulty unit to perform the corresponding calculation, thereby realizing timely, efficient and accurate computing array repair and improving the reliability of the neural network processor.

[0065] Secondly, refer to Figure 2An embodiment of the present invention provides a method for repairing a faulty unit in a neural network processor. The method is applied to a system for repairing a faulty unit in a neural network processor. The system includes a redundant computing array, a fault detection module, an address control module, and a control module. The method includes:

[0066] S101, performing a first calculation by the redundant computing array to generate a first calculation result;

[0067] The first calculation is an intermediate calculation when the neural network processor performs calculations.

[0068] S102: Based on the first calculation result, check whether the second calculation result is wrong by the fault detection module;

[0069] The second calculation result is the result obtained by the computing array of the neural network processor performing the first calculation.

[0070] Specifically, in one embodiment of the present invention, error detection and repair of faulty units in a neural network processor are performed through a combination of software and hardware. A checkpoint is set at the software level, and the checkpoint is located after each intermediate calculation (the first calculation) of the neural network processor. Specifically, after the calculation array and redundant calculation array of the neural network processor perform the first calculation, the fault detection module performs error detection on the second calculation result at the checkpoint, specifically including:

[0071] (1) comparing the first calculation result and the second calculation result;

[0072] (2) when the first calculation result and the second calculation result are different, determining that the second calculation result is wrong;

[0073] (3) When the first calculation result and the second calculation result are the same, it is determined that the second calculation result is not wrong.

[0074] S103: If yes, obtain the first position through the fault detection module according to the second calculation result;

[0075] The first position is the position of a first unit, and the first unit is a processing element unit in the computing array that performs the first calculation.

[0076] Specifically, in an embodiment of the present invention, when the first calculation result and the second calculation result are the same, that is, when the second calculation result is not wrong, the second calculation result is cached by the control module.

[0077] In an embodiment of the present invention, the neural network processor fault unit repair system further includes a fault list. In this embodiment of the present invention, the first position is recorded in the fault list.

[0078] S104. Generate an address and a control signal through the address control module according to the first position;

[0079] According to step S103 , the first position is obtained from the fault list by the address control module.

[0080] S105 : Cache the first calculation result through the control module according to the address and the control signal, and set a second unit to perform the first calculation instead of the first unit.

[0081] The second unit is a processing element unit in the redundant computing array that performs the first calculation.

[0082] Specifically, according to step S102, in one embodiment of the present invention, when the second calculation result is erroneous, the calculation state of the neural network processor is rolled back to the previous checkpoint and the current round of calculation is repeated. After the first calculation is repeated, the control module caches the first calculation result according to the address and control signal, and configures the second unit to perform the first calculation instead of the first unit.

[0083] It can be understood that the embodiments of the present invention perform timely error detection and correction on intermediate calculation results without considering the final calculation results, so that the accuracy of the neural network processor in each intermediate calculation is not affected by previous erroneous calculation results and faulty units, and can achieve more efficient, more timely and more accurate repair of neural network processor faulty units.

[0084] The contents of the above method embodiments are all applicable to the present system embodiments. The functions specifically implemented by the present system embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0085] In some optional embodiments, the function / operation mentioned in the block diagram may not occur in the order mentioned in the operation diagram. For example, depending on the function / operation involved, the two boxes shown in succession can actually be executed substantially simultaneously or the boxes can sometimes be executed in reverse order. In addition, the embodiments presented and described in the flow chart of the present application are provided in an exemplary manner for the purpose of providing a more comprehensive understanding of the technology. The disclosed method is not limited to the operations and logical flows presented herein. Optional embodiments are contemplated in which the order of the various operations is changed and the sub-operations described as a part of a larger operation are performed independently.

[0086] In addition, although the present application is described in the context of functional modules, it should be understood that, unless otherwise stated, one or more of the functions and / or features may be integrated into a single physical device and / or software module, or one or more functions and / or features may be implemented in separate physical devices or software modules. It is also understood that a detailed discussion of the actual implementation of each module is not necessary for understanding the present application. More specifically, given the properties, functions, and internal relationships of the various functional modules in the devices disclosed herein, the actual implementation of the module will be understood within the routine skills of an engineer. Therefore, a person skilled in the art can implement the present application as set forth in the claims using ordinary techniques without undue experimentation. It is also understood that the specific concepts disclosed are merely illustrative and are not intended to limit the scope of the present application, which is determined by the full scope of the appended claims and their equivalents.

[0087] It should be understood that various parts of the present application can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in a memory and executed by a suitable program execution system. For example, if implemented using hardware, as in another embodiment, any one of the following technologies known in the art or a combination thereof can be used to implement: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application-specific integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0088] In the above description of this specification, reference to the terms "one embodiment / example," "another embodiment / example," or "certain embodiments / examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples.

[0089] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions, and variations may be made to the embodiments without departing from the principles and intent of the present application, and that the scope of the present application is defined by the claims and their equivalents.

[0090] The above is a specific description of the preferred implementation of the present application, but the present application is not limited to the embodiments. Those skilled in the art may make various equivalent modifications or substitutions without violating the spirit of the present application. These equivalent modifications or substitutions are all included in the scope defined by the claims of the present application.

Claims

1. A neural network processor fault unit repair system, characterized in that: include: a redundant computing array, configured to perform a first computing operation to generate a first computing result, wherein the first computing operation is an intermediate computing operation performed by the neural network processor; a fault detection module, configured to check whether a second calculation result is erroneous based on the first calculation result, the second calculation result being a result obtained by a calculation array of a neural network processor performing the first calculation; for obtaining a first position according to the second calculation result, where the first position is a position of a first unit, and the first unit is a processing element unit in the calculation array that performs the first calculation; an address control module, configured to generate an address and a control signal according to the first position; A control module is configured to cache the first calculation result according to the address and the control signal, replace the second calculation result with the first calculation result, and set a second unit to replace the first unit to perform the first calculation, where the second unit is a processing element unit in the redundant computing array that performs the first calculation.

2. A neural network processor fault unit repair system according to claim 1, characterized in that: The redundant computing array and the computing array operate in a dual-core lock-step state.

3. A neural network processor fault unit repair system according to claim 1, characterized in that: Also included is a fault list, which is used to record the first position.

4. A neural network processor fault unit repair system according to claim 1, characterized in that: The fault detection module compares the first calculation result with the second calculation result to check whether the second calculation result is wrong; When the first calculation result and the second calculation result are different, determining that the second calculation result is wrong; When the first calculation result and the second calculation result are the same, it is determined that the second calculation result is correct.

5. A neural network processor fault unit repair system according to claim 4, characterized in that: When the second calculation result is not wrong, the control module caches the second calculation result.

6. A neural network processor fault unit repair system according to claim 5, characterized in that: It also includes an output buffer area, which is used to cache the first calculation result and the second calculation result.

7. A method for repairing a faulty unit of a neural network processor, characterized in that: The method is applied to a neural network processor fault unit repair system, which includes a redundant computing array, a fault detection module, an address control module, and a control module. The method includes: Performing a first calculation by the redundant calculation array to generate a first calculation result, wherein the first calculation is an intermediate calculation when the neural network processor performs the calculation; Based on the first calculation result, checking whether a second calculation result is wrong by the fault detection module, the second calculation result being a result obtained by a calculation array of a neural network processor performing the first calculation; If yes, obtaining a first position through the fault detection module according to the second calculation result, where the first position is a position of a first unit, and the first unit is a processing element unit in the calculation array that performs the first calculation; generating an address and a control signal by the address control module according to the first position; According to the address and control signal, the first calculation result is cached by the control module, the first calculation result is used to replace the second calculation result, and a second unit is set to replace the first unit to perform the first calculation, and the second unit is a processing element unit in the redundant computing array that performs the first calculation.

8. A method for repairing a faulty unit in a neural network processor according to claim 7, characterized in that: The neural network processor fault unit repair system also includes a fault list; The method for repairing a faulty unit in a neural network processor further includes: Recording the first position through the fault list; The first position is obtained from the fault list by the address control module.

9. A method for repairing a faulty unit in a neural network processor according to claim 7, characterized in that: The step of checking, by the fault detection module, whether the second calculation result is wrong according to the first calculation result includes: comparing the first calculation result and the second calculation result; When the first calculation result and the second calculation result are different, determining that the second calculation result is wrong; When the first calculation result and the second calculation result are the same, it is determined that the second calculation result is correct.

10. A method for repairing a faulty unit of a neural network processor according to claim 7, characterized in that: After the step of checking whether the second calculation result is wrong by the fault detection module according to the first calculation result, the method further includes: If not, the second calculation result is cached by the control module.

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