Method and device for determining electrostatic discharge failure voltage model of capacitor

Abstract

The embodiment of the present disclosure provides a method and device for determining the electrostatic discharge failure voltage model of a capacitor. The method includes: obtaining electrostatic discharge test data of a first group of capacitors; obtaining gap breakdown simulation data of the first group of capacitors; determining the gap breakdown voltage model based on the gap breakdown simulation data and the gap breakdown voltage basic model, the gap breakdown voltage model being a relationship formula including the gap breakdown voltage of the capacitor, the plate facing length of the capacitor, and the plate gap of the capacitor; determining the electrostatic discharge failure voltage model based on the gap breakdown voltage model, the electrostatic discharge failure voltage basic model, and the electrostatic discharge test data of the first group of capacitors, the electrostatic discharge failure voltage model being a relationship formula including the electrostatic discharge failure voltage of the capacitor, the plate facing length of the capacitor, and the plate gap of the capacitor. The technical solution disclosed in the present disclosure can provide a theoretical basis for quantitative anti-static design and improve the accuracy and efficiency of anti-static design.

Description

Technical Field

[0001] The present disclosure relates to the field of electrostatic discharge technology, and in particular to a method and device for determining an electrostatic discharge failure voltage model of a capacitor. Background Art

[0002] At present, there has been relatively in-depth research on the electrostatic discharge immunity test of components. However, due to the complexity of the ESD (ElectroStatic Discharge) field and the limitations of the ESD test standards, the design and development departments can only blindly conduct repeated trials to modify the anti-static measures to meet the electrostatic discharge immunity requirements.

[0003] Therefore, it is necessary to establish a capacitor electrostatic discharge failure voltage model to provide a theoretical basis for more specific anti-static design. Summary of the Invention

[0004] Embodiments of the present disclosure provide a method and apparatus for determining an electrostatic discharge failure voltage model of a capacitor to solve or alleviate one or more technical problems in the prior art.

[0005] As a first aspect of an embodiment of the present disclosure, an embodiment of the present disclosure provides a method for determining an electrostatic discharge failure voltage model of a capacitor, comprising:

[0006] Obtaining electrostatic discharge test data of the first group of capacitors, the electrostatic discharge test data including the length of the capacitor plates facing each other, the gap between the capacitor plates, and the electrostatic discharge failure voltage of the capacitor;

[0007] Obtaining gap breakdown simulation data of the first group of capacitors, the gap breakdown simulation data including the length of the capacitor plates facing each other, the gap between the capacitor plates, and the gap breakdown voltage of the capacitor;

[0008] Determine a gap breakdown voltage model based on gap breakdown simulation data and a gap breakdown voltage basic model, wherein the gap breakdown voltage model is a relationship between the gap breakdown voltage of the capacitor, the length of the capacitor plates facing each other, and the gap between the capacitor plates;

[0009] The electrostatic discharge failure voltage model is determined based on the gap breakdown voltage model, the electrostatic discharge failure voltage basic model and the electrostatic discharge test data of the first group of capacitors. The electrostatic discharge failure voltage model is a relationship between the electrostatic discharge failure voltage of the capacitor, the facing length of the capacitor plates and the gap between the capacitor plates.

[0010] In some possible implementations, determining a gap breakdown voltage model based on gap breakdown simulation data and a gap breakdown voltage basic model includes:

[0011] According to Paschen's law and dielectric layer defect density theory, a gap breakdown voltage basic model is determined. The gap breakdown voltage basic model is a relationship equation including the gap breakdown voltage of the capacitor, the plate facing length of the capacitor, the plate gap of the capacitor, the fifth parameter, the sixth parameter, and the seventh parameter.

[0012] According to the gap breakdown simulation data, a gap breakdown voltage basic model is fitted to determine the fifth parameter, the sixth parameter and the seventh parameter to determine the gap breakdown voltage model.

[0013] In some possible implementations, the gap breakdown voltage basic model satisfies the following relationship:

[0014]

[0015] Wherein, V0 is the gap breakdown voltage of the capacitor, D is the plate gap of the capacitor, L is the plate facing length of the capacitor, k3, e, and α are the fifth parameter, the sixth parameter, and the seventh parameter, respectively.

[0016] In some possible implementations,

[0017] The value range of the fifth parameter k3 is 68 to 71; and / or,

[0018] The value range of the sixth parameter e is (-0.2) to (-0.4); and / or,

[0019] The numerical range of the seventh parameter α is (-0.104) to (-0.107).

[0020] In some possible implementations, the electrostatic discharge failure voltage basic model satisfies the following relationship:

[0021]

[0022] Among them, V esd is the electrostatic discharge failure voltage of the capacitor, D is the gap between the capacitor plates, L is the length of the capacitor plates facing each other, V0 is the gap breakdown voltage of the capacitor, a, b, c, and d are the first parameter, second parameter, third parameter, and fourth parameter respectively.

[0023] In some possible implementations,

[0024] The numerical range of the first parameter a is 0.42 to 0.62; and / or,

[0025] The value range of the second parameter b is 230 to 234; and / or,

[0026] The value range of the third parameter c is 20 to 21; and / or,

[0027] The value range of the fourth parameter d is 2-4.

[0028] In some possible implementations, the method further includes:

[0029] Obtain electrostatic discharge test data of the second group of capacitors;

[0030] A revised electrostatic discharge failure voltage model is determined based on the gap breakdown voltage model, the electrostatic discharge failure voltage basic model, the electrostatic discharge test data of the first group of capacitors, and the electrostatic discharge test data of the second group of capacitors. The revised electrostatic discharge failure voltage model is a relationship equation including the electrostatic discharge failure voltage of the capacitor, the facing length of the capacitor's plates, and the gap between the capacitor's plates.

[0031] In some possible implementations,

[0032] In the electrostatic discharge test data of the second group of capacitors, the length of the capacitor plates facing each other is greater than or equal to 30μm, and the gap between the capacitor plates is greater than or equal to 5μm;

[0033] The modified electrostatic discharge failure voltage model satisfies the following relationship:

[0034]

[0035] Among them, V esd is the electrostatic discharge failure voltage of the capacitor, D is the gap between the capacitor plates, L is the length of the capacitor plates, V0 is the gap breakdown voltage of the capacitor, the numerical range of the corrected first parameter a1 is 0.25~0.45, the numerical range of the corrected second parameter b1 is 252~256, the numerical range of the corrected third parameter c1 is 15~16.5, and the numerical range of the corrected fourth parameter d1 is 5~7.5.

[0036] In some possible implementations,

[0037] In the electrostatic discharge test data of the second group of capacitors, the length of the capacitor plates facing each other is less than or equal to 10μm;

[0038] The modified electrostatic discharge failure voltage model satisfies the following relationship:

[0039]

[0040] Among them, V esd is the electrostatic discharge failure voltage of the capacitor, D is the plate gap of the capacitor, L is the plate facing length of the capacitor, V0 is the gap breakdown voltage of the capacitor, the numerical range of the corrected first parameter a2 is 2.5~3.5, the numerical range of the corrected second parameter b2 is 21.5~23, the numerical range of the corrected third parameter c2 is 15~16, and the numerical range of the corrected fourth parameter d2 is 0.4~0.55.

[0041] In some possible implementations, obtaining gap breakdown simulation data of the first group of capacitors includes:

[0042] Establish an electrostatic discharge simulator model, an external probe station equivalent circuit model, and a capacitance model;

[0043] Connect the electrostatic discharge simulator model, the external probe station equivalent circuit model and the capacitor model to establish a capacitor electrostatic discharge simulation model;

[0044] The simulation parameters of the capacitor electrostatic discharge simulation model are set to obtain gap breakdown simulation data of the first group of capacitors. The gap breakdown simulation data of the first group of capacitors includes the facing length of the capacitor plates, the gap between the capacitor plates, and the corresponding gap breakdown voltage of the capacitor.

[0045] In some possible implementations, the capacitor is a T-type flat plate capacitor.

[0046] As a second aspect of an embodiment of the present disclosure, an embodiment of the present disclosure provides a device for determining an electrostatic discharge failure voltage model of a capacitor, comprising:

[0047] A first acquisition module is configured to acquire electrostatic discharge test data of a first group of capacitors, the electrostatic discharge test data including a length of opposite plates of the capacitors, a gap between the plates of the capacitors, and an electrostatic discharge failure voltage of the capacitors;

[0048] a second acquisition module, configured to acquire gap breakdown simulation data of the first group of capacitors, the gap breakdown simulation data including the length of the capacitor plates facing each other, the gap between the capacitor plates, and the gap breakdown voltage of the capacitor;

[0049] A first determining module is configured to determine a gap breakdown voltage model based on the gap breakdown simulation data and the gap breakdown voltage basic model, wherein the gap breakdown voltage model is a relationship between the gap breakdown voltage of the capacitor, the length of the capacitor plates facing each other, and the gap between the capacitor plates;

[0050] The second determination module is used to determine the electrostatic discharge failure voltage model based on the gap breakdown voltage model, the electrostatic discharge failure voltage basic model and the electrostatic discharge test data of the first group of capacitors. The electrostatic discharge failure voltage model is a relationship between the electrostatic discharge failure voltage of the capacitor, the facing length of the capacitor's plates and the gap between the capacitor's plates.

[0051] As a third aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide an electronic device, including:

[0052] at least one processor; and

[0053] a memory communicatively connected to at least one processor; wherein,

[0054] The memory stores instructions that can be executed by at least one processor. The instructions are executed by the at least one processor to enable the at least one processor to perform the method in any embodiment of the present disclosure.

[0055] As a second aspect of an embodiment of the present disclosure, an embodiment of the present disclosure provides a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to enable a computer to execute a method according to any embodiment of the present disclosure.

[0056] The electrostatic discharge failure voltage model determined by the embodiment of the present disclosure can provide a theoretical basis for the quantitative design of anti-static, and can provide a theoretical basis for the quantitative design of anti-static for wiring of special shapes, so that the anti-static design no longer remains in the qualitative test stage, avoiding the modification of anti-static measures by blindly changing the design, and improving the accuracy and efficiency of the anti-static design.

[0057] The above summary is for illustrative purposes only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments and features described above, further aspects, embodiments and features of the present disclosure will be readily apparent by reference to the accompanying drawings and the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar components or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments according to the present disclosure and should not be regarded as limiting the scope of the present disclosure.

[0059] Figure 1 Schematic diagram of a method for determining an electrostatic discharge failure voltage model of a capacitor in an embodiment of the present disclosure;

[0060] Figure 2 This is a schematic diagram of the structure of a capacitor in one embodiment of the present disclosure;

[0061] Figure 3 Schematic diagram of capacitor breakdown failure in one embodiment of the present disclosure;

[0062] Figure 4a This is the failure diagram when the breakdown voltage is closest to the failure voltage;

[0063] Figure 4b This is a failure diagram when the breakdown voltage is slightly greater than the failure voltage;

[0064] Figure 4c This is a failure diagram when the breakdown voltage is much greater than the failure voltage;

[0065] Figure 5The device discharge equivalent circuit diagram for the human body discharge model;

[0066] Figure 6 is a schematic diagram of a physical model of an electrostatic discharge simulator in one embodiment;

[0067] Figure 7 is a schematic diagram of lumped circuit elements of an electrostatic discharge simulator according to one embodiment;

[0068] Figure 8 is a schematic diagram of an excitation voltage waveform in one embodiment;

[0069] Figure 9 Schematic diagram of the short-circuit output waveform of the electrostatic discharge simulator (1kV voltage);

[0070] Figure 10 Schematic diagram of the output waveform of the ESD simulator with a 500Ω load (1kV voltage);

[0071] Figure 11 In one embodiment, a schematic diagram of an equivalent circuit model of an external probe station is provided;

[0072] Figure 12 is a geometric model of a T-shaped plate capacitor in one embodiment;

[0073] Figure 13 is a schematic diagram of a probe discharge port in one embodiment;

[0074] Figure 14 is an electrostatic discharge simulation model of a T-shaped plate capacitor in one embodiment;

[0075] Figure 15 A schematic diagram of discrete port circuit connections in one embodiment;

[0076] Figure 16 : is a fitting diagram of the gap breakdown voltage model of V0=f(D, L) in one embodiment;

[0077] Figure 17 In one embodiment, V esd =G(D, L) electrostatic discharge failure voltage model fitting diagram;

[0078] Figure 18 is the corrected V in one embodiment of the present disclosure esd = G1(D, L) electrostatic discharge failure voltage model fitting diagram (L≥30μm);

[0079] Figure 19 A schematic diagram of predicting electrostatic discharge failure voltage using a model according to an embodiment of the present disclosure when L=45 μm;

[0080] Figure 20: This is a fitting diagram of the modified Vesd=G2(D, L) electrostatic discharge failure voltage model in one embodiment of the present disclosure (L≤10μm);

[0081] Figure 21 4 is a structural block diagram of a device for determining an electrostatic discharge failure voltage model of a capacitor in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0082] In the following, only certain exemplary embodiments are briefly described. As will be appreciated by those skilled in the art, the described embodiments may be modified in various ways without departing from the spirit or scope of the present disclosure, and different embodiments may be combined in any manner without conflict. Therefore, the drawings and description are to be regarded as illustrative in nature and not restrictive.

[0083] First, several terms involved in this disclosure are introduced and explained:

[0084] GOA: Gate Driver on Array (GOA);

[0085] TFT-LCD: Thin Film Transistor Liquid Crystal Display;

[0086] ESD: Electrostatic discharge;

[0087] Pad: In this article, it refers to the area used for probe insertion in electrostatic discharge testing.

[0088] The inventors of the present disclosure have discovered that, in addition to the panel and backlight system, the thin-film transistor liquid crystal display (TFT-LCD) drive system includes three modules: a scan drive circuit, a data drive circuit, and a common voltage (VCOM) module. Gate Driver on Array (GOA) technology integrates the gate driver of a liquid crystal display (LCD) panel onto a glass substrate, replacing an external gate integrated circuit (IC) chip. This technology forms a scan drive for the panel on the substrate, reducing the use of gate driver ICs, lowering power consumption and costs. GOA technology is a crucial component of LCD screens and has a critical impact on the reliability of LCD products.

[0089] Electrostatic discharge (ESD) is a serious problem plaguing many electronic products. However, in the development of GOA technology, most research has focused on drive circuits, studying the balance between improving drive capability and reducing power consumption to address issues in large-scale and high-resolution applications. However, research on ESD failures in GOA products has mostly focused on how to reduce static electricity generation during the manufacturing process. Improving the anti-static capabilities of GOA products through design improvements is a bottleneck that needs to be addressed urgently.

[0090] The contact, friction, compression, and separation processes involved in TFT-LCD substrate production are all prone to static electricity generation. Glass substrates are inherently insulating materials, so static electricity dissipates slowly. Furthermore, with the expansion of circuit scale, the reduction of circuit feature sizes, and the simultaneous pursuit of high resolution and miniaturization, the wiring density in the GOA area has increased, while the wiring pitch and size have continued to decrease. This makes the GOA wiring area susceptible to electrostatic breakdown failure, causing circuit damage. Therefore, as a critical component of TFT-LCD products, the anti-static capability of GOA directly impacts the reliability of the entire LCD system. Limited research has been conducted on wiring electrostatic failure. Existing literature has compared two gate test lines and found that in microelectronic device circuits, with the same footprint and test line width, the longer the line, the more susceptible it is to electrostatic discharge. When the longer line is 14% longer than the shorter line, electrostatic discharge primarily occurs on the longer line. This provides guidance for circuit design on how to avoid electrostatic discharge, particularly by shortening functional lines or adding longer dummy lines.

[0091] During production practice, it was found that the T-shaped wiring structure is more prone to electrostatic discharge failure than other side-by-side wiring structures. Therefore, it is necessary to conduct in-depth research on the factors affecting the electrostatic discharge failure of the T-shaped wiring of GOA products. The T-shaped wiring structure can be regarded as a T-shaped flat plate capacitor structure.

[0092] After further research, the inventors of the present disclosure found that most of the research on electrostatic discharge failure of T-shaped wiring in GOA products has remained at the stage of improving production equipment and process flow or simply adding an insulating layer to prevent the generation of electrostatic discharge during the manufacturing process. Only a few have considered taking structural design methods to improve the product's anti-electrostatic discharge ability. The present disclosure focuses on changing the anti-electrostatic ability of the product through wiring design. A large number of electrostatic discharge tests have been carried out, but the test standards have not been updated, and the electrostatic discharge test is still at the stage of qualitative testing. The present disclosure can obtain quantitative electrostatic discharge failure voltage of the test samples. In the research of electrostatic discharge simulation technology, a large amount of research has focused on establishing system-level and device-level circuit simulation models, while the present disclosure conducts research on electrostatic discharge simulation of smaller structures and establishes a simulation model for wiring structure. Due to the lack of research on structure-related wiring electrostatic discharge failure voltage models in the existing technology, product designers and research and development departments can only blindly change the design and repeatedly conduct electrostatic discharge tests to modify the anti-static measures to meet the requirements of electrostatic discharge immunity.

[0093] Due to the complexity of ESD fields and the limitations of ESD test standards, related technologies for ESD immunity testing of components can only blindly and repeatedly conduct trials and modify anti-static measures to meet ESD immunity requirements. Therefore, it is necessary to further establish a quantitative capacitor ESD failure voltage model to provide a theoretical basis for more specific anti-static design.

[0094] Figure 1 FIG. 1 is a schematic diagram of a method for determining an electrostatic discharge failure voltage model of a capacitor in an embodiment of the present disclosure. Figure 1 As shown, the method for determining the electrostatic discharge failure voltage model of a capacitor may include:

[0095] S110, obtaining electrostatic discharge test data of the first group of capacitors, where the electrostatic discharge test data includes the length of the capacitor plates facing each other, the gap between the capacitor plates, and the electrostatic discharge failure voltage of the capacitor;

[0096] S120, obtaining gap breakdown simulation data of the first group of capacitors, where the gap breakdown simulation data includes the length of the capacitor plates facing each other, the gap between the capacitor plates, and the gap breakdown voltage of the capacitor;

[0097] S130, determining a gap breakdown voltage model based on the gap breakdown simulation data and the gap breakdown voltage basic model, where the gap breakdown voltage model is a relationship equation including the gap breakdown voltage of the capacitor, the length of the capacitor plates facing each other, and the gap between the capacitor plates;

[0098] S140. Determine an electrostatic discharge failure voltage model based on the gap breakdown voltage model, the electrostatic discharge failure voltage basic model, and the electrostatic discharge test data. The electrostatic discharge failure voltage model is a relationship equation including the electrostatic discharge failure voltage of the capacitor, the length of the capacitor's plates facing each other, and the gap between the capacitor's plates.

[0099] Exemplarily, electrostatic discharge test data may be obtained through an experimental method.

[0100] Exemplarily, gap breakdown simulation data can be obtained through a model simulation method.

[0101] The technical solution of the disclosed embodiments determines a gap breakdown voltage model based on gap breakdown simulation data and a basic gap breakdown voltage model. Furthermore, an ESD failure voltage model is determined based on the gap breakdown voltage model, the basic ESD failure voltage model, and ESD test data. In determining the ESD failure voltage model, the gap breakdown simulation data and ESD test data of the first group of capacitors are used. Compared to using only ESD test data, this can avoid the influence of parasitic resistance and capacitance inductance of the external circuit on the waveform during the test, thereby improving the accuracy of the determined ESD failure voltage model.

[0102] The electrostatic discharge failure voltage model determined by the embodiment of the present disclosure can provide a theoretical basis for the quantitative design of anti-static, and can provide a theoretical basis for the quantitative design of anti-static for wiring of special shapes, so that the anti-static design no longer remains in the qualitative test stage, avoiding the modification of anti-static measures by blindly changing the design, and improving the accuracy and efficiency of the anti-static design.

[0103] For example, the capacitor can be a T-shaped flat plate capacitor. A T-shaped wiring structure is more susceptible to electrostatic discharge failure than a side-by-side wiring structure. Therefore, by setting the capacitor as a T-shaped flat plate capacitor, an electrostatic discharge failure voltage model for the T-shaped flat plate capacitor can be obtained, which can provide a quantitative theoretical basis for the design of the T-shaped wiring structure.

[0104] In one embodiment, obtaining electrostatic discharge test data of the first group of capacitors may include obtaining electrostatic discharge test data of the first group of T-shaped flat plate capacitors. This step may include the following process: designing electrostatic discharge test samples based on the key influencing factors of the electrostatic discharge failure voltage of the first group of T-shaped flat plate capacitors; formulating an electrostatic discharge test plan to determine the basis for judging the electrostatic discharge failure of the T-shaped flat plate capacitors; performing an electrostatic discharge test on the test samples, recording the electrostatic discharge failure voltage of T-shaped flat plate capacitors with different structures, and obtaining failure voltage data of the T-shaped flat plate capacitors that changes with the structure. Then, the test results are analyzed and invalid data is eliminated from the obtained test data. This step is described in detail below in conjunction with specific embodiments.

[0105] 1. Test sample design

[0106] Design and manufacture test samples, including substrate selection, power pad design, T-shaped plate capacitor structure design, etc. In the structural design, it is necessary to consider the orthogonal combination test of different key influencing factors, and eliminate interference factors through structural design. The sample structure is as follows: Figure 2 As shown, Figure 2 Schematic diagram of the structure of a capacitor in one embodiment of the present disclosure.

[0107] like Figure 2 As shown, the capacitor includes a first metal line structure 210 and a second metal line structure 220. The first metal line structure 210 and the second metal line structure 220 are arranged in a T-shape, respectively serving as the two plates of the capacitor. For example, the first metal line structure 210 includes a first portion 211 and a second portion 212. The second metal line structure 220 includes a third portion 221, a fourth portion 222, and a fifth portion 223.

[0108] See also Figure 2 As shown, the first direction X and the second direction Y are perpendicular, the first metal line structure 210 is arranged along the second direction Y, and the second metal line structure 220 is arranged along the first direction X. W1 is the dimension of the second portion 212 in the second direction Y, W2 is the dimension of the third portion 221 in the first direction X, W3 is the dimension of the third portion 221 and the fourth portion 222 in the first direction X, the plate gap D is the gap dimension between the second portion 212 and the third portion 221, L1 is the dimension of the second portion 212 in the first direction X, the plate facing length L is the dimension of the third portion 221 in the second direction Y, and L3 is the dimension of the fourth portion 222 in the second direction Y.

[0109] For example, the plate gap D and the plate facing length L are variable dimensional parameters on the same substrate 100 . The substrate 100 can be a glass substrate, and the pad size can be 200 μm (micrometers) * 200 μm.

[0110] For example, the structural parameters of the T-shaped flat plate capacitor may be shown in Table 1. In Table 1, the plate gap D and the plate facing length L each have four different values.

[0111] Table 1 Geometric model parameters of T-shaped plate capacitor

[0112]

[0113] 2. Test Plan Development

[0114] To formulate a test plan, at least ten of the above-mentioned sample groups need to be prepared. The prepared sample groups can be called the first group of capacitors. Select equipment with a suitable electrostatic discharge voltage range, eliminate environmental interference through vibration and noise reduction measures, ground the interference signal through a shielded wire, and consider the release of the accumulated charge of the capacitor after each discharge. By reducing the applied voltage interval and conducting multiple tests, the voltage level at the time of electrostatic discharge failure is recorded when a gap appears in the T-shaped structure of the capacitor or a wiring fuse occurs, and multiple sets of relatively accurate failure voltage data are obtained. The test equipment includes (a) a probe station, (b) a HED-N5000 ESD antistatic tester, and (c) a PC. The probe station is used to power the sample, the antistatic tester is the static electricity source, and the PC is used to control the tester and observe the failure of the T-shaped flat capacitor.

[0115] 3. Experimental implementation

[0116] First, connect the probe station to the discharge equipment with a coaxial cable, and adjust the probe so that the probe touches the pads at both ends of the T-shaped capacitor. Then set the parameters of the software used by the electrostatic discharge instrument, set the input and output pins, the discharge model to the HBM model, the discharge form to +, the discharge interval to 1s, the number of discharges to 1, and automatically release the residual charge after each discharge. The remaining parameters are set according to the relevant requirements of the test equipment. Finally, set the initial voltage value with a step of 5v, and observe the T-shaped capacitor through the microscope camera until a breakdown failure occurs, such as Figure 3 As shown, Figure 3 This is a schematic diagram of the breakdown failure of a capacitor in one embodiment of the present disclosure. The voltage value at this time is recorded to obtain the electrostatic discharge test data before treatment.

[0117] It should be noted that during the test, the discharge interval time, discharge times and voltage step value can be set as needed and are not limited to the specific values ​​listed above.

[0118] 4. Analysis of test results

[0119] Due to some error interference in the test environment and the inconsistency of the samples themselves, the failure voltage of the same structure samples is also different. During the test, different degrees of failure were observed, such as Figure 4a 、 Figure 4b and Figure 4c shown. Figure 4a This is the failure diagram when the breakdown voltage is closest to the failure voltage. Figure 4b This is a failure diagram when the breakdown voltage is slightly greater than the failure voltage. Figure 4c This is a failure diagram when the breakdown voltage is much greater than the failure voltage. Figure 4a As shown in , when the breakdown voltage is closest to the failure voltage, failure only occurs at the conductor junction. Figure 4bAs shown in Figure 2, when the breakdown voltage is slightly greater than the failure voltage, the transverse wires also show slight burnout. Figure 4c As shown, when the breakdown voltage is too high, much greater than the failure voltage, all the transverse wires melt, and even some of the longitudinal wires melt.

[0120] 5. Electrostatic discharge test data processing

[0121] The electrostatic discharge test data before processing obtained during the experiment is pre-processed, the influence of the test environment interference is analyzed, and abnormal data and invalid data are cleared. Generally speaking, if a quantity is the result of the influence of many tiny independent random factors, then it can be considered that this quantity has a normal distribution, so the method of normal distribution fitting is adopted to exclude the invalid data of each test point. After importing the data in Minitab, normal distribution fitting is selected. After removing the invalid data, the standard deviation of the normal distribution curve fitted is as small as possible while the P value is as large as possible. When P>0.05, it is judged that the data obeys the normal distribution. The larger the P value, the more the data obeys the normal distribution. The data results after processing are finally obtained as shown in Table 2. The data shown in Table 2 can be the electrostatic discharge test data of the first group of capacitors in an embodiment.

[0122] Table 2 T-shaped plate capacitor electrostatic discharge test data

[0123]

[0124]

[0125] In Table 2, A31 refers to a T-shaped plate capacitor with L = 30 μm and D = 10 μm; A32 refers to a T-shaped plate capacitor with L = 30 μm and D = 15 μm; A33 refers to a T-shaped plate capacitor with L = 30 μm and D = 20 μm; A34 refers to a T-shaped plate capacitor with L = 30 μm and D = 25 μm;

[0126] A41 refers to a T-shaped flat plate capacitor with L = 42.5 μm and D = 10 μm; A42 refers to a T-shaped flat plate capacitor with L = 42.5 μm and D = 15 μm; A43 refers to a T-shaped flat plate capacitor with L = 42.5 μm and D = 20 μm; A44 refers to a T-shaped flat plate capacitor with L = 42.5 μm and D = 25 μm;

[0127] A51 refers to a T-shaped flat plate capacitor with L = 53 μm and D = 10 μm; A52 refers to a T-shaped flat plate capacitor with L = 53 μm and D = 15 μm; A53 refers to a T-shaped flat plate capacitor with L = 53 μm and D = 20 μm; A54 refers to a T-shaped flat plate capacitor with L = 53 μm and D = 25 μm;

[0128] A61 refers to a T-shaped flat plate capacitor with L = 64μm and D = 10μm; A62 refers to a T-shaped flat plate capacitor with L = 64μm and D = 15μm; A63 refers to a T-shaped flat plate capacitor with L = 64μm and D = 20μm; A64 refers to a T-shaped flat plate capacitor with L = 64μm and D = 25μm.

[0129] As can be seen from Table 2, the electrostatic discharge test data includes the capacitor's plate facing length L, the capacitor's plate gap D, and the capacitor's electrostatic discharge failure voltage V esd For each sample number of T-shaped flat capacitor, obtain 10 electrostatic discharge failure voltages V esd The mean values ​​in Table 2 are the normal distribution means of the valid data of multiple electrostatic discharge failure voltages of the corresponding T-shaped flat plate capacitors.

[0130] In one embodiment, obtaining gap breakdown simulation data of the first group of capacitors may include: obtaining gap breakdown simulation data of the first group of T-shaped plate capacitors.

[0131] Exemplarily, obtaining gap breakdown simulation data of a first group of capacitors may include: establishing an electrostatic discharge simulator model, an external probe station equivalent circuit model, and a capacitor model; connecting the electrostatic discharge simulator model, the external probe station equivalent circuit model, and the capacitor model to establish a capacitor electrostatic discharge simulation model; setting simulation parameters for the capacitor electrostatic discharge simulation model to obtain gap breakdown simulation data of a first group of capacitors, the gap breakdown simulation data of the first group of capacitors including the facing length of the capacitor plates, the capacitor plate gap, and the corresponding gap breakdown voltage of the capacitor.

[0132] It should be noted that when performing the above-mentioned ESD test, the discharge waveform of the equipment strictly complies with the prescribed waveform of the JEDEC standard. Due to the need for an external probe station to carry out the discharge test, although a coaxial cable is added to the discharge circuit to eliminate external interference, the parasitic resistance and capacitance of the external circuit may still have a certain impact on the waveform, causing the ESD test source (i.e., electrostatic discharge equipment) waveform to be attenuated to a certain extent when it is transmitted to the sample, thereby causing an error to occur between the set voltage value of the equipment and the actual failure voltage value of the T-shaped flat plate capacitor. In order to obtain a more accurate T-shaped flat plate capacitor electrostatic discharge failure voltage value, i.e., the T-shaped flat plate capacitor gap breakdown voltage, it is necessary to establish a circuit simulation model that is more in line with actual test conditions and perform simulation solution. Below, in conjunction with specific embodiments, the step of obtaining the gap breakdown simulation data of the first group of T-shaped flat plate capacitors is described in detail.

[0133] 1. Construction of Electrostatic Discharge Simulator

[0134] In one embodiment of the present disclosure, according to the object simulated by the ESD immunity test and the main features of the ESD test model, the human body discharge model (HBM) specified in the JEDEC standard can be used as the equivalent model of the electrostatic discharge device, and the simulation circuit of the output current waveform of the device itself can be simulated. Figure 5 As shown, Figure 5 This is the device discharge equivalent circuit diagram for the Human Body Model (HBM). C1 is the discharge capacitor (C1 = 100pF); R1 is the discharge resistor (R1 = 1500Ω); L1 and C2 are parasitic inductance and capacitance. It should be noted that the equivalent model for ESD devices is not limited to the Human Body Model (HBM). Other ESD device equivalent models can be selected as needed.

[0135] The electrostatic discharge simulator required by this embodiment is built in simulation software such as CST software, and the discharge waveform specified by the JEDEC standard is met by adjusting the size parameters and circuit structure. Figure 6 As shown, Figure 6 FIG. 1 is a schematic diagram of an electrostatic discharge simulator physical model in one embodiment. The electrostatic discharge simulator may include a dielectric and a metal part. The relative dielectric constant of the dielectric is 1. The conductivity S of the metal part is 1s / m. Figure 6 The structures other than dielectrics (all set to ideal conductor PEC materials to reduce calculation time) in the ESD simulator also include lumped circuit elements. The lumped circuit element loops used in the model refer to Figure 5 The equivalent circuit diagram is established, such as Figure 7 As shown, Figure 7 FIG. 1 is a schematic diagram of a lumped circuit element of an electrostatic discharge simulator in one embodiment. Figure 7 As shown, the electrostatic discharge simulator is excited at port 4, and the excitation port is set to a voltage of a step function waveform with a voltage rise time of 10ns and a voltage amplitude of 1kV. The collector switch of the electrostatic discharge simulator is simulated, that is, the charging and rapid discharge process of electrostatic discharge is reproduced. The applied voltage signal is as follows Figure 8 As shown, Figure 8 FIG. 4 is a schematic diagram of an excitation voltage waveform in one embodiment.

[0136] Using the electrostatic discharge simulator model built above, simulation analysis is carried out in simulation software such as CST software. After meshing the electrostatic discharge simulator model, for example, using the built-in hexahedral mesh to mesh the electrostatic discharge simulator model, set the frequency range to 0-500MHz, and the boundary condition to Zmin plane grounding at the ground plate. The output current waveform of the electrostatic discharge simulator obtained by simulation is as follows: Figure 9 and Figure 10 As shown, Figure 9This is a schematic diagram of the short-circuited output waveform of the electrostatic discharge simulator (1kV voltage). Figure 10 The following diagram shows the output waveform of the ESD simulator with a 500Ω load (1kV voltage). Table 3 compares the output waveform with the JEDEC standard waveform parameters. As can be seen from Table 3, both the peak current and the waveform rise time meet the standard requirements, though the waveform falls off too quickly. However, ESD failure typically occurs at maximum current, so the fall time has little impact on the subsequent ESD simulation of the T-shaped plate capacitor. Therefore, the constructed ESD simulator model meets the requirements.

[0137] Table 3 Comparison of the simulated waveform parameters of the ESD simulator short-circuit current and the standard waveform parameters

[0138]

[0139] 2. Establishment of the Equivalent Circuit Model of the Equipment External Probe Station

[0140] Due to the tiny structure of the T-shaped flat capacitor, it is impossible to conduct ESD immunity tests directly through discharge equipment, and an external probe station is required to test the sample. For example, the external probe station (i.e., the connection from the device to the sample) can be divided into three parts. The first part is two parallel thin wires with pins, with a length of 20 cm. One end of the wire is connected to the two pins of the test equipment through the pin, and the other end is connected to the core wire end of the coaxial cable in the second part; the second part is a coaxial cable with a length of 20 cm. The core wire of the coaxial cable is connected to the first part, the shielding layer is grounded, and the other end is connected to the probe wire of the third part; the third part is a probe station wire with a length of 240 cm. The equivalent circuit model parameters of the three parts are determined below.

[0141] (1) Parallel thin wires

[0142] The first part has two wires, one for the output and one for the ground. The wires are close together, which creates coupling capacitance. Therefore, there are three circuit parameters that need to be confirmed: ① The capacitance between the two wires, C3; ② The resistance of the output wire, R2; and ③ The inductance of the output wire, L2. The radius of the parallel thin wire, R A =0.5mm, the distance between the two lines d = 10mm, the length L A =20cm.

[0143] When R A1 =R A2 =, the capacitance C3 per unit length of two cylindrical parallel straight wires with equal radius can be calculated using the relation (1), which is:

[0144]

[0145] Wherein, ε0 is the dielectric constant of vacuum, ε0 = 8.85*10^(-12)F / m.

[0146] The resistance R2 can be calculated using the conductor resistance relationship (2):

[0147] R=ρ*L / S Relationship (2)

[0148] Where ρ is the conductor resistivity, the copper conductor resistivity is 1.75 × 10^(-8)Ω·m, L is the conductor length, and S is the conductor cross-sectional area. The resistance of the other two parts of the connecting wire are calculated using this formula.

[0149] The inductance per unit length of the conductor can be calculated using equation (3):

[0150]

[0151] Wherein, μ0 is the magnetic permeability of vacuum, μ0=4π*10^(-7)H / m.

[0152] Calculation shows that C3 = 1.86*10^(-12)F, R2 = 4.46*10^(-3)Ω, and L2 = 1*10^(-8)H.

[0153] (2) Coaxial cable

[0154] In this embodiment, the shielding layer of the coaxial cable is grounded during the test, so there are three circuit parameters that need to be confirmed: ① the capacitance C4 between the inner and outer conductors; ② the resistance R3 of the inner conductor; ③ the inductance L3 of the coaxial line. The radius of the inner conductor is r B =0.45mm, the inner radius of the outer conductor is R B =1.6mm, length L B = 20 cm. The space between the inner and outer conductors is filled with a uniform insulating dielectric, polyethylene (PE). The inner and outer conductors can be considered ideal conductors, and the current is distributed over their surfaces. Using Gauss's theorem, the capacitance and inductance per unit length of the coaxial cable can be calculated.

[0155] The calculation formulas for the capacitance and inductance of coaxial cable per unit length are as follows:

[0156]

[0157]

[0158] Wherein, ε is the dielectric constant of the insulating dielectric layer, and the relative dielectric constant of polyethylene is 2.3.

[0159] Calculation shows that C4 = 2.02*10^(-11)F, R3 = 5.50*10^(-3)Ω, and L3 = 2.54*10^(-7)H.

[0160] (3) Probe station wire

[0161] Since the probe station wires are spaced far apart, there is no capacitance between the two wires, and one of the wires is grounded, there are two circuit parameters that need to be determined for the probe station wire: ① The resistance R4 of the probe station wire; ② The inductance L4 of the probe station wire. C =240cm, radius R C =1mm.

[0162] Calculation shows that R4 = 1.34*10^(-2)Ω, L4 = 1.2*10^(-7)H.

[0163] The equivalent circuit model of the external probe station of the equipment is as follows Figure 11 As shown, Figure 11 In one embodiment, a schematic diagram of an equivalent circuit model of an external probe station is shown. Figure 11 C in o Refers to structural samples with different structural parameters, for example, Figure 11 C in o Refers to T-shaped plate capacitors with different structural parameters. The parameters of the external probe station simulation circuit model can be shown in Table 4.

[0164] Table 4 Parameters of the external probe station simulation circuit model

[0165]

[0166] 3. T-shaped plate capacitor gap breakdown voltage simulation

[0167] (1) Construction of T-shaped flat plate capacitor model

[0168] First, according to Figure 2 The geometric structure and structural parameters of the T-shaped flat plate capacitor listed in Table 1 are used to directly establish a geometric model in the CST software. In order to reduce the number of grids and calculation time, only a single T-shaped flat plate capacitor structure is selected and placed on the glass substrate for model building and simulation. For example, the length and width of the glass substrate can be set to 10mm, the thickness is 0.5mm, the material is set to glass with a relative dielectric constant of 6, the thickness of the T-shaped flat plate capacitor is set to 260nm according to the actual wiring thickness during sample production, and the wiring material is set to an ideal conductor PEC. The constructed geometric model is as follows: Figure 12 As shown, Figure 12 FIG. 4 is a geometric model of a T-shaped flat plate capacitor in one embodiment.

[0169] (2) Gap breakdown voltage simulation circuit connection and simulation settings

[0170] When conducting the experiment, the discharge port diagram of the two pads of the T-shaped flat capacitor is as follows: Figure 13 As shown, Figure 13 The figure is a schematic diagram of the probe discharge port in one embodiment. The Co-Simulation function of the CST software, i.e., the function of combining the circuit module with the electromagnetic field module, can be used to connect the established electrostatic discharge simulator, the external probe station equivalent circuit model, and the T-shaped plate capacitor geometric model through the added discrete ports to form a complete T-shaped plate capacitor electrostatic discharge simulation model, as shown in FIG. Figure 14 As shown, Figure 14 FIG. 1 is a simulation model of electrostatic discharge of a T-shaped plate capacitor in one embodiment. Figure 14 As shown, port 1 is the step voltage excitation port; port 2 is the ground terminal of the two probes; port 3 is the power terminal of the two probes, that is, the terminal connected to the output port of the external circuit; port 4 is the ground terminal of the ground wire; port 5 is the output terminal of the device outputting the standard waveform; the equivalent circuit of the external probe station is connected between port 3 and port 5, and the overall circuit connection is as shown Figure 15 As shown, Figure 15 FIG. 1 is a schematic diagram of discrete port circuit connections in one embodiment. Figure 15 The resistor R o1 , resistor R o2 , resistor R o3 、Inductor L o1 、Inductor L o2 、Inductor L o3 , capacitor C o1 , capacitor C o2 The parameter values ​​are shown in Table 4.

[0171] After the simulation circuit is completed, grid division is required. Set 25 grids for each wavelength. Since the size of the T-shaped flat capacitor is smaller than that of the electrostatic discharge simulator, especially the wiring thickness is only 260nm, in order to obtain more accurate simulation results, the software automatically divides the grid and then divides the grid of the T-shaped flat capacitor separately. The grid thickness is set to 260nm to ensure that there is only one material in each grid at the connection between the metal wiring and the glass substrate, and to ensure that there are at least two grids in the length and width of the wiring. The grid at the gap of the T-shaped flat capacitor is encrypted. The gap width (plate gap) D of the sample is 10μm, 15μm, 20μm, and 25μm, and the facing length (plate facing length) L is 30μm, 42.5μm, 53μm, and 64μm, so the width of each grid at the gap is set to 2.5μm and the length is 3μm.

[0172] The remaining parameters can be set as follows: the frequency range is set to 0-500MHz; the simulation time is set to 15ns, covering the entire rise time of the electrostatic discharge waveform; the boundary condition is set to Open; the background material is set to air; and the solver is selected as the time domain solver. The input of the simulation includes the structural parameters: gap width D and facing length L, and the normal distribution mean μ of the electrostatic discharge failure voltage of the T-shaped flat capacitor corresponding to each parameter combination listed in Table 2 is set to the step voltage amplitude V esd The simulation output results include the electric field distribution monitored by the E-field monitor and the breakdown voltage V0 of the T-shaped plate capacitor gap monitored by the Voltage-Monitor.

[0173] (3) Simulation results of T-shaped plate capacitor gap breakdown voltage

[0174] The voltage monitor can be used to obtain the gap breakdown voltage V0 of the T-shaped plate capacitor, that is, the actual breakdown voltage across the plate-like capacitor structure formed by the short vertical trace and the long trace of the opposite length during electrostatic discharge. The gap breakdown voltage simulation results corresponding to the sixteen groups of structures are listed in Table 5, thus obtaining the gap breakdown simulation data for the first group of capacitors, as shown in Table 5. As can be seen from Table 5, the gap breakdown simulation data includes the capacitor's plate facing length L, the capacitor's plate gap D, and the capacitor's gap breakdown voltage V0.

[0175] Table 5 Simulation results of gap breakdown voltage V0

[0176]

[0177] In one embodiment, the method for determining the electrostatic discharge failure voltage model of a capacitor may further include: establishing an electrostatic discharge failure voltage basic model.

[0178] The electrostatic discharge charge Q and the electrostatic discharge current i are in a linear relationship when the discharge time t is the same, as shown in equation (6):

[0179]

[0180] Electrostatic discharge voltage V esd and the peak discharge current i max It also shows a linear relationship, so when the discharge current is the largest, that is, when the gap of the T-shaped flat capacitor reaches the maximum breakdown voltage and breakdown occurs, max When the discharge charge Q and the electrostatic discharge failure voltage V esd There is a linear relationship, as shown in equation (7):

[0181] V esd =k1*Q=k1*C*V0 Relationship (7)

[0182] The size C of the T-shaped plate capacitor is related to the plate gap D and the plate facing length L. The capacitance relationship is expressed as equation (8):

[0183]

[0184] Where ε is a constant, S is the area of ​​the capacitor plates facing each other, S = plate facing length L * wiring layer thickness, D is the gap between the capacitor plates, and K is the electrostatic force constant. However, the T-shaped flat plate capacitor in this embodiment is not a conventional flat plate capacitor structure consisting of two plates, so the size of the T-shaped flat plate capacitor satisfies the relationship (9) as follows:

[0185]

[0186] Through equations (7) and (9), the basic model of electrostatic discharge failure voltage can be obtained as shown in equation (10):

[0187]

[0188] Among them, a, b, c, and d are the first parameter, the second parameter, the third parameter, and the fourth parameter respectively, and a, b, c, and d can be obtained by a data fitting method.

[0189] In one embodiment, determining a gap breakdown voltage model based on gap breakdown simulation data and a gap breakdown voltage basic model includes:

[0190] According to Paschen's law and dielectric layer defect density theory, the basic model of gap breakdown voltage is determined. The basic model of gap breakdown voltage includes the gap breakdown voltage of the capacitor, the plate facing length of the capacitor, the plate gap of the capacitor, the fifth parameter, the sixth parameter and the seventh parameter. According to the gap breakdown simulation data, the basic model of gap breakdown voltage is fitted to determine the fifth parameter, the sixth parameter and the seventh parameter to determine the gap breakdown voltage model.

[0191] The model for determining the gap breakdown voltage is described in detail below through specific embodiments.

[0192] (1) Paschen's law

[0193] Paschen's law describes the relationship between the breakdown voltage and the product of (pressure, distance). The Paschen curve reflects the Townsend avalanche theory formulated by Townsend, which considers two main breakdown mechanisms: electron impact ionization (EII) and secondary electron emission (SEE). When the electric field between the two electrodes is high enough, electrons are locally emitted from the sharpest bumps. The electrons are accelerated by the electric field and gain enough energy to ionize the gas molecules in the gap. The cations present in the gap are accelerated until they hit the cathode and cause SEE. EII is defined by the ionization coefficient α, which depends on the voltage V, gas pressure P, gap distance d and two gas-related constants A and B. SEE is related to the secondary ionization coefficient γ according to the formula:

[0194] α=Ape -Bpd / V

[0195] 1-γ(e αd -1)=0

[0196] The classic Paschen formula is given based on the EII and SEE breakdown mechanisms:

[0197]

[0198] Among them, the air gap breakdown coefficient in air is generally A=12cm -1 Torr -1 , B=365Vcm -1 Torr -1 The unit of air pressure p is Torr (one standard atmospheric pressure p = 760 Torr), and the coefficient γ is determined by the cathode material of the discharge electrode.

[0199] (2) Dielectric layer defect density theory

[0200] The breakdown voltage of a thin film capacitor depends on the defect density in the dielectric layer, and its breakdown probability depends on the capacitor area. The relationship (12) is satisfied:

[0201] p=e -γA Relationship (12)

[0202] Where γ is the defect density / weakness and A is the capacitor area.

[0203] Some scholars have derived the relationship between the breakdown voltage U and the capacitor area A by combining formula deduction with experimental verification, as shown in equation (13), where the parameter α should be a Weibull distribution constant less than zero:

[0204] U=kA α Relationship (13)

[0205] (3) Establishment of the basic model of gap breakdown voltage

[0206] As shown in Table 5, the simulation results show that at similar electrostatic discharge failure voltage V esd Under the effect of , the larger the facing length L of the T-shaped flat capacitor, the smaller the gap breakdown voltage V0, and the electric field strength decreases as the gap breakdown voltage decreases, which should be less likely to fail. However, the test results show that the facing length L does not have much effect on the electrostatic discharge failure voltage, which shows that the T-shaped flat capacitor is affected by the defects of the dielectric layer. The longer L is, the more defects there are in the dielectric layer between the capacitor structures, and the more likely it is to fail. The effects of the two laws cancel each other out, so the effect of the facing length L on the failure voltage is not reflected in the electrostatic discharge failure voltage, but it should still be taken into account when establishing the model. Referring to the Paschen formula and the dielectric layer defect theory formula, the basic model of the gap breakdown voltage is determined to be the relationship (14), as follows:

[0207]

[0208] Among them, k3, e, and α are the fifth parameter, the sixth parameter, and the seventh parameter, respectively. The values ​​of k3, e, and α can be obtained by fitting.

[0209] According to the plate gap D, facing length L and corresponding gap breakdown voltage V0 in Table 5, the gap breakdown voltage basic model is fitted. The data fitting diagram is shown in Figure 16 As shown, Figure 16 Figure 2 is a fitting diagram of the gap breakdown voltage model for V0 = f(D, L). The values ​​of k3, e, and α are obtained by fitting. The value range of the fifth parameter k3 is 68 to 71 (inclusive), the value range of the sixth parameter e is (-0.2) to (-0.4) (inclusive), and the value range of the seventh parameter α is (-0.104) to (-0.107) (inclusive), thereby obtaining the gap breakdown voltage model.

[0210] Exemplarily, the value of the fifth parameter k3 is 69.6, the value of the sixth parameter e is -0.3, and the value of the seventh parameter α is -0.1056.

[0211] Then, the gap breakdown voltage model, that is, V0 = f(D, L) is:

[0212]

[0213] In one embodiment, the electrostatic discharge failure voltage model is determined based on the gap breakdown voltage model, the electrostatic discharge failure voltage basic model, and electrostatic discharge test data.

[0214] For example, the ESD failure voltage data in Table 2 can be imported into the Matlab software, and the gap breakdown voltage model V0=f(D, L) obtained by fitting is substituted into the ESD failure voltage basic model such as the relationship (10), and the first parameter a, the second parameter b, the third parameter c and the fourth parameter d in the ESD failure voltage basic model are fitted. The Bisquare tool is used, that is, the weighting is based on the distance from the fitting line. Some outliers are weighted to 0, which is equivalent to removing them. The data fitting diagram is shown in FIG. Figure 17 As shown, Figure 17 In one embodiment, V esd =G(D, L) ESD failure voltage model fitting diagram. The fitting results in the values ​​of the first parameter a, the second parameter b, the third parameter c, and the fourth parameter d. The first parameter a ranges from 0.42 to 0.62, the second parameter b ranges from 230 to 234, the third parameter c ranges from 20 to 21, and the fourth parameter d ranges from 2 to 4, thereby determining the ESD failure voltage model.

[0215] For example, the gap breakdown voltage model relationship (15) can be substituted into the electrostatic discharge failure voltage basic model such as relationship (10), and the fitting results are that the value of the first parameter a is 0.527, the value of the second parameter b is 231.9, the value of the third parameter c is 20.35, and the value of the fourth parameter d is 3.085.

[0216] Then, V esd =G(D, L) The electrostatic discharge failure voltage model satisfies the relationship (16):

[0217]

[0218] In one embodiment, to verify the accuracy of the determined ESD failure voltage model, a second set of capacitor test samples can be designed and ESD test data for the second set of capacitors can be obtained. The sample structural parameters shown in Table 6 can be used as the structural parameters of the second set of capacitors.

[0219] Table 6 Geometric model parameters of the second group of T-shaped plate capacitors

[0220]

[0221] Exemplarily, D can be designed into 8 groups, among which 13μm and 23μm are used to verify the prediction accuracy within the test data coverage range (10μm~25μm), 5μm, 7μm, 30μm, 35μm, 40μm and 60μm are used to verify the applicability of the model extension range, and the 5μm and 7μm samples are used to observe the inflection point of the Paschen curve.

[0222] For example, L2 can be designed in 5 groups: 6μm and 10μm are used to observe the influence of shape-induced electric field concentration on failure voltage, 45μm is used to verify the prediction accuracy within the coverage range of experimental data; 80μm and 100μm can be used to verify the applicability of the model expansion range, and to explore whether the effect of the opposite length L on the failure voltage is significant.

[0223] The above process of obtaining electrostatic discharge test data of the first group of capacitors can be used to test samples of the second group of capacitors and obtain electrostatic discharge test data of the second group of capacitors, thereby obtaining the test data shown in Table 7.

[0224] Table 7 Comparison of model prediction results and verification sample test results

[0225]

[0226] As can be seen from Table 7, for the verification samples with L = 45μm, 80μm, and 100μm, the established ESD failure model has a very good prediction effect, with the error almost within 5%. However, for the verification samples with L = 6μm and 10μm, their test results are far from the failure voltage predicted by the established model, and the error at some points can reach more than 25%.

[0227] It should be noted that, by using the above process of obtaining the electrostatic discharge test data of the first group of capacitors, when testing the samples of the second group of capacitors, multiple electrostatic discharge failure voltages V can be obtained for each T-shaped plate capacitor with a sample number. esd For example, 6 electrostatic discharge failure voltages V esd The V in Table 7 esd The mean is the normal distribution mean of multiple ESD failure voltages.

[0228] In one embodiment, the method for determining the electrostatic discharge failure voltage model of a capacitor may further include: obtaining electrostatic discharge test data of a second group of capacitors; determining a revised electrostatic discharge failure voltage model based on a gap breakdown voltage model, an electrostatic discharge failure voltage basic model, the electrostatic discharge test data of a first group of capacitors, and the electrostatic discharge test data of a second group of capacitors, wherein the revised electrostatic discharge failure voltage model includes the electrostatic discharge failure voltage of the capacitor, the facing length of the capacitor's plates, and the plate gap of the capacitor.

[0229] For example, the electrostatic discharge test data of the first group of capacitors and the electrostatic discharge test data of the second group of capacitors can be imported into Matlab, and the gap breakdown voltage model V0=f(D, L) obtained by fitting is substituted into the electrostatic discharge failure voltage basic model such as the relationship (10), and the first parameter a, the second parameter b, the third parameter c and the fourth parameter d in the electrostatic discharge failure voltage basic model are fitted. The Bisquare tool is used, that is, the weighting is based on the distance from the fitting line. Some outliers are weighted to 0, which is equivalent to eliminating them. The values ​​of the corrected first parameter a, the corrected second parameter b, the corrected third parameter c and the corrected fourth parameter d are obtained by fitting, thereby determining the corrected electrostatic discharge failure voltage model.

[0230] As can be seen from the test results of the verification sample in Table 7, the ESD failure voltage model determined by the disclosed embodiment is applicable within the range L∈[30,100]μm and D∈[5,60]μm. However, the model prediction performance is poor when L=6μm and 10μm. This is likely due to the formation of a discharge tip due to the small L, which makes the gap more susceptible to failure. Therefore, the ESD failure voltage model can be analyzed and modified.

[0231] (1) When the capacitor's facing length L ≥ 30 μm and D ≥ 5 μm, the electrostatic discharge failure voltage model is modified.

[0232] The modified electrostatic discharge failure voltage model satisfies the following relationship (17):

[0233]

[0234] Wherein, a1 is the corrected first parameter, b1 is the corrected second parameter, c1 is the corrected third parameter, and d1 is the corrected fourth parameter.

[0235] The electrostatic discharge test data of the first group of capacitors and the electrostatic discharge test data of the second group of capacitors in Table 2 with L = 45μm, 80μm, and 100μm are all imported into matlab, and the gap breakdown voltage model V0 = f(D, L) obtained by fitting is substituted into the modified electrostatic discharge failure voltage basic model such as the relationship (17), and the modified first parameter a1, the modified second parameter b1, the modified third parameter c1, and the modified fourth parameter d1 in the modified electrostatic discharge failure voltage basic model are fitted. When the model is modified, the parameters related to the cathode material and the test environment are guaranteed to remain unchanged, and the materials and test environments of the samples used for modeling and verification are consistent. The data fitting diagram is shown in FIG. Figure 18 As shown, Figure 18 is the corrected V in one embodiment of the present disclosure esd= G1(D, L) ESD failure voltage model fitting diagram (L ≥ 30 μm). The values ​​of the corrected first parameter a1, the corrected second parameter b1, the corrected third parameter c1, and the corrected fourth parameter d1 are obtained by fitting. Among them, the value range of the corrected first parameter 1a is 0.25-0.45, the value range of the corrected second parameter b1 is 252-256, the value range of the corrected third parameter c1 is 15-16.5, and the value range of the corrected fourth parameter d1 is 5-7.5, thereby determining the corrected ESD failure voltage model V esd =G1(D,L).

[0236] For example, the gap breakdown voltage model relationship (15) can be substituted into the modified electrostatic discharge failure voltage basic model such as relationship (17), and the value of the modified first parameter a1 is fitted to be 0.355, the value of the modified second parameter b1 is 253.7, the value of the modified third parameter c1 is 15.72, and the value of the modified fourth parameter d1 is 6.3.

[0237] Then, the corrected V esd =G1(D, L) The electrostatic discharge failure voltage model satisfies the relationship (18):

[0238]

[0239] The prediction results of the revised ESD failure voltage model are compared with the test results, as shown in Table 8. As can be seen from Table 8, for samples with L ≥ 30 μm, the revised ESD failure voltage model has strong applicability.

[0240] Table 8 V esd = Comparison of the prediction results of the G1(D, L) model and the test results of the verification sample

[0241]

[0242]

[0243] For example, Figure 19 Schematic diagram of predicting electrostatic discharge failure voltage using a model according to an embodiment of the present disclosure when L=45μm. Figure 19 As can be seen in the figure, when the facing length L is fixed at 45μm, the failure voltage model shows an inflection point near the gap width D = 4μm, which means that the model may not be applicable to gap widths of 4μm and below. Therefore, for the model's applicable range for the plate gap D, it is recommended to use the ESD failure voltage model of the embodiment of the present disclosure to predict the failure voltage when D ≥ 5μm.

[0244] (2) When the capacitor's facing length L≤10μm, the electrostatic discharge failure voltage model is modified

[0245] The modified electrostatic discharge failure voltage model satisfies the following relationship (19):

[0246]

[0247] Wherein, a2 is the corrected first parameter, b2 is the corrected second parameter, c2 is the corrected third parameter, and d2 is the corrected fourth parameter.

[0248] When the length L≤10μm, the T-shaped flat capacitor forms a discharge tip structure, and the resulting electric field concentration will cause the failure voltage to drop. However, since the wiring material and the test environment remain unchanged, the parameters that need to be corrected in the model should be those related to the shape, that is, its own capacitance and coupling capacitance. The electrostatic discharge test data of the second group of capacitors with L=6μm and 10μm are imported into matlab, and the gap breakdown voltage model V0=f(D, L) obtained by fitting is substituted into the corrected electrostatic discharge failure voltage basic model such as relation (19). The corrected first parameter a, the corrected second parameter b, the corrected third parameter c and the corrected fourth parameter d in the electrostatic discharge failure voltage basic model are fitted. The data fitting diagram is shown in FIG. Figure 20 As shown, Figure 20 is the corrected V in one embodiment of the present disclosure esd = G2(D, L) ESD failure voltage model fitting diagram (L≤10μm). The values ​​of the corrected first parameter a2, the corrected second parameter b2, the corrected third parameter c2, and the corrected fourth parameter d2 are obtained by fitting. Among them, the value range of the corrected first parameter a2 is 2.5 to 3.5, the value range of the corrected second parameter b2 is 21.5 to 23, the value range of the corrected third parameter c2 is 15 to 16, and the value range of the corrected fourth parameter d2 is 0.4 to 0.55, thereby determining the corrected ESD failure voltage model V esd =G2(D,L).

[0249] For example, the gap breakdown voltage model relationship (15) can be substituted into the electrostatic discharge failure voltage basic model such as relationship (19), and the value of the corrected first parameter a2 is fitted to be 3, the value of the corrected second parameter b2 is 22.25, the value of the corrected third parameter c2 is 15.38, and the value of the corrected fourth parameter d2 is 0.4716.

[0250] Then, the modified electrostatic discharge failure voltage model V esd =G2(D, L) satisfies the relationship (20):

[0251]

[0252] The prediction results of the revised ESD failure voltage model are compared with the test results, as shown in Table 9. As can be seen from Table 9, for samples with L ≤ 10 μm, the revised ESD failure voltage model has strong applicability.

[0253] Table 9 V esd = Comparison of the prediction results of the G2(D, L) model and the test results of the verification sample

[0254]

[0255] The electrostatic discharge failure voltage model determined by the embodiment of the present disclosure can provide a theoretical basis for anti-static design, and can provide a theoretical basis for realizing quantitative anti-static design of special-shaped wiring, so that anti-static design no longer remains in the qualitative test stage, avoiding the modification of anti-static measures by blindly changing the design, and improving the efficiency of anti-static design.

[0256] Figure 21 The present disclosure also provides a device for determining the electrostatic discharge failure voltage model of a capacitor, such as Figure 21 As shown, including:

[0257] A first acquisition module 211 is configured to acquire electrostatic discharge test data of a first group of capacitors, the electrostatic discharge test data including the length of the capacitor plates facing each other, the gap between the capacitor plates, and the electrostatic discharge failure voltage of the capacitor;

[0258] A second acquisition module 212 is configured to acquire gap breakdown simulation data of the first group of capacitors, the gap breakdown simulation data including the length of the capacitor plates facing each other, the gap between the capacitor plates, and the gap breakdown voltage of the capacitor;

[0259] A first determining module 213 is configured to determine a gap breakdown voltage model based on the gap breakdown simulation data and the gap breakdown voltage basic model, wherein the gap breakdown voltage model is a relationship between the gap breakdown voltage of a capacitor, the length of the capacitor plates facing each other, and the gap between the capacitor plates;

[0260] The second determination module 214 is used to determine the electrostatic discharge failure voltage model based on the gap breakdown voltage model, the electrostatic discharge failure voltage basic model and the electrostatic discharge test data of the first group of capacitors, where the electrostatic discharge failure voltage model is a relationship between the electrostatic discharge failure voltage of the capacitor, the length of the capacitor's plates facing each other, and the gap between the capacitor's plates.

[0261] According to an embodiment of the present disclosure, the present disclosure also provides an electronic device, a readable storage medium, and a computer program product.

[0262] Various embodiments of the systems and techniques described herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), system-on-chip systems (SOCs), programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include being implemented in one or more computer programs that are executable and / or interpreted on a programmable system that includes at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0263] The program code for implementing the method of the present disclosure can be written in any combination of one or more programming languages. These program codes can be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device so that when the program code is executed by the processor or controller, the functions / operations specified in the flow chart and / or block diagram are implemented. The program code can be executed entirely on the machine, partially on the machine, as a stand-alone software package, partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0264] In the context of the present disclosure, a machine-readable medium can be a tangible medium that can contain or store a program for use by or in conjunction with an instruction execution system, device or equipment. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium can include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0265] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0266] The systems and techniques described herein can be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network (LAN), a wide area network (WAN), and the Internet.

[0267] A computer system may include a client and a server. The client and server are generally remote from each other and typically interact through a communication network. The client-server relationship arises through computer programs running on the respective computers and having a client-server relationship with each other. The server may be a cloud server, a server in a distributed system, or a server integrated with a blockchain.

[0268] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in this disclosure can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved. This is not a limitation herein.

[0269] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of such features. Throughout the present disclosure, "plurality" means two or more, unless otherwise specifically defined.

[0270] In this disclosure, unless otherwise expressly specified or limited, terms such as "mounted," "connected," "connect," and "fixed" should be understood broadly. For example, they may refer to fixed connections, detachable connections, or integration; mechanical connections, electrical connections, or communication; direct connections or indirect connections through an intermediate medium; and internal connections between two components or interactions between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure based on specific circumstances.

[0271] The disclosure above provides many different embodiments or examples for implementing different structures of the present disclosure. In order to simplify the present disclosure, the components and settings of specific examples are described above. Of course, these are merely examples and are not intended to limit the present disclosure. In addition, the present disclosure may repeat reference numbers and / or reference letters in different examples. Such repetition is for the purpose of simplicity and clarity and does not in itself indicate the relationship between the various embodiments and / or settings discussed.

[0272] The above specific embodiments do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure shall be included within the scope of protection of this disclosure.

Claims

1. A method for determining an electrostatic discharge failure voltage model of a capacitor, characterized in that: include: Obtaining electrostatic discharge test data of the first group of capacitors, the electrostatic discharge test data including the length of the plates facing each other of the capacitors, the gap between the plates of the capacitors, and the electrostatic discharge failure voltage of the capacitors; Acquire gap breakdown simulation data of the first group of capacitors, the gap breakdown simulation data including the length of the plates facing each other of the capacitors, the plate gap of the capacitors, and the gap breakdown voltage of the capacitors; Determining a gap breakdown voltage model based on the gap breakdown simulation data and the gap breakdown voltage basic model, wherein the gap breakdown voltage model is a relationship equation including the gap breakdown voltage of the capacitor, the plate facing length of the capacitor, and the plate gap of the capacitor; Determine an electrostatic discharge failure voltage model based on the gap breakdown voltage model, the electrostatic discharge failure voltage basic model, and the electrostatic discharge test data of the first group of capacitors, wherein the electrostatic discharge failure voltage model is a relationship equation including the electrostatic discharge failure voltage of the capacitor, the length of the capacitor plates facing each other, and the gap between the capacitor plates; Wherein, determining the gap breakdown voltage model according to the gap breakdown simulation data and the gap breakdown voltage basic model includes: determining the gap breakdown voltage basic model according to Paschen's law and dielectric layer defect density theory, wherein the gap breakdown voltage basic model is a relationship formula including the gap breakdown voltage of the capacitor, the plate facing length of the capacitor, the plate gap of the capacitor, a fifth parameter, a sixth parameter, and a seventh parameter; performing model fitting on the gap breakdown voltage basic model according to the gap breakdown simulation data, determining the fifth parameter, the sixth parameter, and the seventh parameter to determine the gap breakdown voltage model; The gap breakdown voltage basic model satisfies the following relationship: Wherein, V0 is the gap breakdown voltage of the capacitor, D is the plate gap of the capacitor, L is the plate facing length of the capacitor, k3, e, and α are the fifth parameter, the sixth parameter, and the seventh parameter, respectively.

2. The method according to claim 1, characterized in that The value range of the fifth parameter k3 is 68 to 71; and / or, The numerical range of the sixth parameter e is (-0.2) to (-0.4); and / or, The numerical range of the seventh parameter α is (-0.104) to (-0.107).

3. The method according to claim 1 or 2, characterized in that The electrostatic discharge failure voltage basic model satisfies the following relationship: Among them, V esd is the electrostatic discharge failure voltage of the capacitor, D is the plate gap of the capacitor, L is the plate facing length of the capacitor, V0 is the gap breakdown voltage of the capacitor, and a, b, c, and d are the first parameter, the second parameter, the third parameter, and the fourth parameter, respectively.

4. The method according to claim 3, characterized in that The numerical range of the first parameter a is 0.42 to 0.62; and / or, The value range of the second parameter b is 230 to 234; and / or, The value range of the third parameter c is 20 to 21; and / or, The value range of the fourth parameter d is 2-4.

5. The method according to claim 1 or 2, characterized in that Also includes: Obtain electrostatic discharge test data of the second group of capacitors; A revised electrostatic discharge failure voltage model is determined based on the gap breakdown voltage model, the electrostatic discharge failure voltage basic model, the electrostatic discharge test data of the first group of capacitors, and the electrostatic discharge test data of the second group of capacitors. The revised electrostatic discharge failure voltage model is a relationship equation including the electrostatic discharge failure voltage of the capacitor, the facing length of the capacitor's plates, and the plate gap of the capacitor.

6. The method according to claim 5, characterized in that In the electrostatic discharge test data of the second group of capacitors, the length of the plates of the capacitors is greater than or equal to 30 μm, and the gap between the plates of the capacitors is greater than or equal to 5 μm; The modified electrostatic discharge failure voltage model satisfies the following relationship: Among them, V esd is the electrostatic discharge failure voltage of the capacitor, D is the plate gap of the capacitor, L is the plate facing length of the capacitor, V0 is the gap breakdown voltage of the capacitor, the numerical range of the corrected first parameter a1 is 0.25~0.45, the numerical range of the corrected second parameter b1 is 252~256, the numerical range of the corrected third parameter c1 is 15~16.5, and the numerical range of the corrected fourth parameter d1 is 5~7.

5.

7. The method according to claim 5, characterized in that In the electrostatic discharge test data of the second group of capacitors, the length of the plates facing each other of the capacitors is less than or equal to 10 μm; The modified electrostatic discharge failure voltage model satisfies the following relationship: Among them, V esd is the electrostatic discharge failure voltage of the capacitor, D is the plate gap of the capacitor, L is the plate facing length of the capacitor, V0 is the gap breakdown voltage of the capacitor, the numerical range of the corrected first parameter a2 is 2.5 to 3.5, the numerical range of the corrected second parameter b2 is 21.5 to 23, the numerical range of the corrected third parameter c2 is 15 to 16, and the numerical range of the corrected fourth parameter d2 is 0.4 to 0.

55.

8. The method according to claim 1, characterized in that Obtaining gap breakdown simulation data of the first group of capacitors, including: Establish an electrostatic discharge simulator model, an external probe station equivalent circuit model, and a capacitance model; Connecting the electrostatic discharge simulator model, the external probe station equivalent circuit model and the capacitor model to establish a capacitor electrostatic discharge simulation model; The simulation parameters of the capacitor electrostatic discharge simulation model are set to obtain the gap breakdown simulation data of the first group of capacitors, the gap breakdown simulation data of the first group of capacitors including the facing length of the capacitor plates, the plate gap of the capacitor and the corresponding gap breakdown voltage of the capacitor.

9. The method according to claim 1, characterized in that The capacitor is a T-type flat plate capacitor.

10. A device for determining an electrostatic discharge failure voltage model of a capacitor, characterized in that: include: A first acquisition module is configured to acquire electrostatic discharge test data of a first group of capacitors, wherein the electrostatic discharge test data includes a length of opposite plates of the capacitors, a gap between the plates of the capacitors, and an electrostatic discharge failure voltage of the capacitors; a second acquisition module, configured to acquire gap breakdown simulation data of the first group of capacitors, the gap breakdown simulation data including the plate facing length of the capacitors, the plate gap of the capacitors, and the gap breakdown voltage of the capacitors; A first determining module is configured to determine a gap breakdown voltage model based on the gap breakdown simulation data and a gap breakdown voltage basic model, wherein the gap breakdown voltage model is a relationship equation including the gap breakdown voltage of the capacitor, the plate facing length of the capacitor, and the plate gap of the capacitor; a second determining module, configured to determine an electrostatic discharge failure voltage model based on the gap breakdown voltage model, the electrostatic discharge failure voltage basic model, and the electrostatic discharge test data of the first group of capacitors, wherein the electrostatic discharge failure voltage model is a relationship equation including the electrostatic discharge failure voltage of the capacitor, the plate facing length of the capacitor, and the plate gap of the capacitor; Wherein, the first determination module is further used to determine the gap breakdown voltage basic model according to Paschen's law and dielectric layer defect density theory, the gap breakdown voltage basic model is a relationship formula including the gap breakdown voltage of the capacitor, the plate facing length of the capacitor, the plate gap of the capacitor, a fifth parameter, a sixth parameter and a seventh parameter; according to the gap breakdown simulation data, the gap breakdown voltage basic model is fitted to determine the fifth parameter, the sixth parameter and the seventh parameter to determine the gap breakdown voltage model; The gap breakdown voltage basic model satisfies the following relationship: Wherein, V0 is the gap breakdown voltage of the capacitor, D is the plate gap of the capacitor, L is the plate facing length of the capacitor, k3, e, and α are the fifth parameter, the sixth parameter, and the seventh parameter, respectively.

11. An electronic device comprising: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 9.

12. A non-transitory computer-readable storage medium storing computer instructions, wherein: The computer instructions are used to cause the computer to execute the method according to any one of claims 1 to 9.

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