Computing method, device, chip, electronic device and storage medium

Abstract

The present disclosure provides a computing method, device, chip, electronic device and storage medium, which relate to the field of computer technology, in particular to the field of chip technology and artificial intelligence. The implementation scheme is: based on a plurality of first floating-point numbers of a first vector and a plurality of second floating-point numbers of a second vector input into the computing device, a plurality of first fixed-point numbers and a plurality of first exponents corresponding to the plurality of first floating-point numbers, and a plurality of second fixed-point numbers and a plurality of second exponents corresponding to the plurality of second floating-point numbers are obtained; a fixed-point product value and a corresponding fixed-point product exponent of each first fixed-point number in the plurality of first fixed-point numbers and a second fixed-point number corresponding thereto are obtained; based on the fixed-point product exponent corresponding to each fixed-point product value in the plurality of fixed-point product values, a fixed-point inner product calculation result of the first vector and the second vector is obtained; and based on the fixed-point inner product calculation result, a floating-point inner product calculation result in a floating-point data format corresponding to the fixed-point inner product calculation result is obtained.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, in particular to the field of chip technology and artificial intelligence, and specifically to a computing method, device, chip, electronic device, computer-readable storage medium and computer program product. Background Art

[0002] With the development of artificial intelligence technology, more and more applications based on artificial intelligence technology have achieved results far exceeding traditional algorithms; deep learning is the core technology of artificial intelligence technology. Deep learning is a data-intensive algorithm and a computationally intensive algorithm, and it is also an algorithm that develops rapidly.

[0003] Traditional general-purpose processing devices such as CPU, GPU, DSP, etc. are designed for general computing tasks. When processing deep learning applications, they have disadvantages such as low computing performance and low efficiency, and cannot effectively support the large-scale deployment of deep learning algorithms in scenarios such as data centers. ASIC / FPGA-based deep learning dedicated acceleration devices have deeply customized hardware structures based on the computing characteristics of deep learning, and can achieve higher computing performance and computing efficiency compared to traditional CPU, GPU, DSP and other devices.

[0004] The methods described in this section are not necessarily methods that have been previously conceived or employed. Unless otherwise indicated, it should not be assumed that any method described in this section is considered to be prior art simply because it is included in this section. Similarly, unless otherwise indicated, the issues mentioned in this section should not be considered to have been recognized in any prior art. Summary of the invention

[0005] The present disclosure provides a computing method, an apparatus, a chip, an electronic device, a computer-readable storage medium, and a computer program product.

[0006] According to one aspect of the present disclosure, a computing method performed by a computing device is provided, comprising: based on a plurality of first floating-point numbers of a first vector and a plurality of second floating-point numbers of a second vector input into the computing device, obtaining a plurality of first fixed-point numbers and a plurality of first exponents in binary representation corresponding to the plurality of first floating-point numbers, and a plurality of second fixed-point numbers and a plurality of second exponents in binary representation corresponding to the plurality of second floating-point numbers, wherein the plurality of first floating-point numbers correspond one-to-one to the plurality of second floating-point numbers, and each of the plurality of first fixed-point numbers and the plurality of second fixed-point numbers respectively includes a sign bit and a first preset number of fixed-point value bits; obtaining a fixed-point product value and a corresponding fixed-point product exponent of each first fixed-point number in the plurality of first fixed-point numbers and a second fixed-point number corresponding to the first fixed-point number; obtaining a fixed-point inner product calculation result of the first vector and the second vector based on a fixed-point product exponent corresponding to each of the plurality of fixed-point product values ​​corresponding to the plurality of first fixed-point numbers; and obtaining a floating-point inner product calculation result in a floating-point data format corresponding to the fixed-point inner product calculation result based on the fixed-point inner product calculation result.

[0007] According to another aspect of the present disclosure, a calculation method performed by a calculation device is provided, including: obtaining a first matrix and a second matrix, wherein the first matrix includes a first number of row vectors, the second matrix includes a second number of column vectors, and the row vectors and the column vectors have the same vector length; according to the calculation method performed by the above-mentioned calculation device for calculating the inner product of vectors, respectively obtaining the inner product results of each row vector in the first matrix and each column vector in the second matrix to obtain the inner product result matrix of the first matrix and the second matrix.

[0008] According to another aspect of the present disclosure, a computing device is provided, comprising: a first acquisition unit configured to acquire, based on a plurality of first floating-point numbers of a first vector and a plurality of second floating-point numbers of a second vector input into the computing device, a plurality of first fixed-point numbers and a plurality of first exponents in binary representation corresponding to the plurality of first floating-point numbers, and a plurality of second fixed-point numbers and a plurality of second exponents in binary representation corresponding to the plurality of second floating-point numbers, wherein the plurality of first floating-point numbers correspond one-to-one to the plurality of second floating-point numbers, and each of the plurality of first fixed-point numbers and the plurality of second fixed-point numbers respectively includes a sign bit and a first exponent; a preset number of fixed-point numerical bits; a multiplier configured to obtain a fixed-point product value and a corresponding fixed-point product exponent of each first fixed-point number among a plurality of first fixed-point numbers and a second fixed-point number corresponding to the first fixed-point number; a second obtaining unit configured to obtain a fixed-point inner product calculation result of the first vector and the second vector based on the fixed-point product exponent corresponding to each of the plurality of fixed-point product values ​​corresponding to the plurality of first fixed-point numbers; and a third obtaining unit configured to obtain a floating-point inner product calculation result in a floating-point data format corresponding to the fixed-point inner product calculation result based on the fixed-point inner product calculation result.

[0009] According to another aspect of the present disclosure, a computing device is provided, including: a fourth acquisition unit, configured to acquire a first matrix and a second matrix, wherein the first matrix includes a first number of row vectors, the second matrix includes a second number of column vectors, and the row vectors and the column vectors have the same vector length; a fifth acquisition unit, configured to acquire the inner product results of each row vector in the first matrix and each column vector in the second matrix respectively according to the computing method performed by the above-mentioned computing device for calculating the inner product of vectors, so as to acquire the inner product result matrix of the first matrix and the second matrix.

[0010] According to another aspect of the present disclosure, a chip is provided, comprising at least one of the following devices: the above-mentioned computing device for calculating vector inner products, and the above-mentioned computing device for calculating matrix inner products.

[0011] According to another aspect of the present disclosure, an electronic device is provided, comprising the above chip.

[0012] According to another aspect of the present disclosure, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can perform the above-mentioned operation method for calculating the inner product of the vector or the above-mentioned operation method for calculating the inner product of the matrix.

[0013] According to another aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided, wherein the computer instructions are used to enable a computer to execute the above-mentioned operation method for calculating vector inner products or the above-mentioned operation method for calculating matrix inner products.

[0014] According to another aspect of the present disclosure, a computer program product is provided, including a computer program, wherein the computer program implements the above-mentioned operation method for calculating vector inner products or the above-mentioned operation method for calculating matrix inner products when executed by a processor.

[0015] According to one or more embodiments of the present disclosure, floating-point data input into a computing device can be converted into fixed-point data through calculations within the computing device, and related calculations can be completed based on the fixed-point data, thereby realizing a seamless operation of converting floating-point data into fixed-point data, saving labor costs and computing resources.

[0016] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings exemplarily illustrate the embodiments and constitute a part of the specification, and together with the text description of the specification, are used to explain the exemplary implementation of the embodiments. The embodiments shown are for illustrative purposes only and do not limit the scope of the claims. In all drawings, the same reference numerals refer to similar but not necessarily identical elements.

[0018] Figure 1 A flowchart showing a computing method performed by a computing device according to an embodiment of the present disclosure is shown;

[0019] Figure 2 A structural block diagram of a vector multiplication device according to an embodiment of the present disclosure is shown;

[0020] Figure 3 A flowchart of obtaining a plurality of first fixed-point numbers and a plurality of first-order codes and a plurality of second fixed-point numbers and a plurality of second-order codes according to an embodiment of the present disclosure is shown;

[0021] Figure 4 A flowchart of obtaining fixed-point product values ​​corresponding to a plurality of first fixed-point numbers and corresponding fixed-point product orders according to an embodiment of the present disclosure is shown;

[0022] Figure 5 A structural block diagram of a vector multiplication device according to another embodiment of the present disclosure is shown;

[0023] Figure 6 A flow chart showing a calculation method performed by a calculation device for calculating matrix multiplication according to an embodiment of the present disclosure is shown;

[0024] Figure 7 A structural block diagram of a matrix multiplication device according to an embodiment of the present disclosure is shown;

[0025] Figure 8 A structural block diagram of a computing device for calculating vector inner products according to an embodiment of the present disclosure is shown;

[0026] Fig. 9 A structural block diagram of a computing device for calculating matrix multiplication according to an embodiment of the present disclosure is shown;

[0027] Fig.10 A structural block diagram of an exemplary electronic device that can be used to implement the embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0028] The following is a description of exemplary embodiments of the present disclosure in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding, which should be considered as merely exemplary. Therefore, it should be recognized by those of ordinary skill in the art that various changes and modifications may be made to the embodiments described herein without departing from the scope of the present disclosure. Similarly, for the sake of clarity and conciseness, the description of well-known functions and structures is omitted in the following description.

[0029] In the present disclosure, unless otherwise specified, the use of the terms "first", "second", etc. to describe various elements is not intended to limit the positional relationship, temporal relationship, or importance relationship of these elements, and such terms are only used to distinguish one element from another element. In some examples, the first element and the second element may refer to the same instance of the element, and in some cases, based on the description of the context, they may also refer to different instances.

[0030] The terms used in the description of various examples in this disclosure are only for the purpose of describing specific examples and are not intended to be limiting. Unless the context clearly indicates otherwise, if the number of elements is not specifically limited, the element can be one or more. In addition, the term "and / or" used in this disclosure covers any one of the listed items and all possible combinations.

[0031] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0032] The core operation of deep learning algorithms is matrix multiplication. Mainstream language models (such as BERT, ERNIE, etc.) contain a large number of matrix multiplications. Mainstream machine vision models (such as RESNET, MASK-RCNN, YOLO, SSD, etc.) contain a large number of convolution operations, and convolution operations are usually converted into matrix operations.

[0033] Deep learning networks all perform matrix multiplication operations based on single-precision floating-point format (also known as float format) data. With the development of deep learning, relevant technicians have found that for matrix multiplication and convolution operations, using fixed-point precision such as signed 16-bit fixed-point data can significantly reduce the area and power consumption of hardware implementation, achieve better performance / power consumption ratio and performance / area ratio, while ensuring no significant loss of accuracy.

[0034] In the related art, the matrix multiplication operation in the deep learning network can be completed by the matrix multiplication device in the deep learning chip. The matrix multiplication device supports fixed-point operation, but it requires relevant technicians to use an independent device to first convert the floating-point precision data into fixed-point data through fixed-point conversion, and then input the fixed-point data into the matrix multiplication device for operation.

[0035] The embodiments of the present disclosure provide a computing method executed by a computing device, which can convert floating-point data input into the computing device into fixed-point data through calculations inside the computing device, and then perform vector multiplication or matrix multiplication operations based on the fixed-point data, thereby realizing a seamless operation of converting floating-point data into fixed-point data, saving labor costs and computing resources.

[0036] According to the embodiments of the present disclosure, Figure 1 As shown, a computing method performed by a computing device is provided, which may include: step S101, based on a plurality of first floating-point numbers of a first vector and a plurality of second floating-point numbers of a second vector input into the computing device, obtaining a plurality of first fixed-point numbers and a plurality of first orders of magnitude corresponding to the plurality of first floating-point numbers in binary representation, and a plurality of second fixed-point numbers and a plurality of second orders of magnitude corresponding to the plurality of second floating-point numbers in binary representation, wherein the plurality of first floating-point numbers correspond to the plurality of second floating-point numbers in one-to-one correspondence, and each of the plurality of first fixed-point numbers and the plurality of second fixed-point numbers respectively includes a sign bit And a first preset number of fixed-point numerical bits; step S102, obtaining a fixed-point product value and a corresponding fixed-point product exponent of each first fixed-point number in a plurality of first fixed-point numbers and a second fixed-point number corresponding to the first fixed-point number; step S103, based on the fixed-point product exponent corresponding to each fixed-point product value in a plurality of fixed-point product values ​​corresponding to the plurality of first fixed-point numbers, obtaining a fixed-point inner product calculation result of the first vector and the second vector; and step S104, based on the fixed-point inner product calculation result, obtaining a floating-point inner product calculation result in a floating-point data format corresponding to the fixed-point inner product calculation result.

[0037] Thus, the floating-point data input into the computing device can be converted into fixed-point data through calculations inside the computing device, and related calculations can be completed based on the fixed-point data, thereby realizing the seamless operation of converting floating-point data into fixed-point data and saving labor costs and computing resources.

[0038] Figure 2 A structural block diagram of a vector multiplication device according to an embodiment of the present disclosure is shown.

[0039] In some embodiments, Figure 2 The vector multiplication device 200 shown may be an operation device arranged on a chip, and the above operation method may be implemented by the vector multiplication device 200. Specifically, the vector multiplication device 200 includes a data extraction module 210, a fixed-point multiplication module 220, an order comparison module 230, a shift module 240, an adder 250, and a defixed-point module 260.

[0040] According to the IEEE 754 standard, a single-precision floating-point data is represented as {S, E, M}, which includes a 1-bit sign bit S, an 8-bit exponent bit E, and a 23-bit floating-point value bit M. The actual value N of the floating-point data can be calculated using the following formula:

[0041] N=(-1) S ×1.M×2 (E-127)

[0042] In some embodiments, the first vector A{a[0], a[1], ..., a[k-1]} and the second vector B{b[0], b[1], ..., b[k-1]} are firstly inputted in parallel into the data extraction module 210 in the vector multiplication device 200, where k is a positive integer greater than 2. Each first floating point number a[i] in the first vector A and each second floating point number b[i] in the second vector B are single-precision floating point data (where i∈[0, k-1]), and their storage formats are as described above.

[0043] In some embodiments, each first floating point number a[k-1] and each second floating point number b[k-1] may first be processed by the data extraction module 210 to convert them into a first fixed point number and a second fixed point number, respectively.

[0044] In some embodiments, Figure 3 As shown, obtaining a plurality of first fixed-point numbers and a plurality of first exponents in binary representation corresponding to a plurality of first floating-point numbers, and a plurality of second fixed-point numbers and a plurality of second exponents in binary representation corresponding to a plurality of second floating-point numbers includes: for each of the plurality of first floating-point numbers and the plurality of second floating-point numbers, performing the following operations: step S301, extracting a sign bit, an exponent bit, and a floating-point value bit in the floating-point number, wherein the floating-point number is represented by binary; step S302, extracting a second preset number of high-order value bits of the highest bit in the floating-point value bits; step S303, determining a fixed-point number corresponding to the floating-point number based on the high-order value bit and the sign bit of the floating-point number; and step S304, determining an exponent corresponding to the floating-point number based on the exponent bit of the floating-point number.

[0045] Therefore, the input floating-point number can be converted into a fixed-point number through the computing device disclosed in the present invention, thereby realizing the seamless conversion of floating-point data into fixed-point data and improving the user experience; at the same time, no additional resources are required for data fixed-point processing, thus saving computing resources.

[0046] First, the sign bit, exponent bit and floating-point value bit in each first floating-point number a[i] and each second floating-point number b[i] are extracted in parallel by the data extraction unit 210, wherein the sign bit is denoted as a[i]

[31] and b[i]

[31] , the exponent bit is denoted as a[i][30:23] and b[i][30:23], and the floating-point value bit is denoted as a[i][22:0] and b[i][22:0].

[0047] Then, a second preset number of high-order numerical bits of the most significant bits are extracted from the floating-point numerical bits.

[0048] In some embodiments, the first fixed-point number and the second fixed-point number to be converted can be 16-bit fixed-point data, and accordingly, the second preset number can be 14 bits, that is, the highest 14 bits of data are extracted from a[i][22:0] and b[i][22:0] respectively, and the obtained high-dimensional numerical bits are a[i][22:9] and b[i][22:9] respectively.

[0049] In some embodiments, the fixed-point number corresponding to each floating-point number can be obtained based on the high-dimensional value bit and the sign bit based on the following formula:

[0050] a.us[i]={1′b0,1′b1,a[i][22:9]},i∈[0,k-1]

[0051] b.us[i]={1′b0,1′b1,b[i][22:9]},i∈[0,k-1]

[0052] Wherein, a.us[i] and b.us[i] represent the first fixed-point number and the second fixed-point number corresponding to the first floating-point number a[i] and the second floating-point number b[i] respectively, and wherein 1′b0 of the two bits of data added before a[i][22:9] and b[i][22:9] is the sign bit, and 1′b1 is used to fill in the integer before the decimal point that is omitted when the floating-point data is stored.

[0053] The first-order code ae[i] and the second-order code be[i] corresponding to the first fixed-point number a.us[i] and the second fixed-point number b.us[i] respectively can be obtained based on the following formula:

[0054] ae[i]=a[i][30:23],i∈[0,k-1]

[0055] be[i]=b[i][30:23],i∈[0,k-1]

[0056] In some embodiments, Figure 4As shown, obtaining the fixed-point product value and the corresponding fixed-point product exponent of each first fixed-point number among a plurality of first fixed-point numbers and a second fixed-point number corresponding to the first fixed-point number may include: step S401, obtaining a plurality of first complement codes corresponding to the plurality of first fixed-point numbers and a plurality of second complement codes corresponding to the plurality of second fixed-point numbers; step S402, calculating the product of each first complement code among the plurality of first complement codes and the second complement code corresponding to the first complement code, to obtain the fixed-point product value; and step S403, calculating the sum of the first exponent code corresponding to each first fixed-point number among the plurality of first fixed-point numbers and the second exponent code corresponding to the second fixed-point number corresponding to the first fixed-point number, to obtain the fixed-point product exponent.

[0057] Therefore, by converting the fixed-point number into a two's complement code and performing subsequent operations, the sign bit can also be involved in the operation, thereby eliminating the need to calculate the sign bit separately, saving computing resources.

[0058] In some embodiments, the first complement as[i] and the second complement bs[i] corresponding to the first fixed-point number a.us[i] and the second fixed-point number b.us[i] can be obtained by the following formulas based on the sign bits a[i]

[31] and b[i]

[31] corresponding to the first floating-point number a[i] and the second floating-point number b[i], respectively:

[0059]

[0060]

[0061] Thus, for each first floating point number a[i] in the first vector A and each second floating point number b[i] in the second vector B, each first fixed point number a.us[i] and its complement as[i] and each second fixed point number b.us[i] and its complement bs[i] are obtained through the data extraction module 210, and the given point multiplication module 220 is transmitted through the data extraction module 210. At the same time, the data extraction module can transmit each first order code ae[i] and each second order code be[i] to the order code comparison module 230.

[0062] In some embodiments, the fixed-point multiplication module 220 may include k groups of 16-bit fixed-point data fixed-point multiplication sub-modules, and the input data of the fixed-point multiplication module 220 may be each first fixed-point number a.us[i] and each second fixed-point number b.us[i], and by multiplying the corresponding first fixed-point number and the second fixed-point number, a corresponding fixed-point product value is obtained, and the sign of the fixed-point product value needs to be judged by the sign bits of the first floating-point number and the second floating-point number corresponding to the first fixed-point number and the second fixed-point number.

[0063] In some embodiments, the fixed-point multiplication module 220 may include k groups of 16-bit fixed-point data fixed-point multiplication submodules, and the input data of the fixed-point multiplication module 220 may also be the first complement as[i] corresponding to each first fixed-point number and the second complement bs[i] corresponding to each second fixed-point number. And for each pair of corresponding first complement as[i] and second complement bs[i], respectively, multiply them to obtain a fixed-point product value m[i]. The specific formula is as follows:

[0064] m[i]=as[i]*bs[i],i∈[0,k-1]

[0065] The number of bits of each fixed-point product value m[i] is 32 bits.

[0066] At the same time, correspondingly, the fixed-point product order ab.e[i] corresponding to each fixed-point product value m[i] can be obtained through the order comparison module 230. The specific formula is as follows:

[0067] ab.e[i]=ae[i]+be[i],i∈[0,k-1]

[0068] Since the exponents corresponding to each fixed-point product value are different, each fixed-point product value needs to be unified into the same numerical range before summing each fixed-point product value. For example, if the numerical bits of two fixed-point product values ​​are both 1001, but the numerical values ​​corresponding to their exponents are 2 and -2, respectively, then their actual values ​​are 100.1 and 0.01001 respectively (that is, the two fixed-point product values ​​are shifted and aligned based on the exponent 0, so that the two fixed-point product values ​​are unified into the same numerical range), and then the summation calculation result is correct.

[0069] In the related art, usually before inputting data, the maximum value in each vector is first obtained, and the numerical range of each data in the vector is unified based on the maximum value. This method will cause the data to lose a large amount of precision again after being converted into fixed-point data.

[0070] In some embodiments, obtaining a fixed-point inner product calculation result of a first vector and a second vector based on a fixed-point product exponent corresponding to each of a plurality of fixed-point product values ​​corresponding to a plurality of first fixed-point numbers includes: performing an arithmetic shift on the fixed-point product value based on a fixed-point product exponent corresponding to each of a plurality of fixed-point product values ​​corresponding to a plurality of first fixed-point numbers; and summing a plurality of arithmetically shifted fixed-point product values ​​corresponding to the plurality of first fixed-point numbers to obtain a fixed-point inner product calculation result of the first vector and the second vector.

[0071] Therefore, by shifting each fixed-point product value to unify the numerical range of each fixed-point product value after obtaining each fixed-point product value and before calculating the fixed-point inner product calculation result, compared with the method in the related art, the loss of data precision can be reduced and the accuracy of the calculation can be improved.

[0072] In some embodiments, each fixed-point product value and each fixed-point product exponent can be input into the shift module 240 accordingly, so that each fixed-point product value can be arithmetically shifted based on the corresponding fixed-point product exponent, thereby aligning each fixed-point product value to the same numerical range; then, the fixed-point product values ​​after alignment are input into the adder 250, so as to obtain the fixed-point inner product calculation result of the first vector and the second vector.

[0073] In some embodiments, performing an arithmetic shift on the fixed-point product value based on a fixed-point product exponent corresponding to each of a plurality of fixed-point product values ​​corresponding to a plurality of first fixed-point numbers respectively includes: determining a first fixed-point product exponent among a plurality of fixed-point product exponents corresponding to the plurality of first fixed-point numbers; obtaining an arithmetic shift value corresponding to each of a plurality of fixed-point product values ​​based on each fixed-point product exponent in the plurality of fixed-point product exponents and the first fixed-point product exponent; and performing an arithmetic shift on the fixed-point product value based on the arithmetic shift value corresponding to each of the plurality of fixed-point product values.

[0074] In some embodiments, a first fixed-point product order can be determined from all fixed-point product orders as a reference for arithmetic shift, and the shift distance corresponding to each fixed-point product value can be determined by calculating the difference between other fixed-point product orders and the first fixed-point product order. In this way, the operation can be further simplified, the operation efficiency can be improved, and the computing resources can be saved.

[0075] In some embodiments, determining a first fixed-point product exponent among a plurality of fixed-point product exponents corresponding to a plurality of first fixed-point numbers includes: obtaining a fixed-point product exponent with the largest value among a plurality of fixed-point product exponents corresponding to the plurality of first fixed-point numbers as the first fixed-point product exponent; and wherein, based on each fixed-point product exponent in the plurality of fixed-point product exponents and the first fixed-point product exponent, obtaining an arithmetic shift value corresponding to each fixed-point product value in the plurality of fixed-point product values ​​includes: calculating a difference between the first fixed-point product exponent and each fixed-point product exponent in the plurality of fixed-point product exponents as the corresponding arithmetic shift value of the fixed-point product value corresponding to the fixed-point product exponent.

[0076] Therefore, by determining the first fixed-point product order, which is the reference order, as the maximum order among all orders, it is possible to avoid the data with a larger actual value from losing much precision, thereby ensuring the accuracy of the calculation.

[0077] In some embodiments, the maximum order of all fixed-point product orders ab.e[i] can be obtained by the order comparison module 230 to serve as the first fixed-point product order ab.e.max. The specific formula is as follows:

[0078] ab.e.max=max(ab.e[i])

[0079] Then, each arithmetic shift value sft[i] is obtained by calculating the difference between the first fixed-point product order ab.e.max and each fixed-point product order ab.e[i]. The specific formula is as follows:

[0080] sft[i]=ab.e.max-ab.e[i],i∈[0,k-1]

[0081] Each arithmetic shift value sft[i] output by the order comparison module 230 and each fixed-point multiplication value m[i] output by the fixed-point multiplication module output 220 are input into the shift module 240, and the shift module 240 performs arithmetic right shift processing on each fixed-point multiplication value m[i] based on its corresponding arithmetic shift value sft[i] to obtain the corresponding fixed-point product value ms[i] after arithmetic shift. The specific formula is as follows:

[0082] ms[i]=m[i]>>>sft[i],i∈[0,k-1]

[0083] In some embodiments, each arithmetic shifted fixed-point product value ms[i] output by the shift module 240 may be input into the adder 250, and the arithmetic shifted fixed-point product values ​​may be summed based on the adder 250 to obtain a fixed-point inner product calculation result si of the first vector A and the second vector B. The specific formula is as follows:

[0084] si=sum(ms[i]),i∈[0,k-1]

[0085] The fixed-point inner product calculation result si is a signed fixed-point data with a bit number of (32+j) bits, and j is determined by the following formula:

[0086] j = ceiling(log2k)

[0087] Wherein, ceiling(x) is a function for rounding up data. Thus, by setting more digits for the fixed-point inner product calculation result si, data overflow in the summation process is prevented.

[0088] In some embodiments, based on the fixed-point inner product calculation result, obtaining the floating-point inner product calculation result in a floating-point data format corresponding to the fixed-point inner product calculation result may be processed by the defixed-point module 260 .

[0089] The adder 250 transmits the fixed-point inner product calculation result si to the de-fixed-point conversion module 260 , and the de-fixed-point conversion module 260 first converts the fixed-point inner product calculation result si into equivalent floating-point format data sf.

[0090] At the same time, the order comparison device 230 transmits the first fixed-point product order ab.e.max to the de-fixed-point module 260, and the de-fixed-point module 260 converts the first fixed-point product order ab.e.max into the order data df in floating-point format. The specific formula is as follows:

[0091] df

[31] =1′b0

[0092] df[30:23] = ab.e.max-282

[0093] df[22:0]=23′b0

[0094] Then, the product of sf and df is calculated by the floating-point multiplier in the defixed-point module 260, so as to obtain the floating-point inner product calculation result res of the first vector and the second vector in the floating-point data format. The specific formula is as follows:

[0095] res = df * sf

[0096] In some embodiments, the computing device is capable of calculating the inner product of two vectors of a first predetermined length within one computing cycle. For a third vector and a fourth vector having the same vector length and both greater than the first predetermined length, the method further includes: based on the first predetermined length, dividing the third vector and the fourth vector into a plurality of first vectors and a plurality of second vectors, respectively, wherein the plurality of first vectors and the plurality of second vectors correspond one to one; respectively calculating floating-point inner product calculation results of multiple groups of corresponding first vectors and second vectors; and calculating the sum of the floating-point inner product calculation results of multiple groups of corresponding first vectors and second vectors to obtain the inner product calculation result of the third vector and the fourth vector.

[0097] Therefore, by splitting the input vector and inputting them into the computing device respectively in different computing cycles, and accumulating the results obtained in each computing cycle, it is possible to implement the inner product calculation of a larger-scale vector.

[0098] Figure 5 A structural block diagram of a vector multiplication device according to another embodiment of the present disclosure is shown.

[0099] In some embodiments, Figure 5The vector multiplication device 500 shown may be an operation device arranged on a chip, and the above operation method may be implemented by the vector multiplication device 500. Specifically, the vector multiplication device 500 includes a data extraction module 510, a fixed-point multiplication module 520, an order comparison module 530, a shift module 540, an adder 550, a defixed-point module 560, and an accumulation module 570.

[0100] The operations of modules 510 to 560 in the vector multiplication device 500 are similar to the operations of modules 210 to 260 in the above-mentioned vector multiplication device 200, and are not described in detail here.

[0101] In some embodiments, the data extraction module 510 may sequentially extract the first vector and the second vector of the first predetermined length from the third vector and the fourth vector input into the vector multiplication device 500 in each operation cycle, and obtain the floating-point inner product calculation result of the first vector and the second vector in the operation cycle, and store it in the accumulation module 570. After each floating-point inner product calculation result is obtained, the sum of all floating-point inner product calculation results is calculated by the accumulation module 570, so as to obtain the inner product calculation result of the third vector and the fourth vector in floating-point format.

[0102] In some embodiments, a method for performing a calculation on a computing device for calculating matrix multiplication is also provided, such as Figure 6 As shown, it includes: step S601, obtaining a first matrix and a second matrix, wherein the first matrix includes a first number of row vectors, the second matrix includes a second number of column vectors, and the row vectors and the column vectors have the same vector length; step S602, according to the above-mentioned operation method for calculating the inner product of the vectors, respectively obtaining the inner product results of each row vector in the first matrix and each column vector in the second matrix to obtain the inner product result matrix of the first matrix and the second matrix.

[0103] Figure 7 A structural block diagram of a matrix multiplication device according to an embodiment of the present disclosure is shown.

[0104] In some embodiments, Figure 7 The matrix multiplication device shown may be an operation device arranged on a chip, and the above operation method for calculating matrix multiplication may be implemented by the matrix multiplication device.

[0105] The first matrix includes m row vectors A(0), A(1), ..., A(m-1), and the second matrix includes n column vectors B(0), B(1), ..., B(n-1). Figure 7 The matrix multiplication device shown includes m×n vector multiplication devices, each of which can be Figure 2 Vector multiplication device 200 or Figure 5 The vector multiplication device 500 is shown, and each vector multiplication device can calculate the vector inner product of the row vector A and the column vector B by the above-mentioned method of calculating the vector inner product. Then, by obtaining the calculation result of each vector multiplication device, the inner product result matrix of the first matrix and the second matrix can be obtained.

[0106] In some embodiments, Figure 8 As shown, a computing device 800 is provided, which may include: a first acquisition unit 810, configured to acquire a plurality of first fixed-point numbers and a plurality of first exponents in binary representation corresponding to the plurality of first floating-point numbers, and a plurality of second fixed-point numbers and a plurality of second exponents in binary representation corresponding to the plurality of second floating-point numbers, based on a plurality of first floating-point numbers of a first vector and a plurality of second floating-point numbers input into the computing device, wherein the plurality of first floating-point numbers correspond to the plurality of second floating-point numbers in one-to-one correspondence, and each of the plurality of first fixed-point numbers and the plurality of second fixed-point numbers respectively includes a sign bit and a first preset number fixed-point numerical bits; a multiplier 820, configured to obtain a fixed-point product value and a corresponding fixed-point product exponent of each first fixed-point number in a plurality of first fixed-point numbers and a second fixed-point number corresponding to the first fixed-point number; a second obtaining unit 830, configured to obtain a fixed-point inner product calculation result of the first vector and the second vector based on a fixed-point product exponent corresponding to each of a plurality of fixed-point product values ​​corresponding to the plurality of first fixed-point numbers; and a third obtaining unit 840, configured to obtain a floating-point inner product calculation result in a floating-point data format corresponding to the fixed-point inner product calculation result based on the fixed-point inner product calculation result.

[0107] The operations of the units 810 to 840 in the computing device 800 are similar to the operations of steps S101 to S104 in the computing method executed by the computing device, and are not described in detail herein.

[0108] In some embodiments, the second acquisition unit may include: a shifter, configured to perform arithmetically shift the fixed-point product value based on a fixed-point product exponent corresponding to each of the multiple fixed-point product values ​​corresponding to the multiple first fixed-point numbers; and an adder, configured to sum the multiple fixed-point product values ​​corresponding to the multiple first fixed-point numbers after arithmetically shifting, so as to obtain a fixed-point inner product calculation result of the first vector and the second vector.

[0109] In some embodiments, the shifter may include: a determination module, configured to determine a first fixed-point product exponent among a plurality of fixed-point product exponents corresponding to a plurality of first fixed-point numbers; an acquisition module, configured to acquire an arithmetic shift value corresponding to each of a plurality of fixed-point product values ​​based on each of the plurality of fixed-point product exponents and the first fixed-point product exponent; and a shift module, configured to perform an arithmetic shift on the fixed-point product value based on the arithmetic shift value corresponding to each of the plurality of fixed-point product values.

[0110] In some embodiments, the determination module can be configured to: obtain the fixed-point product exponent with the largest value among multiple fixed-point product exponents corresponding to multiple first fixed-point numbers as the first fixed-point product exponent; and wherein the acquisition module can be configured to: calculate the difference between the first fixed-point product exponent and each fixed-point product exponent in the multiple fixed-point product exponents as the corresponding arithmetic shift value of the fixed-point product value corresponding to the fixed-point product exponent.

[0111] In some embodiments, the first acquisition unit can be configured to perform the operations of the following subunits on each floating-point number of a plurality of first floating-point numbers and a plurality of second floating-point numbers: a first extraction subunit is configured to extract a sign bit, an exponent bit, and a floating-point value bit in the floating-point number, wherein the floating-point number is represented in binary; a second extraction subunit is configured to extract a second preset number of high-order value bits of the highest bit in the floating-point value bits; a first determination subunit is configured to determine a fixed-point number corresponding to the floating-point number based on the high-order value bits; and a second determination subunit is configured to determine the exponent corresponding to the floating-point number based on the exponent bit of the floating-point number.

[0112] In some embodiments, the multiplier may include: an acquisition subunit, configured to acquire a plurality of first complements corresponding to the plurality of first fixed-point numbers and a plurality of second complements corresponding to the plurality of second fixed-point numbers based on the sign bits of the plurality of first floating-point numbers respectively corresponding to the plurality of first fixed-point numbers and the sign bits of the plurality of second floating-point numbers respectively corresponding to the plurality of second fixed-point numbers; a first calculation subunit, configured to calculate the product of each first complement in the plurality of first complements and the second complement corresponding to the first complement to obtain a fixed-point product value; and a second calculation subunit, configured to calculate the sum of the first exponent corresponding to each first fixed-point number in the plurality of first fixed-point numbers and the second exponent corresponding to the second fixed-point number corresponding to the first fixed-point number to obtain a fixed-point product exponent.

[0113] In some embodiments, the above-mentioned computing device is capable of calculating the inner product of two vectors of a first predetermined length within one computing cycle. For a third vector and a fourth vector having the same vector length and both greater than the first predetermined length, the above-mentioned computing device may further include: a division unit, configured to divide the third vector and the fourth vector into a plurality of first vectors and a plurality of second vectors, respectively, based on the first predetermined length, wherein the plurality of first vectors and the plurality of second vectors correspond one to one; a first calculation unit, configured to respectively calculate floating-point inner product calculation results of multiple groups of corresponding first vectors and second vectors; and a second calculation unit, configured to calculate the sum of floating-point inner product calculation results of multiple groups of corresponding first vectors and second vectors to obtain the inner product calculation result of the third vector and the fourth vector.

[0114] In some embodiments, Fig. 9 As shown, a computing device 900 is also provided, including: a fourth acquisition unit 910, configured to acquire a first matrix and a second matrix, wherein the first matrix includes a first number of row vectors, the second matrix includes a second number of column vectors, and the row vectors and the column vectors have the same vector length; a fifth acquisition unit 920, configured to acquire the inner product results of each row vector in the first matrix and each column vector in the second matrix respectively according to the computing method performed by the above-mentioned computing device for calculating the inner product of the vector, so as to acquire the inner product result matrix of the first matrix and the second matrix.

[0115] The operations of the units 910 to 920 in the computing device 900 are similar to the operations of steps S601 to S602 in the computing method performed by the computing device for computing matrix multiplication, and are not described in detail here.

[0116] In some embodiments, a chip is provided, comprising at least one of the following devices: the above-mentioned computing device for calculating vector inner products, and the above-mentioned computing device for calculating matrix inner products.

[0117] In some embodiments, an electronic device is provided, comprising the above-mentioned chip.

[0118] In some embodiments, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the above-mentioned operation method for calculating the inner product of the vector or the above-mentioned operation method for calculating the inner product of the matrix.

[0119] In some embodiments, a non-transitory computer-readable storage medium storing computer instructions is provided, wherein the computer instructions are used to enable a computer to execute the above-mentioned operation method for calculating the inner product of a vector or the above-mentioned operation method for calculating the inner product of a matrix.

[0120] In some embodiments, a computer program product is provided, including a computer program, wherein the computer program implements the above-mentioned operation method for calculating vector inner products or the above-mentioned operation method for calculating matrix inner products when executed by a processor.

[0121] According to an embodiment of the present disclosure, an electronic device, a readable storage medium and a computer program product are also provided.

[0122] refer to Fig.10 , a block diagram of an electronic device 1000 that can be used as a server or client of the present disclosure will now be described, which is an example of a hardware device that can be applied to various aspects of the present disclosure. The electronic device is intended to represent various forms of digital electronic computer devices, such as laptop computers, desktop computers, workbenches, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present disclosure described and / or required herein.

[0123] like Fig.10 As shown, the electronic device 1000 includes a computing unit 1001, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 1002 or a computer program loaded from a storage unit 1008 into a random access memory (RAM) 1003. In the RAM 1003, various programs and data required for the operation of the electronic device 1000 can also be stored. The computing unit 1001, the ROM 1002, and the RAM 1003 are connected to each other via a bus 1004. An input / output (I / O) interface 1005 is also connected to the bus 1004.

[0124] Multiple components in the electronic device 1000 are connected to the I / O interface 1005, including: an input unit 1006, an output unit 1007, a storage unit 1008, and a communication unit 1009. The input unit 1006 can be any type of device that can input information to the electronic device 1000. The input unit 1006 can receive input digital or character information, and generate key signal input related to user settings and / or function control of the electronic device, and can include but is not limited to a mouse, a keyboard, a touch screen, a track pad, a track ball, a joystick, a microphone, and / or a remote controller. The output unit 1007 can be any type of device that can present information, and can include but is not limited to a display, a speaker, a video / audio output terminal, a vibrator, and / or a printer. The storage unit 1008 can include but is not limited to a disk and an optical disk. The communication unit 1009 allows the electronic device 1000 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks, and may include but is not limited to a modem, a network card, an infrared communication device, a wireless communication transceiver and / or a chipset, such as a Bluetooth™ device, an 802.11 device, a WiFi device, a WiMax device, a cellular communication device and / or the like.

[0125] The computing unit 1001 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the computing unit 1001 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The computing unit 1001 performs the various methods and processes described above, such as the above-mentioned operation method for calculating the inner product of the vector or the above-mentioned operation method for calculating the inner product of the matrix. For example, in some embodiments, the above-mentioned operation method for calculating the inner product of the vector or the above-mentioned operation method for calculating the inner product of the matrix may be implemented as a computer software program, which is tangibly contained in a machine-readable medium, such as a storage unit 1008. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 1000 via the ROM 1002 and / or the communication unit 1009. When the computer program is loaded into RAM 1003 and executed by computing unit 1001, one or more steps of the above-described method for calculating vector inner products or the above-described method for calculating matrix inner products may be performed. Alternatively, in other embodiments, computing unit 1001 may be configured to perform the above-described method for calculating vector inner products or the above-described method for calculating matrix inner products in any other appropriate manner (e.g., by means of firmware).

[0126] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0127] The program code for implementing the method of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that the program code, when executed by the processor or controller, enables the functions / operations specified in the flow chart and / or block diagram to be implemented. The program code may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0128] In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0129] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0130] The systems and techniques described herein may be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), and the Internet.

[0131] A computer system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The relationship of client and server is generated by computer programs running on respective computers and having a client-server relationship with each other. The server may be a cloud server, a server of a distributed system, or a server combined with a blockchain.

[0132] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in this disclosure can be performed in parallel, sequentially or in different orders, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved, and this document does not limit this.

[0133] Although the embodiments or examples of the present disclosure have been described with reference to the accompanying drawings, it should be understood that the above-mentioned methods, systems and devices are merely exemplary embodiments or examples, and the scope of the present invention is not limited by these embodiments or examples, but only by the claims after authorization and their equivalent scope. Various elements in the embodiments or examples can be omitted or replaced by their equivalent elements. In addition, each step can be performed in an order different from that described in the present disclosure. Further, the various elements in the embodiments or examples can be combined in various ways. It is important that with the evolution of technology, many elements described herein can be replaced by equivalent elements that appear after the present disclosure.

Claims

1. A computing method performed by a computing device, the method comprising: Based on a plurality of first floating-point numbers of a first vector and a plurality of second floating-point numbers of a second vector input into the computing device, a plurality of first fixed-point numbers and a plurality of first exponents represented in binary corresponding to the plurality of first floating-point numbers, and a plurality of second fixed-point numbers and a plurality of second exponents represented in binary corresponding to the plurality of second floating-point numbers are obtained, wherein the plurality of first floating-point numbers correspond one-to-one to the plurality of second floating-point numbers, and each of the plurality of first fixed-point numbers and the plurality of second fixed-point numbers respectively includes a sign bit and a first preset number of fixed-point value bits; Obtaining a fixed-point product value and a corresponding fixed-point product exponent of each first fixed-point number among the plurality of first fixed-point numbers and a second fixed-point number corresponding to the first fixed-point number; Obtaining a fixed-point inner product calculation result of the first vector and the second vector based on a fixed-point product order corresponding to each of a plurality of fixed-point product values ​​corresponding to the plurality of first fixed-point numbers, including: Based on a fixed-point product exponent corresponding to each of the fixed-point product values ​​of the plurality of fixed-point product values ​​corresponding to the plurality of first fixed-point numbers, performing an arithmetic shift on the fixed-point product value; and summing a plurality of fixed-point product values ​​after arithmetic shift corresponding to the plurality of first fixed-point numbers to obtain a fixed-point inner product calculation result of the first vector and the second vector; and Based on the fixed-point inner product calculation result, a floating-point inner product calculation result in a floating-point data format corresponding to the fixed-point inner product calculation result is obtained.

2. The method according to claim 1, wherein: The performing arithmetic shift on the fixed-point product value based on the fixed-point product exponent corresponding to each fixed-point product value in the plurality of fixed-point product values ​​corresponding to the plurality of first fixed-point numbers comprises: Determining a first fixed-point product exponent among a plurality of fixed-point product exponents corresponding to the plurality of first fixed-point numbers; Based on each fixed-point product exponent in the plurality of fixed-point product exponents and the first fixed-point product exponent, obtaining an arithmetic shift value corresponding to each fixed-point product value in the plurality of fixed-point product values; and The fixed-point product value is arithmetically shifted based on the corresponding arithmetic shift value of each fixed-point product value in the plurality of fixed-point product values.

3. The method according to claim 2, wherein: Determining a first fixed-point product order from a plurality of fixed-point product orders corresponding to the plurality of first fixed-point numbers comprises: Obtaining the largest fixed-point product exponent among the multiple fixed-point product exponents corresponding to the multiple first fixed-point numbers as the first fixed-point product exponent; and wherein, The acquiring, based on each fixed-point product exponent in the plurality of fixed-point product exponents and the first fixed-point product exponent, an arithmetic shift value corresponding to each fixed-point product value in the plurality of fixed-point product values ​​comprises: A difference between the first fixed-point product exponent and each of the plurality of fixed-point product exponents is calculated as a corresponding arithmetic shift value of a fixed-point product value corresponding to the fixed-point product exponent.

4. The method according to any one of claims 1 to 3, wherein: The step of obtaining a plurality of first fixed-point numbers and a plurality of first exponents represented by binary codes corresponding to the plurality of first floating-point numbers, and a plurality of second fixed-point numbers and a plurality of second exponents represented by binary codes corresponding to the plurality of second floating-point numbers comprises: For each of the plurality of first floating-point numbers and the plurality of second floating-point numbers, perform the following operation: Extracting a sign bit, an exponent bit, and a floating point value bit from the floating point number, wherein the floating point number is represented by binary; Extracting a second preset number of high-order numerical bits of the most significant bits in the floating-point numerical bits; Determine the fixed-point number corresponding to the floating-point number based on the high-order numerical bit; and Based on the exponent bits of the floating-point number, an exponent corresponding to the floating-point number is determined.

5. The method according to claim 4, wherein: The step of obtaining a fixed-point product value of each first fixed-point number among the plurality of first fixed-point numbers and a second fixed-point number corresponding to the first fixed-point number and a corresponding fixed-point product exponent comprises: Based on the sign bits of the first floating-point numbers respectively corresponding to the first fixed-point numbers and the sign bits of the second floating-point numbers respectively corresponding to the second fixed-point numbers, obtaining a plurality of first complement codes corresponding to the first fixed-point numbers and a plurality of second complement codes corresponding to the second fixed-point numbers; Calculating the product of each first complement of the plurality of first complements and a second complement corresponding to the first complement to obtain the fixed-point product value; and The sum of a first exponent corresponding to each first fixed-point number in the plurality of first fixed-point numbers and a second exponent corresponding to a second fixed-point number corresponding to the first fixed-point number is calculated to obtain the fixed-point product exponent.

6. The method according to any one of claims 1 to 3, wherein: The computing device is capable of calculating the inner product of two vectors of a first predetermined length within one computing cycle. For a third vector and a fourth vector having the same vector length and both greater than the first predetermined length, the method further comprises: Based on the first predetermined length, the third vector and the fourth vector are divided into a plurality of first vectors and a plurality of second vectors respectively, wherein the plurality of first vectors correspond to the plurality of second vectors one by one; Calculating floating-point inner product calculation results of a plurality of corresponding groups of first vectors and second vectors respectively; and The sum of the floating-point inner product calculation results of the plurality of corresponding groups of first vectors and second vectors is calculated to obtain the inner product calculation result of the third vector and the fourth vector.

7. A computing method performed by a computing device, the method comprising: Obtain a first matrix and a second matrix, wherein the first matrix includes a first number of row vectors, the second matrix includes a second number of column vectors, and the row vectors and the column vectors have the same vector length; According to the method described in any one of claims 1 to 6, the inner product results of each row vector in the first matrix and each column vector in the second matrix are obtained respectively to obtain the inner product result matrix of the first matrix and the second matrix.

8. A computing device, comprising: A first acquisition unit is configured to acquire, based on a plurality of first floating-point numbers of a first vector and a plurality of second floating-point numbers of a second vector input into the computing device, a plurality of first fixed-point numbers and a plurality of first exponents represented in binary corresponding to the plurality of first floating-point numbers, and a plurality of second fixed-point numbers and a plurality of second exponents represented in binary corresponding to the plurality of second floating-point numbers, wherein the plurality of first floating-point numbers correspond one-to-one to the plurality of second floating-point numbers, and each of the plurality of first fixed-point numbers and the plurality of second fixed-point numbers respectively includes a sign bit and a first preset number of fixed-point value bits; a multiplier configured to obtain a fixed-point product value and a corresponding fixed-point product exponent of each first fixed-point number among the plurality of first fixed-point numbers and a second fixed-point number corresponding to the first fixed-point number; A second acquisition unit is configured to acquire a fixed-point inner product calculation result of the first vector and the second vector based on a fixed-point product order corresponding to each of a plurality of fixed-point product values ​​corresponding to the plurality of first fixed-point numbers, the second acquisition unit comprising: a shifter configured to perform arithmetic shift on each of the fixed-point product values ​​among a plurality of fixed-point product values ​​corresponding to the plurality of first fixed-point numbers based on a fixed-point product exponent corresponding to the fixed-point product value; and an adder configured to sum a plurality of arithmetically shifted fixed-point product values ​​corresponding to the plurality of first fixed-point numbers to obtain a fixed-point inner product calculation result of the first vector and the second vector; and The third acquisition unit is configured to acquire, based on the fixed-point inner product calculation result, a floating-point inner product calculation result in a floating-point data format corresponding to the fixed-point inner product calculation result.

9. The device according to claim 8, wherein: The shifter comprises: A determination module configured to determine a first fixed-point product order from a plurality of fixed-point product orders corresponding to the plurality of first fixed-point numbers; an acquisition module configured to acquire an arithmetic shift value corresponding to each of the plurality of fixed-point product values ​​based on each of the plurality of fixed-point product exponents and the first fixed-point product exponent; and The shift module is configured to perform an arithmetic shift on each of the plurality of fixed-point product values ​​based on an arithmetic shift value corresponding to the fixed-point product value.

10. The device according to claim 9, wherein: The determination module is configured to: Obtaining the largest fixed-point product exponent among the multiple fixed-point product exponents corresponding to the multiple first fixed-point numbers as the first fixed-point product exponent; and wherein, The acquisition module is configured as follows: A difference between the first fixed-point product exponent and each of the plurality of fixed-point product exponents is calculated as a corresponding arithmetic shift value of a fixed-point product value corresponding to the fixed-point product exponent.

11. The device according to any one of claims 8 to 10, wherein: The first acquisition unit is configured to perform the following sub-unit operations on each of the plurality of first floating-point numbers and the plurality of second floating-point numbers: A first extraction subunit is configured to extract a sign bit, an exponent bit, and a floating point value bit from the floating point number, wherein the floating point number is represented by binary; A second extraction subunit is configured to extract a second preset number of high-order numerical bits of the most significant bits in the floating-point numerical bits; A first determining subunit is configured to determine a fixed-point number corresponding to the floating-point number based on the high-order numerical bit; and The second determining subunit is configured to determine the exponent corresponding to the floating point number based on the exponent bit of the floating point number.

12. The device according to claim 11, wherein The multiplier comprises: an acquisition subunit, configured to acquire a plurality of first complement codes corresponding to the plurality of first fixed-point numbers and a plurality of second complement codes corresponding to the plurality of second fixed-point numbers based on the sign bits of the plurality of first floating-point numbers respectively corresponding to the plurality of first fixed-point numbers and the sign bits of the plurality of second floating-point numbers respectively corresponding to the plurality of second fixed-point numbers; A first calculation subunit is configured to calculate the product of each first complement of the plurality of first complements and a second complement corresponding to the first complement to obtain the fixed-point product value; and The second calculation subunit is configured to calculate the sum of a first exponent corresponding to each first fixed-point number in the plurality of first fixed-point numbers and a second exponent corresponding to a second fixed-point number corresponding to the first fixed-point number, so as to obtain the fixed-point product exponent.

13. The device according to any one of claims 8 to 10, wherein: The computing device is capable of calculating the inner product of two vectors of a first predetermined length within one computing cycle, and for a third vector and a fourth vector having the same vector length and both greater than the first predetermined length, the device further comprises: a dividing unit configured to divide the third vector and the fourth vector into a plurality of first vectors and a plurality of second vectors respectively based on the first predetermined length, wherein the plurality of first vectors and the plurality of second vectors correspond to each other one by one; A first calculation unit is configured to respectively calculate floating-point inner product calculation results of a plurality of groups of corresponding first vectors and second vectors; and The second calculation unit is configured to calculate the sum of the floating-point inner product calculation results of the multiple groups of corresponding first vectors and second vectors to obtain the inner product calculation result of the third vector and the fourth vector.

14. A computing device, comprising: a fourth acquisition unit, configured to acquire a first matrix and a second matrix, wherein the first matrix includes a first number of row vectors, the second matrix includes a second number of column vectors, and the row vectors have the same vector length as the column vectors; A fifth acquisition unit is configured to obtain the inner product results of each row vector in the first matrix and each column vector in the second matrix respectively according to the method described in any one of claims 1 to 6, so as to obtain the inner product result matrix of the first matrix and the second matrix.

15. A chip comprising at least one of the following devices: The device according to any one of claims 8 to 13, and The device of claim 14.

16. An electronic device comprising the chip according to claim 15.

17. An electronic device comprising: at least one processor; as well as a memory communicatively coupled to the at least one processor; in The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 7.

18. A non-transitory computer-readable storage medium storing computer instructions, wherein: The computer instructions are used to cause the computer to execute the method according to any one of claims 1-7.

19. A computer program product comprising a computer program, wherein: When the computer program is executed by a processor, the method according to any one of claims 1 to 7 is implemented.

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