Display panel and display device

Abstract

Provided is a display panel and a display device. The display panel includes: a substrate; sub-pixels located on the substrate, including a pixel circuit and a light-emitting element, the pixel circuit being configured to drive the light-emitting element, the light-emitting element including a first electrode, a second electrode, and a light-emitting functional layer located between the first electrode and the second electrode; and a first power supply line configured to provide a constant first power supply voltage to the pixel circuit, wherein the pixel circuit includes a driving transistor and a first capacitor provided between the gate of the driving transistor and the first power supply line, the first electrode of the light-emitting element is connected to a first pole of the driving transistor, the second pole of the driving transistor is connected to the first power supply line, and the pixel circuit further includes a second capacitor provided between the first electrode of the light-emitting element and the first power supply line.

Description

[0001] This application is a divisional application of the application with the application number 202210079283.8 filed on January 24, 2022. Technical Field

[0002] Embodiments of the present disclosure relate to a display panel and a display device. Background Art

[0003] With the development of display technology, compared with a liquid crystal display (LCD) panel, a new generation of organic light emitting diode (OLED) display panel has advantages such as lower manufacturing cost, faster response speed, higher contrast ratio, wider viewing angle, larger operating temperature range, no need for a backlight unit, bright colors, and being thin and light. Generally, in an OLED display panel, a plurality of pixel units (sub-pixels) are arranged in an array. Pixel units in the same row are connected to the same gate line, and pixel units in the same column are connected to the same data line. Each pixel unit performs display under the drive of a scan signal provided by the gate line and a data signal provided by the data line. Summary of the Invention

[0004] Embodiments of the present disclosure provide a display panel and a display device.

[0005] Embodiments of the present disclosure provide a display panel, including: a substrate; sub-pixels located on the substrate, including a pixel circuit and a light-emitting element, the pixel circuit being configured to drive the light-emitting element, the light-emitting element including a first electrode, a second electrode, and a light-emitting functional layer located between the first electrode and the second electrode; and a first power supply line configured to provide a constant first power supply voltage to the pixel circuit, wherein the pixel circuit includes a driving transistor, a first capacitor provided between the gate of the driving transistor and the first power supply line, the first electrode of the light-emitting element is connected to the first pole of the driving transistor, the second pole of the driving transistor is connected to the first power supply line, and the pixel circuit further includes a second capacitor provided between the first electrode of the light-emitting element and the first power supply line.

[0006] For the display panel provided by the embodiments of the present disclosure, the range of the first capacitor is greater than 20.0 fF and less than 80.0 fF.

[0007] For the display panel provided by the embodiments of the present disclosure, the range of the first capacitor is greater than 30.0 fF and less than 70.0 fF.

[0008] According to the display panel provided by the embodiment of the present disclosure, the range of the first capacitor is greater than 40.0 fF and less than 60.0 fF.

[0009] According to the display panel provided by the embodiment of the present disclosure, the range of the second capacitor is greater than 41.0 fF and less than 130.0 fF.

[0010] According to the display panel provided by the embodiment of the present disclosure, the range of the second capacitor is greater than 50.0 fF and less than 120.0 fF.

[0011] According to the display panel provided by the embodiment of the present disclosure, the range of the second capacitor is greater than 70.0 fF and less than 110.0 fF.

[0012] According to the display panel provided by the embodiment of the present disclosure, the range of the second capacitor is greater than 80.0 fF and less than 100.0 fF. According to the display panel provided by the embodiment of the present disclosure, the display panel further includes a first reset control signal line and a first initialization signal line. Wherein, the first reset control signal line is configured to provide a first reset control signal to the pixel circuit, the first initialization signal line is configured to provide a first initialization signal to the pixel circuit, the pixel circuit further includes a first reset transistor, a gate of the first reset transistor is connected to the first reset control signal line, a first pole of the first reset transistor is connected to the first initialization signal line, a second pole of the first reset transistor is connected to a gate of the driving transistor, and the first reset transistor is configured to reset the gate of the driving transistor.

[0013] According to the display panel provided by the embodiment of the present disclosure, the first reset transistor is an oxide transistor, and the oxide transistor has a double-gate structure.

[0014] According to the display panel provided by the embodiment of the present disclosure, the pixel circuit further includes a third capacitor provided between a gate of the first reset transistor and the first power supply line.

[0015] According to the display panel provided by the embodiment of the present disclosure, the range of the third capacitor is greater than 0.5 fF and less than 3.0 fF.

[0016] According to the display panel provided by the embodiment of the present disclosure, the pixel circuit further includes a threshold compensation transistor, a first pole of the threshold compensation transistor is connected to a first pole of the driving transistor, a second pole of the threshold compensation transistor is connected to a gate of the driving transistor, and the pixel circuit further includes a fourth capacitor provided between a gate of the threshold compensation transistor and the first power supply line.

[0017] The display panel provided according to an embodiment of the present disclosure, wherein the threshold compensation transistor is an oxide transistor, and the oxide transistor has a double-gate structure.

[0018] The display panel provided according to an embodiment of the present disclosure, wherein the fourth capacitor ranges from greater than 0.5 fF to less than 3.0 fF.

[0019] The display panel provided according to an embodiment of the present disclosure, wherein the pixel circuit further includes a fifth capacitor provided between the gate of the first reset transistor and the first initialization signal line.

[0020] The display panel provided according to an embodiment of the present disclosure, the display panel further includes a second reset control signal line and a second initialization signal line, the second reset control signal line is configured to provide a second reset control signal to the pixel circuit, the second initialization signal line is configured to provide a second initialization signal to the pixel circuit, the pixel circuit further includes a second reset transistor, the second reset transistor is configured to reset the first electrode of the light-emitting element, a first pole of the second reset transistor is connected to the second initialization signal line, a second pole of the second reset transistor is connected to the first electrode of the light-emitting element, a gate of the second reset transistor is connected to the second reset control signal line, and the pixel circuit further includes a fifth capacitor provided between the gate of the first reset transistor and the second initialization signal line.

[0021] The display panel provided according to an embodiment of the present disclosure, wherein the fifth capacitor ranges from greater than 1.0 fF to less than 10.0 fF.

[0022] The display panel provided according to an embodiment of the present disclosure, wherein the second initialization signal line and the first reset control signal line at least partially overlap.

[0023] The display panel provided according to an embodiment of the present disclosure, the display panel further includes a data line, the data line is configured to provide a data signal to the pixel circuit, and the pixel circuit further includes a data writing transistor, and a first pole and a second pole of the data writing transistor are respectively connected to the data line and a second pole of the driving transistor.

[0024] The display panel provided according to an embodiment of the present disclosure, the sub-pixels are provided in multiple, the multiple sub-pixels include a first sub-pixel, a positive projection of the first electrode of the light-emitting element of the first sub-pixel on the substrate does not overlap with a positive projection of the data line on the substrate, a ratio of an overlapping area between the first electrode of the first sub-pixel and the first power supply line to an area of the first electrode of the first sub-pixel is r1, and 0.8 < r1 < 1.

[0025] A display panel provided according to an embodiment of the present disclosure, wherein the plurality of sub-pixels include second sub-pixels, the emission color of the second sub-pixels is different from the emission color of the first sub-pixels, a positive projection of a first electrode of the light-emitting element of the second sub-pixels on the substrate does not overlap with a positive projection of the data line on the substrate, and a ratio of an overlapping area between the first electrode of the second sub-pixels and the first power line to an area of the first electrode of the second sub-pixels is r2, where 0.8 < r2 < 1.

[0026] A display panel provided according to an embodiment of the present disclosure, wherein the plurality of sub-pixels include third sub-pixels, the emission color of the third sub-pixels is different from the emission color of the first sub-pixels and different from the emission color of the second sub-pixels, a positive projection of a first electrode of the light-emitting element of the third sub-pixels on the substrate overlaps with a positive projection of the data line on the substrate, and a ratio of an overlapping area between the first electrode of the third sub-pixels and the first power line to an area of the first electrode of the third sub-pixels is r3, where 0 < r3 < 0.4.

[0027] A display panel provided according to an embodiment of the present disclosure, wherein the sub-pixels are provided in a plurality, and the plurality of sub-pixels form a plurality of data bars arranged in a first direction, each data bar extends in a second direction, the data bar includes a first column of sub-pixels and a second column of sub-pixels, the data lines include a first data line and a second data line, the first column of sub-pixels is connected to the first data line, the second column of sub-pixels is connected to the second data line, pixel circuits for driving the first column of sub-pixels and pixel circuits for driving the second column of sub-pixels are located between the first data line and the second data line, the first column of sub-pixels includes a plurality of first sub-pixels and a plurality of second sub-pixels arranged alternately in the second direction, and the second column of sub-pixels includes a plurality of third sub-pixels arranged in the second direction.

[0028] A display panel provided according to an embodiment of the present disclosure, a positive projection of a first electrode of the light-emitting element of the first sub-pixel on the substrate does not overlap with a positive projection of the data line on the substrate, and a ratio of an overlapping area between the first electrode of the first sub-pixel and the first power supply line to an area of the first electrode of the first sub-pixel is r1; a positive projection of a first electrode of the light-emitting element of the second sub-pixel on the substrate does not overlap with a positive projection of the data line on the substrate, and a ratio of an overlapping area between the first electrode of the second sub-pixel and the first power supply line to an area of the first electrode of the second sub-pixel is r2; emission colors of every two of the first sub-pixel, the second sub-pixel, and the third sub-pixel are different, a positive projection of a first electrode of the light-emitting element of the third sub-pixel on the substrate overlaps with a positive projection of the data line on the substrate, and a ratio of an overlapping area between the first electrode of the third sub-pixel and the first power supply line to an area of the first electrode of the third sub-pixel is r3, where r3 < r1 and r3 < r2.

[0029] For the display panel provided according to an embodiment of the present disclosure, 0.8 < r1 < 1, 0.8 < r2 < 1, and 0 < r3 < 0.4.

[0030] For the display panel provided according to an embodiment of the present disclosure, the first power supply line includes a first power supply conductive portion and a second power supply conductive portion spaced apart in a second direction, the first initialization signal line includes a first initialization conductive portion extending in a first direction and a second initialization conductive portion extending in the second direction, the first initialization conductive portion and the second initialization conductive portion are connected, and a positive projection of the second initialization conductive portion on the substrate is located between a positive projection of the first power supply conductive portion on the substrate and a positive projection of the second power supply conductive portion on the substrate.

[0031] For the display panel provided according to an embodiment of the present disclosure, a positive projection of the second initialization conductive portion on the substrate overlaps with positive projections of the first electrode of the first sub-pixel and the first electrode of the second sub-pixel on the substrate.

[0032] For the display panel provided according to an embodiment of the present disclosure, the first power supply line includes a third power supply conductive portion and a fourth power supply conductive portion spaced apart in the second direction, the second initialization signal line includes a third initialization conductive portion extending in the first direction and a fourth initialization conductive portion extending in the second direction, the third initialization conductive portion and the fourth initialization conductive portion are connected, and a positive projection of the fourth initialization conductive portion on the substrate is located between a positive projection of the third power supply conductive portion on the substrate and a positive projection of the fourth power supply conductive portion on the substrate.

[0033] According to the display panel provided by an embodiment of the present disclosure, a positive projection of the fourth initialization conductive portion on the substrate substrate overlaps with positive projections of the first electrodes of the first sub-pixel and the second sub-pixel on the substrate substrate.

[0034] According to the display panel provided by an embodiment of the present disclosure, a plurality of second initialization conductive portions and a plurality of fourth initialization conductive portions are alternately arranged along a second direction.

[0035] According to the display panel provided by an embodiment of the present disclosure, the second initialization conductive portion and the fourth initialization conductive portion are located in different data bars.

[0036] According to the display panel provided by an embodiment of the present disclosure, a positive projection of the first power supply line on the substrate substrate overlaps with a positive projection of the gate of the first reset transistor on the substrate substrate to form a third capacitor.

[0037] According to the display panel provided by an embodiment of the present disclosure, the display panel further includes a first connection portion. The first power supply conductive portion and the second power supply conductive portion are connected through the first connection portion. The first power supply conductive portion and the second power supply conductive portion are located in the same layer, and the first connection portion is located in the same layer as the first power supply conductive portion and the second power supply conductive portion.

[0038] According to the display panel provided by an embodiment of the present disclosure, the display panel further includes a first connection portion. Wherein, the first power supply conductive portion and the second power supply conductive portion are connected through the first connection portion. The first power supply conductive portion and the second power supply conductive portion are located in the same layer, and the first connection portion is located in a layer different from the first power supply conductive portion and the second power supply conductive portion.

[0039] According to the display panel provided by an embodiment of the present disclosure, a dimension of the first connection portion in the second direction is smaller than a dimension of a portion of the first power supply line overlapping with the first electrode of the light-emitting element in the second direction.

[0040] According to the display panel provided by an embodiment of the present disclosure, a dimension of the first connection portion in the second direction is smaller than a minimum dimension of the first electrode of the light-emitting element in the second direction.

[0041] According to the display panel provided by an embodiment of the present disclosure, the display panel further includes a second connection portion. The second power supply conductive portion and the third power supply conductive portion are connected through the second connection portion. The second connection portion, the second power supply conductive portion, and the third power supply conductive portion are located in the same layer.

[0042] The display panel provided according to an embodiment of the present disclosure further includes a second connection portion. The second power conductive portion and the third power conductive portion are connected through the second connection portion, and the second connection portion, the second power conductive portion, and the third power conductive portion are located in different layers.

[0043] For the display panel provided according to an embodiment of the present disclosure, the orthographic projection of the second connection portion on the substrate substrate overlaps with the orthographic projection of the first electrode of the third sub-pixel on the substrate substrate. The ratio of the overlapping area between the first electrode of the third sub-pixel and the second connection portion to the area of the first electrode of the third sub-pixel is r3, where 0.8 < r3 < 1.

[0044] For the display panel provided according to an embodiment of the present disclosure, the orthographic projection of the second connection portion on the substrate substrate overlaps with the orthographic projection of the first electrode of the third sub-pixel on the substrate substrate. The ratio of the overlapping area between the first electrode of the third sub-pixel and the second connection portion to the area of the first electrode of the third sub-pixel is r3, where 0 ≤ r3 < 0.5.

[0045] For the display panel provided according to an embodiment of the present disclosure, the orthographic projection of the first electrode of the light-emitting element of the first sub-pixel on the substrate substrate does not overlap with the orthographic projection of the data line on the substrate substrate. The ratio of the overlapping area between the first electrode of the first sub-pixel and the first power supply line to the area of the first electrode of the first sub-pixel is r1; the orthographic projection of the first electrode of the light-emitting element of the second sub-pixel on the substrate substrate does not overlap with the orthographic projection of the data line on the substrate substrate. The ratio of the overlapping area between the first electrode of the second sub-pixel and the first power supply line to the area of the first electrode of the second sub-pixel is r2; the light-emitting colors of any two of the first sub-pixel, the second sub-pixel, and the third sub-pixel are different. The orthographic projection of the first electrode of the light-emitting element of the third sub-pixel on the substrate substrate overlaps with the orthographic projection of the data line on the substrate substrate. The ratio of the overlapping area between the first electrode of the third sub-pixel and the first power supply line to the area of the first electrode of the third sub-pixel is r3, where 0.8 < r1 < 1 and 0.8 < r2 < 1.

[0046] A display panel provided according to an embodiment of the present disclosure further includes a first conductive pattern layer, a second conductive pattern layer, a third conductive pattern layer, a fourth conductive pattern layer, a fifth conductive pattern layer, and a sixth conductive pattern layer which are sequentially arranged. The first conductive pattern layer is closer to the substrate than the sixth conductive pattern layer. The first capacitor includes a first electrode plate and a second electrode plate. The gate of the driving transistor serves as the first electrode plate of the first capacitor and is located in the first conductive pattern layer. The second electrode plate of the first capacitor is located in the second conductive pattern layer and is connected to the first power supply line. The two electrode plates of the second capacitor include the first electrode of the light-emitting element located in the sixth conductive pattern layer and the first power supply line located in the fifth conductive pattern layer. The two electrode plates of the third capacitor include the top gate in the gate of the first reset transistor located in the third conductive pattern layer and the first power supply line located in the fifth conductive pattern layer. The two electrode plates of the fourth capacitor include the top gate in the gate of the threshold compensation transistor located in the third conductive pattern layer and the first power supply line located in the fifth conductive pattern layer. The two electrode plates of the fifth capacitor include the top gate in the gate of the first reset transistor located in the third conductive pattern layer and the second initialization signal line located in the fourth conductive pattern layer. The bottom gate in the gate of the first reset transistor and the bottom gate in the gate of the threshold compensation transistor are both located in the second conductive pattern layer.

[0047] An embodiment of the present disclosure further provides a display device including any of the above display panels. Description of the Drawings

[0048] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure and do not limit the present disclosure.

[0049] Figure 1 It is a schematic diagram of a pixel circuit and a light-emitting element in a sub-pixel of a display panel.

[0050] Figures 2 to 6 It is a schematic diagram of a pixel circuit and a light-emitting element in a sub-pixel of a display panel provided by some embodiments of the present disclosure.

[0051] Figure 7 It is a layout diagram of a display panel provided by some embodiments of the present disclosure.

[0052] Figure 8 It is Figure 7 a cross-sectional view along line A-A' in

[0053] FIG. 9A to FIG. 9K It is Figure 7 a plan view of a single-layer structure in

[0054] FIG. 10A to FIG. 10I is Figure 7 a plan view of the stacked structure in

[0055] Fig.11 a layout diagram of a display panel provided by an embodiment of the present disclosure.

[0056] FIG. 12A to FIG. 12K is Fig.11 a plan view of the single-layer structure in

[0057] FIG. 13A to FIG. 13B is Fig.11 a plan view of a partially single-layer stacked structure in

[0058] Fig.14 a layout diagram of a display panel provided by an embodiment of the present disclosure.

[0059] Fig.15 is Fig.14 a cross-sectional view along line B-B' in

[0060] FIG. 16A to FIG. 16E is Fig.14 a plan view of the single-layer or multi-layer of the display panel in

[0061] Fig.17 another layout diagram of a display panel provided by an embodiment of the present disclosure.

[0062] Fig.18A is Fig.17 a plan view of the fifth conductive pattern layer in

[0063] Fig.18B is Fig.17 a plan view of the fifth conductive pattern layer and the first electrode layer of the light-emitting element in

[0064] Fig. 18C is Fig.17 a plan view of the fourth conductive pattern layer and the fifth conductive pattern layer in

[0065] Fig.19 another layout diagram of a display panel provided by an embodiment of the present disclosure.

[0066] Fig. 20A is Fig.19 a plan view of the fourth conductive pattern layer, the planarization layer and the fifth conductive pattern layer in

[0067] Fig. 20B is Fig.19 a plan view of the fourth conductive pattern layer, the planarization layer, the fifth conductive pattern layer and the sixth conductive pattern layer in

[0068] Fig.21Another layout diagram of a display panel provided by an embodiment of the present disclosure.

[0069] Fig.22A It is Fig.21 a plan view of the fourth conductive pattern layer, the planarization layer, and the fifth conductive pattern layer in

[0070] Fig. 22B It is Fig.21 a plan view of the fourth conductive pattern layer, the planarization layer, the fifth conductive pattern layer, and the sixth conductive pattern layer in

[0071] Fig.23 It is Fig.21 a cross-sectional view along line C-C' in

[0072] Fig.24 It is Figures 1 to 7 a signal waveform timing diagram of the pixel circuit of Detailed implementation manners

[0073] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present disclosure without creative efforts shall fall within the scope of protection of the present disclosure.

[0074] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure shall have the ordinary meanings understood by those of ordinary skill in the art to which the present disclosure pertains. The "first", "second", and similar terms used in the present disclosure do not denote any order, quantity, or importance, but are only used to distinguish different components. Similarly, words such as "including" or "comprising" mean that the elements or items appearing before the word cover the elements or items listed after the word and their equivalents, without excluding other elements or items. "Connection" or "coupling" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The "connection" or "coupling" between components in a circuit may refer to coupling.

[0075] In the current OLED pixel circuit, a 7T1C circuit structure is generally adopted. There is a parasitic capacitance between the gate of the driving transistor and the first electrode E1 of the light-emitting element 100b. When driving the OLED to emit light, for each frame of signal, the first electrode E1 of the light-emitting element 100b needs to be initialized. At this time, a voltage change ΔV occurs in the voltage of the first electrode E1 of the light-emitting element 100b. This voltage change ΔV is coupled to the gate of the driving transistor through the parasitic capacitance, resulting in fluctuations in the OLED driving current.

[0076] Figure 1 Schematic diagram of a pixel circuit and a light-emitting element in a sub-pixel of a display panel. Figures 2 to 6 Schematic diagram of a pixel circuit and a light-emitting element in a sub-pixel of a display panel provided by some embodiments of the present disclosure. Figure 7 Layout diagram of a display panel provided by some embodiments of the present disclosure. Figure 8 For Figure 7 Cross-sectional view along line A-A' in FIG. 9A to FIG. 9K For Figure 7 Plan view of the single-layer structure in FIG. 10A to FIG. 10I For Figure 7 Plan view of the stacked structure in FIG. 10A to FIG. 10I The upper right corner of indicates the single layer included in this figure. Figure 7 Shows the display panel 201.

[0077] As Figures 1 to 7 shown, the display panel includes a plurality of sub-pixels 100. Figures 1 to 7 Shows a sub-pixel 100. As Figure 1 shown, each sub-pixel 100 includes a pixel circuit 100a and a light-emitting element 100b. The pixel circuit 100a drives the light-emitting element 100b. The pixel circuit 100a drives the light-emitting element 100b to emit light. The pixel circuit 100a provides a driving current to drive the light-emitting element 100b to emit light.

[0078] Figure 1 Shows the sub-pixel 1001, Figure 2 Shows the sub-pixel 1002, Figure 3 Shows the sub-pixel 1003, Figure 4 Shows the sub-pixel 1004, Figure 5 Shows the sub-pixel 1005, Figure 6 Shows the sub-pixel 1006. Figures 1 to 6 The structures of the pixel circuits of the sub-pixels are different.

[0079] As Figures 1 to 7As shown, the pixel circuit 100a includes six switching transistors (T1 - T2, T4 - T7), a driving transistor T3, and a capacitor C1. The six switching transistors are respectively a data writing transistor T4, a threshold compensation transistor T2, a light emission control transistor T5, a light emission control transistor T6, a reset transistor T1, and a reset transistor T7. The light emitting element 100b includes a first electrode E1 and a second electrode E2, and a light emitting functional layer located between the first electrode E1 and the second electrode E2. For example, the first electrode E1 is an anode, and the second electrode E2 is a cathode.

[0080] As Figures 1 to 7 shown, the display panel includes gate lines GT, data lines DT, a first power supply line PL1, a second power supply line PL2, a light emission control signal line EML, an initialization signal line INT, a reset control signal line RST, etc. For example, the reset control signal line RST includes a reset control signal line RST1 and a reset control signal line RST2. The first power supply line PL1 is configured to supply a constant first voltage signal VDD to the sub - pixel 100, the second power supply line PL2 is configured to supply a constant second voltage signal VSS to the sub - pixel 100, and the first voltage signal VDD is greater than the second voltage signal VSS. The gate line GT is configured to supply a scan signal SCAN to the sub - pixel 100, the data line DT is configured to supply a data signal (data voltage) DATA to the sub - pixel 100, the light emission control signal line EML is configured to supply a light emission control signal EM to the sub - pixel 100, the reset control signal line RST1 is configured to supply a reset control signal RESET1 to the sub - pixel 100, and the reset control signal line RST2 is configured to supply a scan signal SCAN to the sub - pixel 100. The initialization signal line INT1 is configured to supply a first initialization signal Vinit1 to the sub - pixel 100. The initialization signal line INT2 is configured to supply a second initialization signal Vinit2 to the sub - pixel 100. For example, the first initialization signal Vinit1 and the second initialization signal Vinit2 are constant voltage signals, and their magnitudes can, for example, be between the first voltage signal VDD and the second voltage signal VSS, but are not limited thereto. For example, in some embodiments of the present disclosure, the initialization signal line INT1 and the initialization signal line INT2 are connected and are both configured to supply an initialization signal Vinit to the sub - pixel 100, that is, the initialization signal line INT1 and the initialization signal line INT2 are both referred to as the initialization signal line INT, the first initialization signal Vinit1 and the second initialization signal Vinit2 are equal, both being Vinit, but are not limited thereto. In other embodiments, the initialization signal line INT1 and the initialization signal line INT2 are insulated from each other to provide different initialization signals.

[0081] As Figures 1 to 7 shown, the driving transistor T3 is electrically connected to the light-emitting element 100b, and outputs a driving current to drive the light-emitting element 100b to emit light under the control of signals such as a scan signal SCAN, a data signal DATA, a first voltage signal VDD, and a second voltage signal VSS.

[0082] For example, the light-emitting element 100b includes an organic light-emitting diode (OLED), and the light-emitting element 100b emits red light, green light, blue light, or white light, etc. under the drive of its corresponding pixel circuit 100a.

[0083] For example, as Figures 1 to 7 shown, the gate T4g of the data writing transistor T4 is connected to the gate line GT (gate line GT2), the first pole T4a of the data writing transistor T4 is connected to the data line DT, and the second pole T4b of the data writing transistor T4 is connected to the second pole T3b of the driving transistor T3.

[0084] For example, as Figures 1 to 7 shown, the pixel circuit 100a further includes a threshold compensation transistor T2. The gate T2g of the threshold compensation transistor T2 is connected to the gate line GT (gate line GT1), the first pole T2a of the threshold compensation transistor T2 is connected to the first pole T3a of the driving transistor T3, and the second pole T2b of the threshold compensation transistor T2 is connected to the gate T3g of the driving transistor T3.

[0085] For example, as Figures 1 to 7 shown, the display panel further includes a light emission control signal line EML. The pixel circuit 100a further includes a light emission control transistor T5 and a light emission control transistor T6. The gate T5g of the light emission control transistor T5 is connected to the light emission control signal line EML, the first pole T5a of the light emission control transistor T5 is connected to the first power line PL1, and the second pole T5b of the light emission control transistor T5 is connected to the second pole T3b of the driving transistor T3; the gate T6g of the light emission control transistor T6 is connected to the light emission control signal line EML, the first pole T6a of the light emission control transistor T6 is connected to the first pole T3a of the driving transistor T3, and the second pole T6b of the light emission control transistor T6 is connected to the first electrode E1 of the light-emitting element 100b.

[0086] As Figures 1 to 7As shown, the reset transistor T1 is connected to the gate T3g of the driving transistor T3 and is configured to reset the gate T3g of the driving transistor T3. The reset transistor T7 is connected to the first electrode E1 of the light-emitting element 100b and is configured to reset the first electrode E1 of the light-emitting element 100b. The initialization signal line INT1 is connected to the gate T3g of the driving transistor T3 through the reset transistor T1. The initialization signal line INT2 is connected to the first electrode E1 of the light-emitting element 100b through the reset transistor T7. For example, the initialization signal line INT1 and the initialization signal line INT2 are connected to provide the same initialization signal, but not limited thereto. In some embodiments of the present disclosure, the initialization signal line INT1 and the initialization signal line INT2 may also be insulated from each other and are configured to provide signals separately.

[0087] For example, as Figures 1 to 7 shown, the first pole T1a of the reset transistor T1 is connected to the initialization signal line INT1, the second pole T1b of the reset transistor T1 is connected to the gate T3g of the driving transistor T3, the first pole T7a of the reset transistor T7 is connected to the initialization signal line INT2, and the second pole T7b of the reset transistor T7 is connected to the first electrode E1 of the light-emitting element 100b. For example, as Figures 1 to 7 shown, the gate T1g of the reset transistor T1 is connected to the reset control signal line RST1, and the gate T7g of the reset transistor T7 is connected to the reset control signal line RST2.

[0088] As Figures 1 to 7 shown, the first power supply line PL1 is configured to provide the first voltage signal VDD to the pixel circuit 100a; the pixel circuit further includes a capacitor C1. The first plate C11 of the capacitor C1 is connected to the gate T3g of the driving transistor T3, and the second plate C12 of the capacitor C1 is connected to the first power supply line PL1 and the first pole T5a of the light-emitting control transistor T5, respectively.

[0089] For example, as Figures 1 to 6 shown, the display panel further includes a second power supply line PL2, and the second power supply line PL2 is connected to the second electrode E2 of the light-emitting element 100b. Figures 1 to 6 The first node N1, the second node N2, the third node N3, and the fourth node N4 are shown.

[0090] As Figures 1 to 7 shown, the gate line GT includes a gate line GT1 and a gate line GT2. The gate line GT1 is connected to the gate T2g of the threshold compensation transistor T2. The gate line GT2 is connected to the gate T4g of the data writing transistor T4. For example, in a sub-pixel, the gate line GT1 is configured to provide the n-th row scan signal SCAN(N)(n), and the gate line GT2 is configured to provide the n-th row scan signal SCAN(P)(n).

[0091] In some embodiments of the present disclosure, as Figures 1 to 7 shown, the pixel circuit 100a further includes a capacitor C1. A first electrode plate C11 of the capacitor C1 is connected to a gate T3g of the driving transistor T3, and the first electrode plate C11 of the capacitor C1 is respectively connected to the reset transistor T1 and the threshold compensation transistor T2. For example, as Figures 1 to 7 shown, the first electrode plate C11 of the capacitor C1 is respectively connected to a second electrode T1b of the reset transistor T1 and a second electrode T2b of the threshold compensation transistor T2.

[0092] The P-type thin film transistor has higher mobility and a more stable source voltage, and is suitable for driving the light-emitting element. The N-type thin film transistor has lower leakage current and can better maintain the voltage stability of the driving transistor T3 and the capacitor C1.

[0093] For example, as Figures 1 to 7 shown, both the threshold compensation transistor T2 and the reset transistor T1 are oxide thin film transistors, and the remaining transistors T3-T7 are all low temperature polycrystalline silicon (LTPS) thin film transistors. Thus, the display panel provided by the embodiments of the present disclosure adopts a low temperature polycrystalline-oxide (LTPO) pixel circuit to improve the display quality.

[0094] In some embodiments of the present disclosure, both the driving transistor T3 and the data writing transistor T4 are P-type thin film transistors, and both the threshold compensation transistor T2 and the reset transistor T1 are N-type thin film transistors.

[0095] For example, in some drawings, SCAN(N)(n) represents the gate line of the N-type thin film transistor in the nth row, that is, the scan signal on the gate line GT1. SCAN(P)(n) represents the gate line of the P-type thin film transistor in the nth row, that is, the scan signal on the gate line GT2. SCAN(N)(n-1) represents the scan signal on the reset control signal line of the N-type thin film transistor in the (n-1)th row, and can also represent the scan signal on the gate line of the N-type thin film transistor in the (n-1)th row. As Figures 2 to 6 shown, the gate T2g of the threshold compensation transistor T2 is cascaded to the nth stage of the GOA to be provided with the scan signal of the nth row. The gate T1g of the reset transistor T1 is cascaded to the (n-1)th stage of the GOA to be provided with the scan signal of the (n-1)th row. The gate T4g of the data writing transistor T4 is cascaded to the nth stage of the GOA to be provided with the scan signal of the nth row.

[0096] As Figures 2 to 8 shown, the display panel provided by some embodiments of the present disclosure includes: a substrate substrate BS, a sub-pixel 100, and a first power supply line PL1.

[0097] As Figure 7 and Figure 8 shown, the sub-pixel 100 is located on the substrate BS. The sub-pixel 100 includes a pixel circuit 100a and a light-emitting element 100b. The pixel circuit 100a is configured to drive the light-emitting element 100b. The light-emitting element 100b includes a first electrode E1, a second electrode E2, and a light-emitting functional layer FL located between the first electrode E1 and the second electrode E2.

[0098] For example, as Figure 8 shown, the light-emitting functional layer FL is located between the first electrode E1 and the second electrode E2. The light-emitting functional layer FL includes a light-emitting layer. For example, the light-emitting functional layer FL may further include at least one of an electron injection layer, an electron transport layer, a hole transport layer, and a hole injection layer. The types and numbers of the film layers included in the light-emitting functional layer FL can be determined as needed.

[0099] As Figure 7 and Figure 8 shown, the first power supply line PL1 is configured to provide a constant first voltage signal (first power supply voltage) VDD to the pixel circuit 100a. The pixel circuit 100a includes a driving transistor T3 and a capacitor C1 provided between the gate T3g of the driving transistor T3 and the first power supply line PL1. The first electrode E1 of the light-emitting element 100b is connected to the first pole of the driving transistor T3.

[0100] As Figures 1 to 8 shown, the capacitor C1 includes a first electrode plate C11 and a second electrode plate C12. As Figure 8 shown, an interlayer dielectric layer ILD1 is provided between the first electrode plate C11 and the second electrode plate C12. The capacitor C1 is a storage capacitor for storing the gate voltage of the driving transistor T3.

[0101] For example, C1 = ε * ε0 * S / d; where: S is the facing area of the two electrode plates of the capacitor, in square meters; d is the distance between the two electrode plates, in meters, ε is the relative dielectric constant of the insulating layer between the first electrode plate C11 and the second electrode plate C12; ε0 is the vacuum dielectric constant 8.85×10 -12 , in units of F / m.

[0102] The magnitude of the capacitor C1 determines the ability of the pixel circuit to hold the potential of the first node N1. A larger capacitor C1 is beneficial for maintaining the potential of the first node N1 in the pixel circuit for a longer time during low-frequency driving. However, during high-frequency driving, a larger capacitor C1 is not conducive to the reset transistor timely resetting the potential of the first node N1 to the initialization potential Vinit. Therefore, in the display panel provided in some embodiments of the present disclosure, the range of the capacitor C1 is greater than 20.0 fF and less than 80.0 fF. That is, 20.0 fF < C1 < 80.0 fF. For example, the range of the capacitor C1 is greater than 30.0 fF and less than 70.0 fF. Further for example, the range of the capacitor C1 is greater than 40.0 fF and less than 60.0 fF.

[0103] As Figures 2 to 8 shown, the pixel circuit 100a further includes a capacitor C2 provided between the first electrode E1 of the light-emitting element 100b and the first power supply line PL1. As Figures 2 to 8 shown, the capacitor C2 includes a first plate C21 and a second plate C22. The capacitor C2 is connected to the first electrode E1 of the light-emitting element 100b and the first power supply line PL1 respectively, which can reduce the voltage fluctuation of the first electrode E1 of the light-emitting element 100b and improve the brightness uniformity.

[0104] Figure 2 The pixel circuit shown Figure 1 has added a capacitor C2 compared to the pixel circuit shown Figure 1 The other parts are the same as the normal pixel circuit shown Figure 1 In the normal pixel circuit, within the time of each frame, the voltage on the first electrode E1 of the light-emitting element 100b needs to be initialized. The voltage on the first electrode E1 of the light-emitting element 100b is initialized to Vinit2. Since the voltage on the first electrode E1 of the light-emitting element 100b is different within the time of each frame, and this voltage is related to the data voltage on the write data line, during initialization, the voltage change amount △V on the first electrode E1 of the light-emitting element 100b is different. This voltage change amount △V will be coupled to the gate T3g of the driving transistor T3 through the parasitic capacitance, causing a change in the driving current of the light-emitting element 100b. In the pixel circuit of the display panel provided in some embodiments of the present disclosure, a capacitor C2 is added between the first electrode E1 of the light-emitting element 100b and the first power supply line PL1. This voltage change amount △V is released to the first power supply line PL1 through the capacitor C2, reducing the voltage coupled to the gate T3g of the driving transistor T3 through the parasitic capacitance.

[0105] As Figure 8 shown, a planarization layer PLN2 is provided between the first plate C21 and the second plate C22.

[0106] For example, C2 = ε * ε0 * S / d; where: S is the area of the opposing surfaces of the two plates of the capacitor, in square meters; d is the distance between the two plates, in meters, and ε is the relative permittivity of the insulating layer between the first plate C21 and the second plate C22; ε0 is the permittivity of free space 8.85×10 -12 , with the unit F / m.

[0107] To reduce the voltage coupled to the gate T3g of the driving transistor T3 through the parasitic capacitance, resulting in large fluctuations in the voltage on the gate T3g, in the display panel provided in some embodiments of the present disclosure, the capacitance C2 ranges from greater than 41.0 fF to less than 130.0 fF. That is, 41.0 fF < C2 < 130.0 fF.

[0108] For example, the capacitance C2 ranges from greater than 50.0 fF to less than 120.0 fF. Further for example, the capacitance C2 ranges from greater than 70.0 fF to less than 110.0 fF. Further for example, the capacitance C2 ranges from greater than 80.0 fF to less than 100.0 fF.

[0109] For example, in some embodiments, C1 < C2.

[0110] As Figure 3 and Figure 4 shown, in the display panel provided in some embodiments of the present disclosure, the gate T1g of the reset transistor T1 is connected to the reset control signal line RST1, the first pole T1a of the reset transistor T1 is connected to the initialization signal line INT1, the second pole T2a of the reset transistor T1 is connected to the gate T3g of the driving transistor T3, the reset transistor T1 is configured to reset the gate T3g of the driving transistor T3, and the pixel circuit 100a further includes a capacitor C3 provided between the gate of the reset transistor T1 and the first power supply line PL1. As Figure 3 and Figure 4 shown, the capacitor C3 includes a first plate C31 and a second plate C32.

[0111] Compared with the pixel circuit shown in Figure 2 , the pixel circuit shown in Figure 3 and Figure 4 has an additional capacitor C3. The second plate C32 of the capacitor C3 is connected to the first power supply line PL1, the first plate C31 of the capacitor C3 is connected to the gate T1g of the reset transistor T1, and the high-frequency component of the signal SCAN(N)(n)(RESET1) on the reset control signal line RST1 will be released to the first power supply line PL1 through the capacitor C3, reducing the coupling of this high-frequency component to the first node N1 through the gate-drain parasitic capacitance of the reset transistor T1 and avoiding fluctuations in the driving current of the driving transistor T3.

[0112] For example, C3 = ε * ε0 * S / d; where: S is the facing area of the two plates of the capacitor, in square meters; d is the distance between the two plates, in meters, ε is the relative permittivity of the insulating layer between the first plate C31 and the second plate C32; ε0 is the permittivity of free space 8.85×10 -12 , in units of F / m.

[0113] To reduce the coupling of the above high-frequency components to the first node N1 through the gate-drain parasitic capacitance of the reset transistor T1 and avoid fluctuations in the driving current of the driving transistor T3; in the display panel provided in some embodiments of the present disclosure, the capacitance C3 ranges from greater than 0.5 fF to less than 3.0 fF. That is, 0.5 fF < C3 < 3 fF.

[0114] For example, in some embodiments, C3 < C1, C3 < C2. For example, in some embodiments, C3 < C1 < C2.

[0115] As Figure 4 shown, in the display panel provided in some embodiments of the present disclosure, the pixel circuit 100a further includes a threshold compensation transistor T2. The first pole T2a of the threshold compensation transistor T2 is connected to the first pole T1a of the driving transistor T3. The second pole T2b of the threshold compensation transistor T2 is connected to the gate T3g of the driving transistor T3. The pixel circuit 100a further includes a capacitor C4 provided between the gate T2g of the threshold compensation transistor T2 and the first power line PL1. As Figure 4 shown, the capacitor C4 includes a first plate C41 and a second plate C42.

[0116] Compared with Figure 3 the pixel circuit shown, Figure 4 the pixel circuit shown in

[0117] adds a capacitor C4. The second plate C42 of the capacitor C4 is connected to the first power line PL1. The first plate C41 of the capacitor C4 is connected to the gate T2g of the threshold compensation transistor T2. The high-frequency components of the signal SCAN(N)(n) on the gate line GT1 will be released to the first power line PL1 through the capacitor C4, reducing the coupling of this high-frequency component to the first node N1 through the gate-drain parasitic capacitance of the threshold compensation transistor T2 and avoiding fluctuations in the driving current of the driving transistor T3. Figure 2 It should be noted that a capacitor C4 can also be added on the basis of the pixel circuit shown in

[0118] For example, C4 = ε * ε0 * S / d; where: S is the facing area of the two plates of the capacitor, in square meters; d is the distance between the two plates, in meters, ε is the relative permittivity of the insulating layer between the first plate C41 and the second plate C42; ε0 is the permittivity of free space 8.85×10 -12, unit F / m.

[0119] To reduce the coupling of the above high-frequency components to the first node N1 through the gate-drain parasitic capacitance of the threshold compensation transistor T2 and avoid fluctuations in the driving current of the driving transistor T3; in the display panel provided in some embodiments of the present disclosure, the capacitance C4 ranges from greater than 0.5 fF to less than 3.0 fF. That is, 0.5 fF < C4 < 3 fF. For example, in some embodiments, C4 < C1, C4 < C2. For example, in some embodiments, C4 < C1 < C2.

[0120] As Figure 5 shown, in the display panel provided in some embodiments of the present disclosure, the display panel further includes a reset control signal line RST2 and an initialization signal line INT2. Among them, the reset control signal line RST2 is configured to provide a reset control signal SCAN(P)(n + 1), that is, the reset control signal RESET2, to the pixel circuit 100a. The initialization signal line INT2 is configured to provide a second initialization signal Vinit2 to the pixel circuit 100a. The pixel circuit 100a further includes a reset transistor T7, and the reset transistor T7 is configured to reset the first electrode E1 of the light-emitting element 100b. The first pole T7a of the reset transistor T7 is connected to the initialization signal line INT2, the second pole T7b of the reset transistor T7 is connected to the first electrode E1 of the light-emitting element 100b, and the gate T7g of the reset transistor T7 is connected to the reset control signal line RST2. The pixel circuit 100a further includes a capacitor C5 provided between the gate T1g of the reset transistor T1 and the initialization signal line INT2.

[0121] As Figure 6 shown, in the display panel provided in some embodiments of the present disclosure, the pixel circuit 100a further includes a capacitor C5 provided between the gate T1g of the reset transistor T1 and the initialization signal line INT1.

[0122] As Figure 5 and Figure 6 shown, the capacitor C5 includes a first electrode plate C51 and a second electrode plate C52.

[0123] Based on the pixel circuit shown in Figure 2 adding the capacitor C5, the first electrode plate C51 of the capacitor C5 is connected to the initialization signal line INT1 or the initialization signal line INT2, and the second electrode plate C52 of the capacitor C5 is connected to the gate T1g of the reset transistor T1. The high-frequency components of the signal RESET1 on the reset control signal line RST1 will be released to the initialization signal line INT1 or the initialization signal line INT2 through the capacitor C5, reducing the coupling of this high-frequency component to the first node N1 through the gate-drain parasitic capacitance of the reset transistor T1 and avoiding fluctuations in the driving current of the driving transistor T3.

[0124] For example, C5 = ε * ε0 * S / d; where: S is the facing area of the two plates of the capacitor, in square meters; d is the distance between the two plates, in meters, ε is the relative permittivity of the insulating layer between the first plate C51 and the second plate C52; ε0 is the vacuum permittivity 8.85×10 -12 , in F / m.

[0125] In order to reduce the coupling of the above high-frequency components to the first node N1 through the gate-drain parasitic capacitance of the reset transistor T1 and avoid the driving current fluctuation of the driving transistor T3. In the display panel provided by some embodiments of the present disclosure, the capacitance C5 ranges from greater than 1.0 fF and less than 10.0 fF. That is, 1.0 fF < C5 < 10.0 fF. For example, in some embodiments, C5 < C1, C5 < C2. For example, in some embodiments, C5 < C1 < C2.

[0126] The display panel provided by the embodiments of the present disclosure includes the capacitor C1 and the capacitor C2, and may further include at least one of the capacitors C3 to C5.

[0127] As Figure 8 , FIG. 9A to FIG. 9K , FIG. 10A to FIG. 10I As shown, the barrier layer BR is disposed on the substrate BS, the polysilicon semiconductor layer SM1 is located on the barrier layer BR, the gate insulating layer GI1 is located on the polysilicon semiconductor layer SM1, the first conductive pattern layer LY1 is located on the gate insulating layer GI1, the interlayer insulating layer ILD1 is located on the first conductive pattern layer LY1, the second conductive pattern layer LY2 is located on the interlayer insulating layer ILD1, the gate insulating layer GI2 is located on the second conductive pattern layer LY2, the oxide semiconductor layer SM2 is located on the gate insulating layer GI2, the gate insulating layer GI3 is located on the oxide semiconductor layer SM2, the third conductive pattern layer LY3 is located on the gate insulating layer GI3, the interlayer insulating layer ILD2 is located on the third conductive pattern layer LY3, the fourth conductive pattern layer LY4 is located on the interlayer insulating layer ILD2, the planarization layer PLN1 is located on the fourth conductive pattern layer LY4, the fifth conductive pattern layer LY5 is located on the planarization layer PLN1, the planarization layer PLN2 is located on the fifth conductive pattern layer LY5, the first electrode E1 of the light-emitting element is located on the planarization layer PLN2, and the pixel defining layer PDL is located on the first electrode E1 of the light-emitting element and has an opening OPN to define the light-emitting region of the light-emitting element 100b. The light-emitting element 100b includes the first electrode E1, the light-emitting functional layer FL, and the second electrode E2. The encapsulation layer EPS covers the light-emitting element 100b.

[0128] As Figure 8As shown, the first electrode E1 includes a first portion E1a and a second portion E1b. The orthographic projection of the first portion E1a on the substrate overlaps with the orthographic projection of the opening OPN on the substrate, and the orthographic projection of the second portion E1b on the substrate overlaps with the orthographic projection of the via Vd on the substrate.

[0129] Fig.9A The polysilicon semiconductor layer SM1 is shown. For example, the material of the polysilicon semiconductor layer SM1 includes low-temperature polysilicon (LTPS), but is not limited thereto.

[0130] Fig. 9B The first conductive pattern layer LY1 is shown. As Fig. 9C shown, the first conductive pattern layer LY1 includes a light emission control signal line EML, a gate line GT2, and a first electrode plate C11 of the capacitor C1.

[0131] Fig. 9C The second conductive pattern layer LY2 is shown. As Fig. 9C shown, the second conductive pattern layer LY2 includes: a second electrode plate C12 of the capacitor C1, a reset control signal sub-line RSTa of the reset control signal line RST1, and a gate sub-line GTa of the gate line GT1. As Figure 7 , Fig. 9B , and Fig. 9C shown, the second electrode plate C12 has an opening OPN a to facilitate the connection of the electrode CEa to the first electrode plate C11.

[0132] Fig.9D The oxide semiconductor layer SM2 is shown. For example, the material of the oxide semiconductor layer SM2 includes indium gallium zinc oxide (IGZO), but is not limited thereto.

[0133] Fig.9E The third conductive pattern layer LY3 is shown. As Fig.9E shown, the third conductive pattern layer LY3 includes a reset control signal sub-line RSTb of the reset control signal line RST1 and a gate sub-line GTb of the gate line GT1.

[0134] Fig.9F The vias in the interlayer insulating layer ILD2 are shown. As Figure 7 and Fig.9F shown, the vias V1 to V10 penetrate the interlayer insulating layer ILD2.

[0135] Figure 9G The fourth conductive pattern layer LY4 is shown. As Figure 9GAs shown, the fourth conductive pattern layer LY4 includes an initialization signal line INT2, and connection electrodes CEa, CEb, CEc, CEd, CEe, and CEf. The components in the fourth conductive pattern layer LY4 are connected to the components below through vias penetrating the insulating layer. For example, the components in the fourth conductive pattern layer LY4 can be connected to the components in at least one of the polysilicon semiconductor layer SM1, the first conductive pattern layer LY1, the second conductive pattern layer LY2, the oxide semiconductor layer SM2, and the third conductive pattern layer LY3 through vias. That is, each connection electrode is connected to the conductive structure below through a via. The conductive structure includes components in at least one of the polysilicon semiconductor layer SM1, the first conductive pattern layer LY1, the second conductive pattern layer LY2, and the oxide semiconductor layer SM2.

[0136] Figure 9H Vias Va, Vb, and Vc in the planarization layer PLN1 are shown.

[0137] Fig.9I The fifth conductive pattern layer LY5 is shown. As Fig.9I shown, the fifth conductive pattern layer LY5 includes a data line DT and a first power line PL1.

[0138] Figure 9J Via Vd in the planarization layer PLN2 is shown.

[0139] Figure 9K The first electrode layer LY6 is shown. Figure 9K The first electrode E1 of the light-emitting element is shown. A plurality of first electrodes E1 are arranged at intervals.

[0140] In some embodiments of the present disclosure, as Figures 1 to 7 shown, the gate T2g of the threshold compensation transistor T2 and the gate T1g of the reset transistor T1 are cascaded to different output stages of a gate driver on array (GOA) on the array. Figures 2 to 6 The gate T2g of the threshold compensation transistor T2 and the gate T1g of the reset transistor T1 are shown cascaded to the nth stage and the (n - 1)th stage of the GOA respectively. n is a natural number greater than or equal to 2. The structure of the GOA can be selected in the common technology as needed.

[0141] In some embodiments of the present disclosure, as Figures 1 to 7 shown, the gate T2g of the threshold compensation transistor T2 and the gate T4g of the data writing transistor T4 are cascaded to the same output stage of the GOA. As Figures 1 to 7 shown, the data writing transistor T4 accesses the output signal of the corresponding P-type transistor, and the threshold compensation transistor T2 accesses the output signal of the corresponding N-type transistor.

[0142] FIG. 10A to FIG. 10I Shows a schematic diagram of a partial stacked structure. Fig. 10A Is a schematic diagram of the stack of the polysilicon semiconductor layer SM1 and the first conductive pattern layer LY1. Fig. 10A Shows the polysilicon semiconductor layer SM1 and the first conductive pattern layer LY1.

[0143] Fig. 10B Is a schematic diagram of the stack of the polysilicon semiconductor layer SM1, the first conductive pattern layer LY1, and the second conductive pattern layer LY2.

[0144] Fig. 10C Is a schematic diagram of the stack of the polysilicon semiconductor layer SM1, the first conductive pattern layer LY1, the second conductive pattern layer LY2, and the oxide semiconductor layer SM2.

[0145] Fig. 10B and Fig. 10C Shows the reset control signal sub-line RSTa. Fig. 10B and Fig. 10C Also shows the gate sub-line GTa.

[0146] The oxide semiconductor layer SM2 is formed after the second conductive pattern layer LY2. As Figure 7 and Fig. 10C shown, the reset control signal sub-line RSTa and the gate sub-line GTa in the second conductive pattern layer LY2 can serve as the bottom gate of the oxide thin film transistor.

[0147] Fig. 10D Shows a schematic diagram of the stack of the polysilicon semiconductor layer SM1, the first conductive pattern layer LY1, the second conductive pattern layer LY2, the oxide semiconductor layer SM2, and the third conductive pattern layer LY3.

[0148] As Figure 7 and Fig. 10D shown, the reset control signal sub-line RSTb and the gate sub-line GTb of the gate line GT1 can serve as the top gate of the oxide thin film transistor. A double-gate thin film transistor is used to reduce the leakage current.

[0149] Fig.10E Shows a schematic diagram of the stack of the polysilicon semiconductor layer SM1, the first conductive pattern layer LY1, the second conductive pattern layer LY2, the oxide semiconductor layer SM2, the third conductive pattern layer LY3, and the interlayer insulating layer ILD2. The interlayer insulating layer ILD2 is shown as a via.

[0150] Fig.10FA stacked schematic diagram of a polysilicon semiconductor layer SM1, a first conductive pattern layer LY1, a second conductive pattern layer LY2, an oxide semiconductor layer SM2, a third conductive pattern layer LY3, an interlayer insulating layer ILD2, and a fourth conductive pattern layer LY4 is shown.

[0151] Figure 10G A stacked schematic diagram of a polysilicon semiconductor layer SM1, a first conductive pattern layer LY1, a second conductive pattern layer LY2, an oxide semiconductor layer SM2, a third conductive pattern layer LY3, an interlayer insulating layer ILD2, a fourth conductive pattern layer LY4, and a fifth conductive pattern layer LY5 is shown.

[0152] Fig. 10H A stacked schematic diagram of the second conductive pattern layer LY2 and the third conductive pattern layer LY3 is shown.

[0153] Fig.10I A stacked schematic diagram of the first conductive pattern layer LY1, the fifth conductive pattern layer LY5, and the first electrode E1 of the light-emitting element is shown. As Figure 7 and Fig.10I shown, the pixel circuit includes a capacitor C1 and a capacitor C2.

[0154] As Figure 7 and Fig. 9C shown, the second electrode plate C12 of the capacitor C1 has an opening OPN a so that a via V1 connecting the gate T3g of the driving transistor T3 can be formed in a subsequent process, enabling the connection electrode CE a to be connected to the gate T3g of the driving transistor T3.

[0155] Fig. 10D The semiconductor layers of each transistor are shown. Fig. 10D The semiconductor layer T33 of the driving transistor T3, the semiconductor layer T43 of the data writing transistor T4, the semiconductor layer T23 of the threshold compensation transistor T2, the semiconductor layer T53 of the light-emitting control transistor T5, the semiconductor layer T63 of the light-emitting control transistor T6, the semiconductor layer T13 of the reset transistor T1, and the semiconductor layer T73 of the reset transistor T7 are shown. The portions of the signal lines overlapping with the respective semiconductor layers are the gates of the corresponding transistors. It can be seen from Fig. 10D that the reset transistor T1 and the threshold compensation transistor T2 are both double-gate transistors. The bottom gate of the double-gate transistor is located in the second conductive layer LY2, and the top gate of the double-gate transistor is located in the third conductive layer LY3. The portions of the second conductive layer LY2 overlapping with the semiconductor layers of the respective double-gate transistors are the bottom gates of the double-gate transistors, and the portions of the third conductive layer LY3 overlapping with the semiconductor layers of the respective double-gate transistors are the top gates of the double-gate transistors.

[0156] For example, in an embodiment of the present disclosure, the reset transistor T1 is an oxide transistor, and the oxide transistor has a double-gate structure. For example, in an embodiment of the present disclosure, the threshold compensation transistor T2 is an oxide transistor, and the oxide transistor has a double-gate structure. The double-gate structure means that the gate of the transistor includes a bottom gate and a top gate.

[0157] As Figure 7 , FIG. 9A to FIG. 9K , FIG. 10A to FIG. 10I shown, one end of the connection electrode CEa is connected to the gate T3g of the driving transistor T3 through the via V1, and the other end of the connection electrode CEa is connected to the second pole T1b of the reset transistor T1 (the second pole T1b of the reset transistor T1 also serves as the second pole T2b of the compensation transistor T2) through the via V2.

[0158] As Figure 7 , FIG. 9A to FIG. 9K , FIG. 10A to FIG. 10I shown, one end of the connection electrode CEb is connected to the first pole T6a of the light-emitting control transistor T6 (the first pole T6a of the light-emitting control transistor T6 also serves as the first pole T3a of the driving transistor T3) through the via V4, and the other end of the connection electrode CEb is connected to the first pole T2a of the threshold compensation transistor T2 through the via V3.

[0159] As Figure 7 , FIG. 9A to FIG. 9K , FIG. 10A to FIG. 10I shown, one end of the connection electrode CEf is connected to the first pole T5a of the light-emitting control transistor T5 through the via V8, and the other end of the connection electrode CEf is connected to the first power line PL1 through the via Va.

[0160] As Figure 7 , FIG. 9A to FIG. 9K , FIG. 10A to FIG. 10I shown, one end of the connection electrode CEc is connected to the initialization signal line INT1 through the via V6, and the other end of the connection electrode CEc is connected to the first pole T1a of the reset transistor T1 through the via V5.

[0161] As Figure 7 , FIG. 9A to FIG. 9K , FIG. 10A to FIG. 10I shown, one end of the connection electrode CEd is connected to the first pole T4a of the data writing transistor T4 through the via V7, and the other end of the connection electrode CEd is connected to the data line DT through the via Vc.

[0162] As Figure 7 , FIG. 9A to FIG. 9K , FIG. 10A to FIG. 10IAs shown, one end of the connection electrode CEe is connected to the second pole T6b of the light-emitting control transistor T6 through a via V9, and the other end of the connection electrode CEe is connected to the first electrode E1 of the light-emitting element through a via Vd.

[0163] As Figure 7 , FIG. 9A to FIG. 9K , FIG. 10A to FIG. 10I shown, the first power line PL1 is connected to the second electrode plate C12 of the capacitor C1 through a via Vb and is connected to the first pole T5a of the light-emitting control transistor T5.

[0164] As Figure 7 , FIG. 9A to FIG. 9K , FIG. 10A to FIG. 10I shown, the first electrode E1 of the light-emitting element is connected to the connection electrode CEe through a via Vd and is further connected to the second pole T6b of the light-emitting control transistor T6.

[0165] As Figure 7 , FIG. 9A to FIG. 9K , FIG. 10A to FIG. 10I shown, the initialization signal line INT2 is connected to the first pole T7a of the reset transistor through a via V10.

[0166] For example, as Figure 7 , FIG. 10D to FIG. 10H shown, the initialization signal line INT2 is arranged above the reset control signal line RST1 that provides the SCAN(N)(n - 1) signal to shield the influence of the second initialization signal Vinit2 on the reset transistor T1 and further shield the semiconductor layer of the reset transistor T1, so that the reset transistor T1 has a stable and relatively high on-state current and a low leakage current; to make the gate of the driving transistor T3 and the voltage of the storage capacitor more stable and not easily leak electricity. Thus, the driving current of the driving transistor T3 is more stable, the light-emitting efficiency of the light-emitting element is more stable, and the display quality is improved.

[0167] In some embodiments of the present disclosure, as Figure 7 shown, in order to reduce the influence of the second initialization signal Vinit2 on the semiconductor layer (channel) of the oxide thin film transistor (for example, the reset transistor T1), the positive projection of the initialization signal line INT2 on the substrate BS covers the positive projection of the semiconductor layer T13 of the reset transistor T1 on the substrate BS (as Fig. 10D shown) on the substrate BS to further shield the semiconductor layer T13 of the reset transistor T1. For example, as Figure 7 , Fig. 10D shown, the initialization signal line INT2 overlaps with the semiconductor layer T13 of the reset transistor T1.

[0168] In some embodiments of the present disclosure, as Figure 4As shown, the threshold compensation transistor T2 and the reset transistor T1 are both double-gate transistors. For example, the double-gate transistor includes a bottom gate and a top gate. For example, the threshold compensation transistor T2 and the reset transistor T1 adopt the form of double-gate thin film transistors (TFTs) to reduce leakage current.

[0169] As Figure 7 and Figure 10G shown, the gate T1g of the reset transistor T1 and the initialization signal line INT2 form a capacitor C5. The gate T1g of the reset transistor T1 and the initialization signal line INT2 overlap in the positive projection on the substrate, constituting two plates of the capacitor C5.

[0170] In Figure 7 it, the initialization signal line INT1 is located in the second conductive pattern layer LY2, the initialization signal line INT2 is located in the fourth conductive pattern layer LY4, and the initialization signal line INT2 overlaps with the gate part of the reset transistor T1 to form the capacitor C5.

[0171] As Figure 7 and Figure 10G shown, in the display panel provided by some embodiments of the present disclosure, the initialization signal line INT2 and the reset control signal line RST1 at least partially overlap to form two plates of the capacitor C5.

[0172] As Figures 1 to 7 shown, in the display panel provided by some embodiments of the present disclosure, the display panel further includes a data line DT, the data line DT is configured to provide a data signal to the pixel circuit 100a, and the pixel circuit 100a further includes a data writing transistor T4. The first pole and the second pole of the data writing transistor T4 are respectively connected to the data line DT and the second pole of the driving transistor T3.

[0173] As Figure 4 , Figure 7 and Figure 8 shown, the positive projection of the gate T3g of the driving transistor T3 on the substrate BS and the positive projection of the first power supply line PL1 on the substrate BS overlap to form a capacitor C1. That is, the gate T3g of the driving transistor T3 and the first power supply line PL1 form the capacitor C1. The second plate C12 of the capacitor C1 is located in the second conductive pattern LY2. As Figure 7 shown, the second plate C12 is connected to the first power supply line PL1 through a via Vb, and the first plate C12 of the capacitor C1 is located in the first conductive pattern LY1.

[0174] As Figure 4 and Figure 7As shown, the orthographic projection of the first electrode E1 of the light-emitting element 100b on the substrate substrate BS and the orthographic projection of the first power supply line PL1 on the substrate substrate BS overlap to form a capacitor C2. That is, the first electrode E1 of the light-emitting element 100b and the first power supply line PL1 form the capacitor C2.

[0175] As Figure 4 and Figure 7 shown, the orthographic projection of the first power supply line PL1 on the substrate substrate BS and the orthographic projection of the gate T1g of the reset transistor T1 on the substrate substrate BS overlap to form a capacitor C3. That is, the first power supply line PL1 and the gate T1g of the reset transistor T1 form the capacitor C3.

[0176] As Figure 4 and Figure 7 shown, the orthographic projection of the first power supply line PL1 on the substrate substrate BS and the orthographic projection of the gate T2g of the threshold compensation transistor T2 on the substrate substrate BS overlap to form a capacitor C4. That is, the first power supply line PL1 and the gate T2g of the threshold compensation transistor T2 form the capacitor C4.

[0177] As Figure 5 and Figure 7 shown, the orthographic projection of the gate T1g of the reset transistor T1 on the substrate substrate BS and the orthographic projection of the initialization signal line INT2 on the substrate substrate BS overlap to form a capacitor C5. That is, the gate T1g of the reset transistor T1 and the initialization signal line INT2 form the capacitor C5.

[0178] Thus, as Figure 7 shown, the display panel includes capacitors C1, C2, C3, C4, and C5. The specific details regarding capacitors C1 to C5 can be referred to the above description and will not be elaborated here.

[0179] Fig.11 This is a layout diagram of a display panel provided by an embodiment of the present disclosure. FIG. 12A to FIG. 12K It is Fig.11 a plan view of the single-layer structure in FIG. 12A to FIG. 12K The upper right corner of FIG. 13A to FIG. 13B It is Fig.11 a plan view of the stacked structure of some single layers in Fig.11 It shows the display panel 202.

[0180] Fig.13A It is Fig.11 a plan view of the first electrode of the light-emitting element and the vias penetrating the planarization layer in Fig. 13B It is Fig.11 a plan view of the fifth conductive pattern layer and the first electrode layer in

[0181] As Fig.11 , Fig.13A and Fig. 13B As shown in Fig.11 , Fig.13A , and Fig. 13B , the first electrodes E1 of the light-emitting elements of multiple sub-pixels 100 can be arranged in an array.

[0182] As Fig.11 shown, the direction X is the row direction of the sub-pixels, and the direction Y is the column direction of the sub-pixels. Fig.11 Four columns of sub-pixels are shown. Fig.11 The first column of sub-pixels 4001, the second column of sub-pixels 4002, the third column of sub-pixels 4003, and the fourth column of sub-pixels 4004 arranged in sequence along the direction X are shown.

[0183] As Fig.11 shown, the driving transistors of two adjacent sub-pixels in the same row are located between the data lines DT corresponding to these two sub-pixels, and the pixel circuits of two adjacent sub-pixels in the same row are arranged in a mirror image.

[0184] As Fig.11 , Figure 12K and Fig. 13B shown, between adjacent data lines DT, two columns of sub-pixels are provided, and between adjacent data lines and the two columns of sub-pixels corresponding to them form a data bar 400. Among them, one column of pixel circuits alternately drives the light-emitting elements of the first sub-pixel 101 and the second sub-pixel 102, and the other column of pixel circuits drives the light-emitting elements of the third sub-pixel 103. This driving method can be obtained through the arrangement of the first electrode E1 of the light-emitting element 100b.

[0185] As Fig.11 shown, in a data bar 400, the first electrodes E1 of the light-emitting elements 100b of the first sub-pixel 101 and the second sub-pixel 102 are located between adjacent data lines DT, and the first electrode E1 of the light-emitting element 100b of the third sub-pixel 103 overlaps with one of the two data lines DT and also overlaps with one of the two data lines DT corresponding to the adjacent data bar 400.

[0186] As Figure 4 and Fig.11 shown, the positive projection of the gate T3g of the driving transistor T3 on the substrate substrate BS and the positive projection of the first power line PL1 on the substrate substrate BS overlap to form a capacitor C1. That is, the gate T3g of the driving transistor T3 and the first power line PL1 form a capacitor C1.

[0187] As Figure 4 and Fig.11As shown, the orthographic projection of the first electrode E1 of the light-emitting element 100b on the substrate substrate BS and the orthographic projection of the first power line PL1 on the substrate substrate BS overlap to form a capacitor C2. That is, the first electrode E1 of the light-emitting element 100b and the first power line PL1 form a capacitor C2.

[0188] As Figure 4 and Fig.11 shown, the orthographic projection of the first power line PL1 on the substrate substrate BS and the orthographic projection of the gate T1g of the reset transistor T1 on the substrate substrate BS overlap to form a capacitor C3. That is, the first power line PL1 and the gate T1g of the reset transistor T1 form a capacitor C3.

[0189] As Figure 4 and Fig.11 shown, the orthographic projection of the first power line PL1 on the substrate substrate BS and the orthographic projection of the gate T2g of the threshold compensation transistor T2 on the substrate substrate BS overlap to form a capacitor C4. That is, the first power line PL1 and the gate T2g of the threshold compensation transistor T2 form a capacitor C4.

[0190] As Figure 5 and Fig.11 shown, the orthographic projection of the gate T1g of the reset transistor T1 on the substrate substrate BS and the orthographic projection of the initialization signal line INT2 on the substrate substrate BS overlap to form a capacitor C5. That is, the gate T1g of the reset transistor T1 and the initialization signal line INT2 form a capacitor C5.

[0191] Thus, as Fig.11 shown, the display panel includes a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, and a capacitor C5. The specific details regarding capacitors C1 to C5 can be referred to the above description and will not be elaborated here.

[0192] Fig.14 This is a layout diagram of a display panel provided by an embodiment of the present disclosure. Fig.15 It is Fig.14 a cross-sectional view along line B-B' in FIG. 16A to FIG. 16E It is Fig.14 a plan view of a single layer or multiple layers of the display panel in Fig.14 It shows the display panel 203.

[0193] For the first sub-pixel 101 and the second sub-pixel 102, the first power supply line PL1 overlapping with the first electrode E1 of the light-emitting element 100b is separated into two parts. The initialization signal line INT1 is routed in a network shape. The portion of the initialization signal line INT1 extending in the X direction is located in the second conductive pattern layer LY2, and the portion of the initialization signal line INT1 extending in the Y direction is located in the fourth conductive pattern layer LY4. The portion of the initialization signal line INT1 extending in the Y direction is located below the first electrode E1 of the light-emitting elements of the first sub-pixel 101 and the second sub-pixel 102, and is located between the two parts of the first power supply line PL1. The portion of the initialization signal line INT1 extending in the Y direction and the portion of the initialization signal line INT1 extending in the X direction are connected by vias; the initialization signal line INT2 is routed in a network shape. The portion of the initialization signal line INT2 extending in the X direction is located in the second conductive pattern layer LY2, and the portion of the initialization signal line INT2 extending in the Y direction is located below the first electrode E1 of the light-emitting elements of the third sub-pixel 101 and the second sub-pixel 102, and is located between the two parts of the first power supply line PL1. The portion of the initialization signal line INT2 extending in the X direction and the portion of the initialization signal line INT2 extending in the Y direction are connected by vias. The portion of the initialization signal line INT1 extending in the Y direction and the portion of the initialization signal line INT2 extending in the Y direction are alternately arranged in the X direction. The portion of the initialization signal line INT1 extending in the Y direction and the portion of the initialization signal line INT2 extending in the Y direction are located in different data columns 400.

[0194] As Fig.14 and Fig.16E shown, the initialization signal line INT2 does not overlap with the gate of the reset transistor T1, and the overlapping portion of the first power supply line PL1 and the top gate of the reset transistor T1 forms C3.

[0195] As Figure 4 and Fig.14 shown, the positive projection of the gate T3g of the driving transistor T3 on the substrate base BS and the positive projection of the first power supply line PL1 on the substrate base BS overlap to form a capacitor C1. That is, the gate T3g of the driving transistor T3 and the first power supply line PL1 form a capacitor C1.

[0196] As Figure 4 and Fig.14 shown, the positive projection of the first electrode E1 of the light-emitting element 100b on the substrate base BS and the positive projection of the first power supply line PL1 on the substrate base BS overlap to form a capacitor C2. That is, the first electrode E1 of the light-emitting element 100b and the first power supply line PL1 form a capacitor C2.

[0197] As Figure 4 and Fig.14As shown, the positive projection of the first power line PL1 on the substrate BS overlaps with the positive projection of the gate T1g of the reset transistor T1 on the substrate BS to form a capacitor C3. That is, the first power line PL1 and the gate T1g of the reset transistor T1 form the capacitor C3.

[0198] As Figure 4 and Fig.14 shown, the positive projection of the first power line PL1 on the substrate BS overlaps with the positive projection of the gate T2g of the threshold compensation transistor T2 on the substrate BS to form a capacitor C4. That is, the first power line PL1 and the gate T2g of the threshold compensation transistor T2 form the capacitor C4.

[0199] Thus, as Fig.14 shown, the display panel includes capacitors C1, C2, C3, and C4. The specific details regarding capacitors C1 to C4 can be referred to the previous description and will not be elaborated here. Of course, based on the layout of the display substrate Fig.14 shown, the shape of the initialization signal line INT2 can be adjusted so that the gate T1g of the reset transistor T1 and the initialization signal line INT2 form a capacitor C5.

[0200] Fig.17 FIG. is a layout diagram of another display panel provided by an embodiment of the present disclosure. Figure 18A It is Figure 17 a plan view of the fifth conductive pattern layer LY5 in Figure 18B It is Figure 17 a plan view of the fifth conductive pattern layer LY5 and the first electrode layer LY6 of the light-emitting element in Figure 18C It is Figure 17 a plan view of the fourth conductive pattern layer LY4 and the fifth conductive pattern layer LY5 in Figure 17 It shows the display panel 204.

[0201] As Figure 17 , Figure 18A and Figure 18B shown, in the display panel provided by some embodiments of the present disclosure, the display panel further includes a connection portion CP1. The first power conductive portion 301 and the second power conductive portion 302 are connected through the connection portion CP1. The first power conductive portion 301 and the second power conductive portion 302 are located in the same layer, and the connection portion CP1 is located in the same layer as the first power conductive portion 301 and the second power conductive portion 302. Of course, in other embodiments, the connection portion CP1 can also be located in a layer different from the first power conductive portion 301 and the second power conductive portion 302.

[0202] As Figure 17 , Figure 18A and Figure 18BAs shown, in the display panel provided by some embodiments of the present disclosure, the display panel further includes a connection portion CP2, and the second power conductive portion 302 and the third power conductive portion 303 are connected through the connection portion CP2. The connection portion CP2, the second power conductive portion 302, and the third power conductive portion 303 are located in the same layer. Of course, in other embodiments, the connection portion CP2 may also be located in a layer different from the first power conductive portion 301 and the second power conductive portion 302.

[0203] As Figure 17 , Figure 18A and Figure 18B shown, the first power conductive portion 301 and the second power conductive portion 302 are located in the same data column, and the second power conductive portion 302 and the third power conductive portion 303 are located in different data columns.

[0204] For example, the connection portion CP1 is set to at least one, as Figure 17 , Figure 18A and Figure 18B shown, the connection portion CP1 is set to two.

[0205] For example, the connection portion CP2 is set to at least one, as Figure 17 , Figure 18A and Figure 18B shown, the connection portion CP2 is set to two.

[0206] As Figure 17 , Figure 18A and Figure 18B shown, the connection portion CP1 and the connection portion CP2 are located in the fifth conductive pattern layer.

[0207] As Figure 4 and Figure 17 shown, the positive projection of the gate T3g of the driving transistor T3 on the substrate substrate BS and the positive projection of the first power supply line PL1 on the substrate substrate BS overlap to form a capacitor C1. That is, the gate T3g of the driving transistor T3 and the first power supply line PL1 form a capacitor C1.

[0208] As Figure 4 and Figure 17 shown, the positive projection of the first electrode E1 of the light-emitting element 100b on the substrate substrate BS and the positive projection of the first power supply line PL1 on the substrate substrate BS overlap to form a capacitor C2. That is, the first electrode E1 of the light-emitting element 100b and the first power supply line PL1 form a capacitor C2.

[0209] As Figure 4 and Figure 17As shown, the positive projection of the first power supply line PL1 on the substrate BS overlaps with the positive projection of the gate T1g of the reset transistor T1 on the substrate BS to form a capacitor C3. That is, the first power supply line PL1 and the gate T1g of the reset transistor T1 form the capacitor C3.

[0210] As Figure 4 and Figure 17 shown, the positive projection of the first power supply line PL1 on the substrate BS overlaps with the positive projection of the gate T2g of the threshold compensation transistor T2 on the substrate BS to form a capacitor C4. That is, the first power supply line PL1 and the gate T2g of the threshold compensation transistor T2 form the capacitor C4.

[0211] Thus, as Figure 17 shown, the display panel includes capacitors C1, C2, C3, and C4. The specific details regarding capacitors C1 to C4 can be referred to the previous description and will not be elaborated here.

[0212] Figure 19 This is a layout diagram of another display panel provided by an embodiment of the present disclosure. Figure 20A It is Figure 19 a plan view of the fourth conductive pattern layer LY4, the planarization layer PLN1, and the fifth conductive pattern layer LY5 in Figure 20B It is Figure 19 a plan view of the fourth conductive pattern layer LY4, the planarization layer PLN1, the fifth conductive pattern layer LY5, and the sixth conductive pattern layer LY6 in Figure 19 It shows the display panel 205.

[0213] As Figure 19 and Figure 20A shown, the display panel further includes a connection portion CP3, and the second power supply conductive portion 302 and the third power supply conductive portion 303 are connected through the connection portion CP3. The connection portion CP3 is located in the fourth conductive pattern layer LY4. The second power supply conductive portion 302 and the third power supply conductive portion 303 are respectively connected to the connection portion CP3 through vias H3 and H4. The vias H3 and H4 penetrate through the planarization layer PLN1.

[0214] As Figure 19 and Figure 20A shown, the connection portion CP3 is provided between two adjacent data columns 400.

[0215] As Figure 19 and Figure 20AAs shown, the orthographic projection of the connection portion CP3 on the substrate overlaps with the orthographic projection of the first electrode of the third sub-pixel 103 on the substrate. The ratio of the overlapping area between the first electrode of the third sub-pixel 103 and the connection portion CP3 to the area of the first electrode of the third sub-pixel 103 is r3, where 0 ≤ r3 < 0.5. In some other embodiments, 0 < r3 < 0.5.

[0216] As Figure 19 shown, the display panel includes capacitors C1, C2, C3, and C4. The specific details regarding capacitors C1 to C4 can be referred to as described previously and will not be elaborated here. Of course, based on the layout of the display substrate Figure 19 shown, the shape of the initialization signal line INT2 can be adjusted such that a capacitor C5 is formed between the gate T1g of the reset transistor T1 and the initialization signal line INT2.

[0217] Figure 21 This is a layout diagram of another display panel provided by an embodiment of the present disclosure. Figure 22A It is Figure 21 a plan view of the fourth conductive pattern layer LY4, the planarization layer PLN1, and the fifth conductive pattern layer LY5 in Figure 22B It is Figure 21 a plan view of the fourth conductive pattern layer, the planarization layer, the fifth conductive pattern layer, and the sixth conductive pattern layer in Figure 23 It is Figure 21 a cross-sectional view along line C-C' in Figure 20A It shows the display panel 206.

[0218] Figure 21 Compared with the display panel 205 shown in Figure 19 shown, the shape and size of the connection portion CP3 are adjusted.

[0219] As Figure 21 shown, between two adjacent data columns 400, a connection portion CP3 is provided. The connection portion CP3 is located below the first electrode E1 of the light-emitting element of the third sub-pixel 103. The ratio of the overlapping area between the connection portion CP3 and the first electrode E1 of the light-emitting element of the third sub-pixel 103 to the area of the first electrode E1 of the light-emitting element of the third sub-pixel 103 is 0.8 < r3 < 1.2, and the connection portion CP3 is located within the adjacent data columns 400.

[0220] Thus, as Figure 21 shown, the display panel includes capacitors C1, C2, C3, and C4. The specific details regarding capacitors C1 to C4 can be referred to as described previously and will not be elaborated here. Of course, based on Figure 20ABased on the layout of the display substrate shown, the shape of the initialization signal line INT2 can be adjusted so that a capacitor C5 is formed between the gate T1g of the reset transistor T1 and the initialization signal line INT2.

[0221] As Figure 11 , Figure 14 , Figure 17 , Figure 19 , Figure 21 As shown in, in the display panel provided by some embodiments of the present disclosure, a plurality of sub-pixels 100 are provided. The plurality of sub-pixels 100 include a first sub-pixel 101. The positive projection of the first electrode E1 of the light-emitting element 100b of the first sub-pixel 101 on the substrate substrate BS does not overlap with the positive projection of the data line DT on the substrate substrate BS. The overlapping area between the first electrode E1 of the first sub-pixel 101 and the first power supply line PL1 and the area of the first electrode E1 of the first sub-pixel 101 have a ratio of r1, where 0.8 < r1 < 1.

[0222] As Figure 11 , Figure 14 , Figure 17 , Figure 19 , Figure 21 As shown in, a partial area of the first power supply line PL1 is relatively large, which serves to flatten the first electrode E1 of the first sub-pixel 101, facilitating the improvement of the flatness of the first electrode E1 of the first sub-pixel 101 and the light-emitting functional layer thereon, and improving the display quality.

[0223] As Figure 9I As shown in, the first power supply line PL1 includes a first part PL1a and a second part PL1b. The dimension of the first part PL1a in the X direction is larger than the dimension of the second part PL1b in the X direction.

[0224] As Figure 9I As shown in, the dimension of the first part PL1a in the X direction is larger than the dimension of the first part PL1a in the Y direction.

[0225] As Figure 11 , Figure 14 , Figure 17 , Figure 19 , Figure 21 As shown in, in the display panel provided by some embodiments of the present disclosure, the plurality of sub-pixels 100 include a second sub-pixel 102. The light-emitting color of the second sub-pixel 102 is different from that of the first sub-pixel 101. The positive projection of the first electrode E1 of the light-emitting element 100b of the second sub-pixel 102 on the substrate substrate BS does not overlap with the positive projection of the data line DT on the substrate substrate BS. The overlapping area between the first electrode E1 of the second sub-pixel 102 and the first power supply line PL1 and the area of the first electrode E1 of the second sub-pixel 102 have a ratio of r2, where 0.8 < r2 < 1.

[0226] As Figure 11 , Figure 14 , Figure 17 , Figure 19 , Figure 21 shown, the partial area of the first power line PL1 is relatively large, which serves to level the first electrode E1 of the second sub-pixel 102, facilitating the improvement of the flatness of the first electrode E1 of the second sub-pixel 102 and the light-emitting functional layer thereon, and improving the display quality.

[0227] As Figure 11 , Figure 14 , Figure 17 , and Figure 19 shown, in the display panel provided by some embodiments of the present disclosure, the plurality of sub-pixels 100 include a third sub-pixel 103. The light-emitting color of the third sub-pixel 103 is different from that of the first sub-pixel 101 and different from that of the second sub-pixel 102. The positive projection of the first electrode E1 of the light-emitting element 100b of the third sub-pixel 103 on the substrate substrate BS overlaps with the positive projection of the data line DT on the substrate substrate BS. The ratio of the overlapping area of the first electrode E1 of the third sub-pixel 103 and the first power line PL1 to the area of the first electrode E1 of the third sub-pixel 103 is r3, where 0 < r3 < 0.4. As Figure 11 , Figure 14 , Figure 17 , and Figure 19 shown, r3 < r1, r3 < r2.

[0228] As Figure 11 , Figure 14 , Figure 17 , Figure 19 and Figure 21 shown, in the display panel provided by some embodiments of the present disclosure, the sub-pixels 100 are provided as a plurality. The plurality of sub-pixels 100 form a plurality of data bars 400 arranged along the direction X. Each data bar 400 extends along the direction Y. The data bar 400 includes a first column of sub-pixels 100 and a second column of sub-pixels 100. The data line DT includes a first data line DT and a second data line DT. The first column of sub-pixels 100 is connected to the first data line DT, and the second column of sub-pixels 100 is connected to the second data line DT. The pixel circuits 100a for driving the first column of sub-pixels 100 and the pixel circuits 100a for driving the second column of sub-pixels 100 are located between the first data line DT and the second data line DT. The first column of sub-pixels 100 includes a plurality of first sub-pixels 101 and a plurality of second sub-pixels 102 arranged alternately along the direction Y, and the second column of sub-pixels 100 includes a plurality of third sub-pixels 103 arranged along the direction Y.

[0229] In the display panel provided by some embodiments of the present disclosure, the positive projection of the first electrode E1 of the light-emitting element 100b of the first sub-pixel 101 on the substrate substrate BS does not overlap with the positive projection of the data line DT on the substrate substrate BS, and the overlapping area between the first electrode E1 of the first sub-pixel 101 and the first power supply line PL1 and the area of the first electrode E1 of the first sub-pixel 101 is a ratio of r1.

[0230] As Figure 11 , Figure 14 , Figure 17 , and Figure 19 shown, the positive projection of the first electrode E1 of the light-emitting element 100b of the second sub-pixel 102 on the substrate substrate BS does not overlap with the positive projection of the data line DT on the substrate substrate BS, and the overlapping area between the first electrode E1 of the second sub-pixel 102 and the first power supply line PL1 and the area of the first electrode E1 of the second sub-pixel 102 is a ratio of r2.

[0231] As Figure 11 , Figure 14 , Figure 17 , and Figure 19 shown, the emission colors of every two of the first sub-pixel 101, the second sub-pixel 102, and the third sub-pixel 103 are different. The positive projection of the first electrode E1 of the light-emitting element 100b of the third sub-pixel 103 on the substrate substrate BS overlaps with the positive projection of the data line DT on the substrate substrate BS, and the overlapping area between the first electrode E1 of the third sub-pixel 103 and the first power supply line PL1 and the area of the first electrode E1 of the third sub-pixel 103 is a ratio of r3, where r3 < r1 and r3 < r2.

[0232] As Figure 11 , Figure 14 , Figure 17 , and Figure 19 shown, in the display panel provided by some embodiments of the present disclosure, 0.8 < r1 < 1, 0.8 < r2 < 1, and 0 < r3 < 0.4.

[0233] As Figure 14 and Figure 16C shown, in the display panel provided by some embodiments of the present disclosure, the first power supply line PL1 includes a first power supply conductive portion 301 and a second power supply conductive portion 302 spaced apart in the Y direction. As Figure 14 , Figure 16A and Figure 16BAs shown, the initialization signal line INT1 includes a first initialization conductive portion 311 extending in the X direction and a second initialization conductive portion 312 extending in the Y direction. The first initialization conductive portion 311 and the second initialization conductive portion 312 are connected. The orthographic projection of the second initialization conductive portion 312 on the substrate substrate BS is located between the orthographic projection of the first power conductive portion 301 on the substrate substrate BS and the orthographic projection of the second power conductive portion 302 on the substrate substrate BS. As Figure 14 shown, the first initialization conductive portion 311 and the second initialization conductive portion 312 are connected through a via H1.

[0234] As Figure 14 and Figure 16D shown, in the display panel provided by some embodiments of the present disclosure, the orthographic projection of the second initialization conductive portion 312 on the substrate substrate BS overlaps with the orthographic projections of the first electrodes E1 of the first sub-pixel 101 and the second sub-pixel 102 on the substrate substrate BS.

[0235] As Figure 14 and Figure 16C shown, in the display panel provided by some embodiments of the present disclosure, the first power supply line PL1 includes a third power conductive portion 303 and a fourth power conductive portion 304 spaced apart in the Y direction. As Figure 14 and Figure 16C shown, the third power conductive portion 303 and the fourth power conductive portion 304 are located in the same data column. As Figure 14 、 Figure 16A and Figure 16B shown, the initialization signal line INT2 includes a third initialization conductive portion 313 extending in the X direction and a fourth initialization conductive portion 314 extending in the Y direction. The third initialization conductive portion 313 and the fourth initialization conductive portion 314 are connected; the orthographic projection of the fourth initialization conductive portion 314 on the substrate substrate BS is located between the orthographic projection of the third power conductive portion 303 on the substrate substrate BS and the orthographic projection of the fourth power conductive portion 304 on the substrate substrate BS. As Figure 14 shown, the third initialization conductive portion 313 and the fourth initialization conductive portion 314 are connected through a via H2.

[0236] As Figure 14 and Figure 16D shown, in the display panel provided by some embodiments of the present disclosure, the orthographic projection of the fourth initialization conductive portion 314 on the substrate substrate BS overlaps with the orthographic projections of the first electrodes E1 of the first sub-pixel 101 and the second sub-pixel 102 on the substrate substrate BS.

[0237] As Figure 14As shown, in the display panel provided by some embodiments of the present disclosure, a plurality of second initialization conductive portions 312 and a plurality of fourth initialization conductive portions 314 are alternately arranged along the direction Y.

[0238] In the display panel provided by some embodiments of the present disclosure, the second initialization conductive portion 312 and the fourth initialization conductive portion 314 are located in different data bars 400.

[0239] As Figure 4 , Figure 14 and Figure 16E shown, a capacitor C1 is formed by the gate T3g of the driving transistor T3 and the first power supply line PL1.

[0240] As Figure 4 , Figure 14 and Figure 16E shown, a capacitor C2 is formed by the first electrode E1 of the light-emitting element 100b and the first power supply line PL1.

[0241] As Figure 4 , Figure 14 and Figure 16E shown, in the display panel provided by some embodiments of the present disclosure, the orthographic projection of the first power supply line PL1 on the substrate substrate BS overlaps with the orthographic projection of the gate T1g of the reset transistor T1 on the substrate substrate BS to form a capacitor C3.

[0242] As Figure 4 , Figure 14 and Figure 16E shown, the orthographic projection of the first power supply line PL1 on the substrate substrate BS overlaps with the orthographic projection of the gate T2g of the threshold compensation transistor T2 on the substrate substrate BS to form a capacitor C4.

[0243] As Figure 17 , Figure 18B and Figure 18C shown, the size of the connecting portion CP1 in the direction Y is smaller than the size of the portion of the first power supply line PL1 overlapping with the first electrode E1 of the light-emitting element in the direction Y. To reduce the overlapping size of the first power supply line PL1 and the second initialization conductive portion 312 and reduce the influence of the signal on the first power supply line PL1 on the signal on the initialization signal line INT1.

[0244] As Figure 17 , Figure 18B and Figure 18C shown, for the first sub-pixel 101, the size of the connecting portion CP1 in the direction Y is smaller than the minimum size of the first electrode E1 of the first sub-pixel 101 in the direction Y.

[0245] As Figure 17 , Figure 18B and Figure 18CAs shown, for the second sub-pixel 102, the size of the connecting portion CP1 in the Y direction is smaller than the minimum size of the first electrode E1 of the second sub-pixel 102 in the Y direction.

[0246] As Figures 19 to 22A shown, the orthographic projection of the first power supply line PL1 on the substrate does not overlap with the orthographic projection of the second initialization conductive portion 312 on the substrate.

[0247] As Figure 17 、 Figure 18B and Figure 18C shown, the size of the connecting portion CP2 in the Y direction is smaller than the size of the portion of the first power supply line PL1 overlapping with the first electrode E1 of the light-emitting element in the Y direction. To reduce the overlapping size of the first power supply line PL1 and the fourth initialization conductive portion 314, and reduce the influence of the signal on the first power supply line PL1 on the signal on the initialization signal line INT2.

[0248] As Figures 19 to 22A shown, the orthographic projection of the first power supply line PL1 on the substrate does not overlap with the orthographic projection of the fourth initialization conductive portion 314 on the substrate.

[0249] In the display panel provided by some embodiments of the present disclosure, as Figure 21 、 Figures 22A to 22B shown, the orthographic projection of the connecting portion CP3 on the substrate substrate BS overlaps with the orthographic projection of the first electrode E1 of the third sub-pixel 103 on the substrate substrate BS. The ratio of the overlapping area of the first electrode E1 of the third sub-pixel 103 and the connecting portion CP3 to the area of the first electrode E1 of the third sub-pixel 103 is r3, and 0.8 < r3 < 1.

[0250] As Figure 19 and Figure 20B shown, the orthographic projection of the connecting portion CP3 on the substrate does not overlap with the orthographic projection of the first electrode E1 of the third sub-pixel 103 on the substrate.

[0251] As Figure 21 and Figure 22B shown, the orthographic projection of the connecting portion CP3 on the substrate overlaps with the orthographic projection of the first electrode E1 of the third sub-pixel 103 on the substrate.

[0252] By adjusting Figure 19 and Figure 20A shown shape of the connecting portion CP3, the connecting portion CP3 as Figure 22A shown is formed, as Figure 21 、 Figures 22A to 22BAs shown, by setting a connection part CP3 with a larger area, the first electrode E1 of the third sub-pixel 103 can be made flatter, improving the flatness of the first electrode E1 of the third sub-pixel 103 and the light-emitting functional layer thereon, and improving the display quality.

[0253] For example, in the embodiments of the present disclosure, the turn-on voltage refers to the voltage that can turn on the first and second poles of the corresponding transistor, and the turn-off voltage refers to the voltage that can turn off the first and second poles of the corresponding transistor. When the transistor is a P-type transistor, the turn-on voltage is a low voltage (e.g., 0V), and the turn-off voltage is a high voltage (e.g., 5V); when the transistor is an N-type transistor, the turn-on voltage is a high voltage (e.g., 5V), and the turn-off voltage is a low voltage (e.g., 0V). Figure 24 The shown driving waveform has a low turn-on voltage (e.g., 0V) for the P-type transistor and a high turn-off voltage (e.g., 5V), and a high turn-on voltage (e.g., 5V) for the N-type transistor and a low turn-off voltage (e.g., 0V).

[0254] In the embodiments of the present disclosure, the threshold compensation transistor T2 and the first reset transistor T1 are both N-type thin-film transistors, and the remaining transistors are P-type thin-film transistors.

[0255] In some drawings, SCAN(N)(n) represents the gate line of the N-type thin-film transistor in the nth row, i.e., the gate line GT1. SCAN(P)(n) represents the gate line of the P-type thin-film transistor in the nth row, i.e., the gate line GT2. SCAN(N)(n - 1) represents the reset control signal line of the N-type thin-film transistor in the (n - 1)th row, and can also represent the gate line of the N-type thin-film transistor in the (n - 1)th row. SCAN(N)(n + 1) represents the reset control signal line of the N-type thin-film transistor in the (n + 1)th row, and can also represent the gate line of the N-type thin-film transistor in the (n + 1)th row. As Figure 2 shown, the gate T2g of the threshold compensation transistor T2 is cascaded to the nth stage of the GOA to be provided with the scan signal of the nth row of the N-type transistor. The gate T1g of the first reset transistor T1 is cascaded to the (n - 1)th stage of the GOA to be provided with the scan signal of the (n - 1)th row of the N-type transistor. The gate T4g of the data writing transistor T4 is cascaded to the nth stage of the GOA to be provided with the scan signal of the nth row of the P-type transistor. The nth stage of the GOA includes the scan signal of the nth row of the corresponding N-type transistor and the scan signal of the nth row of the corresponding P-type transistor.

[0256] For example, referring to Figure 7 、 Figure 8 、 Figures 9A to 9K 、 Figures 10A to 10IAs shown, the display panel 201 includes a first conductive pattern layer LY1, a second conductive pattern layer LY2, a third conductive pattern layer LY3, a fourth conductive pattern layer LY4, a fifth conductive pattern layer LY5, and a sixth conductive pattern layer LY6 that are sequentially arranged. The first conductive pattern layer LY1 is closer to the substrate base plate BS than the sixth conductive pattern layer LY6.

[0257] For example, referring to Figure 7 , Figure 8 , Figures 9A to 9K , Figures 10A to 10I As shown, the capacitor C1 includes a first electrode plate C11 and a second electrode plate C12. The gate T3g of the driving transistor T3 serves as the first electrode plate C11 of the capacitor C1 and is located in the first conductive pattern layer LY1. The second electrode plate C12 of the capacitor C1 is located in the second conductive pattern layer LY2 and is connected to the first power supply line PL1.

[0258] For example, referring to Figure 7 , Figure 8 , Figures 9A to 9K , Figures 10A to 10I As shown, the two electrode plates of the capacitor C2 include the first electrode of the light-emitting element located in the sixth conductive pattern layer LY6 and the first power supply line PL1 located in the fifth conductive pattern layer LY5.

[0259] For example, referring to Figure 7 , Figure 8 , Figures 9A to 9K , Figures 10A to 10I As shown, the two electrode plates of the capacitor C3 include the top gate in the gate of the first reset transistor located in the third conductive pattern layer LY3 and the first power supply line PL1 located in the fifth conductive pattern layer LY5.

[0260] For example, referring to Figure 7 , Figure 8 , Figures 9A to 9K , Figures 10A to 10I As shown, the two electrode plates of the capacitor C4 include the top gate in the gate of the threshold compensation transistor located in the third conductive pattern layer LY3 and the first power supply line PL1 located in the fifth conductive pattern layer LY5.

[0261] For example, referring to Figure 7 , Figure 8 , Figures 9A to 9K , Figures 10A to 10I As shown, the two electrode plates of the capacitor C5 include the top gate in the gate of the first reset transistor located in the third conductive pattern layer LY3 and the initialization signal line INT2 located in the fourth conductive pattern layer LY4.

[0262] For example, referring to Figure 7 , Figure 11 , Figure 14 , Figure 17As shown, the bottom gates in the gates of the first reset transistor and the bottom gates in the gates of the threshold compensation transistors are both located in the second conductive pattern layer LY2.

[0263] The display panels 201 - 202 include capacitors C1 - C5. In the other display panels 203 - 206, capacitor C5 is not included. The setting positions of the respective plates of the remaining capacitors can be referred to the settings in the display panel 201, and will not be elaborated here.

[0264] For example, in the embodiments of the present disclosure, each capacitor (capacitor C1 to capacitor C5) may refer to a capacitor within the same sub - pixel. For example, a sub - pixel includes a light - emitting element and a pixel circuit connected to the light - emitting element. For example, as Figure 7 , Figure 11 , Figure 14 , Figure 17 , Figure 19 , and Figure 21 As shown, in the embodiments of the present disclosure, the gate of the transistor and the signal line connected to the gate may be an integral structure. For example, the gate T1g of the reset transistor T1 and the reset control signal line RST1 are an integral structure, and the gate T2g of the threshold compensation transistor T2 and the gate line GT1 are an integral structure.

[0265] Figure 24 is Figures 1 to 6 the signal waveform timing diagram of the pixel circuit. As Figure 24 shown, within one frame display period, the driving method of the sub - pixel includes a first reset stage P1, a data writing and threshold compensation stage P2, a second reset stage P3, and a light - emitting stage P4.

[0266] Referring to Figures 1 to 6 , and Figure 24 shown, in the first reset stage P1, the reset transistor T transmits the first initialization signal (initialization voltage Vinit) Vinit1 to the gate of the driving transistor T3 and is stored by the storage capacitor Cst, resetting the driving transistor T3 and eliminating the data stored during the previous (previous frame) light emission.

[0267] Referring to Figures 1 to 6 , and Figure 24 shown, in the data writing and threshold compensation stage P2, the data writing transistor T4 transmits the data signal DATA to the second pole of the driving transistor T3, and the threshold compensation transistor T2 conducts to connect the driving transistor T3 into a diode structure, thereby charging the gate of the driving transistor T3 until the gate voltage of the driving transistor T3 is VDATA + Vth, at which time the driving transistor T3 is cut off.

[0268] In the second reset phase P3, the reset transistor T7 transmits the second initialization signal (initialization voltage Vinit) Vinit2 to the first electrode E1 of the light-emitting element 100b to reset the light-emitting element 100b.

[0269] In the light-emitting phase P4, the light-emitting control transistors T5 and T6 are in the conducting state. The first voltage signal VDD is transmitted through the light-emitting control transistor T5 to the second pole of the driving transistor T3. The gate voltage of the driving transistor T3 is maintained at VDATA + Vth. The light-emitting current I flows into the light-emitting element 100b through the light-emitting control transistor T5, the driving transistor T3, and the light-emitting control transistor T6, and the light-emitting element 100b emits light.

[0270] For example, the substrate substrate BS, the barrier layer BR, the buffer layer BF, the gate insulating layer GI1, the interlayer insulating layer ILD0, the interlayer insulating layer ILD1, the gate insulating layer GI2, the interlayer insulating layer ILD2, the planarization layer PLN1, the planarization layer PLN2, and the pixel defining layer PDL are all made of insulating materials. For example, the substrate substrate BS includes flexible materials such as polyimide, but is not limited thereto. At least one of the barrier layer BR, the buffer layer BF, the gate insulating layer GI1, the interlayer insulating layer ILD0, the interlayer insulating layer ILD1, the gate insulating layer GI2, and the interlayer insulating layer ILD2 is made of an inorganic insulating material or an organic insulating material. For example, the inorganic insulating materials include silicon oxide, silicon nitride, silicon oxynitride, etc., and the organic insulating materials include resins, but are not limited thereto. For example, the planarization layer PLN1, the planarization layer PLN2, and the pixel defining layer PDL can be made of organic materials. For example, the organic materials include resins, but are not limited thereto. For example, the planarization layer PLN1, the planarization layer PLN2, and the pixel defining layer PDL can be made of polyimide materials, but are not limited thereto.

[0271] For example, the first conductive pattern layer LY1, the second conductive pattern layer LY2, the third conductive pattern layer LY3, the fourth conductive pattern layer LY4, and the fifth conductive pattern layer LY5 are all made of metal materials, and the specific materials can be determined according to needs.

[0272] For example, the material of the first electrode E1 includes silver (Ag) and indium tin oxide (ITO). The first electrode E1 has a three-layer stacked structure of ITO / Ag / ITO, but is not limited thereto.

[0273] For example, the materials of the first conductive pattern layer LY1, the second conductive pattern layer LY2, and the third conductive pattern layer LY3 all include molybdenum (Mo), the material of the fourth conductive pattern layer LY4 includes titanium (Ti) and aluminum (Al), the material of the fifth conductive pattern layer LY5 includes titanium (Ti) and aluminum (Al), and the fourth conductive pattern layer LY4 and the fifth conductive pattern layer LY5 may both adopt a structure of three-layer superposition of Ti / Al / Ti, but are not limited thereto.

[0274] In the embodiments of the present disclosure, the patterns and vias of each single layer can be fabricated by a patterning process. For example, forming a specific pattern includes forming a thin film, forming a photoresist pattern on the thin film, and using the photoresist pattern as a mask to pattern the thin film to form the specific pattern. The first conductive pattern layer LY1, the second conductive pattern layer LY2, the third conductive pattern layer LY3, the fourth conductive pattern layer LY4, the fifth conductive pattern layer LY5, and the vias in the insulating layer can all be formed by this method. For the semiconductor layer SM1, a semiconductor pattern can be first formed, an insulating layer can be formed on the semiconductor pattern, and the first conductive pattern layer LY1 can be formed on the insulating layer. Then, using the first conductive pattern layer LY1 as a mask, the semiconductor pattern is doped to form a semiconductor layer SM1 including a channel and source and drain regions on both sides of the channel.

[0275] For example, the active layer of each transistor may include a source region, a drain region, and a channel (semiconductor layer) located between the source region and the drain region. For example, the channel has semiconductor characteristics; the source region and the drain region are on both sides of the channel and may be doped with impurities and thus have conductivity, and can be used as the first and second poles of the transistor respectively. One of the first and second poles of the transistor is the source, and the other of the first and second poles of the transistor is the drain.

[0276] For example, the materials for fabricating the active layer (semiconductor layer, semiconductor pattern) may include oxide semiconductors, organic semiconductors, or amorphous silicon, polycrystalline silicon, etc. For example, the oxide semiconductor includes metal oxide semiconductors (such as indium gallium zinc oxide (IGZO)), and the polycrystalline silicon includes low-temperature polycrystalline silicon or high-temperature polycrystalline silicon, etc. The embodiments of the present disclosure do not limit this. It should be noted that the above-mentioned source region and drain region may be regions doped with n-type impurities or p-type impurities, and the embodiments of the present disclosure do not limit this.

[0277] It should be noted that the layout of the sub-pixels of the display panel provided by the embodiments of the present disclosure is not limited to Figure 5 as shown, and can be in Figure 5Transformations are performed on this basis to form other layout diagrams. The above is described by taking the sub-pixels including seven transistors as an example, but the embodiments of the present disclosure are not limited thereto. For example, each sub-pixel 100 may include a pixel circuit and a light-emitting element having a circuit structure such as 7T1C, 8T2C, or 4T1C in the art. The pixel circuit operates under the control of a data signal transmitted through a data line, a gate scan signal transmitted through a gate line, and a light-emitting control signal provided by a light-emitting control signal line to drive the light-emitting element to emit light so as to implement operations such as display.

[0278] The embodiments of the present disclosure are described by taking the pixel circuit of 7T1C as an example, and the embodiments of the present disclosure include but are not limited to this. It should be noted that the embodiments of the present disclosure do not limit the number of thin-film transistors and the number of capacitors included in the pixel circuit. For example, in some other embodiments, the pixel circuit of the display panel may also be a structure including other numbers of transistors, such as 7T2C structure, 6T1C structure, 6T2C structure, or 9T2C structure, and the embodiments of the present disclosure do not limit this. Of course, the display panel may also include a pixel circuit with less than seven transistors.

[0279] It should be noted that, for clarity, in the drawings used to describe the embodiments of the present disclosure, the thickness of a layer or region may be enlarged. It can be understood that when an element such as a layer, a film, a region, or a substrate is referred to as being "on" or "under" another element, the element may be "directly" on or under the other element, or there may be an intermediate element.

[0280] In the embodiments of the present disclosure, a patterning or patterning process may only include a lithography process, or include a lithography process and an etching step, or may include other processes for forming a predetermined pattern such as printing and inkjet. The lithography process refers to a process including film formation, exposure, development, etc., and uses a photoresist, a mask, an exposure machine, etc. to form a pattern. The corresponding patterning process can be selected according to the structure formed in the embodiments of the present disclosure.

[0281] As described above, the above is only the specific implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of changes or substitutions, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A display panel, comprising: a substrate; sub-pixels located on the substrate, including a pixel circuit and a light-emitting element, the pixel circuit being configured to drive the light-emitting element, the light-emitting element including a first electrode, a second electrode, and a light-emitting functional layer located between the first electrode and the second electrode; and a first power supply line configured to provide a constant first power supply voltage to the pixel circuit, wherein the pixel circuit includes a driving transistor, a first capacitor provided between the gate of the driving transistor and the first power supply line, the first electrode of the light-emitting element being connected to the first pole of the driving transistor, the second pole of the driving transistor being connected to the first power supply line, and the pixel circuit further includes a second capacitor provided between the first electrode of the light-emitting element and the first power supply line, the pixel circuit further includes a threshold compensation transistor, the first pole of the threshold compensation transistor being connected to the first pole of the driving transistor, the second pole of the threshold compensation transistor being connected to the gate of the driving transistor, and the pixel circuit further includes a fourth capacitor provided between the gate of the threshold compensation transistor and the first power supply line.

2. The display panel according to claim 1, wherein, The display panel further includes a first reset control signal line and a first initialization signal line, wherein the first reset control signal line is configured to provide a first reset control signal to the pixel circuit, the first initialization signal line is configured to provide a first initialization signal to the pixel circuit, the pixel circuit further includes a first reset transistor, the gate of the first reset transistor being connected to the first reset control signal line, the first pole of the first reset transistor being connected to the first initialization signal line, the second pole of the first reset transistor being connected to the gate of the driving transistor, and the first reset transistor is configured to reset the gate of the driving transistor.

3. The display panel according to claim 2, wherein, The pixel circuit further includes a third capacitor provided between the gate of the first reset transistor and the first power supply line, and a planarization layer is provided between the two plates of the third capacitor.

4. The display panel according to claim 2, wherein, The pixel circuit further includes a fifth capacitor provided between the gate of the first reset transistor and the first initialization signal line.

5. The display panel according to claim 1 further includes a second reset control signal line and a second initialization signal line, wherein, The second reset control signal line is configured to provide a second reset control signal to the pixel circuit, the second initialization signal line is configured to provide a second initialization signal to the pixel circuit, the pixel circuit further includes a second reset transistor, the second reset transistor being configured to reset the first electrode of the light-emitting element, the first pole of the second reset transistor being connected to the second initialization signal line, the second pole of the second reset transistor being connected to the first electrode of the light-emitting element, and the gate of the second reset transistor being connected to the second reset control signal line.

6. The display panel according to claim 5, wherein, The pixel circuit further includes a first reset transistor, and the pixel circuit further includes a fifth capacitor provided between the gate of the first reset transistor and the second initialization signal line.

7. The display panel according to claim 5, wherein, The display panel further includes a first reset control signal line and a first initialization signal line. Among them, the first reset control signal line is configured to provide a first reset control signal to the pixel circuit, and the first initialization signal line is configured to provide a first initialization signal to the pixel circuit. The pixel circuit further includes a first reset transistor. The gate of the first reset transistor is connected to the first reset control signal line, the first pole of the first reset transistor is connected to the first initialization signal line, and the second pole of the first reset transistor is connected to the gate of the driving transistor. The first reset transistor is configured to reset the gate of the driving transistor, and the second initialization signal line at least partially overlaps with the first reset control signal line.

8. The display panel according to claim 1 further includes a data line, wherein, The data line is configured to provide a data signal to the pixel circuit. The pixel circuit further includes a data writing transistor. The first pole and the second pole of the data writing transistor are respectively connected to the data line and the second pole of the driving transistor.

9. The display panel according to claim 8, wherein, The sub-pixels are provided in multiple numbers. The multiple sub-pixels include a first sub-pixel. The positive projection of the first electrode of the light-emitting element of the first sub-pixel on the substrate does not overlap with the positive projection of the data line on the substrate. The ratio of the overlapping area between the first electrode of the first sub-pixel and the first power supply line to the area of the first electrode of the first sub-pixel is r1, and 0.8 < r1 < 1.

10. The display panel according to claim 9, wherein, The multiple sub-pixels include a second sub-pixel. The light-emitting color of the second sub-pixel is different from that of the first sub-pixel. The positive projection of the first electrode of the light-emitting element of the second sub-pixel on the substrate does not overlap with the positive projection of the data line on the substrate. The ratio of the overlapping area between the first electrode of the second sub-pixel and the first power supply line to the area of the first electrode of the second sub-pixel is r2, and 0.8 < r2 < 1.

11. The display panel according to claim 10, wherein, The multiple sub-pixels include a third sub-pixel. The light-emitting color of the third sub-pixel is different from that of the first sub-pixel and different from that of the second sub-pixel. The positive projection of the first electrode of the light-emitting element of the third sub-pixel on the substrate overlaps with the positive projection of the data line on the substrate. The ratio of the overlapping area between the first electrode of the third sub-pixel and the first power supply line to the area of the first electrode of the third sub-pixel is r3, and 0 < r3 < 0.

4.

12. The display panel according to claim 8, wherein, The sub-pixels are provided in plurality, and the plurality of sub-pixels form a plurality of data bars arranged in a first direction. Each data bar extends in a second direction. The data bar includes a first column of sub-pixels and a second column of sub-pixels. The data lines include a first data line and a second data line. The first column of sub-pixels is connected to the first data line, and the second column of sub-pixels is connected to the second data line. The pixel circuits for driving the first column of sub-pixels and the pixel circuits for driving the second column of sub-pixels are located between the first data line and the second data line. The first column of sub-pixels includes a plurality of first sub-pixels and a plurality of second sub-pixels alternately arranged in the second direction. The second column of sub-pixels includes a plurality of third sub-pixels arranged in the second direction.

13. The display panel according to claim 12, wherein, The positive projection of the first electrode of the light-emitting element of the first sub-pixel on the substrate does not overlap with the positive projection of the data line on the substrate. The ratio of the overlapping area between the first electrode of the first sub-pixel and the first power supply line to the area of the first electrode of the first sub-pixel is r1. The positive projection of the first electrode of the light-emitting element of the second sub-pixel on the substrate does not overlap with the positive projection of the data line on the substrate. The ratio of the overlapping area between the first electrode of the second sub-pixel and the first power supply line to the area of the first electrode of the second sub-pixel is r2. The light-emitting colors of every two of the first sub-pixel, the second sub-pixel, and the third sub-pixel are different. The positive projection of the first electrode of the light-emitting element of the third sub-pixel on the substrate overlaps with the positive projection of the data line on the substrate. The ratio of the overlapping area between the first electrode of the third sub-pixel and the first power supply line to the area of the first electrode of the third sub-pixel is r3, where r3 < r1 and r3 < r2.

14. The display panel according to claim 13, wherein, 0.8<r1<1，0.8<r2<1，0<r3<0.4。 15. The display panel according to claim 12, wherein The display panel further includes a first reset control signal line and a first initialization signal line. The first reset control signal line is configured to provide a first reset control signal to the pixel circuit, and the first initialization signal line is configured to provide a first initialization signal to the pixel circuit. The pixel circuit further includes a first reset transistor. The gate of the first reset transistor is connected to the first reset control signal line. The first pole of the first reset transistor is connected to the first initialization signal line. The second pole of the first reset transistor is connected to the gate of the driving transistor. The first reset transistor is configured to reset the gate of the driving transistor. The first power supply line includes a first power supply conductive part and a second power supply conductive part spaced apart in the second direction. The first power supply conductive part and the second power supply conductive part are located in the same data bar. The first initialization signal line includes a first initialization conductive portion extending in a first direction and a second initialization conductive portion extending in a second direction. The first initialization conductive portion and the second initialization conductive portion are connected. The positive projection of the second initialization conductive portion on the substrate is located between the positive projection of the first power supply conductive portion on the substrate and the positive projection of the second power supply conductive portion on the substrate.

16. The display panel according to claim 15, wherein, The positive projection of the second initialization conductive portion on the substrate overlaps with the positive projections of the first electrodes of the first sub-pixel and the second sub-pixel on the substrate.

17. The display panel according to claim 15 further includes a second reset control signal line and a second initialization signal line, wherein, The second reset control signal line is configured to provide a second reset control signal to the pixel circuit. The second initialization signal line is configured to provide a second initialization signal to the pixel circuit. The pixel circuit further includes a second reset transistor configured to reset the first electrode of the light-emitting element. A first pole of the second reset transistor is connected to the second initialization signal line. A second pole of the second reset transistor is connected to the first electrode of the light-emitting element. A gate of the second reset transistor is connected to the second reset control signal line. Wherein, the first power supply line includes a third power supply conductive portion and a fourth power supply conductive portion spaced apart in the second direction. The third power supply conductive portion and the fourth power supply conductive portion are located in the same data column. And, the data column where the first power supply conductive portion and the second power supply conductive portion are located is different from the data column where the third power supply conductive portion and the fourth power supply conductive portion are located. The second initialization signal line includes a third initialization conductive portion extending in the first direction and a fourth initialization conductive portion extending in the second direction. The third initialization conductive portion and the fourth initialization conductive portion are connected. The positive projection of the fourth initialization conductive portion on the substrate is located between the positive projection of the third power supply conductive portion on the substrate and the positive projection of the fourth power supply conductive portion on the substrate.

18. The display panel according to claim 17, wherein, The positive projection of the fourth initialization conductive portion on the substrate overlaps with the positive projections of the first electrodes of the first sub-pixel and the second sub-pixel on the substrate.

19. The display panel according to claim 17, wherein, A plurality of second initialization conductive portions and a plurality of fourth initialization conductive portions are alternately arranged along the first direction.

20. The display panel according to claim 17, wherein, The second initialization conductive portion and the fourth initialization conductive portion are located in different data columns.

21. The display panel according to any one of claims 15-20, wherein, The positive projection of the first power supply line on the substrate overlaps with the positive projection of the gate of the first reset transistor on the substrate to form a third capacitor.

22. The display panel according to any one of claims 15-20 further includes a first connection portion, wherein, The first power supply conductive portion and the second power supply conductive portion are connected by the first connection portion. The first power supply conductive portion and the second power supply conductive portion are located in the same layer. The first connection portion is located in the same layer as the first power supply conductive portion and the second power supply conductive portion.

23. The display panel according to any one of claims 15-20 further includes a first connection portion, wherein, The first power conductive part and the second power conductive part are connected by the first connection part. The first power conductive part and the second power conductive part are located on the same layer, and the first connection part is located on a layer different from the first power conductive part and the second power conductive part.

24. The display panel according to claim 23, wherein, The dimension of the first connection part in the second direction is smaller than the dimension of the part of the first power supply line overlapping with the first electrode of the light-emitting element in the second direction.

25. The display panel according to claim 23, wherein, The dimension of the first connection part in the second direction is smaller than the minimum dimension of the first electrode of the light-emitting element in the second direction.

26. The display panel according to any one of claims 17-20 further includes a second connecting portion, wherein, The second power conductive part and the third power conductive part are connected by the second connection part. The second connection part, the second power conductive part, and the third power conductive part are located on the same layer.

27. The display panel according to any one of claims 17-20 further includes a second connection portion, wherein, The second power conductive part and the third power conductive part are connected by the second connection part. The second connection part, the second power conductive part, and the third power conductive part are located on different layers.

28. The display panel according to claim 26, wherein, The orthographic projection of the second connection part on the substrate overlaps with the orthographic projection of the first electrode of the third sub-pixel on the substrate. The ratio of the overlapping area of the first electrode of the third sub-pixel and the second connection part to the area of the first electrode of the third sub-pixel is r3, and 0.8 < r3 < 1.

29. The display panel according to claim 26, wherein, The orthographic projection of the second connection part on the substrate overlaps with the orthographic projection of the first electrode of the third sub-pixel on the substrate. The ratio of the overlapping area of the first electrode of the third sub-pixel and the second connection part to the area of the first electrode of the third sub-pixel is r3, and 0 ≤ r3 < 0.

5.

30. The display panel according to claim 28, wherein, The orthographic projection of the first electrode of the light-emitting element of the first sub-pixel on the substrate does not overlap with the orthographic projection of the data line on the substrate. The ratio of the overlapping area of the first electrode of the first sub-pixel and the first power supply line to the area of the first electrode of the first sub-pixel is r1; The orthographic projection of the first electrode of the light-emitting element of the second sub-pixel on the substrate does not overlap with the orthographic projection of the data line on the substrate. The ratio of the overlapping area of the first electrode of the second sub-pixel and the first power supply line to the area of the first electrode of the second sub-pixel is r2; The light-emitting colors of every two of the first sub-pixel, the second sub-pixel, and the third sub-pixel are different. The orthographic projection of the first electrode of the light-emitting element of the third sub-pixel on the substrate overlaps with the orthographic projection of the data line on the substrate. The ratio of the overlapping area of the first electrode of the third sub-pixel and the first power supply line to the area of the first electrode of the third sub-pixel is r3, where 0.8 < r1 < 1 and 0.8 < r2 < 1.

31. The display panel according to claim 3 further includes a second reset control signal line and a second initialization signal line, wherein, The second reset control signal line is configured to provide a second reset control signal to the pixel circuit, and the second initialization signal line is configured to provide a second initialization signal to the pixel circuit. The pixel circuit further includes a second reset transistor configured to reset a first electrode of the light-emitting element. A first pole of the second reset transistor is connected to the second initialization signal line, a second pole of the second reset transistor is connected to the first electrode of the light-emitting element, and a gate of the second reset transistor is connected to the second reset control signal line. The pixel circuit further includes a fifth capacitor provided between a gate of the first reset transistor and the second initialization signal line.

32. The display panel according to claim 31 further includes a first conductive pattern layer, a second conductive pattern layer, a third conductive pattern layer, a fourth conductive pattern layer, a fifth conductive pattern layer, and a sixth conductive pattern layer that are sequentially arranged, wherein, The first conductive pattern layer is closer to the substrate than the sixth conductive pattern layer. The first capacitor includes a first electrode plate and a second electrode plate. A gate of the driving transistor serves as the first electrode plate of the first capacitor and is located in the first conductive pattern layer. The second electrode plate of the first capacitor is located in the second conductive pattern layer and is connected to the first power supply line. Two electrode plates of the second capacitor include the first electrode of the light-emitting element located in the sixth conductive pattern layer and the first power supply line located in the fifth conductive pattern layer. Two electrode plates of the third capacitor include a top gate in the gate of the first reset transistor located in the third conductive pattern layer and the first power supply line located in the fifth conductive pattern layer. Two electrode plates of the fourth capacitor include a top gate in the gate of the threshold compensation transistor located in the third conductive pattern layer and the first power supply line located in the fifth conductive pattern layer. Two electrode plates of the fifth capacitor include a top gate in the gate of the first reset transistor located in the third conductive pattern layer and the second initialization signal line located in the fourth conductive pattern layer. Bottom gates in the gate of the first reset transistor and bottom gates in the gate of the threshold compensation transistor are both located in the second conductive pattern layer.

33. The display panel according to claim 31, wherein The first capacitor ranges from greater than 20.0 fF and less than 80.0 fF, the second capacitor ranges from greater than 41.0 fF and less than 130.0 fF, the third capacitor ranges from greater than 0.5 fF and less than 3.0 fF, the fourth capacitor ranges from greater than 0.5 fF and less than 3.0 fF, and the fifth capacitor ranges from greater than 1.0 fF and less than 10.0 fF.

34. The display panel according to claim 3, wherein, It further includes a first conductive pattern layer, a second conductive pattern layer, a third conductive pattern layer, a fourth conductive pattern layer, a fifth conductive pattern layer, and a sixth conductive pattern layer arranged in sequence. Among them, the first conductive pattern layer is closer to the substrate than the sixth conductive pattern layer. The first capacitor includes a first electrode plate and a second electrode plate. A gate of the driving transistor serves as the first electrode plate of the first capacitor and is located in the first conductive pattern layer. The second electrode plate of the first capacitor is located in the second conductive pattern layer and is connected to the first power supply line. The two plates of the second capacitor include the first electrode of the light-emitting element located in the sixth conductive pattern layer and the first power line located in the fifth conductive pattern layer; The two plates of the third capacitor include the top gate in the gate of the first reset transistor located in the third conductive pattern layer and the first power line located in the fifth conductive pattern layer; The two plates of the fourth capacitor include the top gate in the gate of the threshold compensation transistor located in the third conductive pattern layer and the first power line located in the fifth conductive pattern layer; The bottom gate in the gate of the first reset transistor and the bottom gate in the gate of the threshold compensation transistor are both located in the second conductive pattern layer.

35. The display panel according to claim 3, wherein, The range of the first capacitor is greater than 20.0 fF and less than 80.0 fF, the range of the second capacitor is greater than 41.0 fF and less than 130.0 fF, the range of the third capacitor is greater than 0.5 fF and less than 3.0 fF, and the range of the fourth capacitor is greater than 0.5 fF and less than 3.0 fF.

36. A display device, comprising the display panel according to any one of claims 1-35.

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