Pixel circuit

Abstract

A pixel circuit. The pixel circuit includes a light-emitting element, a first regional light-emitting switch, a second regional light-emitting switch, a common light-emitting switch, and a driving block. The light-emitting element has a first light-emitting portion and a second light-emitting portion. The first regional light-emitting switch is coupled between a first power supply terminal and the driving block. The second regional light-emitting switch is coupled between a second power supply terminal and the driving block. The common light-emitting switch is coupled between the driving block and the light-emitting element. The driving block provides a first driving current and a second driving current to the first light-emitting portion and the second light-emitting portion respectively based on a first frame gate signal and a second frame gate signal, wherein the direction of the first driving current is different from that of the second driving current.

Description

Technical Field

[0001] The present invention relates to a pixel circuit, and more particularly to an organic light-emitting pixel circuit. Background Art

[0002] In recent years, due to advantages such as low power consumption, a thinner display panel thickness, bright colors, and a more distinct contrast, and in addition, the problem of motion blur has been overcome, the organic light-emitting display technology has become the mainstream of display devices.

[0003] With the progress of semiconductor technology, different light-emitting elements are applied to the display of images, and corresponding drive circuits are configured on the display panel. For a light-emitting element having both forward and reverse drive characteristics, a corresponding drive circuit design is required to form an organic light-emitting pixel circuit. Summary of the Invention

[0004] The present invention provides a pixel circuit that applies a light-emitting element having forward and reverse drive capabilities and provides a novel drive circuit.

[0005] The pixel circuit of the present invention includes a light-emitting element, a first region light-emitting switch, a second region light-emitting switch, a common light-emitting switch, and a driving block. The light-emitting element has one end coupled to a common terminal and has a first light-emitting portion and a second light-emitting portion, wherein the direction of a first drive current for driving the first light-emitting portion is opposite to the direction of a second drive current for driving the second light-emitting portion. The first region light-emitting switch has a first end coupled to a first power supply terminal, a control terminal for receiving a first image light-emitting signal, and a second end. The second region light-emitting switch has a first end coupled to a second power supply terminal, a control terminal for receiving a second image light-emitting signal, and a second end. The common light-emitting switch has a first end, a control terminal for receiving a common light-emitting signal, and a second end coupled to the other end of the light-emitting element. The driving block receives a data signal, a first image gate signal, and a second image gate signal, and is coupled to the second end of the first region light-emitting switch, the second end of the second region light-emitting switch, and the first end of the common light-emitting switch. The driving block forms one of a first current path and a second current path based on the first image gate signal and the second image gate signal, wherein the first current path is formed between the second end of the first region light-emitting switch and the first end of the common light-emitting switch and delivers the first drive current, and the second current path is formed between the second end of the second region light-emitting switch and the first end of the common light-emitting switch and delivers the second drive current, and the data signal sets the current amplitudes of the first drive current and the second drive current.

[0006] Based on the above, the pixel circuit according to the embodiment of the present invention can provide a first driving current and a second driving current I2 in different directions required by a light-emitting element with bidirectional driving ability through a newly designed driving block, so that the pixel circuit can operate smoothly by applying a new type of light-emitting element.

[0007] In order to make the above features and advantages of the present invention more obvious and understandable, specific embodiments are hereinafter given and described in detail in conjunction with the accompanying drawings of the specification as follows. Description of the Drawings

[0008] Figure 1 System schematic diagram of a pixel circuit according to an embodiment of the present invention.

[0009] Figure 2 Circuit schematic diagram of a pixel circuit according to an embodiment of the present invention.

[0010] Figure 3 Operation timing schematic diagram of a pixel circuit according to an embodiment of the present invention.

[0011] Figure 4A Operation schematic diagram of a pixel circuit according to an embodiment of the present invention during a first reset period and a second reset period.

[0012] Figure 4B Operation schematic diagram of a pixel circuit according to an embodiment of the present invention during a first setting period and a second setting period.

[0013] Figure 4C Operation schematic diagram of a pixel circuit according to an embodiment of the present invention during a first light-emitting period.

[0014] Figure 4D Operation schematic diagram of a pixel circuit according to an embodiment of the present invention during a second setting period.

[0015] Figure 4E Operation schematic diagram of a pixel circuit according to an embodiment of the present invention during a second light-emitting period.

[0016] Figure 5 System schematic diagram of a pixel circuit according to another embodiment of the present invention.

[0017] Description of Reference Numerals:

[0018] C1: First capacitor

[0019] C2: Second capacitor

[0020] DVBK: Driving block

[0021] EMD: Light-emitting element

[0022] Frame_1: First frame period

[0023] Frame_2: Second screen period

[0024] FRAME_A: First screen light emission signal

[0025] FRAME_B: Second screen light emission signal

[0026] FSW1: First area light emission switch

[0027] FSW2: Second area light emission switch

[0028] GATE_A: First screen gate signal

[0029] GATE_B: Second screen gate signal

[0030] GEM, GEMX: Common light emission signal

[0031] GSW: Common light emission switch

[0032] I1: First drive current

[0033] I2: Second drive current

[0034] IR_DC: First DC level

[0035] PATH_A: First current path

[0036] PATH_B: Second current path

[0037] PEM1: First light emission part

[0038] PEM2: Second light emission part

[0039] PIXa, PIXb: Pixel circuit

[0040] PM1: First light emission period

[0041] PM2: Second light emission period

[0042] PR1: First reset period

[0043] PR2: Second reset period

[0044] PS1: First setting period

[0045] PS2: Second setting period

[0046] PWBK: Pulse width control block

[0047] RES_DC: Second DC level

[0048] RESET: Reset signal

[0049] SET: Setting signal

[0050] SW1: First switch

[0051] SW10: Tenth switch

[0052] SW2: Second switch

[0053] SW3: Third switch

[0054] SW4: Fourth switch

[0055] SW5: Fifth switch

[0056] SW6: Sixth switch

[0057] SW7: Seventh switch

[0058] SW8: Eighth switch

[0059] SW9: Ninth switch

[0060] T_DC: Time reference DC level

[0061] TDATA: Time data signal

[0062] TP1: First power terminal

[0063] TP2: Second power terminal

[0064] TPC: Common terminal

[0065] TVR: Time voltage slope reference signal

[0066] XDATA: Data signal Detailed implementation manners

[0067] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and this invention, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0068] It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Thus, the "first element", "component", "region", "layer", or "part" discussed below may be referred to as a second element, component, region, layer, or part without departing from the teachings herein.

[0069] The terms used herein are for the purpose of describing particular embodiments only and are not limiting. As used herein, unless the context clearly dictates otherwise, the singular forms "a", "an", and "the" are intended to include the plural forms, including "at least one". "Or" means "and / or". As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It should also be understood that when used in this specification, the terms "comprises" and / or "comprising" specify the presence of the stated features, regions, wholes, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, regions, wholes, steps, operations, elements, components, and / or combinations thereof.

[0070] Figure 1 A system schematic diagram of a pixel circuit according to an embodiment of the present invention. Please refer to Figure 1 , in this embodiment, the pixel circuit PIXa includes a light-emitting element EMD, a first-region light-emitting switch FSW1, a second-region light-emitting switch FSW2, a common light-emitting switch GSW, and a driving block DVBK.

[0071] The light-emitting element EMD has one end coupled to a common terminal TPC and has a first light-emitting portion PEM1 and a second light-emitting portion PEM2, where the light-emitting element EMD is, for example, a nanorod light-emitting element, but the embodiments of the present invention are not limited thereto. The first-region light-emitting switch FSW1 has a first end coupled to a first power terminal TP1, a control end receiving a first frame light-emitting signal FRAME_A, and a second end. The second-region light-emitting switch FSW2 has a first end coupled to a second power terminal TP2, a control end receiving a second frame light-emitting signal FRAME_B, and a second end.

[0072] The common emission switch GSW has a first terminal, a control terminal for receiving a common emission signal GEM, and a second terminal coupled to the other end of the light-emitting element EMD. The driving block DVBK receives a data signal XDATA, a first frame gate signal GATE_A, and a second frame gate signal GATE_B, and is coupled to the second terminal of the first region emission switch FSW1, the second terminal of the second region emission switch FSW2, and the first terminal of the common emission switch GSW. The driving block DVBK forms one of a first current path PATH_A and a second current path PATH_B based on the first frame gate signal GATE_A and the second frame gate signal GATE_B. The first current path PATH_A is formed between the second terminal of the first region emission switch FSW1 and the first terminal of the common emission switch GSW and delivers a first driving current I1, and the second current path PATH_B is formed between the second terminal of the second region emission switch FSW2 and the first terminal of the common emission switch GSW and delivers a second driving current I2.

[0073] In this embodiment, the first driving current I1 is used to drive the first light-emitting portion PEM1, and the second driving current I2 is used to drive the second light-emitting portion PEM2, wherein the direction of the first driving current I1 is opposite to the direction of the second driving current I2. That is to say, the first light-emitting portion PEM1 can be regarded as forward driving, and the second light-emitting portion PEM2 can be regarded as reverse driving. Also, the data signal XDATA sets the current amplitudes of the first driving current I1 and the second driving current I2 to determine the emission brightness of the first light-emitting portion PEM1 and the second light-emitting portion PEM2. Therefore, through the newly designed driving block, the forward current (such as the first driving current I1) and the reverse current (such as the second driving current I2) required for the light-emitting elements with forward driving and reverse driving can be provided, so that the pixel circuit can operate smoothly.

[0074] In this embodiment, the first region emission switch FSW1, the second region emission switch FSW2, and the common emission switch GSW are all exemplified by P-type transistors, but the embodiments of the present invention are not limited thereto.

[0075] In this embodiment, the voltage of the first power supply terminal TP1 is different from the voltage of the second power supply terminal TP2. For example, the voltage of the first power supply terminal TP1 can be greater than the voltage of the second power supply terminal TP2, and the voltage of the common terminal TPC is between the voltage of the first power supply terminal TP1 and the voltage of the second power supply terminal TP2. Therefore, the first driving current I1 delivered by the first current path PATH_A is a forward current, and the second driving current I2 delivered by the second current path PATH_B is a reverse current.

[0076] Figure 2 It is a circuit schematic diagram of a pixel circuit according to an embodiment of the present invention. Please refer toFigure 1 and Figure 2 , where the same or similar elements are denoted by the same or similar reference numerals. In this embodiment, the driving block DVBK includes a first switch SW1, a second switch SW2, a third switch SW3, a fourth switch SW4, a fifth switch SW5, a sixth switch SW6, a seventh switch SW7, an eighth switch SW8, a ninth switch SW9, a tenth switch SW10, a first capacitor C1, and a second capacitor C2.

[0077] The first switch SW1 has a first terminal coupled to a first power supply terminal TP1, a control terminal receiving a first frame emission signal FRAME_A, and a second terminal. The second switch SW2 has a first terminal coupled to the second terminal of the first switch SW1, a control terminal receiving a setting signal SET, and a second terminal receiving a first DC level IR_DC. The third switch SW3 has a first terminal receiving a data signal XDATA, a control terminal receiving a first gate signal GATE_A of a first frame, and a second terminal coupled to a second terminal of a first region emission switch FSW1.

[0078] The fourth switch SW4 has a first terminal coupled to the second terminal of the first region emission switch FSW1, a control terminal receiving a second gate signal GATE_B of a second frame, and a second terminal. The first capacitor C1 is coupled between the second terminal of the first switch SW1 and the second terminal of the fourth switch SW4. The fifth switch SW5 has a first terminal coupled to the second terminal of the fourth switch SW4, a control terminal receiving a reset signal RESET, and a second terminal receiving a second DC level RES_DC.

[0079] The sixth switch SW6 has a first terminal coupled to the second terminal of the first region emission switch FSW1, a control terminal coupled to the second terminal of the fourth switch SW4, and a second terminal. The seventh switch SW7 has a first terminal receiving the data signal XDATA, a control terminal receiving the second gate signal GATE_B of a second frame, and a second terminal coupled to the second terminal of the sixth switch SW6. The eighth switch SW8 has a first terminal coupled to the second terminal of the seventh switch SW7, a control terminal receiving a control terminal of the first gate signal GATE_A of a first frame, and a second terminal coupled to the second terminal of the fourth switch SW4.

[0080] The ninth switch SW9 has a first terminal coupled to the other end of a light emitting element EMD, a control terminal receiving a second frame emission signal FRAME_B, and a second terminal. The second capacitor C2 is coupled between the second terminal of the eighth switch SW8 and the second terminal of the ninth switch SW9. The tenth switch SW10 has a first terminal coupled to the second terminal of the ninth switch SW9, a control terminal receiving the setting signal SET, and a second terminal receiving the first DC level IR_DC.

[0081] In this embodiment, the first switch SW1 to the tenth switch SW10 are taken as P-type transistors as an example, but the embodiments of the present invention are not limited thereto. Also, the second DC level RES_DC may be different from the first DC level IR_DC.

[0082] Figure 3 FIG. is a schematic diagram of the operation timing of a pixel circuit according to an embodiment of the present invention. Please refer to Figure 2 and Figure 3 , in this embodiment, the first frame period Frame_1 and the second frame period Frame_2 are shown for illustration, and the second frame period Frame_2 is shown as the next frame period after the first frame period Frame_1, that is, there is no gap between the second frame period Frame_2 and the first frame period Frame_1. However, the embodiments of the present invention are not limited thereto.

[0083] In this embodiment, the first frame emission signal FRAME_A is enabled during a plurality of first emission periods PM1 in the first frame period Frame_1, the second frame emission signal FRAME_B is enabled during a plurality of second emission periods PM2 in the second frame period Frame_2, and the common emission signal GEM is enabled during the plurality of first emission periods PM1 in the first frame period Frame_1 and the plurality of second emission periods PM2 in the second frame period Frame_2.

[0084] The reset signal RESET is enabled during the first reset period PR1 in the first frame period Frame_1 and the second reset period PR2 in the second frame period Frame_2, the first frame gate signal GATE_A is enabled during the first setting period PS1 in the first frame period Frame_1, the second frame gate signal GATE_B is enabled during the second setting period PS2 in the second frame period Frame_2, and the setting signal SET is enabled during the first reset period PR1 and the first setting period PS1 in the first frame period Frame_1 and the second reset period PR2 and the second setting period PS2 in the second frame period Frame_2.

[0085] In this embodiment, the first setting period PS1 is located after the first reset period PR1, and the second setting period PS2 is located after the second reset period PR2. Also, these first emission periods PM1 are periodically arranged in the first frame period Frame_1, and these second emission periods PM2 are periodically arranged in the second frame period Frame_2. And, the first setting period PS1 and the first reset period PR1 do not overlap with these first emission periods PM1, and the second setting period PS2 and the second reset period PR2 do not overlap with these second emission periods PM2.

[0086] Figure 4A Schematic diagrams of the operation of a pixel circuit according to an embodiment of the present invention during a first reset period and a second reset period. Please refer to Figure 2 , Figure 3 and Figure 4A . During the first reset period PR1 of the first frame period Frame_1 and the second reset period PR2 of the second frame period Frame_2, the reset signal RESET and the set signal SET are enabled, and the first frame gate signal GATE_A, the second frame gate signal GATE_B, the common emission signal GEM, the first frame emission signal FRAME_A, and the second frame emission signal FRAME_B are disabled.

[0087] At this time, the second switch SW2, the fifth switch SW5, and the tenth switch SW10 are turned on, and the first region emission switch FSW1, the second region emission switch FSW2, the common emission switch GSW, the first switch SW1, the third switch SW3, the fourth switch SW4, the sixth switch SW6, the seventh switch SW7, the eighth switch SW8, and the ninth switch SW9 are turned off. Therefore, the first capacitor C1 and the second capacitor C2 store the voltage difference between the first DC level IR_DC and the second DC level RES_DC. The voltage difference between the first DC level IR_DC and the second DC level RES_DC can be used to compensate for the threshold voltage of the transistor or adjust the displayed brightness, but the embodiments of the present invention are not limited thereto.

[0088] Figure 4B Schematic diagrams of the operation of a pixel circuit according to an embodiment of the present invention during a first setting period and a second setting period. Please refer to Figure 2 , Figure 3 and Figure 4B . During the first setting period PS1 of the first frame period Frame_1, the set signal SET and the first frame gate signal GATE_A are enabled, and the reset signal RESET, the second frame gate signal GATE_B, the common emission signal GEM, the first frame emission signal FRAME_A, and the second frame emission signal FRAME_B are disabled.

[0089] At this time, the second switch SW2, the third switch SW3, the sixth switch SW6, the eighth switch SW8, and the tenth switch SW10 are turned on, and the first region emission switch FSW1, the second region emission switch FSW2, the common emission switch GSW, the first switch SW1, the fourth switch SW4, the fifth switch SW5, the seventh switch SW7, and the ninth switch SW9 are turned off. Therefore, the first capacitor C1 and the second capacitor C2 store the sum of the voltage difference between the first DC level IR_DC and the second DC level RES_DC and the voltage level of the data signal XDATA.

[0090] Figure 4C Schematic diagram of the operation of a pixel circuit according to an embodiment of the present invention during a first light emission period. Please refer to Figure 2 、 Figure 3 and Figure 4C , during the first light emission period PM1 of Frame_1 in the first screen period, the common light emission signal GEM and the first screen light emission signal FRAME_A are enabled, and the set signal SET, the reset signal RESET, the first screen gate signal GATE_A, the second screen gate signal GATE_B, and the second screen light emission signal FRAME_B are disabled.

[0091] At this time, the first region light emission switch FSW1, the common light emission switch GSW, the first switch SW1, and the sixth switch SW6 are turned on, and the second region light emission switch FSW2, the second switch SW2, the third switch SW3, the fourth switch SW4, the fifth switch SW5, the seventh switch SW7, the eighth switch SW8, the ninth switch SW9, and the tenth switch SW10 are turned off. Moreover, the first drive current I1 is transmitted to the first light emission part PEM1 through the turned-on first region light emission switch FSW1, the sixth switch SW6, and the common light emission switch GSW. Since the conduction degree of the sixth switch SW6 is related to the voltage stored in the first capacitor C1, the current amplitude of the first drive current I1 is related to the data signal XDATA.

[0092] Figure 4D Schematic diagram of the operation of a pixel circuit according to an embodiment of the present invention during a second setting period. Please refer to Figure 2 、 Figure 3 and Figure 4D , during the second setting period PS2 of Frame_2 in the second screen period, the set signal SET and the second screen gate signal GATE_B are enabled, and the reset signal RESET, the first screen gate signal GATE_A, the common light emission signal GEM, the first screen light emission signal FRAME_A, and the second screen light emission signal FRAME_B are disabled.

[0093] At this time, the second switch SW2, the fourth switch SW4, the sixth switch SW6, the seventh switch SW7, and the tenth switch SW10 are turned on, and the first region light emission switch FSW1, the second region light emission switch FSW2, the common light emission switch GSW, the first switch SW1, the third switch SW3, the fifth switch SW5, the eighth switch SW8, and the ninth switch SW9 are turned off. Therefore, the first capacitor C1 and the second capacitor C2 still store the sum of the voltage difference between the first DC level IR_DC and the second DC level RES_DC and the voltage level of the data signal XDATA.

[0094] Figure 4ESchematic diagram of the operation of a pixel circuit according to an embodiment of the present invention during a second light-emitting period. Please refer to Figure 2 , Figure 3 and Figure 4E , during the second light-emitting period PM2 of Frame_2 in the first screen period, the common light-emitting signal GEM and the second screen light-emitting signal FRAME_B are enabled, and the setting signal SET, the reset signal RESET, the first screen gate signal GATE_A, the second screen gate signal GATE_B, and the first screen light-emitting signal FRAME_A are disabled.

[0095] At this time, the first area light-emitting switch FSW1, the common light-emitting switch GSW, the sixth switch SW6, and the ninth switch SW9 are turned on, and the second area light-emitting switch FSW2, the first switch SW1, the second switch SW2, the third switch SW3, the fourth switch SW4, the fifth switch SW5, the seventh switch SW7, the eighth switch SW8, and the tenth switch SW10 are turned off. And, the second driving current I2 is received from the second light-emitting portion PEM1 via the turned-on second area light-emitting switch FSW2, the sixth switch SW6, and the common light-emitting switch GSW. Since the conduction degree of the sixth switch SW6 is related to the voltage stored in the second capacitor C2, the current amplitude of the second driving current I2 is related to the data signal XDATA.

[0096] Figure 5 System schematic diagram of a pixel circuit according to another embodiment of the present invention. Please refer to Figure 1 and Figure 5 , the pixel circuit PIXb is substantially the same as the pixel circuit PIXa, except that the pixel circuit PIXb further includes a pulse width control block PWBK, where the same or similar elements are denoted by the same or similar reference numerals. In this embodiment, the pulse width control block PWBK is coupled to the control terminal of the common light-emitting switch GSW, and receives a time reference DC level T_DC, a time voltage slope reference signal TVR, and a time data signal TDATA to provide a common light-emitting signal GEMX to replace the common light-emitting signal GEM, where the common light-emitting signal GEMX is adjusted based on the time data signal TDATA.

[0097] In summary, the pixel circuit according to the embodiment of the present invention, through a newly designed driving block, can provide different-direction first driving current and second driving current required for a light-emitting element with bidirectional driving ability, so that the pixel circuit can be applied to a new type of light-emitting element and operate smoothly.

[0098] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes and modifications without departing from the concept and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope defined by the claims.

Claims

1. A pixel circuit, comprising: a light-emitting element having one end coupled to a common terminal and having a first light-emitting portion and a second light-emitting portion, wherein a direction of a first driving current for driving the first light-emitting portion is opposite to a direction of a second driving current for driving the second light-emitting portion; a first region light-emitting switch having a first end coupled to a first power supply terminal, a control terminal receiving a first frame light-emitting signal, and a second end; a second region light-emitting switch having a first end coupled to a second power supply terminal, a control terminal receiving a second frame light-emitting signal, and a second end; a common light-emitting switch having a first end, a control terminal receiving a common light-emitting signal, and a second end coupled to the other end of the light-emitting element; and a driving block receiving a data signal, a first frame gate signal, and a second frame gate signal, and coupled to the second end of the first region light-emitting switch, the second end of the second region light-emitting switch, and the first end of the common light-emitting switch, wherein the driving block forms one of a first current path and a second current path based on the first frame gate signal and the second frame gate signal, the first current path is formed between the second end of the first region light-emitting switch and the first end of the common light-emitting switch and delivers the first driving current, and the second current path is formed between the second end of the second region light-emitting switch and the first end of the common light-emitting switch and delivers the second driving current, wherein the data signal sets current amplitudes of the first driving current and the second driving current, wherein the driving block includes: a first switch having a first end coupled to the first power supply terminal, a control terminal receiving the first frame light-emitting signal, and a second end; a second switch having a first end coupled to the second end of the first switch, a control terminal receiving a setting signal, and a second end receiving a first DC level; a third switch having a first end receiving the data signal, a control terminal receiving the first frame gate signal, and a second end coupled to the second end of the first region light-emitting switch; a fourth switch having a first end coupled to the second end of the first region light-emitting switch, a control terminal receiving the second frame gate signal, and a second end; a first capacitor coupled between the second end of the first switch and the second end of the fourth switch; a fifth switch having a first end coupled to the second end of the fourth switch, a control terminal receiving a reset signal, and a second end receiving a second DC level; a sixth switch having a first end coupled to the second end of the first region light-emitting switch, a control terminal coupled to the second end of the fourth switch, and a second end; a seventh switch having a first end receiving the data signal, a control terminal receiving the second frame gate signal, and a second end coupled to the second end of the sixth switch; an eighth switch having a first end coupled to the second end of the seventh switch, a control terminal receiving the first frame gate signal, and a second end coupled to the second end of the fourth switch; a ninth switch having a first end coupled to the other end of the light-emitting element, a control end receiving the second frame light-emitting signal, and a second end; a second capacitor coupled between the second end of the eighth switch and the second end of the ninth switch; and a tenth switch having a first end coupled to the second end of the ninth switch, a control end receiving the setting signal, and a second end receiving the first DC level.

2. The pixel circuit according to claim 1, wherein the first frame light-emitting signal is enabled during a plurality of first light-emitting periods in a first frame period, the second frame light-emitting signal is periodically enabled during a plurality of second light-emitting periods in a second frame period, the reset signal is enabled during a first reset period in the first frame period and a second reset period in the second frame period, and the setting signal is enabled during the first reset period and a first setting period in the first frame period and the second reset period and a second setting period in the second frame period.

3. The pixel circuit according to claim 2, wherein the second frame period is the next frame period of the first frame period.

4. The pixel circuit according to claim 2, wherein the first setting period is after the first reset period, and the second setting period is after the second reset period.

5. The pixel circuit according to claim 4, wherein the first light-emitting periods are periodically arranged in the first frame period, and the second light-emitting periods are periodically arranged in the second frame period.

6. The pixel circuit according to claim 5, wherein the first setting period and the first reset period do not overlap with the first light-emitting periods, and the second setting period and the second reset period do not overlap with the second light-emitting periods.

7. The pixel circuit according to claim 1, wherein the second DC level is different from the first DC level.

8. The pixel circuit according to claim 1, wherein the first switch to the tenth switch are all P-type transistors.

9. The pixel circuit according to claim 1, wherein the voltage of the first power supply terminal is different from the voltage of the second power supply terminal.

10. The pixel circuit according to claim 9, wherein the voltage of the first power supply terminal is greater than the voltage of the second power supply terminal.

11. The pixel circuit according to claim 10, wherein the voltage of the common terminal is between the voltage of the first power supply terminal and the voltage of the second power supply terminal.

12. The pixel circuit according to claim 1, wherein the first region light-emitting switch, the second region light-emitting switch, and the common light-emitting switch are all P-type transistors.

13. The pixel circuit according to claim 1, wherein the light-emitting element is a nanocolumn light-emitting element.

14. The pixel circuit according to claim 1, further comprising a pulse width control region coupled to the control end of the common light-emitting switch and receiving a time reference DC level, a time voltage slope reference signal, and a time data signal to provide the common light-emitting signal, wherein the pulse width of the common light-emitting signal is adjusted based on the time data signal.

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