Method for manufacturing amorphous silicon layer
By performing plasma heat treatment on the surface of the silicon dioxide layer, the problem of poor adhesion between the amorphous silicon layer and the silicon dioxide layer is solved, and higher etching accuracy and patterning accuracy are achieved.
Patent Information
- Application Number
- CN202210394294.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-04-14
- Publication Date
- 2025-05-23
- Estimated Expiration
- 2042-04-14
AI Technical Summary
The poor adhesion between the existing amorphous silicon layer and the bottom silicon dioxide layer affects the etching accuracy and patterning accuracy of the amorphous silicon layer.
Plasma heat treatment is performed on the surface of the silicon dioxide layer formed by the PECVD process to release and passivate the suspended H bonds to prevent H diffusion during the deposition of the amorphous silicon layer, thereby improving the adhesion between the silicon dioxide layer and the amorphous silicon layer.
By improving the contact interface between the amorphous silicon layer and the silicon dioxide layer, the etching accuracy and patterning accuracy of the amorphous silicon layer are improved, and adhesion is enhanced.
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Figure CN114899084B_ABST
Abstract
Description
Technical Field
[0001] The invention relates to a method for manufacturing a semiconductor integrated circuit, in particular to a method for manufacturing an amorphous silicon layer. Background Art
[0002] As the technology node of integrated circuits advances to 14nm process and below, the key dimensions of integrated circuits are also shrinking. When the stepping (pitch) is below 76nm, the single exposure process of the traditional immersion lithography machine cannot complete the precise control of the pattern, so the mandrel process has begun to be widely used to solve the pattern process below 76nm pitch. The mandrel layer material usually uses amorphous silicon, that is, based on amorphous silicon, after the amorphous silicon pattern is etched, the side of the amorphous silicon pattern is self-aligned to form a sidewall. The sidewall material is usually formed by atomic layer deposition process, and the sidewall material includes SiN or other metal nitrides; then the amorphous silicon is removed, and the remaining sidewall is used as a hard mask; in this way, the stepping of the remaining sidewall pattern will be smaller than that of the amorphous silicon pattern. For example, when the mandrel process is applied in the self-aligned double patterning process (SADP), the stepping can be halved.
[0003] The current Mandrel process deposits an amorphous silicon film on a PEOX or PETEOS film that can serve as an etch stop layer. The PEOX film is a silicon dioxide film formed when deposited using the PECVD process and using silane, i.e., SiH4, as a silicon source. The PETEOS film is a silicon dioxide film formed when deposited using the PECVD process and using TEOS as a silicon source.
[0004] In the existing method, when an amorphous silicon film is deposited on the surface of a silicon dioxide film formed by a PECVD process, problems such as poor contact interface and low adhesion between the two films are likely to occur, and the etching accuracy of the amorphous silicon film will be affected. Summary of the invention
[0005] The technical problem to be solved by the present invention is to provide a method for manufacturing an amorphous silicon layer, which can improve the adhesion between the amorphous silicon layer and the bottom silicon dioxide layer.
[0006] In order to solve the above technical problems, the present invention provides a method for manufacturing a shaped silicon layer, comprising the following steps:
[0007] Step 1: providing a semiconductor substrate having a front layer structure, and forming a silicon dioxide layer on the front layer structure by using a PECVD process; the PECVD process causes the surface of the silicon dioxide layer to have dangling H bonds.
[0008] Step 2: performing plasma heat treatment on the surface of the silicon dioxide layer, wherein the plasma heat treatment is used to release the H of the dangling H bonds of the silicon dioxide layer and to passivate the dangling bonds after the H is released.
[0009] Step three, using a CVD deposition process to form an amorphous silicon layer on the surface of the silicon dioxide layer, utilizing the characteristics that the H on the surface of the silicon dioxide layer is removed and the dangling bonds are passivated to prevent the H in the deposition process of the amorphous silicon layer from diffusing to the surface of the silicon dioxide layer and combining with the H on the surface of the silicon dioxide layer to form hydrogen, thereby improving the adhesion between the amorphous silicon layer and the silicon dioxide layer.
[0010] A further improvement is that the silicon dioxide layer serves as an etching stop layer for the amorphous silicon layer.
[0011] A further improvement is that the amorphous silicon layer serves as a mandrel layer.
[0012] A further improvement is that in step 1, the silicon source in the PECVD process of the silicon dioxide layer is silane, and the silicon dioxide layer is PEOX.
[0013] Alternatively, the silicon source in the PECVD process of the silicon dioxide layer is TEOS, and the silicon dioxide layer is PETEOS.
[0014] A further improvement is that in step 2, the process gas for the plasma heat treatment includes nitrous oxide, namely N2O.
[0015] A further improvement is that the process conditions of the plasma heat treatment include:
[0016] The vacuum pressure is 1 torr to 5 torr, the nitrogen flow rate is 1000 sccm to 10000 sccm, the nitrous oxide flow rate is 100 sccm to 1000 sccm, the temperature is 350°C to 400°C, the high-frequency RF power is 100 watts to 1000 watts, the low-frequency RF power is 50 watts to 200 watts, and the time is 2 seconds to 10 seconds.
[0017] A further improvement is that in step three, the silicon source of each amorphous silicon layer is silane, and the amorphous silicon layer is formed by decomposing silane.
[0018] Further improvements include:
[0019] The amorphous silicon is patterned and etched using the silicon dioxide layer as a stop layer to form a mandrel layer pattern.
[0020] A side wall is formed on the side of the mandrel layer pattern.
[0021] The mandrel layer pattern is removed and the pattern structure of the sidewall is formed.
[0022] A further improvement is that the front layer structure on the semiconductor substrate includes a target layer for patterning; after the pattern structure of the sidewall is formed, etching is performed using the pattern structure of the sidewall as a mask to transfer the pattern structure to the target layer.
[0023] A further improvement is that the semiconductor substrate comprises a silicon substrate.
[0024] A further improvement is that the material of the sidewall spacer includes silicon nitride or metal nitride.
[0025] A further improvement is that the material of the sidewall is formed by an atomic layer deposition process.
[0026] A further improvement is that the pattern of the target layer includes a fin, a gate structure or a conductive line.
[0027] After forming a silicon dioxide layer by adopting a PECVD process, the present invention does not directly deposit an amorphous silicon layer, but adopts plasma heat treatment to release H on the surface of the silicon dioxide layer and passivate the dangling bonds after the H is released before depositing the amorphous silicon layer, so that hydrogen bubbles are avoided from being formed on the surface of the silicon dioxide layer during the subsequent deposition of the amorphous silicon layer, so that a good contact interface can be provided between the silicon dioxide layer and the amorphous silicon layer, thereby improving the adhesion between the amorphous silicon layer and the bottom silicon dioxide layer; in the mandrel process, the etching accuracy of the amorphous silicon can also be improved, thereby improving the patterning accuracy. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:
[0029] Figure 1A-1B It is a schematic diagram of the cross-sectional structure of the device in each step of the existing method for manufacturing an amorphous silicon layer;
[0030] Figure 2 It is a cross-sectional structural photograph of a device formed by using the existing amorphous silicon layer manufacturing method;
[0031] Figure 3 is a flow chart of a method for manufacturing an amorphous silicon layer according to an embodiment of the present invention;
[0032] Figure 4A-4C is a schematic diagram of a cross-sectional structure of a device in each step of a method for manufacturing an amorphous silicon layer according to an embodiment of the present invention;
[0033] Figure 5 This is a photograph of a cross-sectional structure of a device formed by the method for manufacturing an amorphous silicon layer according to an embodiment of the present invention. DETAILED DESCRIPTION
[0034] The method of the embodiment of the present invention is formed on the basis of analyzing the existing technical problems. Before introducing the method of the embodiment of the present invention in detail, the process of analyzing the existing technical problems is first introduced:
[0035] At present, there are many incomplete dangling H bonds such as Si-H bonds on the surface of SiO2 deposited by PECVD, which will absorb water vapor in the air after being placed for a long time. In addition, amorphous silicon is usually deposited by dissociating SiH4. The H ions formed by the dissociation of SiH4 tend to diffuse to the surface of SiO2 under the influence of plasma, so that the dangling H bonds on the surface of SiO2 will combine with the diffused H to form hydrogen molecules, namely hydrogen. After the formation of amorphous silicon, a bubble layer with poor roughness will be generated between the silicon dioxide film and the amorphous silicon, which will greatly affect the adhesion between the silicon dioxide film and the amorphous silicon. In the spindle process, the silicon dioxide film is used as an etching stop layer for amorphous silicon, which will inevitably affect the graphical etching of amorphous silicon, thereby affecting the etching accuracy.
[0036] like Figure 1A to Figure 1B , which is a schematic diagram of the device cross-sectional structure in each step of the existing method for manufacturing an amorphous silicon layer 104; the existing method for manufacturing an amorphous silicon layer includes the following steps:
[0037] Step 1: Figure 1A As shown, a semiconductor substrate having a front layer structure 101 is provided, and a silicon dioxide layer 102 is formed on the front layer structure 101 by using a PECVD process.
[0038] Generally, the PECVD process causes the surface of the silicon dioxide layer 102 to have dangling H bonds such as Si—H bonds. Figure 1A In the figure, the surface layer of the silicon dioxide layer 102 having dangling H bonds is separately marked with a reference numeral 103 .
[0039] Step 3: Figure 1B As shown, an amorphous silicon layer 104 is formed on the surface of the silicon dioxide layer 102 by using a CVD deposition process.
[0040] Typically, the silicon source of the amorphous silicon layer 104 is silane, and the amorphous silicon layer 104 is formed by decomposing silane. During the deposition of the amorphous silicon layer 104, H formed by the decomposition of silane will diffuse to the surface of the silicon dioxide layer 102 and combine with H on the surface of the silicon dioxide layer 102 to form hydrogen. Finally, after the deposition of the amorphous silicon layer 104 is completed, a bubble layer 105 will be formed between the amorphous silicon layer 104 and the silicon dioxide layer 102. The bubble layer 105 will deteriorate the adhesion between the amorphous silicon layer 104 and the silicon dioxide layer 102. Typically, the amorphous silicon layer 104 serves as a mandrel layer, and the silicon dioxide layer 102 serves as an etching stop layer for the amorphous silicon layer 104. The poor adhesion between the amorphous silicon layer 104 and the silicon dioxide layer 102 may deteriorate the etching accuracy of the amorphous silicon layer 104 , thereby affecting the pattern accuracy of the amorphous silicon layer 104 .
[0041] like Figure 2 , which is a cross-sectional structure photo of a device formed by using the existing manufacturing method of the amorphous silicon layer 104, Figure 2 In the figure, the silicon dioxide layer is represented by the mark 102a alone, and the amorphous silicon layer is represented by the mark 104a alone. It can be seen that there is a bubble layer 105 at the contact interface between the two.
[0042] The method for manufacturing the amorphous silicon layer 204 according to the embodiment of the present invention is as follows:
[0043] like Figure 3 As shown, it is a flow chart of a method for manufacturing an amorphous silicon layer 204 according to an embodiment of the present invention; FIG. 4A to FIG. 4C , which is a schematic diagram of the cross-sectional structure of the device in each step of the method for manufacturing the amorphous silicon layer 204 according to an embodiment of the present invention; the method for manufacturing the amorphous silicon layer according to an embodiment of the present invention comprises the following steps:
[0044] Step 1: Figure 4A As shown, a semiconductor substrate having a front layer structure 201 is provided, and a silicon dioxide layer 202 is formed on the front layer structure 201 by a PECVD process; the PECVD process causes the surface of the silicon dioxide layer 202 to have dangling H bonds such as Si-H bonds. Figure 4A In the figure, the surface layer of the silicon dioxide layer 202 having dangling H bonds is separately marked with a mark 203.
[0045] In the embodiment of the present invention, the silicon dioxide layer 202 serves as an etching stop layer for the subsequently formed amorphous silicon layer 204 .
[0046] In some embodiments, the silicon source in the PECVD process of the silicon dioxide layer 202 is silane, and the silicon dioxide layer 202 is PEOX.
[0047] In some embodiments, the silicon source in the PECVD process of the silicon dioxide layer 202 is TEOS, and the silicon dioxide layer 202 is PETEOS.
[0048] The semiconductor substrate includes a silicon substrate.
[0049] Step 2: Figure 4B As shown, the surface of the silicon dioxide layer 202 is subjected to plasma heat treatment, and the plasma heat treatment is used to release the H of the dangling H bonds of the silicon dioxide layer 202 and passivate the dangling bonds after the H release. The surface layer 203 is no longer shown in 4B, that is, the surface layer no longer contains the dangling H bonds.
[0050] In an embodiment of the present invention, the process gas for the plasma heat treatment includes nitrous oxide.
[0051] The process conditions of the plasma heat treatment include: vacuum pressure of 1 torr to 5 torr, nitrogen flow rate of 1000 sccm to 10000 sccm, nitrous oxide flow rate of 100 sccm to 1000 sccm, temperature of 350°C to 400°C, high-frequency RF power of 100 watts to 1000 watts, low-frequency RF power of 50 watts to 200 watts, and time of 2 seconds to 10 seconds.
[0052] Step 3: Figure 4C As shown, an amorphous silicon layer 204 is formed on the surface of the silicon dioxide layer 202 by a CVD deposition process. The characteristics that H on the surface of the silicon dioxide layer 202 is removed and the dangling bonds are passivated are utilized to prevent H in the deposition process of the amorphous silicon layer 204 from diffusing to the surface of the silicon dioxide layer 202 and combining with H on the surface of the silicon dioxide layer 202 to form hydrogen, thereby improving the adhesion between the amorphous silicon layer 204 and the silicon dioxide layer 202.
[0053] In the embodiment of the present invention, the silicon source of each amorphous silicon layer 204 is silane, and the amorphous silicon layer 204 is formed by decomposing silane.
[0054] The amorphous silicon layer 204 is used as a mandrel layer.
[0055] The amorphous silicon is patterned and etched using the silicon dioxide layer 202 as a stop layer to form a mandrel layer pattern.
[0056] A side wall is formed on the side of the mandrel layer pattern.
[0057] The mandrel layer pattern is removed and the pattern structure of the sidewall is formed.
[0058] The material of the sidewalls includes silicon nitride or metal nitride. The material of the sidewalls is formed by an atomic layer deposition process.
[0059] The front layer structure 201 on the semiconductor substrate includes a target layer for patterning; after the pattern structure of the sidewall is formed, etching is performed using the pattern structure of the sidewall as a mask to transfer the pattern structure to the target layer.
[0060] The pattern of the target layer includes a fin, a gate structure or a conductive line.
[0061] In the embodiment of the present invention, after forming the silicon dioxide layer 202 by the PECVD process, the amorphous silicon layer 204 is not deposited directly. Instead, plasma heat treatment is used to release H on the surface of the silicon dioxide layer 202 and passivate the dangling bonds after the H is released before depositing the amorphous silicon layer 204, so that hydrogen bubbles are avoided from being formed on the surface of the silicon dioxide layer 202 during the subsequent deposition of the amorphous silicon layer 204, thereby enabling a good contact interface between the silicon dioxide layer 202 and the amorphous silicon layer 204, thereby improving the adhesion between the amorphous silicon layer 204 and the bottom silicon dioxide layer 202; in the mandrel process, the etching accuracy of the amorphous silicon can also be improved, thereby improving the patterning accuracy.
[0062] like Figure 5 , which is a cross-sectional structure photo of a device formed by the manufacturing method of the amorphous silicon layer 204 according to an embodiment of the present invention, Figure 5 In the figure, the silicon dioxide layer is represented by the mark 202a alone, and the amorphous silicon layer is represented by the mark 204a alone. It can be seen that the contact interface between the two is good and there is no bubble layer.
[0063] The present invention has been described in detail above through specific embodiments, but these do not constitute a limitation of the present invention. Without departing from the principle of the present invention, those skilled in the art may also make many variations and improvements, which should also be regarded as the protection scope of the present invention.
Claims
1. A method for manufacturing an amorphous silicon layer, It is characterized in that The steps include: Step 1: providing a semiconductor substrate having a front layer structure, and forming a silicon dioxide layer on the front layer structure by using a PECVD process; the PECVD process causes the surface of the silicon dioxide layer to have dangling H bonds; Step 2, performing plasma heat treatment on the surface of the silicon dioxide layer, wherein the plasma heat treatment is used to release the H of the dangling H bonds of the silicon dioxide layer and passivate the dangling bonds after the H is released; Step three, using a CVD deposition process to form an amorphous silicon layer on the surface of the silicon dioxide layer, utilizing the characteristics that the H on the surface of the silicon dioxide layer is removed and the dangling bonds are passivated to prevent the H in the deposition process of the amorphous silicon layer from diffusing to the surface of the silicon dioxide layer and combining with the H on the surface of the silicon dioxide layer to form hydrogen, thereby improving the adhesion between the amorphous silicon layer and the silicon dioxide layer.
2. The method for producing an amorphous silicon layer according to claim 1, Features: The silicon dioxide layer serves as an etch stop layer for the amorphous silicon layer.
3. The method for manufacturing an amorphous silicon layer according to claim 2, Features: The amorphous silicon layer serves as a mandrel layer.
4. The method for manufacturing an amorphous silicon layer according to claim 1, Features: In step 1, the silicon source in the PECVD process of the silicon dioxide layer is silane, and the silicon dioxide layer is PEOX; Alternatively, the silicon source in the PECVD process of the silicon dioxide layer is TEOS, and the silicon dioxide layer is PETEOS.
5. The method for manufacturing an amorphous silicon layer according to claim 1, Features: In step 2, the process gas for the plasma heat treatment includes nitrous oxide.
6. The method for manufacturing an amorphous silicon layer according to claim 1, Features: The process conditions of the plasma heat treatment include: The vacuum pressure is 1 torr to 5 torr, the nitrogen flow rate is 1000 sccm to 10000 sccm, the nitrous oxide flow rate is 100 sccm to 1000 sccm, the temperature is 350°C to 400°C, the high-frequency RF power is 100 watts to 1000 watts, the low-frequency RF power is 50 watts to 200 watts, and the time is 2 seconds to 10 seconds.
7. The method for manufacturing an amorphous silicon layer according to claim 1, Features: In step three, the silicon source of each amorphous silicon layer is silane, and the amorphous silicon layer is formed by decomposing silane.
8. The method for manufacturing an amorphous silicon layer according to claim 3, Features: Also includes: Using the silicon dioxide layer as a stop layer, patterning and etching the amorphous silicon to form a mandrel layer pattern; forming side walls on the side surfaces of the mandrel layer pattern; The mandrel layer pattern is removed and the pattern structure of the sidewall is formed.
9. The method for manufacturing an amorphous silicon layer according to claim 8, Features: The front layer structure on the semiconductor substrate includes a target layer for patterning; after the pattern structure of the sidewall is formed, etching is performed using the pattern structure of the sidewall as a mask to transfer the pattern structure to the target layer.
10. The method for manufacturing an amorphous silicon layer according to claim 9, Features: The semiconductor substrate includes a silicon substrate.
11. The method for manufacturing an amorphous silicon layer according to claim 8, Features: The material of the sidewall spacer includes silicon nitride or metal nitride.
12. The method for manufacturing an amorphous silicon layer according to claim 8, Features: The material of the sidewall is formed by an atomic layer deposition process.
13. The method for manufacturing an amorphous silicon layer according to claim 9, Features: The pattern of the target layer includes a fin, a gate structure or a conductive line.
Citation Information
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