Semiconductor device and method for manufacturing the same

Abstract

A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes: a substrate including a memory cell region, the memory cell region including a first drain region, a first channel region, and a source region, the first channel region extending between the first drain region and the source region; a first floating gate located above a first portion of the first channel region; a first erase gate located above the first floating gate; a first select gate located above a second portion of the first channel region and on a side of the first floating gate away from the source region; a first programming channel extending from the first drain region to an edge portion of the first floating gate facing the first select gate; a second programming channel extending from the first drain region to the source region; and a first erase channel extending from an edge portion of the first floating gate facing the first erase gate to the first erase gate.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technologies, and in particular, to a semiconductor device and a method for manufacturing the same. Background Art

[0002] In electronic devices, it is necessary to use a memory to read and store data. Therefore, with the continuous growth of the demand for electronic devices, the requirements for memory technologies are also getting higher and higher.

[0003] Flash memory is an electrically erasable and reprogrammable non-volatile computer storage medium that can retain the on-chip information even after the power supply is turned off. Flash memory is convenient to use, having both the flexibility of reading and writing and a relatively fast access speed, and the characteristic of not losing information after power-off. Therefore, the flash memory technology has developed very rapidly.

[0004] Flash memory includes an array of addressable memory cells, where each memory cell includes a floating gate transistor for storing corresponding information. Therefore, it is desirable to improve the performance and / or parameters of the memory cells in flash memory to improve the overall performance and / or size of flash memory. Summary of the Invention

[0005] According to some embodiments of the present disclosure, there is provided a semiconductor device, including: a substrate including a memory cell region, where the memory cell region includes a first drain region, a first channel region, and a source region, and the first channel region extends between the first drain region and the source region; a first floating gate located above a first portion of the first channel region; a first erase gate located above the first floating gate; a first select gate located above a second portion of the first channel region and on a side of the first floating gate away from the source region; a first programming channel extending from the first drain region to an edge portion of the first floating gate facing the first select gate; a second programming channel extending from the first drain region to the source region; and a first erase channel extending from an edge portion of the first floating gate facing the first erase gate to the first erase gate.

[0006] According to some embodiments of the present disclosure, there is also provided a method for manufacturing a semiconductor device, including: forming an oxide layer on a substrate; forming a floating gate layer on the oxide layer; forming the hard mask layer on the floating gate layer; etching the hard mask layer to form a first opening passing through the hard mask layer; depositing polysilicon in the first opening; etching the polysilicon to form a second opening passing through the polysilicon and the floating gate layer and an erase gate; forming a source region in a region of the substrate below the second opening; etching a remaining portion of the floating gate layer to form the floating gate; forming a select gate on a side of the floating gate away from the source region; and forming a drain region in the substrate on a side of the select gate opposite to the floating gate.

[0007] According to some embodiments of the present disclosure, there is also provided a method for manufacturing a semiconductor device, including: forming an oxide layer on a substrate; forming a floating gate layer on the oxide layer; forming the hard mask layer on the floating gate layer; etching the hard mask layer to form a first opening and a second opening passing through the hard mask layer; depositing polysilicon in the first opening and the second opening respectively to form a first erase gate and a second erase gate; etching a portion of the floating gate layer outside the first opening and the second opening to form a first floating gate and a second floating gate; forming a source region in the substrate below a region between the first floating gate and the second floating gate; forming a first select gate and a second select gate respectively on sides of the first floating gate and the second floating gate away from the source region; and forming a drain region in the substrate on a side of the first select gate opposite to the first floating gate and in the substrate on a side of the second select gate opposite to the second floating gate respectively.

[0008] These and other aspects of the present disclosure will be apparent and will be elucidated with reference to the embodiments described hereinafter. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In the following description of the exemplary embodiments with reference to the accompanying drawings, more details, features and advantages of the present disclosure are disclosed. In the drawings:

[0010] Figure 1 is a schematic cross-sectional structure diagram of a semiconductor device according to some embodiments of the present disclosure;

[0011] Figure 2 is a schematic circuit diagram of a memory cell array according to some embodiments of the present disclosure;

[0012] Figure 3Is a top - down plan view of a memory cell array according to some embodiments of the present disclosure;

[0013] Figure 4 Is a schematic cross - sectional structure diagram of a semiconductor device according to some embodiments of the present disclosure;

[0014] Figure 5 Is a schematic cross - sectional structure diagram of a semiconductor device according to some embodiments of the present disclosure;

[0015] Figure 6 Is a schematic cross - sectional structure diagram of a semiconductor device according to some embodiments of the present disclosure;

[0016] Figure 7 Is a schematic cross - sectional structure diagram of a semiconductor device according to some embodiments of the present disclosure;

[0017] Figure 8 Is a schematic cross - sectional structure diagram of a semiconductor device according to some embodiments of the present disclosure;

[0018] Figure 9 Is a schematic flow chart of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0019] Figures 10A - 10H Is a schematic cross - sectional view of steps of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0020] Figures 11A - 11L Is a schematic cross - sectional view of steps of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0021] Figure 12 Is a schematic flow chart of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0022] Figures 13A - 13G Is a schematic cross - sectional view of steps of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0023] Figures 14A - 14L Is a schematic cross - sectional view of steps of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure. Detailed embodiments

[0024] It will be understood that although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or part from another. Thus, a first element, component, region, layer, or part discussed below may be referred to as a second element, component, region, layer, or part without departing from the teachings of the present disclosure.

[0025] Spatial relative terms such as "below", "beneath", "lower", "under", "above", "upper", etc. may be used herein for convenience of description to describe the relationship of one element or feature to another (or others) as illustrated in the figures. It will be understood that these spatial relative terms are intended to cover different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figure is flipped, an element described as "below" or "beneath" or "under" other elements or features will be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "beneath" can cover both the orientation above and the orientation below. Terms such as "before" or "in front of" and "after" or "subsequent to" can similarly be used, for example, to indicate the order in which light passes through an element. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptors used herein are to be interpreted accordingly. Additionally, it will also be understood that when a layer is referred to as "between two layers", it may be the only layer between the two layers, or there may also be one or more intermediate layers.

[0026] The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the disclosure. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items, and the phrase "at least one of A and B" refers to only A, only B, or both A and B.

[0027] It will be understood that when an element or layer is referred to as "on another element or layer", "connected to another element or layer", "coupled to another element or layer", or "adjacent to another element or layer", it can be directly on the other element or layer, directly connected to the other element or layer, directly coupled to the other element or layer, or directly adjacent to the other element or layer, or there can be intervening elements or layers. In contrast, when an element is referred to as "directly on another element or layer", "directly connected to another element or layer", "directly coupled to another element or layer", "directly adjacent to another element or layer", there are no intervening elements or layers. However, in any case, "on" or "directly on" should not be construed as requiring one layer to completely cover the underlying layer.

[0028] Embodiments of the present disclosure are described herein with reference to schematic illustrations of idealized embodiments of the present disclosure (and intermediate structures). As such, variations in the illustrated shapes are to be expected, for example, as a result of manufacturing techniques and / or tolerances. Accordingly, embodiments of the present disclosure should not be construed as limited to the specific shapes of regions illustrated herein, but should include, for example, shape deviations resulting from manufacturing. Thus, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the present disclosure.

[0029] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning that is consistent with their meaning in the relevant art and / or the context of this specification, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0030] As used herein, the term "substrate" can refer to the substrate of a diced wafer, or can indicate the substrate of an undiced wafer. Similarly, the terms chip and die can be used interchangeably, unless such interchange would cause a conflict.

[0031] In the prior art, memory cells in flash memory have problems of low erasure efficiency and large device size. To solve the above problems, the present disclosure provides a semiconductor device, including: a substrate including a memory cell region, wherein the memory cell region includes a first drain region, a first channel region, and a source region, and wherein the first channel region extends between the first drain region and the source region; a first floating gate located above a first portion of the first channel region; a first erasing gate located above the first floating gate; a first selection gate located above a second portion of the first channel region and on a side of the first floating gate away from the source region; a first programming channel extending from the first drain region to an edge portion of the first floating gate facing the first selection gate; a second programming channel extending from the first drain region to the source region; and a first erasing channel extending from an edge portion of the first floating gate facing the first erasing gate to the first erasing gate.

[0032] Figure 1 is a schematic cross-sectional structure diagram of a semiconductor device 100 according to some embodiments of the present disclosure.

[0033] As Figure 1 shown, the semiconductor device 100 includes a substrate 110 and gate structures 121a, 123a, and 124a formed above the substrate. Among them, the substrate 110 includes a memory cell region 110a, and the memory cell region 110a includes a first drain region 111a, a source region 112, and a first channel region 113a extending between the first drain region 111a and the source region 112. The gate structures 121a, 123a, and 124a include a first floating gate 121a, a first erasing gate 123a, and a first selection gate 124a.

[0034] Specifically, as Figure 1 shown, the first erasing gate 123a is located above the first floating gate 121a, the first floating gate 121a is located above a first portion of the first channel region 113a, and the first selection gate 124a is located above a second portion of the first channel region 113a and on a side of the first floating gate 121a away from the source region 112.

[0035] According to some embodiments, the first floating gate 121a, the first erasing gate 123a, and the first selection gate 124a are electrically insulated from each other. According to some embodiments, a spacer (e.g., an oxide structure and / or a silicon nitride structure) may be provided between any two of the first floating gate 121a, the first erasing gate 123a, and the first selection gate 124a to achieve the effect of electrical insulation.

[0036] According to some embodiments, both the first floating gate 121a and the first select gate 124a are electrically insulated from the substrate 110. According to some embodiments, an oxide structure may be provided between the first floating gate 121a and the first select gate 124a and the substrate to achieve the effect of electrical insulation. According to some embodiments, the oxide structures between the first floating gate 121a and the substrate 110 and between the first select gate 124a and the substrate 110 may be set to different thicknesses to achieve desired performance.

[0037] As Figure 1 shown, the semiconductor device 100 includes a first programming channel 131a, a second programming channel 131b, and an erase channel 132a. Among them, the first programming channel 131a extends from the first drain region 111a to the edge portion of the first floating gate 121a facing the first select gate 124a, the second programming channel 131b extends from the first drain region 111a to the source region 112, and the first erase channel 132a extends from the edge portion of the first floating gate 121a facing the first erase gate 123a to the first erase gate 123a.

[0038] According to some embodiments, when a programming operation is performed, a positive voltage higher than the threshold voltage (e.g., 1V) is applied to the first select gate 124a; positive voltages are applied to both the source region 112 and the first erase gate 123a to provide a strong lateral electric field. For example, a positive voltage of 5 - 8V is applied to the source region 112, and a positive voltage of 4.5V is applied to the first erase gate 123a; a negative current (e.g., -1 μA) is injected into the first drain region 111a. At this time, due to the source-side injection effect of electrons, a part of the hot electrons are injected into the first floating gate 121a through the first programming channel 131a, and a part of the hot electrons migrate to the source region 112 through the second programming channel 131b.

[0039] According to some embodiments, when an erase operation is performed, a relatively high positive voltage (e.g., 11V) is applied to the first erase gate 123a, while the first select gate 124a, the first drain region 111a, and the source region 112 are all set to 0V. At this time, due to the FN (Fowler - Nordheim) tunneling effect, under the action of the voltage difference between the first erase gate 123a and the first floating gate 121a, the electrons in the first floating gate 121a are pulled to the first erase gate 123a.

[0040] According to some embodiments, when a read operation is performed, by applying a positive voltage (e.g., 1.8 V) to the first select gate 124a, applying a lower positive voltage (e.g., 0.6 V) to the first drain region 111a, applying a positive voltage to the first erase gate 123a, and setting the source region 112 to 0 V, at this time, the state of the memory cell in the semiconductor device 100 is determined by the magnitude of the current value between the source and the drain.

[0041] In the embodiments described in the present disclosure, since the erase gate is disposed above the floating gate, the coupling area between the erase gate and the floating gate can be conveniently adjusted by adjusting the width of the erase gate, thereby reducing the coupling voltage between the erase gate and the floating gate, enabling a more efficient erase operation; and, since the erase gate is disposed above the floating gate, the requirement for the thickness of the floating gate can be reduced, and the difficulty of the manufacturing process can be reduced.

[0042] Figure 2 is a circuit schematic diagram of a memory cell array 200 according to some embodiments of the present disclosure. It should be understood that Figure 2 the number of memory cells, word lines, bit lines, source lines, and erase lines in is only illustrative, and any one of the above numbers can be adjusted according to actual application requirements to implement a larger or smaller scale memory cell array.

[0043] As Figure 2 shown, the memory cell array 200 includes a plurality of memory cells (e.g., Figure 2 the memory cell 210 shown), wherein each memory cell can be a semiconductor device 100 as Figure 1 shown. According to some embodiments, each memory cell includes a select transistor and a floating transistor connected in series. For example, Figure 2 the memory cell 210 in includes a select transistor 211 and a floating gate transistor 212, wherein the memory cell with a fixed address can be selected for operation through the select transistor 211, and the floating gate transistor 212 can store information.

[0044] According to some embodiments, each row of memory cells corresponds to a word line. For example, in Figure 2 the memory cells in the upper row correspond to the word line WLn-1, the memory cells in the lower row correspond to the word line WLn, and each word line is connected to the gate of the select transistor in the corresponding memory cell. According to some embodiments, each column of memory cells corresponds to a bit line. For example, in Figure 2In [the figure], the memory cells in the left column correspond to bit line BLn-1, the memory cells in the middle column correspond to bit line BLn, and the memory cells in the right column correspond to bit line BLn+1. Each bit line is connected to the drain of the selection transistor in the corresponding memory cell. According to some embodiments, the memory cells in two adjacent rows correspond to one source line. For example, in Figure 2 the memory cells in the upper and lower rows both correspond to source line SL, and each source line is connected to the source of the floating gate transistor in the corresponding memory cell. According to some embodiments, the memory cells in each row correspond to one erase line. For example, in Figure 2 the memory cells in the upper row correspond to erase line EGn-1, and the memory cells in the lower row correspond to erase line EGn. According to some embodiments, the source lines of all the memory cells in each sector in the memory are electrically connected together.

[0045] According to some embodiments, the drain of the selection transistor in the memory cell corresponds to Figure 1 the first drain region 111a in the semiconductor device 100 shown in [the figure], the gate of the selection transistor in the memory cell corresponds to Figure 1 the first selection gate 124a in the semiconductor device 100 shown in [the figure], the floating gate of the floating transistor in the memory cell corresponds to Figure 1 the first floating gate 121a in the semiconductor device 100 shown in [the figure], and the source of the floating transistor in the memory cell corresponds to Figure 1 the source region 112 in the semiconductor device 100 shown in [the figure].

[0046] Figure 3 is a top plan view of a memory cell array 300 (e.g., Figure 2 the memory cell array 200 shown in the circuit diagram of [the figure]) according to some embodiments of the present disclosure. As Figure 3 shown, the memory cell array 300 includes multiple bit lines BLn-1, BLn, and BLn+1, multiple word lines WLn-1 and WLn, multiple floating gates FG1-FG6, a source line SL, and erase lines EGn and EGn-1.

[0047] According to some embodiments, the memory cells in each column correspond to the same bit line. For example, as Figure 3 shown, the two memory cells in the left column both correspond to bit line BLn-1. It should be understood that although not shown, the bit line structures of the memory cells in the same column are electrically connected.

[0048] According to some embodiments, the memory cells in each row correspond to the same word line. For example, as Figure 3 shown, the three memory cells in the upper row all correspond to word line WLn-1. According to some embodiments, as Figure 3As shown, each word line extends through multiple memory cells in the same row.

[0049] According to some embodiments, each memory cell has a corresponding floating gate. For example, as Figure 3 shown, the memory cell in the upper left corner has a corresponding floating gate FG1.

[0050] According to some embodiments, the memory cells in adjacent rows correspond to the same source line. For example, as Figure 3 shown, the six memory cells in the upper and lower two rows both correspond to the source line SL. According to some embodiments, as Figure 3 shown, the source line SL extends through the memory cells in adjacent rows. According to some embodiments, the memory cells in each row correspond to the same erase line. For example, as Figure 3 shown, the three memory cells in the upper row all correspond to the erase line EGn-1.

[0051] Figure 4 FIG. is a schematic cross-sectional structure diagram of a semiconductor device 400 according to some embodiments of the present disclosure. Figure 4 and Figure 1 the same or similar reference numerals in indicate the same or similar structures.

[0052] According to some embodiments, in addition to having the features described in the semiconductor device 100 with reference to Figure 1 in, Figure 4 the semiconductor device 400 shown also has the following features: A first erase gate 123a is located above a first portion of the first floating gate 121a close to the source region 112. According to some embodiments, the semiconductor device 400 may further include a first erase gate spacer 125 formed above a second portion of the first floating gate 121a away from the source region 112. In some examples, by providing the erase gate spacer 125, the width of the first erase gate 123a can be conveniently adjusted, and thus the coupling area between the first erase gate 123a and the first floating gate 121a can be adjusted. Thereby, the coupling voltage between the erase gate and the floating gate is reduced, so that the erase operation can be performed more efficiently.

[0053] Figure 5 FIG. is a schematic cross-sectional structure diagram of a semiconductor device 500 according to some embodiments of the present disclosure. Figure 5 and Figure 1 the same or similar reference numerals in indicate the same or similar structures.

[0054] According to some embodiments, in addition to having the features described in the semiconductor device 100 with reference to Figure 1 in, Figure 5The semiconductor device 500 shown also has the following characteristics: The first erase gate 123a is located above the first part of the first floating gate 121a, and this first part is close to the central region of the first floating gate 121a. The first erase gate spacer 125 includes a first erase gate spacer 125a and a first erase gate spacer 125b, which are respectively formed above the second part outside the first part of the first floating gate 121a (i.e., on both sides of the first erase gate 123a).

[0055] According to some embodiments, the semiconductor device as described in the present disclosure further includes: a first floating gate spacer located between the first floating gate and the first select gate.

[0056] According to some embodiments, the semiconductor device as described in the present disclosure further includes: a first tunneling oxide structure formed between the first floating gate and the first erase gate and between the first floating gate and the first erase gate spacer.

[0057] According to some embodiments, the semiconductor device as described in the present disclosure further includes: a second floating gate spacer located on the side of the first floating gate away from the first select gate.

[0058] According to some embodiments, the semiconductor device as described in the present disclosure further includes: a first substrate oxide structure located between the first floating gate and the substrate; and a second substrate oxide structure located between the first select gate and the substrate.

[0059] According to some embodiments, the first substrate oxide structure has a different thickness from the second substrate oxide to meet the requirements of different structures of the memory cells (e.g., the first floating gate and the first select gate).

[0060] According to some embodiments, the first drain region further includes a lightly doped drain region and a heavily doped drain region, and the semiconductor device as described in the present disclosure further includes: a first lightly doped drain spacer located above the first drain region and on the side of the first select gate opposite to the first floating gate.

[0061] According to other embodiments, the first drain region only includes a drain region with the same doping concentration. For example, the lightly doped drain process is not performed on the memory cells.

[0062] According to some embodiments, the semiconductor device as described in the present disclosure further includes: a silicide structure located above the first drain region, the first select gate, and the erase gate. In the embodiments as described in the present disclosure, setting the silicide structure above the first drain region, the first select gate, and the erase gate facilitates subsequent electrode lead-out to apply voltage for corresponding operations.

[0063] Figure 6It is a schematic cross-sectional structure diagram of a semiconductor device 600 according to some embodiments of the present disclosure. Figure 6 and Figure 4 The same or similar reference numerals in

[0064] According to some embodiments, in addition to having the features described for the semiconductor device 400 in Figure 4 , the semiconductor device 600 shown also has the following features: Figure 6 Shown in

[0065] 1) The semiconductor device 600 further includes: a first floating gate spacer 141a located between the first floating gate 121a and the first select gate 124a, and a first tunneling oxide structure 142a formed on the lower surface between the first erase gate 123a and the first floating gate 121a and between the first erase gate 123a and the first erase gate spacer 125;

[0066] 2) The semiconductor device 600 further includes: a second floating gate spacer 143a located on the side of the first floating gate 121a opposite to the first select gate 124a;

[0067] 3) The semiconductor device 600 further includes: a first substrate oxide structure 151 located between the first floating gate 121a and the substrate 110, and a second substrate oxide structure 152 located between the first select gate 124a and the substrate 110;

[0068] 4) In the semiconductor device 600, the first drain region 111a further includes a heavily doped drain region 1111a and a lightly doped drain region 1112a, and the semiconductor device 600 further includes: a first lightly doped drain spacer 144 located above the first drain region 111a and on the side of the first select gate 124a opposite to the first floating gate 121a;

[0069] 5) The semiconductor device 600 further includes: silicide structures 161a - 161c formed respectively above the first erase gate 123a, the first select gate 124a, and the first drain region 111a.

[0070] According to some embodiments, the second floating gate spacer can be made of two layers of materials, for example, oxide and silicon nitride. According to other embodiments, the second floating gate spacer can be made of only one layer of material, for example, oxide or silicon nitride.

[0071] Figure 7 It is a schematic cross-sectional structure diagram of a semiconductor device 700 according to some embodiments of the present disclosure. Figure 7 and Figure 5 The same or similar reference numerals in

[0072] According to some embodiments, in addition to having a reference Figure 5 The features of the semiconductor device 500 described in Figure 7 The semiconductor device 700 shown also has the following features:

[0073] 1) The semiconductor device 700 further includes: a first floating gate spacer 141a located between the first floating gate 121a and the first selection gate 124a, and a first tunneling oxide structure 142a formed on the lower surface between the first erase gate 123 and the first floating gate 121a and between the first erase gate 123a and the first erase gate spacer 125 (125a and 125b);

[0074] 2) The semiconductor device 700 further includes: a second floating gate spacer 143a located on a side of the first floating gate 121a opposite to the first selection gate 124a;

[0075] 3) The semiconductor device 700 further includes: a first substrate oxide structure 151 located between the first floating gate 121a and the substrate 110, and a second substrate oxide structure 152 located between the first selection gate 124a and the substrate 110;

[0076] 4) In the semiconductor device 700, the first drain region 111a further includes a heavily doped drain region 1111a and a lightly doped drain region 1112a, and the semiconductor device 700 further includes: a first lightly doped drain spacer 144 located above the first drain region 111a and on a side of the first select gate 124a opposite to the first floating gate 121a;

[0077] 5) The semiconductor device 700 further includes: silicide structures 161a-161c formed respectively on the first erase gate 123a, the first select gate 124a and the first drain region 111a.

[0078] According to some embodiments, the second floating gate spacer may be made of two layers of material, for example, oxide and silicon nitride. According to other embodiments, the second floating gate spacer may be made of only one layer of material, for example, oxide or silicon nitride.

[0079] According to some embodiments, the memory cell region further includes: a second drain region and a second channel region, wherein the second channel region extends between the second drain region and the source region; and the semiconductor device as described in the present disclosure further includes: a second floating gate located above a first portion of the second channel region; a second erase gate located above the second floating gate; a second select gate located above a second portion of the second channel region and on a side of the second floating gate away from the source region; a third programming channel extending from the second drain region to an edge portion of the second floating gate facing the second select gate; a fourth programming channel extending from the second drain region to the source region; and a second erase channel extending from an edge portion of the second floating gate facing the second erase gate to the second erase gate. In the semiconductor structure as described in the present disclosure, by symmetrically arranging a pair of gate structures (i.e., the floating gate, the select gate, and the erase gate), a pair of memory cells (e.g., Figure 2 two memory cells located in the same column in

[0080] Figure 8 is a schematic cross-sectional structure diagram of a semiconductor device 800 according to some embodiments of the present disclosure. Figure 8 and Figure 1 the same or similar reference numerals in

[0081] According to some embodiments, in addition to having the features described in the semiconductor device 100 with reference to Figure 1 in Figure 8 the semiconductor device 800 shown also has the following features:

[0082] 1) The memory cell region 110a further includes: a second drain region 111b symmetrically arranged with the first drain region 111a, and a second channel region 113b extending between the second drain region 111b and the source region 112.

[0083] 2) The semiconductor device 800 further includes: a second floating gate 121b symmetrically arranged with the first floating gate 121a, located above a first portion of the second channel region 113b; and a second select gate 124b symmetrically arranged with the first select gate 124a, located above a second portion of the second channel region 113b and on a side of the second floating gate 121b away from the source region 112.

[0084] 3) With Figure 1Similar to the semiconductor device 100 in [reference], the semiconductor device 800 has a first programming channel 131a and a second programming channel 131b for performing a programming operation on the memory cells on the left side, and a first erasing channel 132a for performing an erasing operation on the memory cells on the left side; and the semiconductor device 800 has a third programming channel 131c and a fourth programming channel 131d for performing a programming operation on the memory cells on the right side, and a second erasing channel 132b for performing an erasing operation on the memory cells on the right side. Among them, the third programming channel 131c extends from the second drain region 111b to the edge portion of the second floating gate 121b facing the second select gate 124b, the fourth programming channel extends from the second drain region 111b to the source region 112, and the second erasing channel 132b extends from the edge portion of the second floating gate 121b facing the second erase gate 121b to the second erase gate 123b. According to some embodiments, the memory cells in the semiconductor device 800 can be programmed, erased, or read in a manner similar to that described in the above reference Figure 1 The memory cells in the semiconductor device 800 can be programmed, erased, or read in a manner similar to that described above.

[0085] According to some other embodiments, similar to that described in the reference Figure 8 Other symmetric gate structures, spacers, oxide structures, and / or drain structures can also be provided on both sides of the source region of the semiconductor device, so that a pair of memory cells (for example, Figure 2 Two memory cells in the same column in [reference]) can share the source region, reducing the overall area and size of the memory cell array. For example, similar to Figure 8 The semiconductor structure can be set as the symmetric structure of the semiconductor structure in Figures 4 - 7 [reference].

[0086] According to some embodiments, the second erase gate is located above the first portion of the second floating gate. The semiconductor device as described in the present disclosure further includes: a second erase gate spacer formed above the second portion of the second floating gate.

[0087] According to some embodiments, the semiconductor device as described in the present disclosure further includes: a third floating gate spacer located between the second floating gate and the second select gate.

[0088] According to some embodiments, the semiconductor device as described in the present disclosure further includes: a second tunneling oxide structure formed between the second floating gate and the second erase gate and between the second erase gate spacer and the second erase gate.

[0089] According to some embodiments, the semiconductor device as described in the present disclosure further includes: a fourth floating gate spacer located on the side of the second floating gate opposite to the second select gate.

[0090] According to some embodiments, the substrate further includes a logic region, and the semiconductor device as described in the present disclosure further includes: logic devices located above the logic region of the substrate. According to some embodiments, a shallow trench isolation may be provided between the logic devices and the memory cells to electrically isolate the logic devices and the memory cells. According to some embodiments, the logic devices include, but are not limited to, control devices and state reading devices for performing programming operations, erasing operations, or reading operations on the memory cells.

[0091] The present disclosure provides a method for manufacturing a semiconductor device, including: forming an oxide layer on a substrate; forming a floating gate layer on the oxide layer; forming a hard mask layer on the floating gate layer; etching the hard mask layer to form a first opening passing through the hard mask layer; depositing polysilicon in the first opening; etching the polysilicon to form a second opening passing through the polysilicon and the floating gate layer and an erase gate; forming a source region in a region of the substrate below the second opening; etching the remaining portion of the floating gate layer to form a floating gate; forming a select gate on a side of the floating gate away from the source region; and forming a drain region in the substrate on a side of the select gate opposite to the floating gate.

[0092] Figure 9 is a schematic flowchart of a manufacturing method 900 of a semiconductor device according to some embodiments of the present disclosure.

[0093] At step S901, an oxide layer is formed on the substrate.

[0094] According to some embodiments, the manufacturing method 900 further includes: before forming the oxide layer on the substrate, forming a shallow trench isolation in the substrate in advance, for example, forming a shallow trench isolation parallel to the bit lines in the memory cell array 300 as shown. According to some embodiments, the manufacturing method 900 further includes: before forming the oxide layer on the substrate, implanting a memory cell well in the substrate in advance. Figure 3 According to some embodiments, the process of forming the shallow trench isolation may include, but is not limited to, the following steps: forming a pad oxide, depositing silicon nitride, active region exposure, shallow insulating trench etching, shallow insulating trench filling, shallow insulating trench planarization, and removing the silicon nitride.

[0095] According to some embodiments, an oxide layer is grown on the upper surface of the substrate.

[0096] At step S902, a floating gate layer is formed on the oxide layer.

[0097] According to some embodiments, floating gate polysilicon is deposited on the upper surface of the oxide layer, and the floating gate polysilicon is planarized.

[0098] According to some embodiments, floating gate polysilicon is deposited on the upper surface of the oxide layer, and the floating gate polysilicon is planarized.

[0099] At step S903, a hard mask layer is formed on the floating gate layer.

[0100] According to some embodiments, a hard mask material is deposited on the upper surface of the floating gate layer.

[0101] Figure 10A A cross-sectional view of an exemplary structure formed after steps S901 - S903 is shown. As Figure 10A shown, the semiconductor structure 1000 includes, from bottom to top in sequence: a substrate 110, an oxide layer 1001, a floating gate layer 1002, and a hard mask layer 1003.

[0102] At step S904, the hard mask layer is etched to form a first opening therethrough.

[0103] According to some embodiments, before etching the hard mask layer, a photoresist is coated on the hard mask layer, and a photolithography process is performed to form a photoresist pattern required for subsequent etching processes.

[0104] Figure 10B A cross-sectional view of an exemplary structure formed after steps S901 - S904 is shown. As Figure 10B shown, the semiconductor structure 1000 further includes a first opening 1010 passing through the hard mask layer 1003.

[0105] At step S905, polysilicon is deposited in the first opening.

[0106] According to some embodiments, before depositing polysilicon in the first opening, an oxide is deposited on the sidewalls of the hard mask layer in the first opening to form a first erase gate spacer. According to some embodiments, it further includes forming a tunneling oxide structure on the side of the first erase gate spacer away from the hard mask layer and on the floating gate layer in the first opening.

[0107] According to some embodiments, the process of depositing polysilicon in the first opening may include but is not limited to the following steps: depositing polysilicon, polysilicon planarization (with or without dummy poly), photolithography of the polysilicon, and etching the polysilicon.

[0108] Figure 10C A cross-sectional view of an exemplary structure formed after steps S901 - S905 is shown. As Figure 10C shown, the semiconductor structure 1000 includes polysilicon 1020 deposited in the first opening 1010. As Figure 10CAs shown, in some embodiments, before depositing polysilicon 1020 in the first opening 1010, the semiconductor structure 1000 may further include a first erase gate spacer 125 and a second erase gate spacer 126 formed by depositing an oxide on the side surfaces of the hard mask layer 1003 in the first opening 1010, and a tunneling oxide structure 142 formed on the side surfaces between the first erase gate spacer 125 and the second erase gate spacer 126 and on the floating gate layer 1002 in the first opening 1010.

[0109] At step S906, the polysilicon is etched to form a second opening passing through the polysilicon and the floating gate layer and an erase gate.

[0110] According to some embodiments, before etching the polysilicon, a photoresist 1004 is coated on the hard mask layer and a portion of the polysilicon, and a photolithography process is performed to form a photoresist pattern required for subsequent etching processes.

[0111] Figure 10D A cross-sectional view of an exemplary structure formed after steps S901 to S906 is shown. As Figure 10D shown, the semiconductor structure 1000 further includes a photoresist 1004 located above the hard mask layer 1003, and a second opening 1030, a first erase gate 123a, and a second erase gate 123b formed by etching. The tunneling oxide structure 142 is formed as a first tunneling oxide structure 142a and a second tunneling oxide structure 142b after step S906.

[0112] At step S907, a source region is formed in the region of the substrate located below the second opening.

[0113] According to some embodiments, a source implantation process (e.g., using arsenic or phosphorus) is performed to form a source region in the region of the substrate located below the first opening.

[0114] Figure 10E A cross-sectional view of an exemplary structure formed after steps S901 to S907 is shown. As Figure 10E shown, the semiconductor structure 1000 further includes a source region 112 located below the second opening 1030.

[0115] At step S908, the remaining portion of the floating gate layer is etched to form a floating gate.

[0116] According to some embodiments, before etching the remaining portion of the floating gate layer, an oxide is deposited in the second opening to close the second opening. The oxide includes, but is not limited to, silicon dioxide.

[0117] According to some embodiments, after depositing an oxide in the second opening, the first oxide is planarized.

[0118] According to some embodiments, before depositing an oxide in the second opening, a second floating gate spacer is formed on the side surfaces of the floating gate layer and the erase gate in the second opening.

[0119] Figure 10F A cross-sectional view of an exemplary structure formed after steps S901 to S908 is shown. As Figure 10F shown, the semiconductor structure 1000 further includes floating gates 121a and 121b formed by etching the remaining portions of the floating gate layer.

[0120] At step S909, a select gate is formed on a side of the floating gate away from the source region.

[0121] According to some embodiments, before forming a select gate on a side of the floating gate away from the source region, a first floating gate spacer is formed on the side of the floating gate away from the source region.

[0122] According to some embodiments, after forming the first floating gate spacer and before forming the select gate, an exposed portion of the oxide layer (i.e., the portion not having a gate structure, polysilicon, or spacer formed thereon) is etched, and an oxide is grown on the substrate to provide an oxide with a desired thickness for the select gate and / or logic device.

[0123] According to some embodiments, before forming a select gate on a side of the floating gate away from the source region, a portion of the oxide layer on the side of the floating gate away from the source region is etched to form a first substrate oxide structure between the floating gate and the substrate; and on the side of the floating gate away from the source region, a second oxide is deposited on the substrate to form a second substrate oxide structure between the select gate and the substrate.

[0124] According to some embodiments, the process of forming the select gate may include but is not limited to the following steps: depositing polysilicon, polysilicon planarization (with or without dummy poly), lithography on the polysilicon, and etching the polysilicon.

[0125] According to some embodiments, before forming the select gate, a word line threshold voltage injection process may be performed to improve the performance of the subsequently formed select gate.

[0126] Figure 10G A cross-sectional view of an exemplary structure formed after steps S901 to S909 is shown. As Figure 10GAs shown, the semiconductor structure 1000 further includes a first select gate 124a formed on a side of the first floating gate 121a away from the source region 112 and a second select gate 124b formed on a side of the second floating gate 121b away from the source region 112.

[0127] At step S910, a drain region is formed in the substrate on a side of the select gate opposite to the floating gate.

[0128] According to some embodiments, a drain implantation process is performed to form a drain region in the substrate on a side of the select gate opposite to the floating gate.

[0129] According to some embodiments, forming a drain region in the substrate on a side of the select gate opposite to the floating gate further includes: performing a lightly doped implantation in the substrate on a side of the select gate opposite to the floating gate to form a lightly doped drain region; forming a lightly doped drain spacer on a side of the select gate opposite to the floating gate; and performing a heavily doped implantation in the substrate on a side of the lightly doped drain spacer opposite to the select gate to form a heavily doped drain region. In the method as described in the present disclosure, by performing a lightly doped implantation to form a lightly doped drain region, the channel electric field distribution in the memory cell can be improved.

[0130] According to some embodiments, the manufacturing method as described in the present disclosure further includes, after forming a drain region in the substrate on a side of the select gate opposite to the floating gate: forming a silicide structure over the drain region, the select gate, and the erase gate.

[0131] Figure 10H A cross-sectional view of an exemplary structure formed after steps S901 to S910 is shown. As Figure 10H shown, the semiconductor structure 1000 further includes a first drain region 111a in the substrate 110 on a side of the first select gate 124a opposite to the first floating gate 121a and a second drain region 111b in the substrate 110 on a side of the second select gate 124b opposite to the second floating gate 121b.

[0132] According to some embodiments, after forming the symmetric structure as Figure 10H shown, it can be cut along the midline of the source region 112 to form a single memory cell structure as Figure 1 、 4 -8 shown. According to other embodiments, it may also not be cut, such that adjacent memory cells in the symmetric structure share the source region, so as to reduce the overall area and size of the memory cell array.

[0133] According to some embodiments, the manufacturing method of the semiconductor device as described in the present disclosure further includes: forming logic devices over the logic region of the substrate.

[0134] Figures 11A - 11L It is a schematic cross-sectional view of the steps of a method for fabricating a semiconductor device 1100 according to some embodiments of the present disclosure.

[0135] According to some embodiments, as Figure 11A shown, and similar to that described with reference to Figure 11A the semiconductor structure 1100 sequentially includes, from bottom to top: a substrate 110, an oxide layer 1101, a floating gate layer 1102, and a hard mask layer 1103.

[0136] According to some embodiments, first, an oxide layer 1401 is grown on the upper surface of the substrate 110; then, floating gate polysilicon is deposited on the upper surface of the oxide layer 1101, and the floating gate polysilicon is planarized to form a floating gate layer 1102; then, a hard mask layer 1103 is deposited on the upper surface of the floating gate layer 1102.

[0137] According to some embodiments, before forming the oxide layer 1101 on the substrate 110, shallow trench isolation is formed in the substrate 110 in advance, and / or memory cell wells are implanted in the substrate 110 in advance.

[0138] According to some embodiments, as Figure 11B shown, the hard mask layer 1103 is etched to form an opening 1110 through the hard mask layer 1103.

[0139] According to some embodiments, as Figure 11C shown, an oxide (e.g., by high-temperature oxidation) is deposited on the sidewalls of the opening 1110 to form a first erase gate spacer 125 and a second erase gate spacer 126. According to some embodiments, the process of forming the first erase gate spacer 125 and the second erase gate spacer 126 may include etching the deposited oxide.

[0140] According to some embodiments, as Figure 11D shown, first, a tunneling oxide is deposited above the floating gate layer 1102 in the opening 1110 to form a tunneling oxide structure 142; then, polysilicon 1020 is deposited on the tunneling oxide structure 142. According to some embodiments, after forming the tunneling oxide structure and depositing the polysilicon, the polysilicon is planarized and the excess tunneling oxide structure is removed.

[0141] According to some embodiments, as Figure 11E shown, first, a photolithography process is performed on the upper surfaces of the hard mask layer 1103, the first erase gate spacer 125, the second erase gate spacer 126, and a portion of the polysilicon 1020 to form a photoresist pattern 1104 to, as Figure 11EThe remaining portion of the polysilicon 1020, the tunneling oxide structure, and the floating gate layer 1102 are etched to form a second opening 1130 that passes through the polysilicon 1020, the tunneling oxide structure, and the floating gate layer 1102, and a first erase gate 123a and a second erase gate 123b are formed.

[0142] According to some embodiments, as Figure 11F shown, a source implantation process is performed in a region of the substrate 110 below the second opening 1130 to form a source region 112.

[0143] According to some embodiments, as Figure 11G shown, first, the photoresist 1104 is removed; second, a first oxide 1140 is deposited over the source region 112 to fill the second opening 1130 as Figure 11F shown, and the deposited first oxide is planarized. According to some embodiments, before depositing the oxide 1140 over the source region 112, a second floating gate spacer 143a is formed on the side surfaces of the floating gate layer 1102 and the first erase gate 123a in the second opening 1130; a fourth floating gate spacer 143b is formed on the side surfaces of the floating gate layer 1102 and the second erase gate 123b in the second opening 1130.

[0144] According to some embodiments, two materials (e.g., oxide and silicon nitride) can be used to form the second control gate spacer and the fourth floating gate spacer, e.g., by depositing oxide, depositing silicon nitride, and etching the deposited oxide and silicon nitride to form the second control gate spacer and the fourth floating gate spacer. According to some embodiments, one material (e.g., oxide or silicon nitride) can be used to form the second control gate spacer and the fourth floating gate spacer, e.g., by depositing a spacer material and etching the deposited material to form the second control gate spacer and the fourth floating gate spacer.

[0145] By depositing on the side surfaces of the floating gate layer 1102, the first erase gate 123a, and the second erase gate 123b in the second opening 1130, the floating gate and the erase gates can be further protected in subsequent processes.

[0146] According to some embodiments, as Figure 11H shown, the remaining portion of the floating gate layer 1102 is etched to form a first floating gate 121a and a second floating gate 121b.

[0147] According to some embodiments, as Figure 11IAs shown, a first floating gate spacer 141a is formed on a side surface of the first floating gate 121a away from the source region 112, and a third floating gate spacer 141b is formed on a side surface of the second floating gate 121b away from the source region 112.

[0148] According to some embodiments, two materials (e.g., oxide and silicon nitride) can be used to form the first control gate spacer and the third floating gate spacer. For example, the first control gate spacer and the third floating gate spacer are formed by depositing an oxide, depositing silicon nitride, and etching the deposited oxide and silicon nitride. According to some embodiments, one material (e.g., oxide or silicon nitride) can be used to form the first control gate spacer and the third floating gate spacer. For example, the first control gate spacer and the third floating gate spacer are formed by depositing a spacer material and etching the deposited material.

[0149] According to some embodiments, as Figure 11J shown, before forming the first select gate 124a and the second select gate 124b, the exposed portions of the oxide layer (i.e., the portions where no gate structure or spacer is formed thereon) are etched; then, oxide structures 152a and 152b are grown on the substrate 110 to provide a desired substrate oxide thickness for the subsequently formed select gates and / or logic devices.

[0150] According to some embodiments, as Figure 11K shown, a first select gate 124a is formed on a side of the first floating gate spacer 141a opposite to the first floating gate 121a, and a second select gate 124b is formed on a side of the third floating gate spacer 141b opposite to the second floating gate 121b. Specifically, forming the select gates 124a and 124b includes, but is not limited to, the following steps: depositing polysilicon, polysilicon planarization (with or without dummy poly), lithography on the polysilicon, and etching the polysilicon.

[0151] According to some embodiments, as Figure 11LAs shown, first, a lightly doped implantation is performed to form a first lightly doped drain region 1112a and a second lightly doped drain region 1112b; then, a first lightly doped drain spacer 144a is formed on a side of the first select gate 124a opposite to the second floating gate spacer 141b, and a second lightly doped drain spacer 144b is formed on a side of the second select gate 124b opposite to the fourth floating gate spacer 141d; then, a heavily doped implantation is performed to form a first heavily doped drain region 1111a and a second heavily doped drain region 1111b. According to some embodiments, before performing the lightly doped implantation, a photoresist may be used to cover the regions on the substrate where logic devices are to be formed to protect these regions from being exposed.

[0152] The present disclosure provides a method for manufacturing a semiconductor device, including: forming an oxide layer on a substrate; forming a floating gate layer on the oxide layer; forming a hard mask layer on the floating gate layer; etching the hard mask layer to form a first opening and a second opening passing through the hard mask layer; depositing polysilicon in the first opening and the second opening respectively to form a first erase gate and a second erase gate; etching a portion of the floating gate layer outside the first opening and the second opening to form a first floating gate and a second floating gate; forming a source region in the substrate below the region between the first floating gate and the second floating gate; forming a first select gate and a second select gate respectively on a side of the first floating gate and the second floating gate away from the source region; and forming drain regions in the substrate on a side of the first select gate opposite to the first floating gate and on a side of the second select gate opposite to the second floating gate respectively.

[0153] Figure 12 is a schematic flowchart of a method 1200 for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0154] At step S1201, an oxide layer is formed on the substrate.

[0155] According to some embodiments, step S1201 may be similar to that described in step S901 of reference Figure 9 as described.

[0156] At step S1202, a floating gate layer is formed on the oxide layer.

[0157] According to some embodiments, step S1202 may be similar to that described in step S902 of reference Figure 9 as described.

[0158] At step S1203, a hard mask layer is formed on the floating gate layer.

[0159] According to some embodiments, step S1203 may be similar to that described in reference Figure 9Similar to that described in step S903.

[0160] Figure 13A Shows a cross-sectional view of the exemplary structure 1300 formed after steps S1201 - S1203. As Figure 13A shown, and similar to that described in reference Figure 10A the semiconductor structure 1300 includes, from bottom to top in sequence: a substrate 110, an oxide layer 1301, a floating gate layer 1302, and a hard mask layer 1303.

[0161] At step S1204, the hard mask layer is etched to form a first opening and a second opening through the hard mask layer.

[0162] According to some embodiments, before etching the hard mask layer, a photoresist is coated on the hard mask layer, and a photolithography process is performed to form a photoresist pattern required for subsequent etching processes.

[0163] Figure 13B Shows a cross-sectional view of the exemplary structure 1300 formed after steps S1201 - S1204. As Figure 13B shown, the semiconductor structure 1300 further includes a first opening 1310 and a second opening 1320.

[0164] At step S1205, polysilicon is deposited in the first opening and the second opening respectively to form a first erase gate and a second erase gate.

[0165] According to some embodiments, before depositing polysilicon in the first opening and the second opening respectively, an oxide is deposited on the sidewalls of the hard mask layer in the first opening and the second opening to form a first erase gate spacer and a second erase gate spacer in the first opening and the second opening; and a tunneling oxide structure is formed between the first erase gate spacer and the second erase gate spacer in the first opening and the second opening.

[0166] According to some embodiments, the process of forming the first erase gate and the second erase gate may include but is not limited to the following steps: depositing polysilicon, polysilicon planarization (with or without dummy poly), performing photolithography on the polysilicon, and etching the polysilicon.

[0167] Figure 13C Shows a cross-sectional view of the exemplary structure 1300 formed after steps S1201 - S1205. As Figure 13C shown, the semiconductor structure 1300 further includes a first erase gate 123a formed in the first opening 1310 and a second erase gate 123b formed in the second opening 1320.

[0168] At step S1206, the portions of the floating gate layer other than those in the first opening and the second opening are etched to form a first floating gate and a second floating gate.

[0169] According to some embodiments, before etching the portions of the floating gate layer other than those in the first opening and the second opening, a third erase gate spacer and a fourth erase gate spacer are respectively formed above the first erase gate and the second erase gate.

[0170] Figure 13D A cross-sectional view of an exemplary structure 1300 formed after steps S1201 - S1206 is shown. As Figure 13D shown, the semiconductor structure 1300 further includes a first floating gate 121a and a second floating gate 121b formed

[0171] At step S1207, a source region is formed in the substrate below the region between the first floating gate and the second floating gate.

[0172] According to some embodiments, step S1207 can be similar to that described in step S907 of reference Figure 9 therein.

[0173] According to some embodiments, a source implantation process (e.g., using arsenic or phosphorus) is performed to form a source region in the region of the substrate below the second opening.

[0174] Figure 13E A cross-sectional view of an exemplary structure 1300 formed after steps S1201 - S1207 is shown. As Figure 13E shown, the semiconductor structure 1300 further includes a source region 112 formed in the substrate below the intermediate region between the first floating gate 121a and the second floating gate 121b.

[0175] At step S1208, a first select gate and a second select gate are respectively formed on the sides of the first floating gate and the second floating gate away from the source region.

[0176] According to some embodiments, step S1208 can be similar to that described in step S909 of reference Figure 9 therein.

[0177] According to some embodiments, before respectively forming a first select gate and a second select gate on the sides of the first floating gate and the second floating gate away from the source region, floating gate spacers are formed on the sides of the first floating gate and the second floating gate.

[0178] According to some embodiments, two materials (e.g., oxide and silicon nitride) can be used to form the control gate spacers, e.g., by depositing oxide, depositing nitrogen, and a third floating gate spacer. According to some embodiments, one material (e.g., oxide or silicon nitride) can be used to form the first control gate spacer and the third floating gate spacer, e.g., by depositing spacer material and etching the deposited material to form the control gate spacers.

[0179] According to some embodiments, after forming the floating gate spacers and before forming the select gates, the exposed portions of the oxide layer (i.e., the portions not having a gate structure, polysilicon, or spacer formed thereon) are etched, and oxide is grown on the substrate to provide an oxide having a desired thickness for the select gates and / or logic devices.

[0180] According to some embodiments, before forming the first select gate and the second select gate on the sides of the first floating gate and the second floating gate away from the source region, respectively, the portions of the oxide layer outside the first floating gate and the second floating gate are etched to form a first substrate oxide structure between the first floating gate, the second floating gate, and the substrate; and on the sides of the first floating gate and the second floating gate away from the source region, a second oxide is deposited on the substrate to form a second substrate oxide structure between the first select gate, the second select gate, and the substrate.

[0181] According to some embodiments, a word line threshold voltage injection process can be performed before forming the first select gate and the second select gate to improve the performance of the subsequently formed select gates.

[0182] According to some embodiments, the process of forming the select gates can include but is not limited to the following steps: depositing polysilicon, polysilicon planarization (with or without dummy poly), photolithography on the polysilicon, and etching the polysilicon.

[0183] Figure 13F A cross-sectional view of an exemplary structure 1300 formed after steps S1201 - S1208 is shown. As Figure 13F shown, the semiconductor structure 1300 further includes a first select gate 124a and a second select gate 124b formed on the sides of the first floating gate 121a and the second floating gate 121b away from the source region 112, respectively.

[0184] At step S1209, drain regions are respectively formed in the substrate on the side of the first select gate opposite to the first floating gate and in the substrate on the side of the second select gate opposite to the second floating gate.

[0185] According to some embodiments, step S1209 can be associated with referenceFigure 9 Similar to that described in step S910 in

[0186] According to some embodiments, forming drain regions in the substrate on the side of the first select gate opposite to the first floating gate and in the substrate on the side of the second select gate opposite to the second floating gate further includes: performing a lightly doped implantation in the substrate on the side of the first select gate opposite to the first floating gate and in the substrate on the side of the second select gate opposite to the second floating gate to form a first lightly doped drain region and a second lightly doped drain region; forming a first lightly doped drain spacer on the side of the first select gate opposite to the first floating gate and a second lightly doped drain spacer on the side of the second select gate opposite to the second floating gate; and performing a heavily doped implantation in the substrate on the side of the first lightly doped drain spacer opposite to the first select gate and in the substrate on the side of the second lightly doped drain spacer opposite to the second select gate to form a first heavily doped drain region and a second heavily doped drain region.

[0187] Figure 13G shows a cross-sectional view of the exemplary structure 1300 formed after steps S1201 to S1209. As Figure 13G shown, the semiconductor structure 1300 further includes a first drain region 111a in the substrate 110 on the side of the first select gate 124a opposite to the first floating gate 121a, and a second drain region 111b in the substrate 110 on the side of the second select gate 124b opposite to the second floating gate 121b.

[0188] According to some embodiments, the manufacturing method as described in the present disclosure further includes, after forming a drain region in the substrate on the side of the select gate opposite to the floating gate: forming a silicide structure over the drain region, the select gate, and the erase gate.

[0189] According to some embodiments, after forming the symmetric structure as Figure 13G shown, it can be sliced along the midline of the erase gate and the source polysilicon to form a single memory cell structure as Figure 1 , 4 shown in -8. According to other embodiments, slicing may not be performed, such that adjacent memory cells in the symmetric structure share the erase gate, the source polysilicon, and the source region, so as to reduce the overall area and size of the memory cell array.

[0190] According to some embodiments, the manufacturing method of the semiconductor device as described in the present disclosure further includes: forming logic devices over the logic region of the substrate.

[0191] Figures 14A - 14LSchematic cross-sectional views of steps of a method for fabricating a semiconductor device 1400 according to some embodiments of the present disclosure.

[0192] According to some embodiments, as Figure 14A shown, and similar to that described with reference to Figure 13A the semiconductor structure 1400 sequentially includes, from bottom to top: a substrate 110, an oxide layer 1401, a floating gate layer 1402, and a hard mask layer 1403.

[0193] According to some embodiments, as Figure 14B shown, and similar to that described with reference to Figure 14B the semiconductor structure 1400 further includes a first opening 1410 and a second opening 1420.

[0194] According to some embodiments, as Figure 14C shown, oxides are deposited on the sidewalls of the opening 1410 (e.g., by high-temperature oxidation) to form first erase gate spacers 125a and 125b; oxides are deposited on the sidewalls of the opening 1420 (e.g., by high-temperature oxidation) to form second erase gate spacers 126a and 126b. According to some embodiments, the process of forming the first erase gate spacers 125 and the second erase gate spacers 126 may include etching the deposited oxides.

[0195] According to some embodiments, as Figure 14D shown, first, a tunneling oxide is deposited over the floating gate layer 1402 in the opening 1410 to form a tunneling oxide structure 142a; a tunneling oxide is deposited over the floating gate layer 1402 in the opening 1420 to form a tunneling oxide structure 142b. Then, polysilicon is deposited on the tunneling oxide structures 142a and 142b to form a first erase gate 123a and a second erase gate 123b. According to some embodiments, after forming the tunneling oxide structures and depositing the polysilicon, the polysilicon is planarized and the excess tunneling oxide structures are removed.

[0196] According to some embodiments, as Figure 14EAs shown, oxides are deposited above the first erase gate 123a and the second erase gate 123b respectively (e.g., by high-temperature oxidation) to form a third erase gate spacer 153a and a fourth erase gate spacer 153b respectively. Alternatively, HTO (High-Temperature Oxidation material) is deposited above the first erase gate 123a and the second erase gate 123b respectively. According to some embodiments, the deposited HTO is planarized. The third erase gate spacer 153a and the fourth erase gate spacer 153b can not only protect the first erase gate 123a and the second erase gate 123b, but also simplify the operation process in subsequent process flows. For specific reference, see Figure 14I for description.

[0197] According to some embodiments, as Figure 14F shown, and similar to that described in reference 13D, the portions of the floating gate layer 1403 outside the first opening and the second opening are etched to form a first floating gate 121a and a second floating gate 121b.

[0198] According to some embodiments, as Figure 14G shown, and similar to that described in reference 13E, source regions 112 in the substrate below the intermediate region between the first floating gate 121a and the second floating gate 121b.

[0199] According to some embodiments, as Figure 14H shown, floating gate spacers 141a, 143a, 141b, and 143b are formed on the sides of the first floating gate 121a and the second floating gate 121b.

[0200] According to some embodiments, as Figure 14I shown, after the floating gate spacers are formed, the exposed portions of the oxide layer (i.e., the portions not having a gate structure, polysilicon, or spacer formed thereon) are etched, and an oxide is grown on the substrate to provide an oxide with a desired thickness for the select gate and / or logic device.

[0201] Specifically, since a third erase gate spacer 153a and a fourth erase gate spacer 153b are respectively formed above the first erase gate 123a and the second erase gate 123b, it is not necessary to further set a mask, but the surface of the semiconductor device 1400 can be directly etched, so as to form first substrate oxide structures 151a and 151b between the first floating gate 121a and the second floating gate 121b and the substrate 110. And, on the side of the first floating gate 121a and the second floating gate 121b away from the source region 112, an oxide layer is deposited on the substrate to provide an oxide with a desired thickness for the select gate and / or logic device.

[0202] According to some embodiments, as Figures 14J - 14K shown, polysilicon is deposited on the sides of the first floating gate 121a and the second floating gate 121b to form a first select gate 124a and a second select gate 124b. At this time, to simplify the process operation, polysilicon is also deposited in the region between the first floating gate 121a and the second floating gate 121b (above the source region 112). According to some embodiments, the polysilicon deposited in the region between the first floating gate 121a and the second floating gate 121b can be removed, as Figure 14K shown. For example, the polysilicon above the source region 112 can be removed by a photolithography process (coating photoresist 1404). According to some embodiments, the polysilicon above the source region 112 can be removed by etching, which is not limited herein.

[0203] According to some embodiments, as Figure 14L shown, a lightly doped implantation is performed in the substrate 110 on the side of the first select gate 124a opposite to the first floating gate 121a and in the substrate on the side of the second select gate 124b opposite to the second floating gate 121b to form a first lightly doped drain region 1112a and a second lightly doped drain region 1112b; a first lightly doped drain spacer 144a and a second lightly doped drain spacer 144b are formed on the sides of the first select gate 124a opposite to the first floating gate 121a and the sides of the second select gate 124b opposite to the second floating gate 121b; and a heavily doped implantation is performed in the substrate on the side of the first lightly doped drain spacer 144a opposite to the first select gate 124a and in the substrate on the side of the second lightly doped drain spacer 144b opposite to the second select gate 124b to form a first heavily doped drain region 1111a and a second heavily doped drain region 1111b.

[0204] In the method for manufacturing a semiconductor device according to an embodiment of the present disclosure, since the erase gate is disposed above the floating gate in the manufactured semiconductor device, the coupling area between the erase gate and the floating gate can be conveniently adjusted (for example, by adjusting the width of the erase gate), thereby reducing the coupling voltage between the erase gate and the floating gate, so that the erase operation can be performed more efficiently; and, since the erase gate is disposed above the source polysilicon, the requirement for the thickness of the floating gate can be reduced, and the difficulty of the manufacturing process can be reduced.

[0205] Also, in the method of manufacturing a semiconductor device as described in the present disclosure, since a source polysilicon is disposed above the source region in the substrate, electrical connection between multiple bit lines can be achieved through the source polysilicon. Therefore, compared with the prior art solution of using a source active region or a combination of a tungsten plug and a metal wire to achieve electrical connection between multiple bit lines, the distance between the floating gates of adjacent memory cells in the memory cell array is shortened, so that the size of the memory cell can be reduced.

[0206] Some exemplary aspects of the present disclosure are described below.

[0207] Aspect 1. A semiconductor device, comprising:

[0208] A substrate including a memory cell region, wherein the memory cell region includes a first drain region, a first channel region, and a source region, and the first channel region extends between the first drain region and the source region;

[0209] A first floating gate located above a first portion of the first channel region;

[0210] A first erase gate located above the first floating gate;

[0211] A first select gate located above a second portion of the first channel region and on a side of the first floating gate away from the source region;

[0212] A first programming channel extending from the first drain region to an edge portion of the first floating gate facing the first select gate;

[0213] A second programming channel extending from the first drain region to the source region; and

[0214] A first erase channel extending from an edge portion of the first floating gate facing the first erase gate to the first erase gate.

[0215] Aspect 2. The semiconductor device according to Aspect 1, wherein the first erase gate is located above a first portion of the first floating gate, and the semiconductor device further comprises:

[0216] A first erase gate spacer formed above a second portion of the first floating gate.

[0217] Aspect 3. The semiconductor device according to Aspect 1, further comprising:

[0218] A first floating gate spacer located between the first floating gate and the first select gate.

[0219] Aspect 4. The semiconductor device according to aspect 2 further includes:

[0220] A first tunneling oxide structure formed between the first floating gate and the first erase gate and between the first floating gate and the first erase gate spacer.

[0221] Aspect 5. The semiconductor device according to any one of aspects 1 further includes:

[0222] A second floating gate spacer located on a side of the first floating gate opposite to the first select gate.

[0223] Aspect 6. The semiconductor device according to any one of aspects 1-5 further includes:

[0224] A first substrate oxide structure located between the first floating gate and the substrate; and

[0225] A second substrate oxide structure located between the first select gate and the substrate.

[0226] Aspect 7. In the semiconductor device according to any one of aspects 1-5, the first drain region further includes a lightly doped drain region and a heavily doped drain region, and the semiconductor device further includes:

[0227] A first lightly doped drain spacer located above the first drain region and on a side of the first select gate opposite to the first floating gate.

[0228] Aspect 8. In the semiconductor device according to any one of aspects 1-5, the memory cell region further includes:

[0229] A second drain region and a second channel region, where the second channel region extends between the second drain region and the source region; and

[0230] The semiconductor device further includes:

[0231] A second floating gate located above a first portion of the second channel region;

[0232] A second erase gate located above the second floating gate;

[0233] A second select gate located above a second portion of the second channel region and on a side of the second floating gate away from the source region;

[0234] A third programming channel extending from the second drain region to an edge portion of the second floating gate facing the second select gate;

[0235] A fourth programming channel extending from the second drain region to the source region; and

[0236] A second erasing channel extending from an edge portion of the second floating gate facing the second erase gate to the second erase gate.

[0237] Aspect 9. The semiconductor device according to aspect 8, wherein the second erase gate is located above a first portion of the second floating gate, and the semiconductor device further comprises:

[0238] A second erase gate spacer formed above a second portion of the second floating gate.

[0239] Aspect 10. The semiconductor device according to aspect 8, further comprising:

[0240] A third floating gate spacer located between the second floating gate and the second select gate.

[0241] Aspect 11. The semiconductor device according to aspect 9, further comprising:

[0242] A second tunneling oxide structure formed between the second floating gate and the second erase gate spacer and the second erase gate.

[0243] Aspect 12. The semiconductor device according to any one of aspects 8, further comprising:

[0244] A fourth floating gate spacer located on a side of the second floating gate opposite to the second select gate.

[0245] Aspect 13. The semiconductor device according to any one of aspects 1-5, wherein the substrate further comprises a logic region, and the semiconductor device further comprises:

[0246] A logic device located above the logic region of the substrate.

[0247] Aspect 14. A method of manufacturing a semiconductor device, comprising:

[0248] Forming an oxide layer on a substrate;

[0249] Forming a floating gate layer on the oxide layer;

[0250] Forming the hard mask layer on the floating gate layer;

[0251] Etching the hard mask layer to form a first opening through the hard mask layer;

[0252] Depositing polysilicon in the first opening;

[0253] Etch the polysilicon to form a second opening passing through the polysilicon and the floating gate layer and an erase gate;

[0254] Form a source region in the region of the substrate below the second opening;

[0255] Etch the remaining portion of the floating gate layer to form the floating gate;

[0256] Form a select gate on a side of the floating gate away from the source region; and

[0257] Form a drain region in the substrate on a side of the select gate opposite to the floating gate.

[0258] Aspect 15. The method according to aspect 14, further comprising before depositing polysilicon in the first opening:

[0259] Deposit an oxide on a side surface of the hard mask layer in the first opening to form a first erase gate spacer; and

[0260] Form a tunneling oxide structure on a side surface of the first erase gate spacer away from the hard mask layer and on the floating gate layer in the first opening.

[0261] Aspect 16. The method according to aspect 14, further comprising before etching the remaining portion of the floating gate layer:

[0262] Deposit an oxide in the second opening to close the second opening.

[0263] Aspect 17. The method according to aspect 14, further comprising before forming a select gate on a side of the floating gate away from the source region:

[0264] Form a first floating gate spacer on a side of the floating gate away from the source region.

[0265] Aspect 18. The method according to aspect 16, further comprising before depositing an oxide in the second opening:

[0266] Form a second floating gate spacer on side surfaces of the floating gate layer and the erase gate in the second opening.

[0267] Aspect 19. The method according to any one of aspects 14-18, further comprising before forming a select gate on a side of the floating gate away from the source region:

[0268] Etch a portion of the oxide layer on a side of the floating gate away from the source region to form a first substrate oxide structure located between the floating gate and the substrate; and

[0269] Deposit a second oxide on the substrate on a side of the floating gate away from the source region to form a second substrate oxide structure located between the select gate and the substrate.

[0270] Aspect 20. The method according to any one of aspects 14 - 18, wherein forming the drain region in the substrate on a side of the select gate opposite to the floating gate further comprises:

[0271] Perform a lightly doped implantation in the substrate on a side of the select gate opposite to the floating gate to form a lightly doped drain region;

[0272] Form a lightly doped drain spacer on a side of the select gate opposite to the floating gate; and

[0273] Perform a heavily doped implantation in the substrate on a side of the lightly doped drain spacer opposite to the select gate to form a heavily doped drain region.

[0274] Aspect 21. The method according to any one of aspects 14 - 18, further comprising:

[0275] Form logic devices above the logic region of the substrate.

[0276] Aspect 22. A method for manufacturing a semiconductor device, comprising:

[0277] Form an oxide layer on a substrate;

[0278] Form a floating gate layer on the oxide layer;

[0279] Form the hard mask layer on the floating gate layer;

[0280] Etch the hard mask layer to form a first opening and a second opening through the hard mask layer;

[0281] Deposit polysilicon in the first opening and the second opening respectively to form a first erase gate and a second erase gate;

[0282] Etch a portion of the floating gate layer outside the first opening and the second opening to form a first floating gate and a second floating gate;

[0283] Form a source region in the substrate below a region between the first floating gate and the second floating gate;

[0284] A first select gate and a second select gate are respectively formed on one side of the first floating gate and the second floating gate away from the source region; and

[0285] Drain regions are respectively formed in the substrate on one side of the first select gate opposite to the first floating gate and in the substrate on one side of the second select gate opposite to the second floating gate.

[0286] Aspect 23. The method according to aspect 22 further includes, before depositing polysilicon in the first opening and the second opening respectively:

[0287] Oxide is deposited on the side surfaces of the hard mask layer in the first opening and the second opening to form a first erase gate spacer and a second erase gate spacer in the first opening and the second opening; and

[0288] A tunneling oxide structure is formed between the first erase gate spacer and the second erase gate spacer in the first opening and the second opening.

[0289] Aspect 24. The method according to aspect 22 further includes, before etching the portions of the floating gate layer outside the first opening and the second opening:

[0290] A third erase gate spacer and a fourth erase gate spacer are respectively formed above the first erase gate and the second erase gate.

[0291] Aspect 25. The method according to aspect 22 further includes, before forming a first select gate and a second select gate on one side of the first floating gate and the second floating gate away from the source region respectively:

[0292] Floating gate spacers are formed on the side surfaces of the first floating gate and the second floating gate.

[0293] Aspect 26. The method according to aspects 22-25 further includes, before forming a first select gate and a second select gate on one side of the first floating gate and the second floating gate away from the source region respectively:

[0294] The portion of the oxide layer outside the first floating gate and the second floating gate is etched to form a first substrate oxide structure located between the first floating gate and the second floating gate and the substrate; and

[0295] On one side of the first floating gate and the second floating gate away from the source region, a second oxide is deposited on the substrate to form a second substrate oxide structure located between the first select gate and the second select gate and the substrate.

[0296] Aspect 27. The method according to aspects 22-25, wherein forming the drain regions in the substrate on the side of the first select gate opposite to the first floating gate and in the substrate on the side of the second select gate opposite to the second floating gate further comprises:

[0297] Performing a lightly doped implantation in the substrate on the side of the first select gate opposite to the first floating gate and in the substrate on the side of the second select gate opposite to the second floating gate to form a first lightly doped drain region and a second lightly doped drain region;

[0298] Forming a first lightly doped drain spacer and a second lightly doped drain spacer on the side of the first select gate opposite to the first floating gate and on the side of the second select gate opposite to the second floating gate; and

[0299] Performing a heavily doped implantation in the substrate on the side of the first lightly doped drain spacer opposite to the first select gate and in the substrate on the side of the second lightly doped drain spacer opposite to the second select gate to form a first heavily doped drain region and a second heavily doped drain region.

[0300] Aspect 28. The method according to aspects 22-25, further comprising:

[0301] Forming logic devices above the logic region of the substrate.

[0302] Although the present disclosure has been described and illustrated in detail in the accompanying drawings and the foregoing description, such description and illustration shall be regarded as illustrative and exemplary, rather than restrictive; the present disclosure is not limited to the disclosed embodiments. By studying the drawings, the disclosure and the appended claims, those skilled in the art can understand and implement variations of the disclosed embodiments when practicing the claimed subject matter. In the claims, the word "comprising" does not exclude other elements or steps not listed, the indefinite article "a" or "an" does not exclude a plurality, and the term "plurality" means two or more. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Claims

1. A semiconductor device, comprising: A substrate including a memory cell region, wherein the memory cell region includes a first drain region, a first channel region, and a source region, and wherein the first channel region extends between the first drain region and the source region; A first floating gate located above a first portion of the first channel region; A first erase gate located above the first floating gate; A first select gate located above a second portion of the first channel region and on a side of the first floating gate away from the source region; A first programming channel extending from the first drain region to an edge portion of the first floating gate facing the first select gate; A second programming channel extending from the first drain region to the source region; and A first erase channel extending from an edge portion of the first floating gate facing the first erase gate to the first erase gate, and a width of the first erase gate facing the substrate is used to determine a coupling area between the first erase gate and the first floating gate.

2. The semiconductor device according to claim 1, wherein, The first erase gate is located above a first portion of the first floating gate, and the semiconductor device further includes: A first erase gate spacer formed above a second portion of the first floating gate.

3. The semiconductor device according to claim 1, further including: A first floating gate spacer located between the first floating gate and the first select gate.

4. The semiconductor device according to claim 2, further including: A first tunneling oxide structure formed between the first floating gate and the first erase gate and between the first floating gate and the first erase gate spacer.

5. The semiconductor device according to any one of claims 1, further including: A second floating gate spacer located on a side of the first floating gate opposite to the first select gate.

6. The semiconductor device according to any one of claims 1-5, further including: A first substrate oxide structure located between the first floating gate and the substrate; And A second substrate oxide structure located between the first select gate and the substrate.

7. The semiconductor device according to any one of claims 1-5, wherein, The first drain region further includes a lightly doped drain region and a heavily doped drain region, and the semiconductor device further includes: A first lightly doped drain spacer located above the first drain region and on a side of the first select gate opposite to the first floating gate.

8. The semiconductor device according to any one of claims 1-5, wherein, The memory cell region further includes: A second drain region and a second channel region, wherein the second channel region extends between the second drain region and the source region; and The semiconductor device further includes: A second floating gate located above a first portion of the second channel region; A second erase gate located above the second floating gate; A second select gate located above a second portion of the second channel region and on a side of the second floating gate away from the source region; A third programming channel extending from the second drain region to an edge portion of the second floating gate facing the second select gate; A fourth programming channel extending from the second drain region to the source region; and A second erasing channel extending from an edge portion of the second floating gate facing the second erasing gate to the second erasing gate.

9. The semiconductor device according to claim 8, wherein, The second erasing gate is located above a first portion of the second floating gate, and the semiconductor device further includes: A second erasing gate spacer formed above a second portion of the second floating gate.

10. The semiconductor device according to claim 8, further including: A third floating gate spacer located between the second floating gate and the second select gate.

11. The semiconductor device according to claim 9, further including: A second tunneling oxide structure formed between the second floating gate and the second erasing gate spacer and the second erasing gate.

12. The semiconductor device according to any one of claims 8, further including: A fourth floating gate spacer located on a side of the second floating gate opposite to the second select gate.

13. The semiconductor device according to any one of claims 1-5, wherein, The substrate further includes a logic region, and the semiconductor device further includes: A logic device located above the logic region of the substrate.

14. A method of manufacturing a semiconductor device, including: Forming an oxide layer on a substrate; Forming a floating gate layer on the oxide layer; Forming a hard mask layer on the floating gate layer; Etching the hard mask layer to form a first opening through the hard mask layer; Depositing polysilicon in the first opening; Etching the polysilicon to form a second opening through the polysilicon and the floating gate layer and an erasing gate; Forming a source region in a region of the substrate below the second opening; Etching a remaining portion of the floating gate layer to form the floating gate; Forming a select gate on a side of the floating gate away from the source region; And Forming a drain region in the substrate on a side of the select gate opposite to the floating gate.

15. The method according to claim 14, further including before depositing polysilicon in the first opening: Depositing an oxide on a side surface of the hard mask layer in the first opening to form a first erasing gate spacer; and Forming a tunneling oxide structure on a side surface of the first erasing gate spacer away from the hard mask layer and on the floating gate layer in the first opening.

16. The method according to claim 14, further including before etching the remaining portion of the floating gate layer: Depositing an oxide in the second opening to close the second opening.

17. The method according to claim 14, further including before forming a select gate on a side of the floating gate away from the source region: Forming a first floating gate spacer on a side of the floating gate away from the source region.

18. The method according to claim 16, further including before depositing an oxide in the second opening: Forming a second floating gate spacer on side surfaces of the floating gate layer and the erasing gate in the second opening.

19. The method according to any one of claims 14-18 further includes, before forming a select gate on a side of the floating gate away from the source region: etching a portion of the oxide layer on the side of the floating gate away from the source region to form a first substrate oxide structure located between the floating gate and the substrate; and depositing a second oxide on the substrate on the side of the floating gate away from the source region to form a second substrate oxide structure located between the select gate and the substrate.

20. The method according to any one of claims 14-18, wherein, The forming a drain region in the substrate on a side of the select gate opposite to the floating gate further includes: performing a lightly doped implantation in the substrate on the side of the select gate opposite to the floating gate to form a lightly doped drain region; forming a lightly doped drain spacer on a side of the select gate opposite to the floating gate; and performing a heavily doped implantation in the substrate on a side of the lightly doped drain spacer opposite to the select gate to form a heavily doped drain region.

21. The method according to any one of claims 14-18 further includes: forming a logic device above a logic region of the substrate.

22. A method of manufacturing a semiconductor device, including: forming an oxide layer on a substrate; forming a floating gate layer on the oxide layer; forming a hard mask layer on the floating gate layer; etching the hard mask layer to form a first opening and a second opening through the hard mask layer; depositing polysilicon in the first opening and the second opening respectively to form a first erase gate and a second erase gate; etching a portion of the floating gate layer outside the first opening and the second opening to form a first floating gate and a second floating gate; forming a source region in the substrate below a region between the first floating gate and the second floating gate; forming a first select gate and a second select gate respectively on sides of the first floating gate and the second floating gate away from the source region; and forming drain regions respectively in the substrate on a side of the first select gate opposite to the first floating gate and in the substrate on a side of the second select gate opposite to the second floating gate.

23. The method according to claim 22 further includes, before depositing polysilicon in the first opening and the second opening respectively: depositing an oxide on side surfaces of the hard mask layer in the first opening and the second opening to form a first erase gate spacer and a second erase gate spacer in the first opening and the second opening; and forming a tunneling oxide structure between the first erase gate spacer and the second erase gate spacer in the first opening and the second opening.

24. The method according to claim 22 further includes, before etching a portion of the floating gate layer outside the first opening and the second opening: forming a third erase gate spacer and a fourth erase gate spacer respectively above the first erase gate and the second erase gate.

25. The method according to claim 22 further includes, before forming a first select gate and a second select gate on a side of the first floating gate and the second floating gate away from the source region respectively: Forming floating gate spacers on sides of the first floating gate and the second floating gate.

26. The method according to any one of claims 22-25 further includes, before forming a first select gate and a second select gate on a side of the first floating gate and the second floating gate away from the source region respectively: Etching portions of the oxide layer other than those over the first floating gate and the second floating gate to form a first substrate oxide structure between the first floating gate, the second floating gate, and the substrate; and Depositing a second oxide on the substrate on a side of the first floating gate and the second floating gate away from the source region to form a second substrate oxide structure between the first select gate, the second select gate, and the substrate.

27. The method according to any one of claims 22-25, wherein, The forming of drain regions in the substrate on a side of the first select gate opposite to the first floating gate and in the substrate on a side of the second select gate opposite to the second floating gate further includes: Performing a lightly doped implantation in the substrate on a side of the first select gate opposite to the first floating gate and in the substrate on a side of the second select gate opposite to the second floating gate to form a first lightly doped drain region and a second lightly doped drain region; Forming a first lightly doped drain spacer and a second lightly doped drain spacer on sides of the first select gate opposite to the first floating gate and of the second select gate opposite to the second floating gate respectively; and Performing a heavily doped implantation in the substrate on a side of the first lightly doped drain spacer opposite to the first select gate and in the substrate on a side of the second lightly doped drain spacer opposite to the second select gate to form a first heavily doped drain region and a second heavily doped drain region.

28. The method according to any one of claims 22-25 further includes: Forming logic devices over the logic region of the substrate.

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