A 4H-SiC-based VDMOS device with shielding effect of super-junction P-pillar and N-channel

Abstract

This invention relates to a 4H-SiC-based VDMOS device with a shielding effect, consisting of a superjunction P-pillar and N-channel, belonging to the field of semiconductor technology. The device includes a P+ polysilicon drain, an N+ substrate region, a P-pillar shielding region, an N-pillar region, a P-field termination region, a silicon dioxide isolation layer, a P+ polysilicon gate electrode, P+ polysilicon source electrode I, P+ polysilicon source electrode II, an N-channel region, and an N+ source region; wherein the P+ polysilicon drain, N+ substrate region, N-pillar region, P+ polysilicon source electrode II, N-channel region, and N+ source region constitute the conductive region of the device; the N-pillar region and P-field termination region constitute the drift region of the device; and the P-pillar shielding region and N-pillar region constitute the lateral superjunction of the device. Based on the traditional 4H-SiC-based VDMOS device, this invention introduces a superjunction structure, an overall asymmetric structure, and an N-channel region in the vertical drift region, which improves the breakdown voltage of the device, significantly reduces Miller capacitance and feedback capacitance, enhances the dynamic performance of the device, and reduces channel resistance and specific on-resistance.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology and relates to a 4H-SiC-based VDMOS device with a superjunction P-pillar and N-channel shielding effect. Background Technology

[0002] Electricity, as one of the main energy sources used by human society, is characterized by its cleanliness, efficiency, and ease of transportation. Power electronics technology plays a crucial role in the transmission and use of electrical energy, and power semiconductors are the core of this technology. Power semiconductors primarily function as rectifyers and switches in circuits, with MOSFETs being commonly used power devices due to their high input impedance. With technological advancements, the industry's requirements for device breakdown voltage and on-resistance are becoming increasingly stringent. Traditional silicon materials are finding it difficult to continue developing power MOSFETs; at this point, silicon carbide (SiC) has demonstrated significant potential in the power semiconductor market. Table 1 lists some basic physical properties of Si and 4H-SiC materials:

[0003] Table 1. Basic physical properties of Si and 4H-SiC materials

[0004]

[0005] Silicon carbide (SiC), as a representative of wide-bandgap semiconductors, possesses characteristics such as high critical breakdown electric field, wide bandgap, high thermal conductivity, and high electron saturation drift velocity, making it suitable for applications in high-voltage and high-frequency fields. SiC has various structures; the common 4H-SiC is used in this study. When SiC MOFETs are applied in circuits, switching losses are much greater than conduction losses; therefore, improving switching performance is a major research focus for SiC MOFETs.

[0006] Firstly, for vertical devices, increasing their vertical height can increase their breakdown voltage, but it also leads to increased on-resistance, increased manufacturing difficulty, and aggravated self-heating issues, making heat dissipation difficult and affecting device reliability. Therefore, how to improve the relationship between breakdown voltage and on-resistance without increasing vertical height has become the main problem for vertical power devices.

[0007] Secondly, as the third generation of semiconductor devices, SiC MOFET devices are mostly used in high-frequency circuits. Therefore, the switching performance of the device is also crucial. The switching performance of a MOS device is mainly measured by its gate-drain charge Q. GD MOSFET parasitic capacitance can be divided into three parts: gate-drain parasitic capacitance C. GD Gate-source parasitic capacitance C GS Source-drain parasitic capacitance C DSTo be relevant to practical applications, capacitors are categorized into three types: input capacitors, output capacitors, and feedback capacitors. The device can only turn on when the input capacitor charges to a threshold voltage and can only turn off when it discharges to a certain value. Therefore, the input capacitor mainly affects the switching speed and switching losses of the device. The output capacitor mainly affects the change in the drain-source voltage of the device, limiting dv / dt during the switching process. The losses caused by the output capacitor are generally negligible. Feedback capacitor C GD Also commonly called Miller capacitance or feedback transfer capacitance, it mainly affects the coupling relationship between the gate voltage and drain-source voltage of a device. This invention focuses on the impact of Miller capacitance on the switching speed of a device. Summary of the Invention

[0008] In view of this, the purpose of the present invention is to provide a 4H-SiC-based VDMOS device with a superjunction P-pillar and N-channel having a shielding effect, which reduces the Miller charge and feedback capacitance of the device, reduces the peak electric field of the device, optimizes the breakdown electric field of the device, and improves the breakdown voltage of the device. At the same time, the introduction of the N-channel region reduces the channel resistance and specific on-resistance of the device.

[0009] To achieve the above objectives, the present invention provides the following technical solution:

[0010] A 4H-SiC-based VDMOS device with a superjunction P-pillar and N-channel shielding effect includes a P+ polysilicon drain 1, an N+ substrate region 2, a P-pillar shielding region 3, an N-pillar region 4, a P-field termination region 5, a silicon dioxide isolation layer 6, a P+ polysilicon gate electrode 7, a P+ polysilicon source electrode I 8, a P+ polysilicon source electrode II 9, an N-channel region 10, and an N+ source region 11;

[0011] The P+ polycrystalline silicon source electrode I8 is located above the P-pillar shielding region 3 and is connected to the zero potential point of the P-pillar shielding region 3. This part does not participate in the conduction of the device and is only used to ensure that this region of the device is at zero potential.

[0012] The P+ polysilicon source electrode II9 is ​​located above the P- electric field termination region 5 and the N+ source region 11, and is connected to the P- electric field termination region 5 and the N+ source region 1. This part is the main part of the device that conducts electricity.

[0013] The P+ polysilicon gate electrode 7 is located between the P+ polysilicon source electrode I 8 and the P+ polysilicon source electrode II 9, and extends into the silicon dioxide isolation layer 6.

[0014] The silicon dioxide isolation layer 6 is embedded in the upper end of the P-pillar shielding region 3, separating the P+ polysilicon gate electrode 7 from the P-pillar shielding region 3, the N+ source region 11 and the N- channel region 10.

[0015] The N-channel region 10 is located above the N-pillar region 4 and to the left of the P-electric field termination region 5;

[0016] The N+ source region 11 is located above the N-channel region 10 and to the left of the P-electric field termination region 5;

[0017] The N+ substrate region 2 is located below the P-pillar shielding region 3 and the N-pillar region 4;

[0018] The P+ polycrystalline silicon drain 1 is located below the N+ substrate region 2.

[0019] Optionally, a 4H-SiC-based VDMOS device with a shielding effect based on another structure is provided: Based on the structure of the above device, the P+ polysilicon source electrode II 9 is symmetrically arranged on both sides of the P+ polysilicon gate electrode 7; the silicon dioxide isolation layer 6 and the P+ polysilicon gate electrode 7 are moved to the right and placed in the center of the N-pillar region 4; the P-pillar shielding region 3 is divided into two parts and placed on both sides of the N-pillar region 4; the N+ source region 11 is divided into two parts and placed on both sides of the silicon dioxide isolation layer 6; an N-channel region 10 is added to the left of the silicon dioxide isolation layer 6; and a P-field termination region 5 is added to the left of the silicon dioxide isolation layer 6.

[0020] Optionally, the P+ polysilicon drain 1, N+ substrate region 2, N pillar region 4, P+ polysilicon source electrode II 9, N- channel region 10 and N+ source region 11 constitute a conductive region.

[0021] Optionally, the N-pillar region 4 and the P-electric field termination region 5 constitute a drift region.

[0022] Optionally, the P-pillar shielding region 3 and the N-pillar region 4 form a lateral superjunction. The P-pillar shielding region 3, as part of the lateral superjunction, does not participate in the device's conductivity. Its main function is to assist in the depletion of the N-pillar region 4, providing charge compensation, optimizing the breakdown electric field, and improving the breakdown voltage. Simultaneously, it shields against the high electric field from the bottom and right side of the silicon dioxide isolation layer 6, assisting in device heat dissipation.

[0023] Optionally, the P+ polycrystalline silicon source electrode I8 has a width of 0.4 μm and a height of 0.75 μm; the P+ polycrystalline silicon source electrode II9 has a width of 0.9 μm and a height of 0.75 μm.

[0024] Optionally, the portion of the P+ polysilicon gate electrode 7 extending into the silicon dioxide isolation layer 6 has a length of 1.25 μm, and the portion not extending into the silicon dioxide isolation layer 6 has a length of 0.75 μm; the width of the P+ polysilicon gate electrode 7 is 0.4 μm.

[0025] The length of the silicon dioxide isolation layer 6 embedded in the P-pillar shielding area 3 is 2μm, the sidewall thickness is 0.05μm, and the thickness at the lower part of the P+ polysilicon gate electrode 7 is 0.5μm.

[0026] Optionally, the N-channel region 10 has a height of 1 μm and a width of 0.2 μm; the N+ source region 11 has a height of 0.25 μm and a width of 0.4 μm.

[0027] Optionally, the height of the P-pillar shielding region 3 is 14 μm; the height of the N-pillar region 4 is 12.75 μm.

[0028] Optionally, the N+ substrate region 2 has a height of 3 μm and a width of 2 μm; the P+ polysilicon drain electrode 1 has a height of 0.5 μm and a width of 2 μm.

[0029] Optionally, the doping concentration range of the P-pillar shielding region (3), N-pillar region (4), and P-field termination region (5) is 1×10⁻⁶. 15 cm -3 ~5×10 16 cm -3 Adjustments should be made based on the device size and the required operating current.

[0030] Alternatively, the N-type VDMOS device can be replaced with a P-type VDMOS device;

[0031] This structure is also applicable to lateral diodes, LIGBTs, and LDMOS.

[0032] Optionally, the thickness of the silicon dioxide isolation layer 6 is adjustable, generally requiring a thickness of 0.01μm or more. If it is too thick, it will affect the gate-drain capacitance (i.e., Miller capacitance) of the device, resulting in a large capacitance and reducing the switching speed of the device; if it is too thin, it may cause the device to be unable to withstand high field strength, resulting in premature breakdown of the device and reducing the breakdown voltage.

[0033] The beneficial effects of this invention are as follows: Based on the traditional 4H-SiC-based VDMOS device, this invention introduces a superjunction structure, an overall asymmetric structure, and an N-channel region in the vertical drift region. During turn-off, the P-pillar shielding region and the N-pillar region on both sides of the device form a PN junction. The P-pillar shielding region provides charge compensation to the N-pillar region of the device's conductive area, aiding in depletion. This results in a wider space charge region on the side of the N-pillar conductive area closer to the P-pillar region, further improving the device's breakdown voltage. On the one hand, this device introduces a zero-potential point above the P-pillar shielding region in the traditional 4H-SiC-based VDMOS structure, shorting it to the source. This makes the depletion of the N-pillar region more pronounced, further optimizing the longitudinal breakdown electric field and improving the breakdown voltage. On the other hand, the device adopts an asymmetric structure. The P-pillar shielding region wraps the bottom and sides of the gate oxide layer, shielding it from the high electric field from the gate oxide layer. Through optimization of structural parameters, the electric field of the gate oxide layer near the channel side does not exceed the safe operating electric field of the silicon dioxide material, significantly reducing Miller charge and feedback capacitance, thus improving the dynamic performance of the device. Simultaneously, when the device is turned on, the channel portion uses lightly doped N-type silicon carbide, making the channel type an accumulation type. Compared with the commonly used depletion type channel, the accumulation type channel has lower resistivity and requires a lower drive voltage, reducing the channel resistance and specific on-resistance of the device.

[0034] Other advantages, objectives, and features of the invention will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art from the following examination, or may be learned from practice of the invention. The objectives and other advantages of the invention can be realized and obtained through the following description. Attached Figure Description

[0035] To make the objectives, technical solutions, and advantages of the present invention clearer, the preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein:

[0036] Figure 1 This is a schematic diagram of the structure of the novel VDMOS device in Embodiment 1 of the present invention;

[0037] Figure 2 This is a schematic diagram of the structure of the novel VDMOS device in Embodiment 2 of the present invention;

[0038] Figure 3 A comparison of the breakdown electric field distribution in the vertical direction of the N-channel region through the interface between the P-pillar shielding region and the N-pillar region to the N+ substrate region in the novel VDMOS device provided by this invention and the conventional 4H-SiC-based VDMOS device.

[0039] Figure 4 The doping concentration in the drift region is 8.0 × 10⁻⁶.16 cm -3 The traditional 4H-SiC-based VDMOS device and the N-pillar region and P-pillar shielding region have a doping concentration of 8.0 × 10⁻⁶. 16 cm -3 Avalanche breakdown characteristics of the novel VDMOS device;

[0040] Figure 5 The doping concentration in the drift region is 8.0 × 10⁻⁶. 16 cm -3 The traditional 4H-SiC-based VDMOS device and the N-pillar region and P-pillar shielding region have a doping concentration of 8.0 × 10⁻⁶. 16 cm -3 Potential distribution of a novel VDMOS device under avalanche breakdown;

[0041] Figure 6 For the present invention in V GS =15V, V DS At 800V, the doping concentration of the N-pillar region and the P-pillar shielding region is 8.0 × 10⁻⁶. 16 cm -3 A comparison of the peak intensity of the gate oxide layer in the novel VDMOS device and the traditional 4H-SiC-based VDMOS device;

[0042] Figure 7 In Embodiment 1 of the present invention, the doping concentration of the N-pillar region and the P-pillar shielding region of the VDMOS device is 5.0 × 10⁻⁶. 16 cm -3 Up to 1.0×10 17 cm -3 Relationship between feedback capacitance and drain voltage in incremental and conventional 4H-SiC-based VDMOS devices;

[0043] Figure 8 A comparison chart of gate charge performance between the VDMOS device of Embodiment 1 and the conventional 4H-SiC-based VDMOS device provided by the present invention;

[0044] Figure 9 The diagram shows the changes in drain-source voltage and drain-source current over time during the turn-on and turn-off processes of a VDMOS device under resistive load, as provided in Embodiment 1 of this invention.

[0045] Figure 10 The diagram shows the changes in drain-source voltage and drain-source current over time during the turn-off process of a VDMOS device under resistive load, as provided in Embodiment 1 of this invention.

[0046] Figure 10 For the present invention in V GS At 15V, the doping concentration in the N-pillar region and the P-pillar shielding region is 5.0 × 10⁻⁶. 16 cm -3Up to 1.0×10 17 cm -3 The relationship between drain current and drain voltage as the voltage increases.

[0047] Figure 11 For the present invention in V GS =15V, V DS At 20V, the doping concentration in the drift region is 8.0 × 10⁻⁶. 16 cm -3 The traditional 4H-SiC-based VDMOS device and the N-pillar region and P-pillar shielding region have a doping concentration of 8.0 × 10⁻⁶. 16 cm -3 The output characteristic curves of the new structure VDMOS device and the comparison of specific on-resistance at the same breakdown voltage are shown in the figure.

[0048] Figure 12 A schematic diagram of the main process flow of the VDMOS device provided in Embodiment 1 of the present invention;

[0049] Figure reference numerals: 1. P+ polysilicon drain electrode; 2. N+ substrate region; 3. P-pillar shielding region; 4. N-pillar region; 5. P- electric field termination region; 6. Silicon dioxide isolation layer; 7. P+ polysilicon gate electrode; 8. P+ polysilicon source electrode I; 9. P+ polysilicon source electrode II; 10. N- channel region; 11. N+ source region. Detailed Implementation

[0050] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0051] The accompanying drawings are for illustrative purposes only and are schematic diagrams, not actual pictures. They should not be construed as limiting the invention. To better illustrate the embodiments of the invention, some parts in the drawings may be omitted, enlarged, or reduced, and do not represent the actual product dimensions. It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings.

[0052] In the accompanying drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components. In the description of the present invention, it should be understood that if terms such as "upper," "lower," "left," "right," "front," and "rear" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the terms used to describe positional relationships in the drawings are only for illustrative purposes and should not be construed as limiting the present invention. For those skilled in the art, the specific meaning of the above terms can be understood according to the specific circumstances.

[0053] Example 1:

[0054] like Figure 1 As shown in Table 2, the present invention proposes a 4H-SiC-based VDMOS device with a shielding effect, consisting of a superjunction P-pillar and an N-channel. The structural parameters and doping concentrations of this device are shown in Table 2.

[0055] Table 2. Structural parameters and doping concentration distribution of Example 1

[0056]

[0057] The device mainly includes a P+ polysilicon drain electrode 1, an N+ substrate region 2, a P-pillar shielding region 3, an N-pillar region 4, a P- electric field termination region 5, a silicon dioxide isolation layer 6, a P+ polysilicon gate electrode 7, a P+ polysilicon source electrode I 8, a P+ polysilicon source electrode II 9, an N-channel region 10, and an N+ source region 11.

[0058] The source design features a separation of the source electrodes. One part (P+ polysilicon source electrode II 9) is located at the upper end of the P- electric field termination region 5 and is connected to the N+ source region 11 and the P- electric field termination region 5. It is 0.9 μm wide and 0.75 μm high, and this is the main part of the device that conducts electricity. The other part (P+ polysilicon source electrode I 8) is located at the zero potential point at the upper end of the P-pillar shielding region (it is the source short-circuit electrode located at the upper end of the P-pillar shielding region). This part does not participate in conduction and is only used to ensure that this region of the device is at zero potential. It is 0.4 μm wide and 0.75 μm high.

[0059] The P+ polysilicon gate electrode 7 is located in the middle of the two source parts and extends into the trench. It is 0.4 μm wide and 0.75 μm high, with a 1.25 μm long embedded in silicon dioxide. The silicon dioxide isolation layer 6 isolates the P+ polysilicon gate electrode 7 from the P-pillar shielding region 3, the N+ source region 11, and the N- channel region 10. The sidewall thickness of the silicon dioxide isolation layer 6 is 0.05 μm, and its height is 0.5 μm at the bottom of the polysilicon gate.

[0060] The total height of the P-pillar shielding region 3 is 14 μm; the silicon dioxide isolation layer 6 has a buried length of 2 μm; the total height of the N-pillar region 4 is 12.75 μm; the N-channel region 10 is 1 μm high and 0.2 μm wide; the N+ source region 11 located above the N-channel region 10 is 0.4 μm wide and 0.25 μm high; the N+ substrate region 2 located below the P-pillar shielding region 3 and the N-pillar region 4 is 3 μm high and 2 μm wide.

[0061] The VDMOS conductive region mainly includes P+ polysilicon drain 1, N+ substrate region 2, N pillar region 4, P+ polysilicon source II 9, N- channel region 10, and N+ source region 11.

[0062] The drift region of this device mainly consists of the N-pillar region 4 and the P-field termination region 5. The left-side P-pillar shielding region 3, as part of the superjunction, does not participate in conduction. It mainly assists in depleting the N-pillar region 4, providing charge compensation, optimizing the breakdown electric field, and improving the breakdown voltage. At the same time, it shields the high electric field from the bottom and right side of the silicon dioxide isolation layer 6, assisting in heat dissipation. The lateral superjunction of this device consists of the P-pillar shielding region 3 and the N-pillar region 4.

[0063] Example 2:

[0064] like Figure 2 As shown, the 4H-SiC-based VDMOS device with shielding effect of superjunction P-pillar and N-channel proposed in this invention mainly includes a P+ polysilicon drain electrode 1, an N+ substrate region 2, a P-pillar shielding region 3, an N-pillar region 4, a P-field termination region 5, a silicon dioxide isolation layer 6, a P+ polysilicon gate electrode 7, a P+ polysilicon source electrode II 9, an N-channel region 10, and an N+ source region 11.

[0065] Based on the structure of Example 1, the gate oxide layer is moved to the right so that it is located in the center of the N-pillar region, and the P-pillar shielding areas are separated on both sides to assist in the depletion of the N-pillar region. Simultaneously, a doping concentration of 2.0 × 10⁻⁶ is added above the N-pillar region. 17 cm -3 The electric field termination region is used to improve the breakdown resistance of the P-pillar shielding region; a heavily doped N-type source region with a doping concentration of 2.0 × 10⁻⁶ is added near the gate oxide layer. 19 cm -3 The main function is to provide the ability to extract electrons when the device is turned on, further reducing the on-resistance of the device. However, although the static performance of the device in Example 2 is improved, this device loses the electric field shielding effect of the P-pillar shielding region on the gate silicon dioxide isolation layer under high drain voltage. Therefore, the reliability of this device in Example 2 under high voltage is not as good as that of the device in Example 1.

[0066] Figure 3The figures show a comparison of the breakdown electric field distribution along the vertical direction from the interface between the P-pillar and N-pillar regions in the N-channel region of the novel VDMOS device provided by this invention to the N+ substrate region in a conventional 4H-SiC-based VDMOS device. As can be seen from the figures, the electric field distribution of the novel structure in Example 1 is more uniform than that of the conventional trench-gate MOSFET device, which allows the new structure to accommodate a higher breakdown voltage. It is particularly noteworthy that the electric field strength in Example 1 drops sharply at a vertical length of 2.5 μm. This is because this drift region is blocked by the silicon dioxide isolation layer and cannot contact the P-type pillar region, thus preventing this portion from being depleted.

[0067] Figure 4 The doping concentration in the drift region is 8.0 × 10⁻⁶. 16 cm -3 The traditional 4H-SiC-based VDMOS device and the N-pillar region and P-pillar shielding region have a doping concentration of 8.0 × 10⁻⁶. 16 cm -3 Avalanche breakdown characteristics of the novel VDMOS device. From Figure 4 It is known that the breakdown voltage of a conventional 4H-SiC-based VDMOS device is 1666V under the same drift region scale, while the breakdown voltage of Embodiment 1 of the present invention is 2260V under the same drift region scale, which is an improvement of about 594V. Therefore, the static avalanche breakdown characteristics of Embodiment 1 of the present invention are better than those of conventional 4H-SiC-based VDMOS, which helps the device to operate at a higher operating voltage.

[0068] Figure 5 The doping concentration in the drift region is 8.0 × 10⁻⁶. 16 cm -3 The traditional 4H-SiC-based VDMOS device and the N-pillar region and P-pillar shielding region have a doping concentration of 8.0 × 10⁻⁶. 16 cm -3 Potential distribution of the novel VDMOS device under avalanche breakdown. From Figure 5 It can be seen that the potential distributions of the two are basically the same. However, the potential distribution of Embodiment 1 of the present invention presents a streamlined shape that tilts towards the upper end of the P-pillar shielding region. This is because the P-pillar shielding region of this device does not participate in conduction. At the same time, the thicker isolation layer at the lower end of the gate silicon dioxide isolates the high potential from the N-pillar region, making the potential distribution of the device more reasonable. This also indirectly indicates that the breakdown voltage of the device will be higher.

[0069] Figure 6 For the present invention in V GS =15V, V DS At 800V, the doping concentration of the N-pillar region and the P-pillar shielding region is 8.0 × 10⁻⁶. 16 cm -3A comparison of the peak intensity of the gate oxide layer of the novel VDMOS device and the traditional 4H-SiC-based VDMOS device is shown. The target operating voltage level of Embodiment 1 of this invention is 1200V. According to power electronic system design specifications, devices typically need to operate at a bus voltage of 800V. Therefore, Embodiment 1 of this invention simulates the operating conditions of the device at an 800V bus voltage. It is known that the maximum withstandable electric field strength of silicon dioxide is 4MV / cm. Figure 6 As can be seen, the peak electric field in Embodiment 1 of the present invention is located at the junction of the gate polysilicon and the bottom of the oxide layer, and the peak electric field strength is 3.68 MV / cm, which is less than 4 MV / cm and is within the safe and acceptable range. Furthermore, the P-pillar shielding area on the left side effectively shields the large electric field from the bottom of the gate oxide layer and the left side.

[0070] Figure 7 In Embodiment 1 of the present invention, the doping concentration of the N-pillar region and the P-pillar shielding region of the VDMOS device is 5.0 × 10⁻⁶. 16 cm -3 Up to 1.0×10 17 cm -3 The relationship between feedback capacitance and drain voltage in incremental and conventional 4H-SiC-based VDMOS devices. Figure 7 It can be seen that the feedback capacitance of Example 1 at a drain operating voltage of 800V is 0.369Nf / cm. 2 Compared to the traditional 4H-SiC-based VDMOS with 1.225 Nf / cm 2 The smaller capacitance reflects the superior performance of the VDMOS device in Example 1 in terms of high-frequency response characteristics. Furthermore, a smaller feedback capacitance means a shorter turn-on and turn-off time, indirectly reducing switching losses. Therefore, the switching characteristics of Example 1 are superior to those of the traditional 4H-SiC-based VDMOS. This figure also reflects that the doping concentration of the N-pillar region and the P-pillar shielding region in Example 1 of this invention is 5.0 × 10⁻⁶. 16 cm -3 Up to 1.0×10 17 cm -3 The change in feedback capacitance during increment, from Figure 7 It is known that the higher the drift region concentration of the device, the lower the feedback capacitance at an 800V drain operating voltage. This is because the feedback capacitance is affected by the space charge region, and the value of the space charge region capacitance is affected by the applied bias voltage. In Embodiment 1 of the present invention, the space charge region is smaller than that of a conventional 4H-SiC-based VDMOS. Therefore, Embodiment 1 of the present invention is less affected by the space charge region capacitance. Figure 7 It can also be observed that although the doping concentration in the drift region of the feedback capacitor changes, the overall change is not significant.

[0071] Figure 8A comparison chart of the gate charge performance of the VDMOS device of Embodiment 1 provided by this invention and a conventional 4H-SiC-based VDMOS device. From Figure 8 It can be seen that when the device is not turned on, the gate charge of each device increases with the increase of the gate-source bias voltage, and the CV relationship is approximately linear, with this part of the curves basically overlapping. When the device is first turned on, but the gate voltage is maintained at slightly higher than the threshold voltage than the Miller plateau voltage, the gate charge increases, and although the gate voltage increases, the magnitude is extremely small. After the device is fully turned on, the total charge of the conventional 4H-SiC-based VDMOS is 1739.97 nC / cm³. 2 The total charge in Implementation Case 1 was 1137.31 nC / cm³. 2 In comparison, the total charge of Embodiment 1 of the present invention is reduced by 34.6% compared to that of a conventional trench MOSFET; at the same time, compared to Miller capacitance, the Miller charge of a conventional 4H-SiC-based VDMOS is 267.11 nC / cm. 2 The Miller charge in Implementation Case 1 is 174.03 nC / cm. 2 In comparison, the Miller charge of Embodiment 1 of the present invention is reduced by 34.9% compared to the conventional 4H-SiC-based VDMOS. Therefore, the device of Embodiment 1 of the present invention is superior to the conventional trench MOSFET in terms of gate charge characteristics.

[0072] Figure 9 The diagram shows the changes in drain-source voltage and drain-source current over time during the turn-on and turn-off processes of the VDMOS device provided in Embodiment 1 of the present invention under resistive load. Figure 9 Figure a shows the turn-on process of the device in Embodiment 1 of the present invention when the parasitic inductance is 10nH. As can be seen from a, the turn-on loss of the device is mainly concentrated within 0.43μs, as shown in the figure. Similarly, the turn-off loss of the device is mainly concentrated within 0.41μs, as shown in the figure. Therefore, minimizing this time length is an important goal for reducing the turn-on and turn-off losses of the device. Meanwhile, Figure b shows that the device voltage changes in the same way, with the three curves almost overlapping. The difference in the current curves mainly lies in the different current magnitudes. With resistive loads of 16Ω, 8Ω, 4Ω, and 2Ω, the device turn-off times are 0.41μs, 0.21μs, 0.04μs, and 0.05μs, respectively, corresponding to turn-on times of 0.43μs, 0.16μs, 0.03μs, and 0.02μs, respectively. Considering the known switching characteristics of traditional trench MOSFET devices, the switching characteristics of Embodiment 1 of the present invention are superior to those of traditional trench MOSFET devices.

[0073] Figure 10 For the present invention in V GS At 15V, the doping concentration in the N-pillar region and the P-pillar shielding region is 5.0 × 10⁻⁶. 16 cm -3Up to 1.0×10 17 cm -3 The relationship between drain current and drain voltage as the voltage increases. Figure 10 As can be seen from the data, when the superjunction is used as the drift region, the lower the doping concentration of the P-type and N-type pillars, the smaller the drain current and the larger the breakdown voltage of the device under the same drain voltage. However, as the doping concentration of the drift region decreases, the on-resistance of the device increases, and the breakdown voltage will show a trend of first increasing and then decreasing. This is because when the device is turned off, as the doping concentration of the P-type and N-type pillars continues to decrease, the P-type pillars are always assisting in the depletion of the N-type pillars. When the doping concentration decreases to a certain value, the device will be directly broken down in the middle of the N-type pillar region, and the breakdown voltage will show a sharp drop.

[0074] Figure 11 For the present invention in V GS =15V, V DS At 20V, the doping concentration in the drift region is 8.0 × 10⁻⁶. 16 cm -3 The traditional 4H-SiC-based VDMOS device has a doping concentration of 8.0 × 10⁻⁶ in the N-pillar and P-pillar shielding regions. 16 cm -3 The output characteristic curves of the two devices with the new structure and the comparison of specific on-resistance at the same breakdown voltage are shown. Based on... Figure 11 It can be seen that the drain current I in implementation case 1 is... DS The on-resistance of the device is much greater than that of the traditional 4H-SiC-based VDMOS, indicating that in Implementation Case 1, the addition of an N-channel region in the channel region reduces the channel resistance during conduction, thereby reducing its on-resistance. Therefore, its static conduction performance is better than that of the traditional 4H-SiC-based VDMOS.

[0075] This invention proposes a 4H-SiC-based VDMOS device with a shielding effect, consisting of a superjunction P-pillar and an N-channel. Taking Example 1 as an example, its main process flow is as follows: Figure 12 As shown. Its main processes include: ion implantation, diffusion, etching, oxidation, deposition, polysilicon filling, and annealing to form the superjunction trench gate region and silicon dioxide isolation layer. Finally, polysilicon electrodes are deposited to form the source, gate, and drain electrodes.

[0076] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A 4H-SiC-based VDMOS device with a shielding effect, consisting of a superjunction P-pillar and an N-channel, characterized in that: It includes a P+ polysilicon drain (1), an N+ substrate region (2), a P-pillar shielding region (3), an N-pillar region (4), a P- electric field termination region (5), a silicon dioxide isolation layer (6), a P+ polysilicon gate electrode (7), a P+ polysilicon source electrode I (8), a P+ polysilicon source electrode II (9), an N-channel region (10), and an N+ source region (11); The P+ polycrystalline silicon source electrode I (8) is located above the P-pillar shielding region (3) and is connected to the zero potential point of the P-pillar shielding region (3); The P+ polycrystalline silicon source electrode II (9) is located above the P- electric field termination region (5) and the N+ source region (11), and is connected to the P- electric field termination region (5) and the N+ source region (11); The P+ polysilicon gate electrode (7) is located between the P+ polysilicon source electrode I (8) and the P+ polysilicon source electrode II (9) and extends into the silicon dioxide isolation layer (6); The silicon dioxide isolation layer (6) is embedded in the upper end of the P-pillar shielding region (3) to isolate the P+ polysilicon gate electrode (7) from the P-pillar shielding region (3), the N+ source region (11) and the N- channel region (10); The N-channel region (10) is located above the N-pillar region (4) and to the left of the P-electric field termination region (5); The N+ source region (11) is located above the N-channel region (10) and to the left of the P-electric field termination region (5); The N+ substrate region (2) is located below the P-pillar shielding region (3) and the N-pillar region (4); The P+ polysilicon drain (1) is located below the N+ substrate region (2); The P+ polysilicon drain (1), N+ substrate region (2), N pillar region (4), P+ polysilicon source electrode II (9), N- channel region (10) and N+ source region (11) constitute the conductive region of the device; The N-pillar region (4) and the N-channel region (10) constitute the drift region of the device; The P-pillar shielding region (3) and the N-pillar region (4) constitute the transverse superjunction of the device.

2. The 4H-SiC-based VDMOS device with shielding effect of superjunction P-pillar and N-channel according to claim 1, characterized in that: The width of the P+ polycrystalline silicon source electrode I (8) is 0.4 μm and the height is 0.75 μm; the width of the P+ polycrystalline silicon source electrode II (9) is 0.9 μm and the height is 0.75 μm.

3. A 4H-SiC-based VDMOS device with shielding effect of superjunction P-pillar and N-channel according to claim 1, characterized in that: The P+ polysilicon gate electrode (7) extends 1.25 μm into the silicon dioxide isolation layer (6), and the portion that does not extend into the silicon dioxide isolation layer (6) has a length of 0.75 μm; the P+ polysilicon gate electrode (7) is 0.4 μm wide; The length of the silicon dioxide isolation layer (6) embedded in the P-pillar shielding area (3) is 2 μm, the sidewall thickness is 0.05 μm, and the thickness at the lower part of the P+ polysilicon gate electrode (7) is 0.5 μm.

4. A 4H-SiC-based VDMOS device with shielding effect of superjunction P-pillar and N-channel according to claim 1, characterized in that: The N-channel region (10) has a height of 1 μm and a width of 0.2 μm; the N+ source region (11) has a height of 0.25 μm and a width of 0.4 μm.

5. A 4H-SiC-based VDMOS device with shielding effect of superjunction P-pillar and N-channel according to claim 1, characterized in that: The height of the P-pillar shielding area (3) is 14 μm; the height of the N-pillar area (4) is 12.75 μm.

6. A 4H-SiC-based VDMOS device with shielding effect of superjunction P-pillar and N-channel according to claim 1, characterized in that: The N+ substrate region (2) has a height of 3 μm and a width of 2 μm; the P+ polysilicon drain electrode (1) has a height of 0.5 μm and a width of 2 μm.

7. A 4H-SiC-based VDMOS device with shielding effect of superjunction P-pillar and N-channel according to claim 1, characterized in that: The doping concentration range of the P-pillar shielding region (3), N-pillar region (4), and P-field termination region (5) is 1×10⁻⁶. 15 cm -3 ~5×10 16 cm -3 Adjustments are made based on the device size and the required operating current.

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