Digital Peak Current Mode Control Method, System and Extended Pulse Width Modulation Method

Abstract

The present invention discloses a digital peak current mode control method, system and extended pulse width modulation method, belonging to the field of power electronics technology. The digital peak current mode control method of the present invention is used to control a boost converter, and the boost converter includes a power stage, and the power stage includes a switching transistor S and an inductor. The control method includes: Step S1, sampling the current on the inductor; Step S2, calculating the duty cycle according to the sampled current during the low-level time of each switching cycle; Step S3, performing pulse width modulation on the duty cycle to generate a pulse signal; Step S4, using the pulse signal to control the conduction and disconnection of the switching transistor S, thereby regulating the peak current of the inductor. In the control method of the present invention, the current tracking delay is one switching cycle. Compared with the prior art, the time of CTD is reduced, and the system response speed and transient performance of the DC-DC converter are improved.

Description

Technical Field

[0001] The present invention belongs to the technical fields of power electronics and integrated circuit design, and more specifically, relates to a digital peak current mode control method, system, and extended pulse width modulation method. Background Art

[0002] In recent years, digital peak current mode (DPCM) control strategies have been widely applied to power converters due to a series of advantages. However, due to the inherent delay caused by sampling and calculation time, they suffer from limited bandwidth problems. Combining with current prediction algorithms, predictive DPCM control is an effective method to improve the current loop bandwidth. When the current sampling frequency is limited, the current is predicted before the next sampling point, thereby minimizing the delay of current sampling.

[0003] Current tracking delay (CTD) refers to the delay from the reference current of the DPCM controller to the actual current of the inductor. This is caused by current sampling and the calculation of digital control algorithms and inevitably exists in the system. When the controller bandwidth is low, the impact of CTD on system stability is small, so CTD can be ignored. However, for applications that require high-bandwidth dynamic response, this impact becomes obvious and needs to be considered in the system small-signal model and controller design.

[0004] For DC-DC converters operating in continuous current mode, in existing digital peak current mode control methods, including linear extrapolation, state current prediction, etc., these methods all generate a long current tracking delay (CTD). The CTD of the linear extrapolation method is 4 switching cycles, and the CTD of the state current prediction method is 2 switching cycles. The long switching cycle will reduce the system response speed of the DC-DC converter, leading to system oscillation and performance degradation. Summary of the Invention

[0005] Aiming at the defects and improvement requirements of the prior art, the present invention provides a digital peak current mode control method, system, and extended pulse width modulation method, aiming to reduce the current tracking delay and improve the system response speed of the boost converter.

[0006] To achieve the above object, according to one aspect of the present invention, a digital peak current mode control method is provided for controlling a boost converter, where the boost converter includes a power stage, and the power stage includes a switching transistor S and an inductor. The control method includes:

[0007] Step S1: Sample the current on the inductor;

[0008] Step S2: Calculate the duty cycle according to the sampled current during the low-level time of each switching cycle;

[0009] Step S3: Perform pulse width modulation on the duty cycle to generate a pulse signal;

[0010] Step S4: Use the pulse signal to control the conduction and disconnection of the switching transistor S, thereby regulating the peak current of the inductor.

[0011] Further, the step S2 includes: within the minimum low-level time t min at the start of each switching cycle, calculate the duty cycle d(k) according to the sampled current; wherein, the minimum low-level time t min =(1 - D max )T, D max is the set maximum duty cycle, T is the switching cycle, and k represents the current moment.

[0012] Further, the step S2 includes:

[0013] Set the direct duty cycle D dir (k), within the low-level time of the direct duty cycle, calculate the extended duty cycle d ex (k), the sum of the direct duty cycle and the extended duty cycle is the actual duty cycle; wherein, the direct duty cycle is used to limit the output voltage in the steady state to be equal to the reference voltage, the extended duty cycle is used for peak current tracking, and k represents the current moment;

[0014] The step S3 includes: within each switching cycle, generate a ramp signal that decreases with time until the end of the current switching cycle; compare the direct duty cycle D dir (k) with the ramp signal, when the ramp signal is greater than the direct duty cycle D dir (k), output a low level, when the ramp signal is less than the direct duty cycle D dir (k), output a high level.

[0015] Further, the duty cycle d(k), the peak current i pk (k) and the output voltage v satisfy:

[0016]

[0017] wherein, i ref (k) represents the reference current, v g represents the supply voltage, L represents the inductance value, and T represents the switching cycle.

[0018] Further, perform rising-edge modulation on the duty cycle.

[0019] Further, the direct duty cycle D dir (k), the supply voltage v g and the reference voltage v ref satisfy:

[0020]

[0021] The extended duty cycle d ex (k) and the peak current i pk (k) satisfy the following:

[0022]

[0023] wherein, i ref (k) represents the reference current, L represents the inductance value, and T represents the switching period.

[0024] According to the second aspect of the present invention, a digital peak current mode control system is provided for controlling a boost converter, the boost converter including a power stage, the power stage including a switching transistor S and an inductor, and the control system including:

[0025] A current sampling module for sampling the current on the inductor;

[0026] A duty cycle calculation module for calculating the duty cycle according to the sampled current during the low-level time of each switching period;

[0027] A pulse width modulation module for performing pulse width modulation on the duty cycle to generate a pulse signal;

[0028] A peak current regulation module for controlling the conduction and disconnection of the switching transistor S according to the pulse signal, thereby regulating the peak current of the inductor.

[0029] Further, the duty cycle calculation module includes: at the minimum low-level time t min at the start of each switching period, calculating the duty cycle d(k) according to the sampled current; wherein, the minimum low-level time t min =(1 - D max )T, D max is the set maximum duty cycle, T is the switching period, and k represents the current moment.

[0030] Further, the duty cycle calculation module includes:

[0031] Setting a direct duty cycle D dir (k), and calculating an extended duty cycle d ex (k) according to the sampled current during the low-level time of the direct duty cycle, the sum of the direct duty cycle and the extended duty cycle being the actual duty cycle; wherein, the direct duty cycle is used to limit the output voltage in the steady state to be equal to the reference voltage, and the extended duty cycle is used for peak current tracking, and k represents the current moment;

[0032] The pulse width modulation module includes: generating a ramp signal that decreases with time within each switching cycle until the end of the current switching cycle; comparing the direct duty ratio D dir (k) with the ramp signal, when the ramp signal is greater than the direct duty ratio D dir (k), outputting a low level, and when the ramp signal is less than the direct duty ratio D dir (k), outputting a high level.

[0033] According to the third aspect of the present invention, an extended pulse width modulation method is provided for digital peak current mode control. The method includes:

[0034] Setting the direct duty ratio D dir (k), within the low level time of the direct duty ratio, calculating the extended duty ratio d ex (k) according to the sampled current, and the sum of the direct duty ratio and the extended duty ratio is the actual duty ratio; wherein, the direct duty ratio is used to limit the output voltage in the steady state to be equal to the reference voltage, and the extended duty ratio is used for peak current tracking;

[0035] Generating a ramp signal that decreases with time within each switching cycle until the end of the current switching cycle; comparing the direct duty ratio D dir (k) with the ramp signal, when the ramp signal is greater than the direct duty ratio D dir (k), outputting a low level, and when the ramp signal is less than the direct duty ratio D dir (k), outputting a high level.

[0036] Generally speaking, through the above technical solutions conceived by the present invention, the following beneficial effects can be achieved:

[0037] (1) In the present invention, within the low level time of each switching cycle, the duty ratio is calculated according to the sampled current, and pulse width modulation is performed on the duty ratio, and then a pulse signal is generated. The conduction and disconnection of the switching transistor S are controlled by this pulse signal, and further the peak current of the inductor on the power stage of the boost converter is regulated. That is, within one switching cycle, the digital calculation of the duty ratio and the modulation of the pulse width are completed simultaneously. Therefore, the current tracking delay CTD is one switching cycle. Compared with the prior art, the time of CTD is reduced, and the system response speed of the DC-DC converter is improved. At the same time, the minimized CTD can optimize the control loop bandwidth and improve the stability of the DC-DC boost converter system.

[0038] (2) Preferably, by calculating the duty cycle within the minimum low-level time at the start of each switching cycle, the digital calculation of the duty cycle and the modulation of the pulse width are completed within one switching cycle. The current tracking delay CTD is one switching cycle, which improves the system response speed of the DC-DC converter. Experimental results also show that this digital peak current mode control method of the present invention improves the transient performance of the boost converter compared with the prior art.

[0039] (3) Preferably, by presetting the direct duty cycle and calculating the extended duty cycle within the low-level time of the direct duty cycle, the digital calculation of the duty cycle and the modulation of the pulse width can also be completed within one switching cycle. The current tracking delay CTD is one switching cycle. Compared with the prior art, the time of CTD is reduced, and the system response speed of the DC-DC converter is improved. Experimental results also show that this digital peak current mode control method of the present invention improves the transient performance of the boost converter compared with the prior art. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 is a schematic diagram of the control method of the present invention.

[0041] Figure 2 is the circuit diagram of the boost converter.

[0042] Figure 3 is a schematic diagram of the pulse signal generated by adopting the duty cycle limiting strategy.

[0043] Figure 4 is a schematic diagram of the pulse signal generated by adopting the duty cycle extension strategy.

[0044] Figure 5 is the circuit diagram of regulating the peak current by adopting the duty cycle extension strategy.

[0045] Figure 6 is a schematic diagram of the process of regulating the duty cycle by adopting the extended pulse width modulation method. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0046] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0047] As Figure 1 shown, the digital peak current mode control method provided by the present invention is used to control a boost converter, wherein the circuit of the boost converter is as Figure 2As shown, the boost converter includes a power stage, which includes a power supply voltage source, a switching transistor S, an inductor L, a diode, a capacitor C, and a load resistor R. When the switching transistor S is turned on, the power supply voltage input from the power supply voltage source is applied across the inductor L, and the diode is reverse-biased and turned off. The inductor L stores the energy from the input power supply voltage. When the switching transistor S is turned off, the stored energy in the inductor L forward-biases the diode and turns it on, and transfers the energy to the output capacitor C and the load resistor R.

[0048] The control method of the present invention includes:

[0049] Step S1: Sample the inductor current in the power stage of the boost converter;

[0050] Step S2: Calculate the duty cycle according to the sampled current during the low-level time of each switching cycle;

[0051] Step S3: Perform pulse-width modulation on the duty cycle to generate a pulse signal;

[0052] Step S4: Use the pulse signal to control the on and off of the switching transistor S, and thereby regulate the peak current of the inductor on the power stage of the boost converter.

[0053] Specifically, for step S2, the present invention provides two ways to calculate the duty cycle, namely the duty cycle limiting strategy and the duty cycle expanding strategy.

[0054] For the duty cycle limiting strategy, step S2 includes:

[0055] During the minimum low-level time t min at the start of each switching cycle, calculate the duty cycle d(k) according to the sampled current; wherein, the minimum low-level time t min =(1 - D max )T, D max is the set maximum duty cycle, T is the switching cycle, and k represents the current moment.

[0056] In step S3, compare the calculated duty cycle d(k) with the set maximum duty cycle D max , and take the smaller one as the actual duty cycle; within the current switching cycle, compare the actual duty cycle with a pre-set ramp signal. If the ramp signal is greater than the actual duty cycle, output a low level; if the ramp signal is less than the actual duty cycle, output a high level, thereby generating a pulse signal. Among them, the rising-edge modulation is used for the duty cycle to ensure that the digital calculation of the duty cycle can be carried out at the beginning of each switching cycle.

[0057] In the duty cycle limiting strategy, calculate the duty cycle within the minimum low-level time t min to avoid modulation errors caused by updating the duty cycle after calculation.

[0058] Specifically, the duty cycle d(k), the peak current i pk (k), and the output voltage v satisfy the relational expression:

[0059]

[0060] wherein, i ref (k) represents the reference current at time k, and v g represents the supply voltage, L represents the inductance value, and T represents the switching period.

[0061] It can be seen from the above calculation formula of the duty cycle that the duty cycle d(k) can adjust both the peak current and the output voltage simultaneously. And since the duty cycle is calculated based on the peak current of the current switching period, this equation ensures in real time that i ref (k) = i pk (k + 1).

[0062] As Figure 3 shown, the pulse signal and the inductor current curve obtained by adopting the duty cycle limiting strategy are shown. In the figure, t M represents the digital calculation time of the duty cycle, d(k)T represents the high-level pulse at time k, and d(k + 1)T represents the high-level pulse at time k + 1. It can be seen from the figure that the duty cycle limiting strategy of the present invention can realize the adjustment of the inductor current peak.

[0063] In this method, for a boost converter, the duty cycle is always limited below a certain maximum value, that is, below the set maximum duty cycle. In most applications, the maximum value is between 0.7 and 0.8. Therefore, the finally output pulse must have a low-level time. During the minimum low-level time t min inside, the duty cycle is calculated, and there is no need to spend extra time or switching period for the digital calculation of the duty cycle. This method ensures that within one switching period, the digital calculation of the duty cycle can be completed. Therefore, the current tracking delay CTD is one switching period. Compared with the prior art, the time of CTD is reduced, the system response speed of the DC-DC converter is improved, and the time margin of the digital calculation is (1 - D max )T.

[0064] For the duty cycle extension strategy, step S2 includes:

[0065] Set the direct duty cycle D dir (k). During the low-level time t of the direct duty cycle, calculate the extended duty cycle d ex (k) according to the sampled current. The sum of the direct duty cycle and the extended duty cycle is the actual duty cycle. Among them, the direct duty cycle is used to limit the output voltage under steady state to be equal to the reference voltage, and the extended duty cycle is used for peak current tracking. k represents the current time, and t = [1 - Ddir (k)]T;

[0066] Step S3 includes: within each switching period, generating a ramp signal that decreases over time until the end of the current switching period, that is, until the duration of the extended duty cycle ends (until less than -d ex (k)T); comparing the direct duty cycle D dir (k) of the current period with the ramp signal. When the ramp signal is greater than the direct duty cycle D dir (k), output a low level. When the ramp signal is less than the direct duty cycle D dir (k), output a high level. That is, at the current moment k, the high-level time of the switching period is increased by d ex (k)T or decreased by d ex (k)T, thereby controlling the conduction time of the switching transistor S to increase by d ex (k)T or decrease by d ex (k)T to ensure peak current tracking.

[0067] Specifically, in step S2, the direct duty cycle is determined by the input supply voltage and the reference voltage. Based on the volt-second balance of the main inductor, the steady-state value of the duty cycle of the boost converter is D = 1 - v g / v. Therefore, to ensure that v = v ref in the steady state, the following relationship is satisfied among the direct duty cycle, the input supply voltage, and the reference voltage:

[0068]

[0069] where v g represents the supply voltage, and v ref represents the reference voltage.

[0070] Since the direct duty cycle cannot adjust the inductor current, in order to achieve peak current tracking, an extended duty cycle d ex (k) is added at the end of each direct duty cycle to achieve peak current tracking.

[0071] where the extended duty cycle d ex (k) and the peak current i pk (k) satisfy:

[0072]

[0073] where i ref (k) represents the reference current at time k, v g represents the supply voltage, L represents the inductor value, and T represents the switching period.

[0074] That is, the extended duty cycle can be positive or negative. The choice between positive and negative is based on the magnitudes of the reference current and the peak current. In each switching period, if the reference current is greater than the peak current, the direct duty cycle d ex (k) is positive. That is, a positive duty cycle is added at the end of the current switching period, making the rising time of the inductor current longer, increasing the peak current, and the conduction time of the switching device S becomes [D dir (k) + d ex (k)]T; if the reference current is less than the peak current, the direct duty cycle d ex (k) is negative. That is, a negative duty cycle is added at the end of the current switching period, making the rising time of the inductor current shorter, decreasing the peak current, and the conduction time of the switching device S becomes [D dir (k) - d ex (k)]T. According to the change in the conduction time of the switching device S, the current on the inductor is regulated.

[0075] As Figure 4 shown, the pulse signal and the inductor current curve obtained by using the duty cycle extension strategy are presented. It can be seen from the figure that the duty cycle extension strategy of the present invention can achieve the regulation of the peak value of the inductor current.

[0076] In the duty cycle extension strategy of the present invention, the peak value of the current on the inductor is jointly regulated by the direct duty cycle D dir (k) and the extended duty cycle d ex (k). The direct duty cycle ensures that v = v at steady state ref , and the extended duty cycle ensures peak current tracking. Moreover, this strategy can make full use of the time of the low level of the direct duty cycle. Compared with the duty cycle limit strategy, it provides a more sufficient time margin for the digital calculation of the duty cycle. The time margin for the digital calculation of the duty cycle is [1 - D dir (k)]T.

[0077] Since the digital calculation of the duty cycle is performed during the low level time of the direct duty cycle, similar to the duty cycle limit strategy, there is no need to spend extra time or switching periods for the digital calculation of the duty cycle. This method ensures that the digital calculation of the duty cycle can be completed within one switching period. Therefore, the current tracking delay CTD is one switching period. Compared with the prior art, the time of CTD is reduced, and the system response speed of the DC-DC converter is improved.

[0078] Based on the above description, the present invention also provides a digital peak current mode control system for controlling the boost converter described in the present invention. The boost converter includes a power stage, and the power stage includes a switching device S and an inductor. The control system includes:

[0079] A current sampling module for sampling the current on the inductor;

[0080] A duty cycle calculation module, configured to calculate a duty cycle according to a sampled current during a low-level time of each switching cycle;

[0081] A pulse width modulation module, configured to perform pulse width modulation on the duty cycle to generate a pulse signal;

[0082] A peak current regulation module, configured to control the conduction and disconnection of a switching transistor S according to the pulse signal, and further regulate the peak current of an inductor.

[0083] Specifically, the duty cycle calculation module includes: calculating a duty cycle d(k) according to a sampled current within a minimum low-level time t at the start of each switching cycle; where the minimum low-level time t min =(1 - D min )T, D max is a set maximum duty cycle, T is a switching cycle, and k represents the current moment. max

[0084] Or the duty cycle calculation module includes:

[0085] Setting a direct duty cycle D dir (k), and calculating an extended duty cycle d ex (k) according to a sampled current during a low-level time of the direct duty cycle, where the sum of the direct duty cycle and the extended duty cycle is an actual duty cycle; where the direct duty cycle is used to limit the output voltage in a steady state to be equal to a reference voltage, and the extended duty cycle is used for peak current tracking, and k represents the current moment;

[0086] The pulse width modulation module includes: generating a ramp signal that decreases with time within each switching cycle until the end of the current switching cycle; comparing the direct duty cycle D dir (k) with the ramp signal, and outputting a low level when the ramp signal is greater than the direct duty cycle D dir (k), and outputting a high level when the ramp signal is less than the direct duty cycle D dir (k).

[0087] The present invention further provides an extended pulse width modulation (ExPWM) method for digital peak current mode control, including:

[0088] Setting a direct duty cycle D dir (k), and a peak current controller calculates an extended duty cycle d ex (k) according to a sampled current during a low-level time t of the direct duty cycle, where the sum of the direct duty cycle and the extended duty cycle is an actual duty cycle; where the direct duty cycle is used to limit the output voltage in a steady state to be equal to a reference voltage, and the extended duty cycle is used for peak current tracking;

[0089] During each switching period, a ramp signal that decreases over time is generated until the end of the current switching period, that is, until the duration of the extended duty cycle ends (until it is less than -d ex (k)T); compare the direct duty cycle D dir (k) of the current period with the ramp signal. If the ramp signal is greater than the direct duty cycle D dir (k), output a low level. If the ramp signal is less than the direct duty cycle D dir (k), output a high level.

[0090] Among them, the direct duty cycle D dir (k), the supply voltage v g and the reference voltage v ref satisfy:

[0091]

[0092] The extended duty cycle d ex (k) and the peak current i pk (k) satisfy:

[0093]

[0094] Among them, i ref (k) represents the reference current, L represents the inductance value, and T represents the switching period.

[0095] In this embodiment, experiments show that when the load resistance on the power stage jumps from 20Ω to 10Ω, when the duty cycle limiting strategy is adopted, the output voltage deviates by 0.40V and stabilizes again within 250us; when the duty cycle extension strategy is adopted, the output voltage deviates by 0.42V and stabilizes again within 240us. Under the same supply voltage and reference voltage, when the linear extrapolation peak current control strategy in the prior art is adopted, the output voltage deviates by 0.67V and stabilizes again within 550us; when the state current prediction peak current control strategy in the prior art is adopted, the output voltage deviates by 0.52V and stabilizes again within 380us.

[0096] When the supply voltage jumps from 6V to 5V, when the duty cycle limiting strategy is adopted, the output voltage deviates by 0.16V and stabilizes again within 220us; when the duty cycle extension strategy is adopted, the output voltage deviates by 0.17V and stabilizes again within 180us. Under the same supply voltage and reference voltage, when the linear extrapolation peak current control strategy in the prior art is adopted, the output voltage deviates by 0.26V and stabilizes again within 490us; when the state current prediction peak current control strategy in the prior art is adopted, the output voltage deviates by 0.21V and stabilizes again within 350us.

[0097] When the reference voltage jumps from 10V to 10.5V, when the duty cycle limiting strategy is adopted, the output voltage follows the reference value within 130us; when the duty cycle extension strategy is adopted, the output voltage follows the reference value within 100us. Under the same supply voltage and reference voltage, when the linear extrapolation peak current control strategy in the prior art is adopted, the output voltage tracks the reference value within 400us; when the state current prediction peak current control strategy in the prior art is adopted, the output voltage tracks the reference value within 220us.

[0098] It can be seen from the above experimental results that compared with the existing predictive DPCM control, the present invention greatly improves the transient performance of the converter.

[0099] Those skilled in the art can easily understand that the above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A digital peak current mode control method for controlling a boost converter, the boost converter including a power stage, the power stage including a switching transistor S and an inductor, characterized in that, The control method includes: Step S1, sampling the current on the inductor; Step S2, calculating the duty cycle according to the sampled current during the low-level time of each switching cycle; Step S3, performing pulse width modulation on the duty cycle to generate a pulse signal; Step S4, using the pulse signal to control the on and off of the switch tube S, thereby regulating the peak current of the inductor; The step S2 includes: Set the direct duty cycle D dir (k), during the low-level time of the direct duty cycle, calculate the extended duty cycle d according to the sampled current ex (k), the sum of the direct duty cycle and the extended duty cycle is the actual duty cycle; wherein, the direct duty cycle is used to limit the output voltage in the steady state to be equal to the reference voltage, and the extended duty cycle is used for peak current tracking, and k represents the current moment; The step S3 includes: generating a ramp signal that decreases with time within each switching period until the end of the current switching period; comparing the direct duty cycle D dir (k) with the ramp signal, if the ramp signal is greater than the direct duty cycle D dir (k), output a low level, if the ramp signal is less than the direct duty cycle D dir (k), output a high level; The direct duty cycle D dir (k), the supply voltage v g and the reference voltage v ref satisfy the following: The extended duty cycle d ex (k) and the peak current i pk (k) satisfy the following: where i ref (k) represents the reference current, L represents the inductance value, and T represents the switching period.

2. The method according to claim 1, characterized in that, The step S2 includes: within the minimum low-level time t at the start of each switching cycle min , calculating the duty ratio d(k) according to the sampled current; wherein, the minimum low-level time t min = (1 - D max )T, D max is the set maximum duty ratio, T is the switching cycle, and k represents the current moment.

3. The control method according to claim 2, characterized in that, The duty cycle d(k), peak current i pk (k) and the output voltage v satisfy: Among them, i ref (k) represents the reference current, v g represents the supply voltage, L represents the inductance value, and T represents the switching period.

4. The control method according to claim 2, characterized in that, Performing rising-edge modulation on the duty cycle.

5. A digital peak current mode control system for controlling a boost converter, the boost converter including a power stage, the power stage including a switching transistor S and an inductor, characterized in that, The control system includes: A current sampling module for sampling the current on the inductor; A duty cycle calculation module for calculating the duty cycle according to the sampled current during the low-level time of each switching cycle; A pulse width modulation module for performing pulse width modulation on the duty cycle to generate a pulse signal; A peak current regulation module for controlling the on and off of the switch tube S according to the pulse signal, thereby regulating the peak current of the inductor; The duty cycle calculation module includes: setting a direct duty cycle D dir (k), within the low-level time of the direct duty cycle, calculating an extended duty cycle d ex (k), the sum of the direct duty cycle and the extended duty cycle is the actual duty cycle; wherein, the direct duty cycle is used to limit the output voltage under steady state to be equal to the reference voltage, the extended duty cycle is used for peak current tracking, and k represents the current moment; The pulse width modulation module includes: generating a ramp signal that decreases with time within each switching cycle until the end of the current switching cycle; comparing the direct duty ratio D dir (k) with the ramp signal, if the ramp signal is greater than the direct duty ratio D dir (k), output a low level, if the ramp signal is less than the direct duty ratio D dir (k), output a high level; The direct duty cycle D dir (k), the supply voltage v g and the reference voltage v ref satisfy the following relationship: The extended duty cycle d ex (k) and the peak current i pk (k) satisfy: where i ref (k) represents the reference current, L represents the inductance value, and T represents the switching period.

6. The control system according to claim 5, characterized in that,The duty cycle calculation module includes: within the minimum low-level time t at the start of each switching cycle min , calculating the duty cycle d(k) according to the sampled current; wherein, the minimum low-level time t min =(1 - D max )T, D max is the set maximum duty cycle, T is the switching cycle, and k represents the current moment.

7. An extended pulse width modulation method for digital peak current mode control, characterized in that, The method includes: Set the direct duty cycle D dir (k), during the low-level time of the direct duty cycle, calculate the extended duty cycle d according to the sampled current ex (k), the sum of the direct duty cycle and the extended duty cycle is the actual duty cycle; wherein, the direct duty cycle is used to limit the output voltage in the steady state to be equal to the reference voltage, and the extended duty cycle is used for peak current tracking Within each switching period, a ramp signal that decreases over time is generated until the end of the current switching period; the direct duty cycle D dir (k) is compared with the ramp signal, and when the ramp signal is greater than the direct duty cycle D dir (k), a low level is output, and when the ramp signal is less than the direct duty cycle D dir (k), a high level is output; The direct duty cycle D dir (k), the supply voltage v g and the reference voltage v ref satisfy the following: The extended duty cycle d ex (k) and the peak current i pk (k) satisfy: where i ref (k) represents the reference current, L represents the inductance value, and T represents the switching period.

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