Data reading and writing method and hybrid memory

Abstract

The embodiments of the present application provide a data reading and writing method and a hybrid memory, which relate to the terminal field and can improve reading and writing performance and reduce power consumption. The hybrid memory includes a storage controller, a volatile storage medium and a non-volatile storage medium. The physical address segment of the volatile storage medium is different from the physical address segment of the non-volatile storage medium. The storage controller can receive a read / write instruction from a processor, and the read / write instruction carries a first address (the first address can be a physical address or a logical address); if the first address corresponds to the storage space of the volatile storage medium, the storage controller can perform data reading and writing processing in the storage space of the volatile storage medium; if the first address corresponds to the storage space of the non-volatile storage medium, the storage controller can perform data reading and writing processing in the storage space of the non-volatile storage medium.

Description

Technical Field

[0001] The present application relates to the field of terminals, and in particular to a data reading and writing method and a hybrid memory. Background Art

[0002] Currently, there are two types of storage media in various electronic devices (such as smartphones, tablets, etc.), namely volatile memory (VM) and non-volatile memory (NVM). Volatile memory may include random access memory (RAM). RAM may be, for example, double data rate (DDR) memory. When the system suddenly loses power, the contents stored in the volatile memory will be lost. Non-volatile memory may include, for example, a hard drive disk (HDD) and a solid state disk (SSD). Data in the non-volatile memory will not be lost when the computer is turned off or shut down suddenly or accidentally.

[0003] Volatile memory and non-volatile memory have the following problems: volatile memory consumes high power when reading and writing data, and non-volatile memory encounters long delays and waits when reading and writing data, resulting in low read and write performance. Summary of the Invention

[0004] The embodiments of the present application provide a data reading and writing method and a hybrid memory, which can improve reading and writing performance and reduce power consumption.

[0005] In a first aspect, an embodiment of the present application provides a hybrid memory, which includes a storage controller, a volatile storage medium and a non-volatile storage medium; the physical address segment of the volatile storage medium (which may also be recorded as a volatile storage medium) is different from the physical address segment of the non-volatile storage medium (which may also be recorded as a non-volatile storage medium); the storage controller is used to receive read / write instructions from a processor, and the read / write instructions carry a first address; the first address corresponds to the storage space of the volatile storage medium or the storage space of the non-volatile storage medium; if the first address corresponds to the storage space of the volatile storage medium, the storage controller is used to write data to the storage space of the volatile storage medium or read data from the storage space of the volatile storage medium; if the first address corresponds to the storage space of the non-volatile storage medium, the storage controller is used to write data to the storage space of the non-volatile storage medium or read data from the storage space of the non-volatile storage medium.

[0006] The volatile storage medium group in the hybrid memory provided in the embodiments of the present application can support high-speed data processing and achieve high read and write performance. The non-volatile storage medium group in the hybrid memory has high performance and low power consumption at lower frequencies. Therefore, the use of hybrid memory can improve the read and write performance of electronic devices and reduce power consumption. This can meet the basic demands of low power consumption and high performance for electronic devices on the market. Furthermore, hybrid memory has simple hardware implementation, simple internal design, and low cost.

[0007] In one possible implementation, the hybrid memory further includes at least one of a bus, a substrate, a packaging shell, and a bus interface. The storage controller, volatile storage medium, and non-volatile storage medium are integrated on the substrate, the volatile storage medium and non-volatile storage medium are connected via the bus, and the storage controller, volatile storage medium, non-volatile storage medium, bus, and substrate are encapsulated within the packaging shell. The packaging shell 006 externally presents the bus interface, which is used to connect to the processor. Hybrid memory has simple hardware implementation and internal design, making it easier to implement and lowering costs.

[0008] In one possible implementation, the volatile storage medium includes at least one of double data rate DDR memory, DDR2, DDR3, DDR4, high bandwidth memory (HBM), dynamic random access memory (DRAM), and 3D super DRAM; the non-volatile storage medium includes at least one of single-layer storage flash memory / single-level cell flash memory (SLC)-NAND, magnetic random access memory (MRAM), resistive random access memory (RRAM), phase change random access memory (PCRAM), 3D-Xpoint storage medium, or 3D-SLC NAND flash memory. The embodiments of the present application do not limit the types of volatile storage media or non-volatile storage media.

[0009] In one possible implementation, a hybrid memory is installed as internal memory in an electronic device. Program data can be stored in the hybrid memory during operation. Thus, when an electronic device uses hybrid memory as internal memory, the volatile storage media group in the hybrid memory can support high-speed data processing and achieve high read and write performance. The non-volatile storage media group in the hybrid memory offers high performance and low power consumption at lower frequencies. Therefore, the use of hybrid memory can improve the read and write performance of electronic devices and reduce power consumption. This can meet the basic demands of low power consumption and high performance for electronic devices in the market.

[0010] In one possible implementation, when the electronic device is in the screen-off state, the hybrid memory is powered off. Traditional memory (for example, RAM as memory) cannot be completely powered off in the screen-off state, otherwise the data in the memory will be lost. The data of the non-volatile storage medium group of the hybrid memory provided in the embodiment of the present application will not be lost, and useful data can be stored in the non-volatile storage medium group, so that the electronic device can be completely powered off in the screen-off state, which can greatly reduce power consumption. In addition, when the traditional memory is powered off, the data in the memory will be lost. After the next power-on, the running program needs to be imported into the memory for processing before the system can be booted up. When the hybrid memory is powered off, the data of the non-volatile storage medium group in the hybrid memory is not lost, and the running program can be stored in the non-volatile storage medium group. In this way, the program to be run can be quickly restored when the computer is turned on next time, which can better reduce standby power consumption and improve startup performance.

[0011] In one possible implementation, a non-volatile storage medium is used to store data of a preset type, and the preset type of data includes at least one of artificial intelligence AI data, models, and training results for real-time training. Compared with the prior art, the need to recalculate the preset type of data after power-on results in power consumption, or reading the preset type of data from slow storage results in low efficiency. In an embodiment of the present application, the SoC can directly read the preset type of data from a hybrid memory serving as a memory, and the time it takes is much less than the time resource consumption of recalculation, and is also much less than the time it takes to read from slow storage.

[0012] In one possible implementation, the first address is a physical address or a logical address; if the first address is a logical address, the storage controller is further configured to convert the logical address into a physical address. If the first address is a physical address, the storage controller can directly address a volatile storage medium or a non-volatile storage medium based on the physical address to determine the storage space corresponding to the physical address. If the first address is a logical address, the storage controller is further configured to convert the logical address into a physical address, then address the volatile storage medium or the non-volatile storage medium based on the physical address to determine the storage space corresponding to the physical address.

[0013] In a second aspect, an embodiment of the present application provides a hybrid memory, which includes a storage controller, a volatile storage medium and a non-volatile storage medium; the physical address segment of the volatile storage medium is the same as the physical address segment of the non-volatile storage medium; the storage controller receives a read / write instruction from a processor, and the read / write instruction carries a first address; if the main frequency of the processor is greater than the maximum read / write frequency of the non-volatile storage medium, the storage controller is used to write data to the storage space of the volatile storage medium or read data from the storage space of the volatile storage medium; if the main frequency of the processor is less than or equal to the maximum read / write frequency of the non-volatile storage medium, the storage controller is used to write data to the storage space of the non-volatile storage medium or read data from the storage space of the non-volatile storage medium.

[0014] In this way, when the processor is at a high main frequency (that is, the clock frequency of the processor is higher than the maximum read and write frequency of the non-volatile storage medium), since the maximum read and write frequency of the non-volatile storage medium is lower than the main frequency (that is, the speed at which the non-volatile storage medium processes data is lower than the speed at which the processor processes data), the data is written to the volatile storage medium to meet the requirements of fast action. When the main frequency of the processor is reduced, the maximum read and write frequency of the non-volatile storage medium is greater than or equal to the main frequency, that is, the speed at which the non-volatile storage medium processes data can reach the speed at which the processor processes data, so the data can be written to the non-volatile storage medium to obtain lower power consumption performance. At this time, the volatile storage medium can enter an extremely low power consumption state, which can achieve the effect of reducing power consumption.

[0015] In one possible implementation, if the main frequency of the processor is greater than the maximum read and write frequency of the non-volatile storage medium, the storage controller is also used to write the data written in the storage space of the volatile storage medium into the storage space of the non-volatile storage medium; if the main frequency of the processor is less than or equal to the maximum read and write frequency of the non-volatile storage medium, the storage controller is also used to write the data written in the storage space of the non-volatile storage medium into the storage space of the volatile storage medium.

[0016] That is, when the processor is running at a high frequency, data is first written to the volatile storage medium, and then the storage controller automatically transfers the data to the slower non-volatile storage medium. When the system is operating at a lower speed range that the non-volatile storage medium can match, data is first written to the non-volatile storage medium, and then the storage controller automatically transfers the data to the volatile storage medium. This process can be completed by the storage controller of the hybrid memory, eliminating the need for processor processing, reducing the processor's load and improving its processing performance.

[0017] In one possible implementation, the hybrid memory also includes at least one of a bus, a substrate, a packaging shell and a bus interface; wherein, the storage controller, the volatile storage medium and the non-volatile storage medium are integrated on the substrate, the volatile storage medium and the non-volatile storage medium are connected through the bus, the storage controller, the volatile storage medium and the non-volatile storage medium, the bus and the substrate are packaged inside the packaging shell, and the packaging shell 006 presents a bus interface to the outside, and the bus interface is used to connect to the processor.

[0018] In one possible implementation, the volatile storage medium includes at least one of double data rate DDR memory, DDR2, DDR3, DDR4, high bandwidth memory HBM, dynamic random access memory DRAM or 3D super DRAM; the non-volatile storage medium includes at least one of single-layer storage flash memory SLC-NAND, magnetic random access memory MRAM, resistive random access memory RRAM, phase change random access memory PCRAM, 3D-Xpoint storage medium or 3D-SLC NAND flash memory.

[0019] In a possible implementation, the hybrid memory is installed in the electronic device as a memory.

[0020] In a possible implementation, when the screen of the electronic device is off, the hybrid memory is powered off.

[0021] In one possible implementation, a non-volatile storage medium is used to store data of a preset type, where the preset type of data includes at least one of artificial intelligence (AI) data, models, and training results for real-time training.

[0022] In a possible implementation, the first address is a physical address or a logical address; if the first address is a logical address, the storage controller is further configured to convert the logical address into a physical address.

[0023] In a third aspect, an embodiment of the present application provides a hybrid memory, which includes a storage controller, a volatile storage medium, and a non-volatile storage medium; the physical address segment of the volatile storage medium is partially identical to the physical address segment of the non-volatile storage medium; the storage controller receives a read / write instruction from a processor, and the read / write instruction carries a first address; when the first address corresponds to the storage space of both the non-volatile storage medium and the volatile storage medium, if the main frequency of the processor is greater than the maximum read and write frequency of the non-volatile storage medium, the storage controller is used to write data to the storage space of the volatile storage medium or read data from the storage space of the volatile storage medium; if the main frequency of the processor is less than or equal to the maximum read / write frequency of the non-volatile storage medium, the storage controller is used to write data to the storage space of the non-volatile storage medium or read data from the storage space of the non-volatile storage medium; in the case where the first address corresponds to the storage space of the non-volatile storage medium or the volatile storage medium, if the first address corresponds to the storage space of the volatile storage medium, the storage controller is used to write data to the storage space of the volatile storage medium or read data from the storage space of the volatile storage medium; if the first address corresponds to the storage space of the non-volatile storage medium, the storage controller is used to write data to the storage space of the non-volatile storage medium or read data from the storage space of the non-volatile storage medium.

[0024] In an embodiment of the present application, after the hybrid memory receives the first address, when the first address corresponds to the storage space of both the non-volatile storage medium and the volatile storage medium, when the processor is at a high main frequency (i.e., the clock frequency of the processor is higher than the maximum read and write frequency of the non-volatile storage medium), since the maximum read and write frequency of the non-volatile storage medium is lower than the main frequency (i.e., the speed at which the non-volatile storage medium processes data is lower than the speed at which the processor processes data), the data is written to the volatile storage medium to meet the requirement of fast action. When the main frequency of the processor is reduced, the maximum read and write frequency of the non-volatile storage medium is greater than or equal to the main frequency, i.e., the speed at which the non-volatile storage medium processes data can reach the speed at which the processor processes data, so the data can be written to the non-volatile storage medium to obtain lower power consumption performance. At this time, the volatile storage medium can enter an extremely low power consumption state, which can achieve the effect of reducing power consumption.

[0025] When the first address corresponds to a storage space of a non-volatile storage medium or a volatile storage medium, data can be read and written directly from the storage space of the non-volatile storage medium or the volatile storage medium indicated by the first address. The volatile storage medium group can support high-speed data processing and achieve high read and write performance. The non-volatile storage medium group in the hybrid memory has higher performance and lower power consumption at lower frequencies. Therefore, the use of hybrid memory can improve the read and write performance of electronic devices and reduce power consumption. This can meet the basic demands of low power consumption and high performance for electronic devices on the market.

[0026] In one possible implementation, if the main frequency of the processor is greater than the maximum read and write frequency of the non-volatile storage medium, the storage controller is also used to write the data written in the storage space of the volatile storage medium into the storage space of the non-volatile storage medium; if the main frequency of the processor is less than or equal to the maximum read and write frequency of the non-volatile storage medium, the storage controller is also used to write the data written in the storage space of the non-volatile storage medium into the storage space of the volatile storage medium.

[0027] In one possible implementation, the hybrid memory also includes at least one of a bus, a substrate, a packaging shell and a bus interface; wherein, the storage controller, the volatile storage medium and the non-volatile storage medium are integrated on the substrate, the volatile storage medium and the non-volatile storage medium are connected through the bus, the storage controller, the volatile storage medium and the non-volatile storage medium, the bus and the substrate are packaged inside the packaging shell, and the packaging shell 006 presents a bus interface to the outside, and the bus interface is used to connect to the processor.

[0028] In one possible implementation, the volatile storage medium includes at least one of double data rate DDR memory, DDR2, DDR3, DDR4, high bandwidth memory HBM, dynamic random access memory DRAM or 3D super DRAM; the non-volatile storage medium includes at least one of single-layer storage flash memory SLC-NAND, magnetic random access memory MRAM, resistive random access memory RRAM, phase change random access memory PCRAM, 3D-Xpoint storage medium or 3D-SLC NAND flash memory.

[0029] In a possible implementation, the hybrid memory is installed in the electronic device as a memory.

[0030] In a possible implementation, when the screen of the electronic device is off, the hybrid memory is powered off.

[0031] In one possible implementation, a non-volatile storage medium is used to store data of a preset type, where the preset type of data includes at least one of artificial intelligence (AI) data, models, and training results for real-time training.

[0032] In a possible implementation, the first address is a physical address or a logical address; if the first address is a logical address, the storage controller is further configured to convert the logical address into a physical address.

[0033] In a fourth aspect, an embodiment of the present application provides a data reading and writing method, which is applied to a hybrid memory, wherein the hybrid memory includes a storage controller, a volatile storage medium and a non-volatile storage medium; the physical address segment of the volatile storage medium is different from the physical address segment of the non-volatile storage medium; the method includes: the storage controller receives a read / write instruction from a processor, and the read / write instruction carries a first address; if the first address corresponds to the storage space of the volatile storage medium, the storage controller writes the data to the storage space of the volatile storage medium or reads the data from the storage space of the volatile storage medium; if the first address corresponds to the storage space of the non-volatile storage medium, the storage controller writes the data to the storage space of the non-volatile storage medium or reads the data from the storage space of the non-volatile storage medium.

[0034] In one possible implementation, the hybrid memory also includes at least one of a bus, a substrate, a packaging shell and a bus interface; wherein, the storage controller, the volatile storage medium and the non-volatile storage medium are integrated on the substrate, the volatile storage medium and the non-volatile storage medium are connected through the bus, the storage controller, the volatile storage medium and the non-volatile storage medium, the bus and the substrate are packaged inside the packaging shell, and the packaging shell 006 presents a bus interface to the outside, and the bus interface is used to connect to the processor.

[0035] In one possible implementation, the volatile storage medium includes at least one of double data rate DDR memory, DDR2, DDR3, DDR4, high bandwidth memory HBM, dynamic random access memory DRAM or 3D super DRAM; the non-volatile storage medium includes at least one of single-layer storage flash memory SLC-NAND, magnetic random access memory MRAM, resistive random access memory RRAM, phase change random access memory PCRAM, 3D-Xpoint storage medium or 3D-SLC NAND flash memory.

[0036] In a possible implementation, the hybrid memory is installed in the electronic device as a memory.

[0037] In a possible implementation, when the screen of the electronic device is off, the hybrid memory is powered off.

[0038] In one possible implementation, a non-volatile storage medium is used to store data of a preset type, where the preset type of data includes at least one of artificial intelligence (AI) data, models, and training results for real-time training.

[0039] In a possible implementation, the first address is a physical address or a logical address; if the first address is a logical address, the storage controller is further configured to convert the logical address into a physical address.

[0040] In a fifth aspect, an embodiment of the present application provides a data reading and writing method, which is applied to a hybrid memory, wherein the hybrid memory includes a storage controller, a volatile storage medium and a non-volatile storage medium; the physical address segment of the volatile storage medium is the same as the physical address segment of the non-volatile storage medium; the method includes: the storage controller receives a read / write instruction from a processor, and the read / write instruction carries a first address; if the main frequency of the processor is greater than the maximum read and write frequency of the non-volatile storage medium, the storage controller writes the data to the storage space of the volatile storage medium or reads the data from the storage space of the volatile storage medium; if the main frequency of the processor is less than or equal to the maximum read and write frequency of the non-volatile storage medium, the storage controller writes the data to the storage space of the non-volatile storage medium or reads the data from the storage space of the non-volatile storage medium.

[0041] In one possible implementation, if the main frequency of the processor is greater than the maximum read and write frequency of the non-volatile storage medium, the storage controller is also used to write the data written in the storage space of the volatile storage medium into the storage space of the non-volatile storage medium; if the main frequency of the processor is less than or equal to the maximum read and write frequency of the non-volatile storage medium, the storage controller is also used to write the data written in the storage space of the non-volatile storage medium into the storage space of the volatile storage medium.

[0042] In one possible implementation, the hybrid memory also includes at least one of a bus, a substrate, a packaging shell and a bus interface; wherein, the storage controller, the volatile storage medium and the non-volatile storage medium are integrated on the substrate, the volatile storage medium and the non-volatile storage medium are connected through the bus, the storage controller, the volatile storage medium and the non-volatile storage medium, the bus and the substrate are packaged inside the packaging shell, and the packaging shell 006 presents a bus interface to the outside, and the bus interface is used to connect to the processor.

[0043] In one possible implementation, the volatile storage medium includes at least one of double data rate DDR memory, DDR2, DDR3, DDR4, high bandwidth memory HBM, dynamic random access memory DRAM or 3D super DRAM; the non-volatile storage medium includes at least one of single-layer storage flash memory SLC-NAND, magnetic random access memory MRAM, resistive random access memory RRAM, phase change random access memory PCRAM, 3D-Xpoint storage medium or 3D-SLC NAND flash memory.

[0044] In a possible implementation, the hybrid memory is installed in the electronic device as a memory.

[0045] In a possible implementation, when the screen of the electronic device is off, the hybrid memory is powered off.

[0046] In one possible implementation, a non-volatile storage medium is used to store data of a preset type, where the preset type of data includes at least one of artificial intelligence (AI) data, models, and training results for real-time training.

[0047] In a possible implementation, the first address is a physical address or a logical address; if the first address is a logical address, the storage controller is further configured to convert the logical address into a physical address.

[0048] In a sixth aspect, an embodiment of the present application provides a data reading and writing method, which is applied to a hybrid memory, wherein the hybrid memory includes a storage controller, a volatile storage medium and a non-volatile storage medium; the physical address segment of the volatile storage medium is partially the same as the physical address segment of the non-volatile storage medium; the method includes: the storage controller receives a read / write instruction from the processor, and the read / write instruction carries a first address; when the first address corresponds to the storage space of the non-volatile storage medium and the volatile storage medium at the same time, if the main frequency of the processor is greater than the maximum read and write frequency of the non-volatile storage medium, the storage controller writes the data to the storage space of the volatile storage medium or reads the data from the storage space of the volatile storage medium ; If the main frequency of the processor is less than or equal to the maximum read and write frequency of the non-volatile storage medium, the storage controller writes data to the storage space of the non-volatile storage medium or reads data from the storage space of the non-volatile storage medium; in the case where the first address corresponds to the storage space of the non-volatile storage medium or the volatile storage medium, if the first address corresponds to the storage space of the volatile storage medium, the storage controller writes data to the storage space of the volatile storage medium or reads data from the storage space of the volatile storage medium; if the first address corresponds to the storage space of the non-volatile storage medium, the storage controller writes data to the storage space of the non-volatile storage medium or reads data from the storage space of the non-volatile storage medium.

[0049] In one possible implementation, if the main frequency of the processor is greater than the maximum read and write frequency of the non-volatile storage medium, the storage controller is also used to write the data written in the storage space of the volatile storage medium into the storage space of the non-volatile storage medium; if the main frequency of the processor is less than or equal to the maximum read and write frequency of the non-volatile storage medium, the storage controller is also used to write the data written in the storage space of the non-volatile storage medium into the storage space of the volatile storage medium.

[0050] In one possible implementation, the hybrid memory also includes at least one of a bus, a substrate, a packaging shell and a bus interface; wherein, the storage controller, the volatile storage medium and the non-volatile storage medium are integrated on the substrate, the volatile storage medium and the non-volatile storage medium are connected through the bus, the storage controller, the volatile storage medium and the non-volatile storage medium, the bus and the substrate are packaged inside the packaging shell, and the packaging shell 006 presents a bus interface to the outside, and the bus interface is used to connect to the processor.

[0051] In one possible implementation, the volatile storage medium includes at least one of double data rate DDR memory, DDR2, DDR3, DDR4, high bandwidth memory HBM, dynamic random access memory DRAM or 3D super DRAM; the non-volatile storage medium includes at least one of single-layer storage flash memory SLC-NAND, magnetic random access memory MRAM, resistive random access memory RRAM, phase change random access memory PCRAM, 3D-Xpoint storage medium or 3D-SLC NAND flash memory.

[0052] In a possible implementation, the hybrid memory is installed in the electronic device as a memory.

[0053] In a possible implementation, when the screen of the electronic device is off, the hybrid memory is powered off.

[0054] In one possible implementation, a non-volatile storage medium is used to store data of a preset type, where the preset type of data includes at least one of artificial intelligence (AI) data, models, and training results for real-time training.

[0055] In a possible implementation, the first address is a physical address or a logical address; if the first address is a logical address, the storage controller is further configured to convert the logical address into a physical address.

[0056] In the seventh aspect, an embodiment of the present application provides an electronic device, including a processor, a hybrid memory and a bus, wherein the processor and the hybrid memory are interconnected via the bus, and the hybrid memory includes a storage controller, a volatile storage medium and a non-volatile storage medium; wherein the hybrid memory is used to store computer program code, and the computer program code includes computer instructions; when the computer instructions are executed by the processor, the processor and the hybrid memory execute any one of the methods provided in the third to fifth aspects above.

[0057] In an eighth aspect, an embodiment of the present application provides a computer-readable storage medium comprising instructions, which, when executed on a computer, enables the computer to execute any one of the methods provided in the third to fifth aspects above.

[0058] In a ninth aspect, an embodiment of the present application provides a computer program product comprising instructions, which, when executed on a computer, enables the computer to execute any one of the methods provided in the third to fifth aspects above.

[0059] In a tenth aspect, an embodiment of the present application provides a chip system, which includes a processor and may also include a memory, for implementing any one of the methods provided in aspects 3 to 5 above. The chip system can be composed of a chip or can include a chip and other discrete devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] Figure 1 A schematic diagram of the structure of a hybrid memory provided in an embodiment of the present application;

[0061] Figure 2 A signal interaction diagram provided in an embodiment of the present application;

[0062] Figure 3 A signal interaction diagram provided in an embodiment of the present application;

[0063] Figure 4 A cross-sectional view and a three-dimensional structural view of a hybrid memory provided in an embodiment of the present application;

[0064] Figure 5 A schematic diagram of a physical address segment of a hybrid memory provided in an embodiment of the present application;

[0065] Figure 6 A schematic diagram of a physical address segment of another hybrid memory provided in an embodiment of the present application;

[0066] Figure 7 A schematic diagram of a physical address segment of another hybrid memory provided in an embodiment of the present application;

[0067] Figure 8 A schematic diagram of a physical address segment of another hybrid memory provided in an embodiment of the present application;

[0068] Figure 9 A schematic diagram of a physical address segment of a hybrid memory provided in an embodiment of the present application;

[0069] Figure 10 A schematic diagram of a physical address segment of a hybrid memory provided in an embodiment of the present application;

[0070] Figure 11 A schematic diagram of a physical address segment of a hybrid memory provided in an embodiment of the present application;

[0071] Figure 12 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0072] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. In the description of the present application, unless otherwise specified, "at least one" means one or more, and "a plurality of" means two or more than two. In addition, in order to facilitate the clear description of the technical solutions in the embodiments of the present application, in the embodiments of the present application, words such as "first" and "second" are used to distinguish between identical or similar items with substantially the same functions and effects. Those skilled in the art will understand that words such as "first" and "second" do not limit the quantity and execution order, and words such as "first" and "second" do not necessarily limit them to be different.

[0073] Currently, the RAM commonly used for fast data access is DDR synchronous dynamic random access memory (DDR-SDRAM). Due to semiconductor leakage, DDR-SDRAM needs to constantly refresh the stored data (i.e., periodically rewrite the data), which consumes a lot of power. When the system suddenly loses power (power outage), the stored content will be lost. Storage, which can access data persistently, processes data slowly. When the system wants to write data to the storage, it usually encounters long delays and waits. For example, the synchronous write command (SyncWrite) of critical data will cause the input and output (IO) performance of the storage to drop instantly.

[0074] The present application provides a hybrid memory (also known as heterogeneous memory or hybrid heterogeneous memory, not limited in this application) that can be flexibly used as a memory device, improving the read and write performance of the operating system (OS) and the performance of databases using the hybrid memory as a storage medium. Furthermore, it can prevent the loss of quickly accessed data during a power outage, enabling power to be turned off immediately after writing is complete, thus saving power.

[0075] like Figure 1As shown, an embodiment of the present application provides a hybrid memory 100. The hybrid memory 100 may include a storage controller 001, a volatile storage medium 002, a non-volatile storage medium 003, a bus 004, a substrate 005, a package 006, and a bus interface 007. The volatile storage medium 002 and the non-volatile storage medium 003 may be connected to the storage controller 001. The storage controller 001, the volatile storage medium 002, and the non-volatile storage medium 003 may be integrated on the substrate 005. The volatile storage medium 002 and the non-volatile storage medium 003 may be connected via the bus 004. The storage controller 001, the volatile storage medium 002, the non-volatile storage medium 003, the bus 004, and the substrate 005 may be encapsulated inside the package 006, and the package 006 may present the bus interface 007 to the outside.

[0076] The volatile storage medium may include DDR memory (DDR for short), DDR2, DDR3, DDR4, high-bandwidth memory (HBM), dynamic random access memory (DRAM), 3D super DRAM (Super-DRAM), etc. For example, the volatile storage medium may be HBM with a width of 512 bits and a capacity of 1 GB.

[0077] Non-volatile storage media can be, for example, single-layer storage flash memory / single-layer cell flash memory SLC-NAND, magnetic random access memory MRAM, resistive random access memory RRAM, phase change random access memory PCRAM, 3D-Xpoint storage media or 3D-SLC NAND flash memory, etc.

[0078] The hybrid memory 100 may be packaged in a flip package, a ball grid array (BGA) package, or a wafer level chip scale package (WLCSP).

[0079] The bus interface 007 presented to the outside by the package shell 006 can be a single interface. For example, it can be a DDR4 interface that complies with the Joint Electron Device Engineering Council (JEDEC) specification. Alternatively, the bus interface 007 presented to the outside by the package shell 006 can include multiple (two or more) interfaces. For example, it can include two DDR4 interfaces that comply with the JEDEC specification.

[0080] The hybrid memory can be provided in an electronic device, and the hybrid memory can be used as the memory of the electronic device, that is, program data can be stored in the hybrid memory during operation. The electronic device also includes a processor (e.g., a system on chip (SoC)). The SoC can serve as a master device (HOST) and the hybrid memory can serve as a slave device (DEVICE). The SoC can write data to the hybrid memory or read data from the hybrid memory.

[0081] The SoC and hybrid memory can be connected via one or more of the DDR5 interface, HBM DDR interface, or PCIe Gen5x4 interface. This means that the bus connection between the SoC and hybrid memory is rich in options and combinations.

[0082] like Figure 2 As shown, when the SoC needs to read data from the hybrid memory, the SoC can send a read instruction to the storage controller 001, and the read instruction includes a first address. After receiving the read instruction, the storage controller 001 determines the storage space corresponding to the first address and reads the data from the storage space. The first address can be a first physical address or a first logical address. If the first address is a first physical address, after receiving the read instruction, the storage controller 001 directly addresses the volatile storage medium or non-volatile storage medium according to the first physical address, determines the storage space corresponding to the first physical address, and reads the first data from the storage space corresponding to the first physical address. If the first address is a first logical address, after receiving the read instruction, the storage controller 001 determines the first physical address according to the first logical address, then addresses the volatile storage medium or non-volatile storage medium according to the first physical address, determines the storage space corresponding to the first physical address, and reads the first data from the storage space corresponding to the first physical address. Then, the storage controller 001 sends the first data to the SoC.

[0083] like Figure 3As shown, when the SoC needs to write data to the hybrid memory, the SoC can send a write instruction to the storage controller 001, which includes a second address and the data to be written. After receiving the write instruction, the storage controller 001 determines the storage space corresponding to the second address and writes the data to be written into the storage space. The second address can be a second physical address or a second logical address. If the second address is a second physical address, after receiving the write instruction, the storage controller 001 directly addresses the volatile storage medium or non-volatile storage medium based on the second physical address, determines the storage space corresponding to the second physical address, and writes the data to be written into the storage space corresponding to the second physical address. If the second address is a second logical address, after receiving the read instruction, the storage controller 001 determines the second physical address based on the second logical address, then addresses the volatile storage medium or non-volatile storage medium based on the second physical address, determines the storage space corresponding to the second physical address, and reads the second data from the storage space corresponding to the second physical address. Optionally, the storage controller 001 can send a response message to the SoC, indicating that the write operation has been completed.

[0084] Figure 4 (a) in FIG. 1 shows a cross-sectional view of a hybrid memory. Figure 4 (b) in FIG. 1 shows a three-dimensional structure diagram of a hybrid memory. Figure 4 (a) includes a substrate 501, internal connections 502, a volatile storage medium group 503 (a volatile storage medium may include multiple ones, which may be referred to as a volatile storage medium group), a non-volatile storage medium group 504 (a non-volatile storage medium may include multiple ones, which may be referred to as a non-volatile storage medium group), a storage controller 505, a housing 506, a BGA pad 507 and a bus interface 508. Figure 4 In (b), it includes a substrate 501 , a volatile storage medium group 503 , a non-volatile storage medium group 504 and a BGA pad 507 .

[0085] A volatile storage medium group 503 and a non-volatile storage medium group 504 may be mounted on substrate 501. Volatile storage medium group 503 may be connected to BGA pads 507 via internal wiring 502. Non-volatile storage medium group 504 may be connected to BGA pads 507 via internal wiring 502. A storage controller 505 may be connected to substrate 501 via pads 507.

[0086] Exemplarily, the thickness of the substrate 501 can be 0.15 mm. The volatile storage medium group 503 can include 4 Micron DDR4 chips using a 1 Alphanm process node. The storage space size of each Micron DDR4 chip can be 8 Gb (i.e., 1 GB). The bonding wires between the Micron DDR4 chips (i.e., internal connections 502) can be gold wires. The non-volatile storage medium group 504 can include 4 GlobalFoundry MRAM chips using a 28nm process node, and the storage space size of each GlobalFoundry MRAM chip can be 1 Gb. The bonding wires between the non-volatile storage media (i.e., internal connections 502) can be gold wires. The storage controller 505 is responsible for communicating with the HOST device (e.g., SoC) and is also responsible for managing the volatile storage medium group 503 and the non-volatile storage medium group 504. The storage space size of the hybrid memory may include the sum of the storage space size of the volatile storage medium group 503 (32Gb, i.e. 4GB) and the storage space size of the non-volatile storage medium group 504 (4Gb, i.e. 1GB). The storage controller 505 may be a customized controller developed based on an application-specific integrated chip (ASIC) at a 22nm process node. The housing 506 may be made of plastic, on which the device model may be marked. The pitch of the BGA pad 507 may be 0.45mm. The hybrid memory may also include a power module, glue and filler, etc. Figure 4 After the hybrid memory is packaged, it can be subjected to package level testing on an automatic test equipment (ATE) machine to ensure the packaging quality.

[0087] It should be noted that when electronic devices use hybrid memory as internal memory, the volatile storage media group in the hybrid memory can support high-speed data processing and achieve high read and write performance. The non-volatile storage media group in the hybrid memory has higher performance and lower power consumption at lower frequencies. Therefore, the use of hybrid memory can improve the read and write performance of electronic devices and reduce power consumption. This can meet the basic demand of low power consumption and high performance for electronic devices in the market.

[0088] In addition, traditional memory (for example, RAM as memory) cannot be completely powered off in the screen-off state, otherwise the data in the memory will be lost. The data of the non-volatile storage medium group of the hybrid memory provided in the embodiment of the present application will not be lost, and useful data can be stored in the non-volatile storage medium group, so that the electronic device can be completely powered off in the screen-off state, which can greatly reduce power consumption. Among them, the screen-off state can also be called the screen-off state. The electronic device may not display any information in the screen-off state, or may display limited information (for example, the current time, date, etc.). In addition, when the traditional memory is powered off, the data in the memory will be lost. After the next power-on, the running program needs to be imported into the memory for processing before the system can be booted. When the hybrid memory is powered off, the data of the non-volatile storage medium group in the hybrid memory is not lost, and the running program can be stored in the non-volatile storage medium group. In this way, the program to be run can be quickly restored when the computer is turned on next time, which can better reduce standby power consumption and improve startup performance.

[0089] The hybrid memory can use different address allocation modes, including parallel mode, shadow mode, and hybrid mode. The parallel mode, shadow mode, and hybrid mode are described below.

[0090] In parallel mode, the physical address segments corresponding to the volatile storage medium and the non-volatile storage medium do not overlap (are different). When the SoC accesses the hybrid memory, it can address the volatile storage medium and the non-volatile storage medium separately.

[0091] In parallel mode, the storage space sizes of the volatile storage medium and the non-volatile storage medium can be equal or different. For example, the number of physical addresses corresponding to the volatile storage medium can be equal to the number of physical addresses corresponding to the non-volatile storage medium. Figure 5 As shown, the volatile storage medium and the non-volatile storage medium may correspond to physical address segment 1 and physical address segment 2 respectively. Physical address segment 1 includes 0x1-0x4; physical address segment 2 includes 0x5-0x8. Alternatively, the number of physical addresses corresponding to the volatile storage medium may be greater than the number of physical addresses corresponding to the non-volatile storage medium. Figure 7 As shown, the volatile storage medium and the non-volatile storage medium may correspond to physical address segment 1 and physical address segment 2 respectively. Physical address segment 1 includes 0x1-0x5; physical address segment 2 includes 0x6-0x8. This application does not limit this. Alternatively, the number of physical addresses corresponding to the volatile storage medium may be less than the number of physical addresses corresponding to the non-volatile storage medium. Figure 6As shown, the volatile storage medium and the non-volatile storage medium may correspond to physical address segment 1 and physical address segment 2, respectively. Physical address segment 1 includes 0x1-0x3; physical address segment 2 includes 0x4-0x8.

[0092] In parallel mode, when the hybrid memory is powered off and then powered on, the data in the non-volatile storage medium will not be lost. For some preset types of data, the preset types of data may include, for example, artificial intelligence (AI) data, models (patterns) and training results for real-time training, etc. The preset types of data can be written to the non-volatile storage medium (for example, FastNVM) of the hybrid memory. These data are stored in FastNVM and can be accessed at any time. Even if the system is powered off, the data will not be lost and there is no need to repeat the calculation. Compared with the prior art, the need to recalculate the preset type of data after power-on results in power consumption, or reading the preset type of data from the slow Storage results in low efficiency. In the embodiment of the present application, the SoC can directly read the preset type of data from the hybrid memory serving as the memory, and the time it takes is much less than the time resource consumption of recalculation, and is also much less than the time it takes to read from the slow Storage.

[0093] The parallel mode hybrid memory has simple hardware implementation and simple internal design, is easier to implement and has lower cost.

[0094] In shadow mode, the physical address segments of volatile storage media and non-volatile storage media are the same (overlap). That is, the same physical address can point to both volatile storage media and non-volatile storage media. In shadow mode, the sizes of volatile storage media and non-volatile storage media are equal. That is, the number of physical addresses corresponding to volatile storage media is equal to the number of physical addresses corresponding to non-volatile storage media. For example, Figure 8 As shown, the volatile storage medium and the non-volatile storage medium may correspond to physical address segment 1 and physical address segment 2, respectively. Physical address segment 1 includes 0x1-0x4; physical address segment 2 also includes 0x1-0x4.

[0095] When the address allocation mode is shadow mode, the hybrid memory can implement multiple data storage modes through the memory controller, including power / performance auto balance mode and data shadow mode. As shown in Table 1, power / performance auto balance mode and data shadow mode can be configured through the mode register (MR).

[0096] Table 1

[0097] Mode register Data storage mode Power-on default 1 Power consumption and performance automatic balance mode √ 0 Data Shadow Mode

[0098] After power-on initialization, the hybrid memory can default to a certain mode. For example, you can define the hybrid memory to default to data shadow mode after power-on. Alternatively, you can define the hybrid memory to default to power / performance automatic balancing mode. Table 1 shows that the hybrid memory defaults to power / performance automatic balancing mode after power-on.

[0099] In power consumption / performance automatic balancing mode: When the SoC is at a high main frequency (i.e., the CPU clock speed is higher than the maximum read / write frequency of the non-volatile storage medium), because the maximum read / write frequency of the non-volatile storage medium is lower than the main frequency (i.e., the speed at which the non-volatile storage medium processes data is lower than the speed at which the processor processes data), data is written to the volatile storage medium to meet the requirements of fast action. When the main frequency of the SoC is reduced, the maximum read / write frequency of the non-volatile storage medium is greater than or equal to the main frequency, i.e., the speed at which the non-volatile storage medium processes data can reach the speed at which the processor processes data. Therefore, data can be written to the non-volatile storage medium to achieve lower power consumption performance. At this time, the volatile storage medium can enter an extremely low power state to reduce power consumption. The above process can be completed by the storage controller of the hybrid memory, eliminating the need for the SoC to write data to two different types of storage sub-units, which can reduce the load on the SoC side and improve the processing performance of the SoC.

[0100] In data shadow mode, when the SoC is operating at a high clock speed, data is first written to the volatile storage medium, and then the storage controller automatically transfers the data to the slower non-volatile storage medium. When the system is operating at a lower speed range that the non-volatile storage medium can match, data is first written to the non-volatile storage medium, and then the storage controller automatically transfers the data to the volatile storage medium. This process can be completed by the hybrid memory's storage controller, eliminating the need for SoC processing, reducing the load on the SoC and improving its processing performance.

[0101] In data shadow mode, when the hybrid memory is powered off and then powered on again, the data on the volatile storage medium of the hybrid memory is lost, but the data on the non-volatile storage medium is still retained. Since the data recorded in the volatile storage medium and the non-volatile storage medium are the same, the data will not be actually lost, effectively avoiding data loss.

[0102] In hybrid mode, some physical address segments of the hybrid memory can point to either volatile or non-volatile storage media, while other physical address segments can point to only one of the two. As shown in Table 2, the physical addresses corresponding to volatile and non-volatile storage media can be combined in various ways. For example, combinations 1, 2, and 3 may be used.

[0103] Table 2

[0104]

[0105] It should be noted that independent addresses can be accessed via direct addressing. Overlapping addresses require access via mode register configuration. This means the memory controller determines how to access overlapping addresses. For example, access can be performed in power / performance balancing mode or data shadow mode. This ensures data processing speed while preventing data loss.

[0106] Overlapping addresses can be flexibly set according to the amount of important data that the electronic device needs to process (such as "user portrait" training data, key context information, AI real-time training data, etc.). If the electronic device needs to process a lot of important data, more overlapping addresses can be set to ensure the processing rate of important data and avoid the loss of important data. If the electronic device needs to process less important data, fewer overlapping addresses can be set to avoid wasting storage space.

[0107] For example, as shown in Table 3, when the combination is combination 1, the volatile storage medium and the non-volatile storage medium both have some independent addresses, while also having some overlapping addresses. The number of independent addresses included in the volatile storage medium and the number of independent addresses included in the non-volatile storage medium can be the same or different, and this application does not limit this.

[0108] Table 3

[0109]

[0110]

[0111] For example, Figure 9As shown, the volatile storage medium and the non-volatile storage medium can correspond to physical address segment 1 and physical address segment 2, respectively. Physical address segment 1 includes 0x1-0x4. Physical address segment 1 includes independent addresses and overlapping addresses, and the independent addresses include 0x1-0x2; the overlapping addresses include 0x3-0x4. Physical address segment 2 includes 0x3-0x6. Physical address segment 2 includes independent addresses and overlapping addresses, and the independent addresses include 0x5-0x6; the overlapping addresses include 0x3-0x4. Of course, the number of independent addresses included in physical address segment 1 and the number of independent addresses included in physical address segment 2 may be different, and this application does not limit it.

[0112] Combination 1 is suitable for complex multi-core electronic devices such as mobile phones and tablets. The CPU of the electronic device can read and write in the storage space indicated by the independent address of the volatile storage medium (for example, 4 to 8GB) at a high main frequency to meet the needs of fast data processing. Important data (such as "user portrait" training data, key context information (context), AI real-time training data, etc.) can be stored in the storage space indicated by the overlapping address (for example, 128MB) to obtain the effect of no loss in the event of power failure, no need for repeated training, and rapid recovery. The boot code of the Boot stage can be stored in the storage space indicated by the independent address of the non-volatile storage medium (for example, 128MB) to achieve fast startup.

[0113] For another example, as shown in Table 4, when the combination is combination 2, only the volatile storage medium has a portion of independent addresses, and a portion of addresses of the non-volatile storage medium and the volatile storage medium completely overlap.

[0114] Table 4

[0115]

[0116] For example, Figure 10 As shown, volatile storage media and non-volatile storage media can correspond to physical address segments 1 and 2, respectively. Physical address segment 1 includes 0x1-0x6. Physical address segment 1 includes independent addresses and overlapping addresses. Independent addresses include 0x1-0x2 and 0x5-0x6; overlapping addresses include 0x3-0x4. Physical address segment 2 includes 0x3-0x4. Physical address segment 2 only includes overlapping addresses, namely 0x3-0x4.

[0117] Combination 2 is also suitable for complex multi-core electronic devices such as mobile phones and tablets. Furthermore, when hybrid memory uses combination 2, the manufacturing cost is lower than when using combination 1. Since non-volatile storage media do not have independent addresses, the boot code in the Boot phase needs to be stored in a storage space indicated by overlapping addresses. This means that when the electronic device is booted during the Boot phase, the volatile storage medium needs to be in a ready state, increasing the current consumption of the volatile storage medium. However, compared to the working state that electronic devices are in most of the time during daily use, the additional power consumption here is minimal, and the chip cost reduction benefit is even greater.

[0118] For another example, as shown in Table 5, when the combination is combination 3, the non-volatile storage medium has a portion of independent addresses, and a portion of addresses of the non-volatile storage medium and the volatile storage medium completely overlap.

[0119] Table 5

[0120]

[0121] For example, Figure 11 As shown, volatile storage media and non-volatile storage media can correspond to physical address segments 1 and 2, respectively. Physical address segment 1 includes 0x1-0x2. Physical address segment 1 only includes overlapping addresses, namely 0x1-0x2. Physical address segment 2 includes independent addresses and overlapping addresses. Independent addresses include 0x3-0x4 and 0x5-0x6; overlapping addresses include 0x1-0x2.

[0122] Combination 3 is suitable for wearable devices, IoT devices, etc. The main frequency of the processors of wearable devices and IoT devices is usually lower than the maximum read and write frequency of the non-volatile storage medium. Therefore, most of the data can be read and written in the storage space indicated by the independent address of the non-volatile storage medium (for example, 256MB). Data that requires high-speed processing (such as real-time training data such as voice recognition) can be processed in the storage space indicated by the overlapping address (for example, 128MB), that is, it can be processed in the storage space of the volatile storage medium to achieve the effect of no loss in the event of power failure, no need for repeated training, and rapid recovery. The processed calculation results can be stored in the non-volatile memory to avoid loss.

[0123] In hybrid mode, the data in the physical address segment of the non-volatile storage medium is retained when the hybrid memory is powered off and then powered on again. If there is an independent volatile storage address segment, the previous data is lost after power is turned on again.

[0124] The hybrid mode allows volatile storage media and non-volatile storage media to reuse physical addresses according to actual needs, which is more flexible and convenient.

[0125] In addition, Soc can use software to use the hybrid memory in parallel mode as shadow mode or hybrid mode according to actual needs, which is not limited in this application.

[0126] An embodiment of the present application also provides an electronic device in which the above-mentioned hybrid memory can be provided. The electronic device can be, for example, a mobile phone, a tablet computer, a desktop computer, a laptop computer, an ultra-mobile personal computer (UMPC), a handheld computer, a netbook, a personal digital assistant (PDA), or the like.

[0127] For example, Figure 12 As shown, the structure of an electronic device (e.g., a mobile phone) provided in an embodiment of the present application is illustrated. The electronic device 200 may include: a processor 210, an external memory interface 220, a hybrid memory (i.e., hybrid memory) 221, a universal serial bus (USB) interface 230, a charging management module 240, a power management module 241, a battery 242, an antenna 1, an antenna 2, a mobile communication module 250, a wireless communication module 260, an audio module 270, a speaker 270A, a receiver 270B, a microphone 270C, an earphone interface 270D, a sensor module 280, a button 290, a motor 291, an indicator 292, a camera 293, a display 294, and a subscriber identification module (SIM) card interface 295, etc.

[0128] Among them, the above-mentioned sensor module 280 may include sensors such as pressure sensor, gyroscope sensor, air pressure sensor, magnetic sensor, acceleration sensor, distance sensor, proximity light sensor, fingerprint sensor, temperature sensor, touch sensor, ambient light sensor and bone conduction sensor.

[0129] It should be understood that the structure illustrated in this embodiment does not constitute a specific limitation on the electronic device 200. In other embodiments, the electronic device 200 may include more or fewer components than shown, or may combine or separate certain components, or arrange the components differently. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0130] The processor 210 may include one or more processing units. For example, the processor 210 may include an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, a memory, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural-network processing unit (NPU). The different processing units may be independent devices or integrated into one or more processors.

[0131] The controller may be the nerve center and command center of the electronic device 200. The controller may generate an operation control signal according to the instruction operation code and the timing signal to complete the control of fetching and executing instructions.

[0132] Processor 210 may also include a memory for storing instructions and data. In some embodiments, the memory in processor 210 is a cache memory. This memory can store instructions or data that have just been used or are being recycled by processor 210. If processor 210 needs to use the same instruction or data again, it can directly access the memory. This avoids duplicate accesses, reduces processor 210 latency, and thus improves system efficiency.

[0133] In some embodiments, the processor 210 may include one or more interfaces. The interfaces may include an inter-integrated circuit (I2C) interface, an inter-integrated circuit sound (I2S) interface, a pulse code modulation (PCM) interface, a universal asynchronous receiver / transmitter (UART) interface, a mobile industry processor interface (MIPI), a general-purpose input / output (GPIO) interface, a subscriber identity module (SIM) interface, and / or a universal serial bus (USB) interface.

[0134] It is understood that the interface connection relationship between the modules illustrated in this embodiment is merely an illustrative illustration and does not limit the structure of the electronic device 200. In other embodiments, the electronic device 200 may also adopt different interface connection methods from the above embodiments, or a combination of multiple interface connection methods.

[0135] The charging management module 240 is used to receive charging input from a charger. The charger can be a wireless charger or a wired charger. While charging the battery 242, the charging management module 240 can also power the electronic device through the power management module 241.

[0136] The power management module 241 is used to connect the battery 242, the charging management module 240, and the processor 210. The power management module 241 receives input from the battery 242 and / or the charging management module 240 and provides power to the processor 210, the hybrid memory 221, the external memory, the display 294, the camera 293, and the wireless communication module 260. In some embodiments, the power management module 241 and the charging management module 240 can also be provided in the same device.

[0137] The wireless communication function of the electronic device 200 can be implemented through antenna 1, antenna 2, mobile communication module 250, wireless communication module 260, a modem processor, and a baseband processor. In some embodiments, the antenna 1 of the electronic device 200 is coupled to the mobile communication module 250, and the antenna 2 is coupled to the wireless communication module 260, so that the electronic device 200 can communicate with the network and other devices through wireless communication technology.

[0138] Antenna 1 and Antenna 2 are used to transmit and receive electromagnetic wave signals. Each antenna in electronic device 200 can be used to cover a single or multiple communication frequency bands. Different antennas can also be reused to improve antenna utilization. For example, antenna 1 can be reused as a diversity antenna for a wireless local area network. In other embodiments, the antennas can be used in conjunction with a tuning switch.

[0139] The mobile communication module 250 can provide wireless communication solutions, including 2G / 3G / 4G / 5G, for the electronic device 200. The mobile communication module 250 can include at least one filter, a switch, a power amplifier, a low-noise amplifier (LNA), etc. The mobile communication module 250 can receive electromagnetic waves from the antenna 1, filter and amplify the received electromagnetic waves, and transmit them to the modem processor for demodulation.

[0140] The mobile communication module 250 can also amplify the signal modulated by the modem processor and convert it into electromagnetic waves for radiation via the antenna 1. In some embodiments, at least some functional modules of the mobile communication module 250 can be set in the processor 210. In some embodiments, at least some functional modules of the mobile communication module 250 can be set in the same device as at least some modules of the processor 210.

[0141] The wireless communication module 260 can provide wireless communication solutions applied to the electronic device 200, including WLAN (such as wireless fidelity, Wi-Fi) network, Bluetooth (bluetooth, BT), global navigation satellite system (global navigation satellite system, GNSS), frequency modulation (frequency modulation, FM), nearfield communication technology (nearfield communication, NFC), infrared technology (infrared, IR), etc.

[0142] Wireless communication module 260 can be one or more devices that integrate at least one communication processing module. Wireless communication module 260 receives electromagnetic waves via antenna 2, frequency-modulates and filters the electromagnetic wave signals, and transmits the processed signals to processor 210. Wireless communication module 260 can also receive signals to be transmitted from processor 210, frequency-modulate and amplify them, and then convert them into electromagnetic waves for radiation via antenna 2.

[0143] Electronic device 200 implements display functionality through a GPU, display screen 294, and an application processor. A GPU is a microprocessor for image processing that connects display screen 294 and the application processor. The GPU is used to perform mathematical and geometric calculations for graphics rendering. Processor 210 may include one or more GPUs that execute program instructions to generate or modify display information.

[0144] The display screen 294 is used to display images, videos, etc. The display screen 294 includes a display panel.

[0145] Electronic device 200 can implement a camera function using an ISP, camera 293, a video codec, a GPU, a display 294, and an application processor. The ISP is used to process data fed back by camera 293. Camera 293 is used to capture still images or video. In some embodiments, electronic device 200 may include one or N cameras 293, where N is a positive integer greater than one.

[0146] The external memory interface 220 can be used to connect an external memory card, such as a Micro SD card, to expand the storage capacity of the electronic device 200. The external memory card communicates with the processor 210 via the external memory interface 220 to implement data storage functions. For example, files such as music and videos can be stored on the external memory card.

[0147] The hybrid memory 221 can be used to store computer executable program code, which includes instructions. The processor 210 executes various functional applications and data processing of the electronic device 200 by running the instructions stored in the hybrid memory 221. For example, in an embodiment of the present application, the processor 210 can execute the instructions stored in the hybrid memory 221, and the hybrid memory 221 can include a program storage area and a data storage area.

[0148] The program storage area may store an operating system, at least one application required for a function (such as a sound playback function, an image playback function, etc.), etc. The data storage area may store data created during the use of the electronic device 200 (such as audio data, a phone book, etc.), etc. In addition, the hybrid memory 221 may include a high-speed random access memory and a non-volatile memory, such as at least one disk storage device, a flash memory device, a universal flash storage (UFS), etc.

[0149] The electronic device 200 can implement audio functions such as music playback and recording through the audio module 270, the speaker 270A, the receiver 270B, the microphone 270C, the headphone jack 270D, and the application processor.

[0150] The buttons 290 include a power button, a volume button, etc. The button 290 can be a mechanical button. It can also be a touch button. The motor 291 can generate a vibration prompt. The motor 291 can be used for an incoming call vibration prompt, or for touch vibration feedback. The indicator 292 can be an indicator light, which can be used to indicate the charging status, power changes, messages, missed calls, notifications, etc. The SIM card interface 295 is used to connect the SIM card. The SIM card can be inserted into the SIM card interface 295, or pulled out from the SIM card interface 295 to achieve contact and separation with the electronic device 200. The electronic device 200 can support 1 or N SIM card interfaces, where N is a positive integer greater than 1. The SIM card interface 295 can support Nano SIM cards, Micro SIM cards, SIM cards, etc.

[0151] It is understandable that the mobile phone 100 may have more Figure 12 More or fewer components may be shown, two or more components may be combined, or the illustrations may have different configurations of components. Figure 12 The various components shown in the drawings may be implemented in hardware, software, or a combination of hardware and software, including one or more signal processing or application specific integrated circuits.

[0152] This embodiment further provides a computer storage medium, in which computer instructions are stored. When the computer instructions are executed on an electronic device, the electronic device executes the above-mentioned related method steps to implement the method in the above-mentioned embodiment.

[0153] This embodiment further provides a computer program product. When the computer program product is run on a computer, it enables the computer to execute the above-mentioned related steps to implement the method in the above-mentioned embodiment.

[0154] In addition, an embodiment of the present application also provides a device, which can specifically be a chip, component or module, and the device may include a connected processor and memory; wherein the memory is used to store computer-executable instructions, and when the device is running, the processor can execute the computer-executable instructions stored in the memory to enable the chip to execute the methods in the above-mentioned method embodiments.

[0155] Among them, the electronic device, computer storage medium, computer program product or chip provided in this embodiment is used to execute the corresponding method provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding method provided above, and will not be repeated here.

[0156] Through the description of the above implementation methods, technical personnel in the relevant field can understand that for the convenience and simplicity of description, only the division of the above-mentioned functional modules is used as an example. In actual applications, the above-mentioned functions can be distributed and completed by different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0157] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of modules or units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0158] Units described as separate components may or may not be physically separate, and components shown as units may be one physical unit or multiple physical units, that is, they may be located in one place or distributed in multiple places. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0159] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0160] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solution of the embodiment of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for enabling a device (which can be a single-chip microcomputer, chip, etc.) or a processor to execute all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a RAM, a magnetic disk or an optical disk.

[0161] The above content is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A hybrid memory, characterized in that: The hybrid memory includes a storage controller, a volatile storage medium, and a non-volatile storage medium; a physical address segment of the volatile storage medium is partially identical to a physical address segment of the non-volatile storage medium; The storage controller receives a read / write instruction from the processor, wherein the read / write instruction carries a first address; In a case where the first address corresponds to storage space of both the non-volatile storage medium and the volatile storage medium, if the main frequency of the processor is greater than the maximum read and write frequency of the non-volatile storage medium, the storage controller is configured to write data to the storage space of the volatile storage medium or read data from the storage space of the volatile storage medium; If the main frequency of the processor is less than or equal to the maximum read and write frequency of the non-volatile storage medium, the storage controller is used to write data into the storage space of the non-volatile storage medium or read data from the storage space of the non-volatile storage medium; In a case where the first address corresponds to a storage space of the non-volatile storage medium or the volatile storage medium, if the first address corresponds to a storage space of the volatile storage medium, the storage controller is configured to write data into the storage space of the volatile storage medium or read data from the storage space of the volatile storage medium; If the first address corresponds to the storage space of the non-volatile storage medium, the storage controller is configured to write data into the storage space of the non-volatile storage medium or read data from the storage space of the non-volatile storage medium.

2. The hybrid memory according to claim 1, wherein: If the main frequency of the processor is greater than the maximum read and write frequency of the non-volatile storage medium, the storage controller is further configured to write the data written into the storage space of the volatile storage medium into the storage space of the non-volatile storage medium; If the main frequency of the processor is less than or equal to the maximum read and write frequency of the non-volatile storage medium, the storage controller is further configured to write the data written into the storage space of the non-volatile storage medium into the storage space of the volatile storage medium.

3. The hybrid memory according to claim 1 or 2, characterized in that: The hybrid memory further includes at least one of a bus, a substrate, a packaging shell, and a bus interface; In which, the storage controller, the volatile storage medium and the non-volatile storage medium are integrated on the substrate, the volatile storage medium and the non-volatile storage medium are connected through the bus, the storage controller, the volatile storage medium and the non-volatile storage medium, the bus and the substrate are encapsulated inside the packaging shell, the packaging shell presents the bus interface to the outside, and the bus interface is used to connect to the processor.

4. The hybrid memory according to claim 1 or 2, characterized in that: The volatile storage medium includes a dynamic random access memory (DRAM), and the DRAM includes at least one of double data rate (DDR) memory, DDR2, DDR3, DDR4, high bandwidth memory (HBM), or 3D super DRAM. The non-volatile storage medium includes at least one of single-layer storage flash memory SLC-NAND, magnetic random access memory MRAM, resistive random access memory RRAM, phase change random access memory PCRAM, 3D-Xpoint storage medium or 3D-SLC NAND flash memory.

5. The hybrid memory according to claim 1 or 2, characterized in that: The hybrid memory is installed in an electronic device as a memory.

6. The hybrid memory according to claim 5, wherein: When the electronic device turns off the screen, the hybrid memory is powered off.

7. The hybrid memory according to claim 1 or 2, characterized in that: The non-volatile storage medium is used to store data of a preset type, and the preset type of data includes at least one of artificial intelligence AI data, models and training results for real-time training.

8. The hybrid memory according to claim 1 or 2, characterized in that: The first address is a physical address or a logical address; If the first address is a logical address, the storage controller is further configured to convert the logical address into a physical address.

9. A data reading and writing method, characterized in that: Applicable to a hybrid memory, the hybrid memory comprising a storage controller, a volatile storage medium, and a non-volatile storage medium; The physical address segment of the volatile storage medium is partially identical to the physical address segment of the non-volatile storage medium; the method comprising: The storage controller receives a read / write instruction from the processor, wherein the read / write instruction carries a first address; In a case where the first address corresponds to both the non-volatile storage medium and the storage space of the volatile storage medium, if the main frequency of the processor is greater than the maximum read and write frequency of the non-volatile storage medium, the storage controller writes data to the storage space of the volatile storage medium or reads data from the storage space of the volatile storage medium; if the main frequency of the processor is less than or equal to the maximum read and write frequency of the non-volatile storage medium, the storage controller writes data to the storage space of the non-volatile storage medium or reads data from the storage space of the non-volatile storage medium; In the case where the first address corresponds to the non-volatile storage medium or the storage space of the volatile storage medium, if the first address corresponds to the storage space of the volatile storage medium, the storage controller writes data to the storage space of the volatile storage medium or reads data from the storage space of the volatile storage medium; if the first address corresponds to the storage space of the non-volatile storage medium, the storage controller writes data to the storage space of the non-volatile storage medium or reads data from the storage space of the non-volatile storage medium.

10. The method according to claim 9, characterized in that If the main frequency of the processor is greater than the maximum read and write frequency of the non-volatile storage medium, the method further includes: The storage controller writes the data written into the storage space of the volatile storage medium into the storage space of the non-volatile storage medium; If the main frequency of the processor is less than or equal to the maximum read and write frequency of the non-volatile storage medium, the method further includes: The storage controller writes the data written into the storage space of the non-volatile storage medium into the storage space of the volatile storage medium.

11. The method according to claim 9 or 10, characterized in that The hybrid memory further includes at least one of a bus, a substrate, a packaging shell, and a bus interface; In which, the storage controller, the volatile storage medium and the non-volatile storage medium are integrated on the substrate, the volatile storage medium and the non-volatile storage medium are connected through the bus, the storage controller, the volatile storage medium and the non-volatile storage medium, the bus and the substrate are encapsulated inside the packaging shell, the packaging shell presents the bus interface to the outside, and the bus interface is used to connect to the processor.

12. The method according to claim 9 or 10, characterized in that The volatile storage medium includes a dynamic random access memory (DRAM), and the DRAM includes at least one of double data rate (DDR) memory, DDR2, DDR3, DDR4, high bandwidth memory (HBM), or 3D super DRAM. The non-volatile storage medium includes at least one of single-layer storage flash memory SLC-NAND, magnetic random access memory MRAM, resistive random access memory RRAM, phase change random access memory PCRAM, 3D-Xpoint storage medium or 3D-SLC NAND flash memory.

13. The method according to claim 9 or 10, characterized in that The hybrid memory is installed in an electronic device as a memory.

14. The method according to claim 13, wherein: When the electronic device turns off the screen, the hybrid memory is powered off.

15. The method according to claim 9 or 10, characterized in that The non-volatile storage medium is used to store data of a preset type, and the preset type of data includes at least one of artificial intelligence AI data, models and training results for real-time training.

16. The method according to claim 9 or 10, characterized in that The first address is a physical address or a logical address; If the first address is a logical address, the method further includes: The memory controller also converts the logical address into a physical address.

17. An electronic device, characterized in that: The invention comprises a processor, a hybrid memory and a bus, wherein the processor and the hybrid memory are interconnected via the bus, and the hybrid memory comprises a storage controller, a volatile storage medium and a non-volatile storage medium; The hybrid memory is used to store computer program code, which includes computer instructions; when the computer instructions are executed by the processor, the processor and the hybrid memory perform the method as described in any one of claims 9 to 16.

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