Electronic device and operating method thereof

Abstract

An electronic device and operating method thereof include a first memory controller, a second memory controller, and a memory access controller. The first memory controller stores configuration information for a predetermined memory, wherein the predetermined memory is defined as an execute-only memory. The second memory controller provides and configures an enable register based on the configuration information for the predetermined memory and generates an enable signal. The memory access controller accesses the first and second memory controllers based on the enable signal and the configuration information for the predetermined memory, and moves data from the predetermined memory to a predetermined memory space corresponding to the enable register.

Description

Technical Field

[0001] The present invention relates to an electronic device, and more particularly to an electronic device and an operating method thereof. Background Art

[0002] Execute-Only-Memory (XOM) is a firmware protection technology that protects critical code by defining execute-only memory areas. With execute-only memory protection, a portion of program memory space supports only program execution, making the memory contents inaccessible to any device.

[0003] Typically, execute-only memory resides in a block of non-volatile memory (NVM). When code is burned into this block, it is also recorded as having execute-only functionality. However, due to the slow data access speed of NVM, this affects data access and usability. Therefore, improving data access speed and usability is a key issue. Summary of the Invention

[0004] The present invention provides an electronic device and an operating method thereof, so that a volatile memory can have the function of executing only memory and can improve the access speed and use convenience of the memory.

[0005] The present invention provides an electronic device comprising a first memory controller, a second memory controller, and a memory access controller. The first memory controller stores configuration information for a predetermined memory, wherein the predetermined memory is defined as an execute-only memory. The second memory controller is coupled to the first memory controller and, based on the configuration information for the predetermined memory, provides and configures an enable register and generates an enable signal. The memory access controller is coupled to the first and second memory controllers and, based on the enable signal and the configuration information for the predetermined memory, accesses the first and second memory controllers to move data from the predetermined memory to a predetermined memory space corresponding to the enable register.

[0006] The present invention provides an operating method for an electronic device, comprising the following steps: storing, via a first memory controller, configuration information for a predetermined memory, wherein the predetermined memory is defined as an execute-only memory; providing and configuring, via a second memory controller, an enable register and generating an enable signal based on the configuration information for the predetermined memory; and accessing, via a memory access controller, the first memory controller and the second memory controller based on the enable signal and the configuration information for the predetermined memory, thereby moving data from the predetermined memory to a predetermined memory space corresponding to the enable register.

[0007] The electronic device and operating method described in the present invention utilize a first memory controller to store configuration information for a predetermined memory, wherein the predetermined memory is defined as execute-only memory. A second memory controller provides and configures an enable register based on the configuration information for the predetermined memory and generates an enable signal. A memory access controller accesses the first and second memory controllers based on the enable signal and the configuration information for the predetermined memory to move data from the predetermined memory to the predetermined memory space corresponding to the enable register. This allows the memory corresponding to the second memory controller to function as execute-only memory, improving memory access speed and ease of use. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 FIG. 1 is a schematic diagram of an electronic device according to an embodiment of the present invention.

[0009] Figure 2 FIG. 1 is a schematic diagram of setting information of a predetermined memory according to an embodiment of the present invention.

[0010] Figure 3 FIG. 4 is a flow chart of an operating method of an electronic device according to an embodiment of the present invention.

[0011] Figure 4 FIG. 4 is a flow chart of an operating method of an electronic device according to another embodiment of the present invention.

[0012] Figure Number:

[0013] 100: Electronic devices

[0014] 110: First memory controller

[0015] 120: Second memory controller

[0016] 121: Filter unit

[0017] 130: Memory access controller

[0018] 140: System bus

[0019] 150: Processing unit

[0020] 160: First memory

[0021] 170: Second memory

[0022] S302~S306, S402~S404: Steps DETAILED DESCRIPTION

[0023] In the various embodiments listed below, the same reference numerals will be used to represent the same or similar elements or components.

[0024] Figure 1 This is a schematic diagram of an electronic device according to an embodiment of the present invention. Figure 1 The electronic device 100 may include a first memory controller 110, a second memory controller 120, a memory access controller 130, and a system bus 140. In this embodiment, the system bus 140 may be an advanced high performance bus (AHB), an advanced eXtensible Interface (AXI), or a combination thereof, and the memory access controller 130 may be a direct memory access (DMA) device, but the embodiment of the present invention is not limited thereto.

[0025] The first memory controller 110 is coupled to the system bus 140 and can transmit data via the system bus 140. It also stores configuration information for a specific memory, where the specific memory is defined as an execute-only memory. In this embodiment, the execute-only memory only allows instruction fetches and disallows data access operations to protect critical code from network attacks or hacker intrusion.

[0026] In addition, the first memory controller 110 may be a non-volatile memory (NVM) controller. In addition, the setting information of the predetermined memory may include a virtual memory address (VMA), a load memory address (LMA), a size of the predetermined memory, a locked value, and an enable value, such as Figure 2 shown.

[0027] The virtual memory address is, for example, the base address where the code of a given memory is placed in the volatile memory, and the load memory address is, for example, the base address where the code of a given memory is placed in the non-volatile memory.

[0028] The lock value and the enable value are both, for example, 1-bit settings, but the present invention is not limited thereto. In this embodiment, the enable value indicates whether the setting of a given memory is valid. For example, when the enable value is a high logic level "1," the setting of the given memory is valid, i.e., the given memory has a read-only function. When the enable value is a low logic level "0," the setting of the given memory is invalid, i.e., the given memory can be read and written.

[0029] The lock value can be used to provide user development convenience. When the lock value is not set, the specified memory can still be accessed, debugged, etc.; conversely, when the lock value is set, the specified memory becomes active, that is, the characteristics of the specified memory (i.e., the execute-only memory characteristics) take effect. For example, when the lock value is set to a high logic level "0", it indicates that the specified memory can have a read-only function. When the lock value is set to a high logic level "1", it indicates that data access is denied to the specified memory, that is, the specified memory has no read and write functions.

[0030] The second memory controller 120 is coupled to the system bus 140 and is coupled to and communicates with the first memory controller 110 via the system bus 140. The second memory controller 120 can receive the setting information of the predetermined memory from the first memory controller 110, and provide and set the enable register according to the setting information of the predetermined memory, and generate an enable signal.

[0031] For example, the second memory controller 120 may provide and set an enable register based on the virtual memory address, the size of the predetermined memory, the lock value, and the enable value in the predetermined memory configuration information. After the enable register is set, the second memory controller 120 may generate an enable signal. In this embodiment, the second memory controller 120 may be a volatile memory (VM) controller, such as a random access memory (RAM) controller.

[0032] The memory access controller 130 is coupled to the system bus 140 and is coupled to and communicates with the first memory controller 110 and the second memory controller 120 via the system bus 140. The memory access controller 130 can receive the configuration information of a predetermined memory from the first memory controller 110 and the enable signal generated by the second memory controller 120. The memory access controller 130 can then access the first memory controller 110 and the second memory controller 120 based on the enable signal and the configuration information of the predetermined memory, and move data from the predetermined memory to the predetermined memory space corresponding to the enabled register.

[0033] Furthermore, the electronic device 100 may further include a processing unit 150 , a first memory 160 , and a second memory 170 .

[0034] The processing unit 150 is coupled to the system bus 140 and is coupled to and communicates with the first memory controller 110, the second memory controller 120, and the memory access controller 130 via the system bus 140. The processing unit 150 can perform access operations on the second memory controller 120, for example, controlling the second memory controller 120 to set an enable register. In this embodiment, the processing unit 150 is, for example, a microprocessor or a microcontroller, but the present invention is not limited thereto.

[0035] The first memory 160 is coupled to the first memory controller 110 and may include a designated memory for storing data in the designated memory, such as a plurality of codes. In this embodiment, the designated memory of the first memory 160 may correspond to a virtual memory address. Alternatively, the first memory 160 may be a non-volatile memory, such as a flash memory or a read-only memory (ROM), but the present invention is not limited thereto.

[0036] The second memory 170 is coupled to the second memory controller 120 and may include a designated memory space corresponding to the enable register. Specifically, after the second memory controller 120 completes setting the enable register according to the configuration information for the designated memory, the second memory 120 may provide the designated memory space corresponding to the enable register. This designated memory space is set to read-only mode, allowing only write operations by the memory access controller 130, thereby transferring and writing data from the designated memory of the first memory 160 to this designated memory space.

[0037] In this embodiment, the predetermined memory space of the second memory 170 may correspond to the load memory address. In addition, the second memory 170 may be a volatile memory, such as a random access memory, a dynamic random access memory (DRAM), a static random access memory (SRAM), a flip-flop array, etc., but the embodiment of the present invention is not limited thereto.

[0038] Furthermore, the second memory controller 120 further includes a filtering unit 121. The filtering unit 121 can filter access operations from the processing unit 150 based on the specified memory configuration information. Specifically, when the processing unit 150 issues an access operation request to the second memory controller 120, the filtering unit 121 can filter the access operation based on the specified memory configuration information and determine the type of access operation, such as an instruction fetch or data access. In one embodiment, the filtering unit 121 can also filter the actions of other active devices on the bus, blocking any data accesses.

[0039] In the overall operation of the electronic device 100, the processing unit 150 can drive the first memory controller 110 to configure the first memory 160 to include a predetermined memory and store data (e.g., code) in the predetermined memory. The first memory controller 110 can then store configuration data for the predetermined memory, including, for example, a virtual memory address (e.g., an address corresponding to the predetermined memory space), a load memory address (e.g., the address of the data stored in the predetermined memory), the size of the predetermined memory, a lock value, and an enable value. The first memory controller 110 can then transmit the configuration information for the predetermined memory to the second memory controller 120 and the memory access controller 130.

[0040] Next, the processing unit 150 can drive the second memory controller 120 so that the second memory controller 120 can provide and set the enable register according to the setting information of the established memory (such as the virtual memory address, the size of the established memory, the lock value and the enable value), so that the second memory 170 can provide the established memory space corresponding to the enable register, wherein the established memory space corresponds to the virtual memory address and the size of the established memory. In addition, the above-mentioned established memory space can be set to read-only mode and only allow the memory access controller 130 to perform write operations. In addition, the execution-only memory feature of the above-mentioned established memory space can be determined based on the lock value in the setting information of the established memory to determine whether it is effective. Furthermore, after the second memory controller 120 completes setting the enable register according to the setting information of the established memory, the second memory controller 120 can generate an enable signal to indicate that the enable register has been set.

[0041] Next, the processing unit 150 can drive the memory access controller 130 (i.e., the memory access controller 130 is externally triggered), allowing the memory access controller 130 to read the enable signal generated by the second memory controller 120. The memory access controller 130 then accesses the first memory controller 110 and the second memory controller 120 based on the enable signal and the configuration information of the predetermined memory (e.g., the virtual memory address, the load memory address, and the size of the predetermined memory), and moves the data of the predetermined memory to the predetermined memory space corresponding to the enable register. In other words, the data of the predetermined memory is read from the first memory 160 based on the load memory address, and then written to the predetermined memory space of the second memory 170 corresponding to the enable register based on the virtual memory address.

[0042] Then, in some embodiments, after the data migration is complete, the memory access controller 130 may generate a completion flag to indicate that the data in the designated memory of the first memory 110 has been completely migrated to the designated memory space of the second memory 170. In some embodiments, after the data migration is complete, the second memory controller 120 may generate a completion flag to indicate that the data in the designated memory of the first memory 110 has been completely migrated to the designated memory space of the second memory 170. In this way, the second memory 170 can function as an execution-only memory. The processing unit 150 may then read the completion flag from the memory access controller 130 or from the second memory controller 120. Furthermore, since the data access speed of the second memory 170 is higher than that of the first memory 160, the memory access speed can also be improved.

[0043] In the above embodiment, the number of times the memory access controller 130 accesses the first memory controller 110 and the second memory controller 120 to move the data of the predetermined memory to the predetermined memory space of the corresponding enable register is once, but the embodiment of the present invention is not limited to this. The memory access controller 130 can support multiple moves. In addition, the number of the predetermined memory, the enable register, and the predetermined memory space of the second memory 170 of the first memory 160 is one example, which is an implementation example of the present invention, but the embodiment of the present invention is not limited to this. The user can, according to their needs, set the number of the predetermined memory, the enable register, and the predetermined memory space of the second memory 170 of the first memory 160 to be multiple, and the same effect can be achieved.

[0044] When there are multiple predetermined memories, enable registers, and predetermined memory spaces, the operations among the memory access controller 130, the first memory controller 110, and the second memory controller 120 can refer to the description of the above embodiment and can achieve the same effect, so they are not repeated here.

[0045] In addition, the memory access controller 130 may further verify the data in the transferred predetermined memory, for example, by performing a checksum or a cyclic redundancy check (CRC) to verify the correctness of the data.

[0046] Based on the description of the above embodiments, an embodiment of the present invention provides an operating method of an electronic device. Figure 3 This is a flowchart according to one embodiment of the present invention. In step S302, a first memory controller stores configuration information for a predetermined memory, where the predetermined memory is defined as an execute-only memory. In step S304, a second memory controller provides and sets an enable register based on the configuration information for the predetermined memory, and generates an enable signal.

[0047] In step S306, the memory access controller accesses the first memory controller and the second memory controller based on the enable signal and the setting information of the predetermined memory, and moves the data of the predetermined memory to the predetermined memory space corresponding to the enable register. In this embodiment, the setting information of the predetermined memory may include a virtual memory address, a load memory address, a size of the predetermined memory, a lock value, and an enable value.

[0048] Figure 4 FIG. 1 is a flow chart of an operating method of an electronic device according to another embodiment of the present invention. In this embodiment, steps S302 to S306 are Figure 3 Steps S302 to S306 are the same or similar to those in Figure 3 The embodiments of the present invention are described in detail, so they will not be repeated here.

[0049] In step S402, a completion flag is generated by the memory access controller or the second memory controller. In step S404, the filtering unit of the second memory controller filters the access operation of the processing unit according to the setting information of the predetermined memory.

[0050] It is worth noting that Figure 3 and Figure 4 The order of the steps is for illustrative purposes only and is not intended to limit the order of the steps of the embodiments of the present invention. The order of the steps may be changed by the user as needed. Furthermore, additional steps may be added or fewer steps may be used without departing from the spirit and scope of the present invention.

[0051] In summary, the electronic device and operating method described herein utilize a first memory controller to store configuration information for a predetermined memory, wherein the predetermined memory is defined as execute-only memory. A second memory controller, based on the configuration information for the predetermined memory, provides and configures an enable register and generates an enable signal. A memory access controller, based on the enable signal and the configuration information for the predetermined memory, accesses the first and second memory controllers to move data from the predetermined memory to the predetermined memory space corresponding to the enable register. This allows the memory corresponding to the second memory controller to function as execute-only memory, improving memory access speed and ease of use.

[0052] Although the present invention is described above with reference to the embodiments, they are not intended to limit the scope of the invention. Any person skilled in the art may make some changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the claims.

Claims

1. An electronic device, characterized in that: include: A first memory controller stores setting information of a predetermined memory, wherein the predetermined memory is defined as an execution memory; a second memory controller coupled to the first memory controller, providing and setting an enable register according to the setting information of the predetermined memory, and generating an enable signal; as well as A memory access controller is coupled to the first memory controller and the second memory controller, and moves the data of the predetermined memory to a predetermined memory space corresponding to the enable register according to the enable signal and the setting information of the predetermined memory.

2. The electronic device according to claim 1, wherein Also includes: a processing unit coupled to the second memory controller to perform a driving operation on the second memory controller; a first memory coupled to the first memory controller, the first memory including the predetermined memory and storing data of the predetermined memory; as well as A second memory is coupled to the second memory controller, and includes a predetermined memory space corresponding to the enable register.

3. The electronic device according to claim 2, wherein: The second memory controller includes: A filtering unit filters the driving operation of the processing unit according to the setting information of the predetermined memory.

4. The electronic device according to claim 1, wherein: The setting information of the predetermined memory includes a virtual memory address, a load memory address, the size of the predetermined memory, a lock value and an enable value.

5. The electronic device according to claim 1, wherein: The memory access controller supports multiple transfers of data in the predetermined memory and verifies the transferred data in the predetermined memory.

6. The electronic device according to claim 1, wherein: After the data in the predetermined memory is moved to the corresponding enable register, the memory access controller or the second memory controller generates a completion flag.

7. A method for operating an electronic device, characterized in that: include: Storing setting information of a predetermined memory through a first memory controller, wherein the predetermined memory is defined as an execution memory; Providing and setting an enable register and generating an enable signal according to the setting information of the predetermined memory through a second memory controller; as well as A memory access controller is used to move the data of the predetermined memory to a predetermined memory space corresponding to the enable register according to the enable signal and the setting information of the predetermined memory.

8. The method for operating an electronic device according to claim 7, wherein: The setting information of the predetermined memory includes a virtual memory address, a load memory address, the size of the predetermined memory, a lock value and an enable value.

9. The method for operating an electronic device according to claim 7, wherein: Also includes: A filter unit of the second memory controller filters a driving operation of a processing unit according to the setting information of the predetermined memory.

10. The method for operating an electronic device according to claim 7, wherein: After the step of moving the data of the predetermined memory to the corresponding enabling register, the method further includes: A completion flag is generated by the memory access controller or the second memory controller.

Images