Volatile register to detect power loss

Abstract

The present application relates to volatile registers for detecting power loss. A memory system may receive a command to enter a first power mode, the first power mode having lower power consumption than a second power mode. The memory system may store data in a register associated with the memory system before entering the first power mode (e.g., a low power mode). The memory system may receive a command to exit the first power mode. The memory system may determine whether the data stored in the register includes one or more errors. The memory system may select a reset operation to be performed to exit the first power mode based on determining whether the data stored in the register includes one or more errors.

Description

[0001] Cross-references

[0002] This patent application claims priority to U.S. patent application No. 17 / 574,044, filed by He et al. on January 12, 2022, entitled “VOLATILE REGISTER TO DETECT POWER LOSS,” which claims the benefit of U.S. Provisional Patent Application No. 63 / 147,983, filed by He et al. on February 10, 2021, entitled “VOLATILE REGISTER TO DETECT POWER LOSS,” each of which is assigned to the present assignee and each of which is expressly incorporated herein by reference in its entirety.

[0003] The technical field relates to volatile registers to detect power loss. Background Art

[0004] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, etc. Information is stored by programming memory cells within the memory device to various states. For example, a binary memory cell can be programmed to one of two supported states that generally correspond to a logical 1 or a logical 0. In some examples, a single memory cell can support more than two possible states, and the memory cell can store any of the possible states. In order to access information stored by a memory device, a component can read or sense the state of one or more memory cells within the memory device. In order to store information, a component can write or program one or more memory cells within the memory device to a corresponding state.

[0005] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), 3-dimensional cross point memory (3D cross point), NOR and NAND memory devices, etc. Memory devices can be volatile or non-volatile. Unless periodically refreshed by an external power source, volatile memory cells (e.g., DRAM cells) may lose their programmed state over time. Non-volatile memory cells (e.g., NAND memory cells) can maintain their programmed state for a long period of time even in the absence of external power. Summary of the invention

[0006] A device is described. The device may include a memory system and a control circuit coupled to the memory system. The control circuit may be configured to cause the device to perform the following operations: receive a first command from a host system to enter a first power mode, the first power mode having lower power consumption than a second power mode; store data associated with the memory system in a register associated with the memory system; receive a second command from the host system to exit the first power mode based on storing the data; and perform a reset operation to exit the first power mode based on determining whether the data stored in the register contains one or more errors based on receiving the second command.

[0007] A non-transitory computer-readable medium is described. The non-transitory computer-readable medium may store code including instructions that, when executed by a processor of an electronic device, cause the electronic device to: receive a first command from a host system to enter a first power mode, the first power mode having lower power consumption than a second power mode; store data associated with a memory system in a register associated with the memory system; receive a second command from the host system to exit the first power mode based on storing the data; and perform a reset operation to exit the first power mode based on determining whether the data stored in the register includes one or more errors based on receiving the second command.

[0008] A method performed at a memory system is described. The method may include: receiving a first command from a host system to enter a first power mode, the first power mode having lower power consumption than a second power mode; storing data associated with the memory system in a register associated with the memory system; receiving a second command from the host system to exit the first power mode based on storing the data; and performing a reset operation to exit the first power mode based on determining whether the data stored in the register includes one or more errors based on receiving the second command. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 An example of a system supporting volatile register detection of power loss according to examples as disclosed herein is described.

[0010] Figure 2 An example of a state diagram supporting volatile register detection of power loss according to examples as disclosed herein is illustrated.

[0011] Figure 3 An example of a flow chart is illustrated to support volatile register detection of power loss according to examples as disclosed herein.

[0012] Figure 4 A block diagram of a memory system supporting volatile register detection of power loss according to examples as disclosed herein is shown.

[0013] Figure 5 A flow chart illustrating one or more methods of supporting volatile registers to detect power loss according to examples as disclosed herein is shown. DETAILED DESCRIPTION

[0014] The memory system may wear out over time and may not be usable as a memory system after so many access operations. For example, when the memory system is power cycled, a large number of reads and writes occur to move data from the cache to a more permanent data storage device. The access operations may reduce the life of the memory system. Therefore, repeatedly power cycling the memory system may reduce the life of the memory system. Some host systems, such as battery powered (such as mobile phones, tablet computers, or other mobile devices), may power cycle the memory system multiple times a day as part of entering and exiting a low power mode to save energy. Such operations may introduce additional access operations to move data to and from the cache as part of entering and exiting a low power mode, and thereby reduce the life of the memory system. Power cycling may also cause read disturbances to the internal data of the memory system, where the data may not be wear leveled, refreshed, or transferred to redundant blocks, thereby reducing the efficiency and startup time of performing operations and the overall performance of the memory system.

[0015] In some cases, the memory system may perform a reset operation to wake up from a lower power state. Some memory systems may support multiple types of reset operations (e.g., hard reset operations and soft reset operations) that may involve different amounts of data movement. For example, the memory system may perform a hard reset to accommodate a potential brown-out condition, interruption, or power loss during a power-off state. In such cases, the memory system may perform a hard reset without identifying whether a power loss event (e.g., brown-out condition, interruption, etc.) has occurred. The memory system may not know the state of the memory system or whether the memory system was affected by power loss while in the power-off state. Performing a hard reset without identifying the problem may increase the loss of the memory system loading internal data, thereby increasing the startup time and the latency to perform operations, reducing the efficiency of the memory system, and reducing the overall performance of the memory system.

[0016] Systems, devices, and techniques are described to improve the overall efficiency and operation of a memory system that undergoes power cycling and reset operations. In some memory systems, efficiency can be improved by storing data in registers of the memory system in response to receiving a command from a host system to enter a low power mode (e.g., a power off state, a sleep state, etc.). The memory system may receive a command to exit the low power mode and check the registers to determine whether the data contains one or more errors. The one or more errors may be the result of the memory system experiencing an undervoltage condition, an interruption, or a power loss during at least a portion of the low power mode. In such cases, the memory system may select a type of reset operation to be performed (e.g., a hard reset operation or a soft reset operation) based on whether the data contains one or more errors. For example, if the memory system determines that the data contains one or more errors, the memory system may perform a hard reset. In other examples, if the memory system determines that the data fails to contain one or more errors, the memory system may perform a soft reset.

[0017] Performing a soft reset instead of a hard reset can reduce the number of access operations implemented as part of the reset operation, thereby reducing the power consumption of the operation and reducing the amount of wear imposed on the memory system by the reset operation. In some examples, determining whether the data contains one or more errors before performing the reset operation can increase the reliability and security of the memory system, thereby allowing the memory system or other components to perform operations with improved speed, efficiency, and performance. In such cases, determining whether the memory system may be affected by a power loss event during a low power mode can reduce the wake-up time from the low power mode and increase the reliability of performing appropriate reset operations based on the condition of the memory system. In some cases, a soft reset operation can take less time than a hard reset operation, which can reduce the amount of time it takes to perform commands sent by the host system when exiting a low power mode.

[0018] First, in the reference Figure 1 The features of the present disclosure are described in the context of the described system. Figures 2 to 3 The features of the present disclosure are described in the context flow chart described. Figures 4 to 5 These and other features of the present disclosure are further illustrated and described with reference to the device diagrams and flow diagrams described involving volatile registers to detect power loss.

[0019] Figure 1 An example of a system 100 supporting volatile register detection of power loss according to examples as disclosed herein is illustrated. The system 100 includes a host system 105 coupled to a memory system 110.

[0020] The memory system 110 may be or include any device or set of devices, wherein the device or set of devices includes at least one memory array. For example, the memory system 110 may be or include a universal flash storage (UFS) device, an embedded multimedia controller (eMMC) device, a flash device, a universal serial bus (USB) flash device, a secure digital (SD) card, a solid-state drive (SSD), a hard disk drive (HDD), a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), or a non-volatile DIMM (NVDIMM), among other possibilities.

[0021] System 100 may be included in a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, drone, train, automobile, or other transportation vehicle), an Internet of Things (IoT) enabled device, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or any other computing device that includes a memory and a processing device.

[0022] The system 100 may include a host system 105 that may be coupled to a memory system 110. In some examples, this coupling may include an interface with a host system controller 106, which may be an example of a control component configured to cause the host system 105 to perform various operations according to examples as described herein. The host system 105 may include one or more devices, and in some cases, may include a processor chipset and a software stack executed by the processor chipset. For example, the host system 105 may include an application configured to communicate with the memory system 110 or a device therein. The processor chipset may include one or more cores, one or more caches (e.g., memory local to or included in the host system 105), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a peripheral component interconnect express (PCIe) controller, a serial advanced technology attachment (SATA) controller). The host system 105 may use the memory system 110, for example, to write data to the memory system 110 and read data from the memory system 110. Although in Figure 1 One memory system 110 is shown in FIG. 1 , but the host system 105 may be coupled to any number of memory systems 110 .

[0023] The host system 105 may be coupled to the memory system 110 via at least one physical host interface. In some cases, the host system 105 and the memory system 110 may be configured to communicate (e.g., exchange or otherwise communicate control, address, data, and other signals between the memory system 110 and the host system 105) via the physical host interface using an associated protocol. Examples of physical host interfaces may include, but are not limited to, SATA interfaces, UFS interfaces, eMMC interfaces, PCIe interfaces, USB interfaces, Fibre Channel interfaces, Small Computer System Interfaces (SCSI), Serial Attached SCSI (SAS), Double Data Rate (DDR) interfaces, DIMM interfaces (e.g., DDR-capable DIMM socket interfaces), Open NAND Flash Interface (ONFI), and Low Power Double Data Rate (LPDDR) interfaces. In some examples, one or more such interfaces may be included in or otherwise supported between a host system controller 106 of the host system 105 and a memory system controller 115 of the memory system 110. In some examples, the host system 105 may be coupled to the memory system 110 via a respective physical host interface for each memory device 130 included in the memory system 110, or via a respective physical host interface for each type of memory device 130 included in the memory system 110 (e.g., the host system controller 106 may be coupled to the memory system controller 115).

[0024] The memory system 110 may include a memory system controller 115 and one or more memory devices 130. The memory devices 130 may include one or more memory arrays of any type of memory cells (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). Figure 1 , two memory devices 130-a and 130-b are shown in the example of , but the memory system 110 may include any number of memory devices 130. Furthermore, if the memory system 110 includes more than one memory device 130, different memory devices 130 within the memory system 110 may include the same or different types of memory cells.

[0025] The memory system controller 115 may be coupled and communicated with the host system 105 (e.g., via a physical host interface), and may be an example of a control component configured to cause the memory system 110 to perform various operations according to examples as described herein. The memory system controller 115 may also be coupled and communicated with the memory devices 130 to perform operations that may generally be referred to as access operations at the memory devices 130, such as reading data, writing data, erasing data, or refreshing data, as well as other such operations. In some cases, the memory system controller 115 may receive commands from the host system 105 and communicate with one or more memory devices 130 to execute such commands (e.g., at a memory array within the one or more memory devices 130). For example, the memory system controller 115 may receive commands or operations from the host system 105, and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices 130. In some cases, the memory system controller 115 may exchange data with the host system 105 and one or more memory devices 130 (e.g., in response to or otherwise in conjunction with commands from the host system 105). For example, the memory system controller 115 may convert responses (e.g., data packets or other signals) associated with the memory devices 130 into corresponding signals for the host system 105.

[0026] The memory system controller 115 may be configured for other operations associated with the memory device 130. For example, the memory system controller 115 may perform or manage operations such as wear leveling operations, garbage collection operations, error control operations such as error detection operations or error correction operations, encryption operations, cache operations, media management operations, background refresh, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 130.

[0027] The memory system controller 115 may include hardware, such as one or more integrated circuits or discrete components, buffer memory, or a combination thereof. The hardware may include circuits with dedicated (e.g., hard-coded) logic to perform the operations attributed herein to the memory system controller 115. The memory system controller 115 may be or include a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry.

[0028] The memory system controller 115 may also include a local memory 120. In some cases, the local memory 120 may include a read-only memory (ROM) or other memory that may store operating codes (e.g., executable instructions) that may be executed by the memory system controller 115 to perform the functions attributed herein to the memory system controller 115. In some cases, the local memory 120 may additionally or alternatively include a static random access memory (SRAM) or other memory that may be used by the memory system controller 115 for, for example, internal storage or operations related to the functions attributed herein to the memory system controller 115. Additionally or alternatively, the local memory 120 may act as a cache for the memory system controller 115. For example, if a memory device 130 is read from or written to, the data may be stored in the local memory 120 and the data may be available in the local memory 120 for subsequent retrieval or manipulation (e.g., update) by the host system 105 according to a cache policy (e.g., with reduced latency relative to the memory device 130).

[0029] although Figure 1 The example of the memory system 110 in FIG. 1 has been illustrated as including a memory system controller 115, but in some cases, the memory system 110 may not include a memory system controller 115. For example, the memory system 110 may additionally or alternatively rely on an external controller (e.g., implemented by the host system 105) or one or more local controllers 135 that may be respectively internal to the memory device 130 to perform the functions attributed herein to the memory system controller 115. In general, one or more functions attributed herein to the memory system controller 115 may instead be performed by the host system 105, the local controller 135, or any combination thereof in some cases. In some cases, a memory device 130 that is at least partially managed by the memory system controller 115 may be referred to as a managed memory device. An example of a managed memory device is a managed NAND (MNAND) device.

[0030] The memory device 130 may include one or more arrays of non-volatile memory cells. For example, the memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase change memory (PCM), self-select memory, other chalcogenide-based memory, ferroelectric random access memory (RAM) (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin transfer torque (STT)-MRAM, conductive bridge RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), electrically erasable programmable ROM (EEPROM), or any combination thereof. Additionally or alternatively, the memory device 130 may include one or more arrays of volatile memory cells. For example, the memory device 130 may include RAM memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0031] In some examples, the memory devices 130 may include (e.g., on the same die or within the same package) a local controller 135 that may perform operations on one or more memory cells of the respective memory devices 130. The local controller 135 may operate in conjunction with the memory system controller 115, or may perform one or more functions attributed herein to the memory system controller 115. For example, Figure 1 As illustrated in FIG. 1 , memory device 130 - a may include a local controller 135 - a and memory device 130 - b may include a local controller 135 - b.

[0032] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include a memory die 160. For example, in some cases, memory device 130 may be a package that includes one or more die 160. In some examples, die 160 may be a piece of electronic grade semiconductor cut from a wafer (e.g., a silicon die cut from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a set of corresponding blocks 170, wherein each block 170 may include a set of corresponding pages 175, and each page 175 may include a set of memory cells.

[0033] In some cases, the NAND memory device 130 may include memory cells configured to store one bit of information each, which may be referred to as a single-level cell (SLC). Additionally or alternatively, the NAND memory device 130 may include memory cells configured to store multiple bits of information each, which may be referred to as a multi-level cell (MLC) if configured to store two bits of information each, a triple-level cell (TLC) if configured to store three bits of information each, a quad-level cell (QLC) if configured to store four bits of information each, or more generally, a multi-level memory cell. Relative to an SLC memory cell, a multi-level memory cell may provide greater storage density, but in some cases may involve narrower read or write tolerances or greater complexity for supporting circuitry.

[0034] In some cases, a plane 165 may refer to a group of blocks 170, and in some cases, parallel operations may be performed within different planes 165. For example, parallel operations may be performed on memory cells within different blocks 170, as long as the different blocks 170 are in different planes 165. In some cases, performing parallel operations in different planes 165 may be subject to one or more restrictions, such as performing the same operation on memory cells within different pages 175 that have the same page address within their respective planes 165 (e.g., related to command decode, page address decode circuitry, or other circuitry shared across planes 165).

[0035] In some cases, block 170 may include memory cells organized into rows (pages 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 may share (e.g., be coupled to) a common word line, and memory cells in the same string may share (e.g., be coupled to) a common digit line (which may alternatively be referred to as a bit line).

[0036] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first level of granularity (e.g., at a page level of granularity), but can be erased at a second level of granularity (e.g., at a block level of granularity). That is, a page 175 can be the smallest unit of memory (e.g., a collection of memory cells) that can be independently programmed or read (e.g., programmed or read simultaneously as part of a single programming or reading operation), and a block 170 can be the smallest unit of memory (e.g., a collection of memory cells) that can be independently erased (e.g., erased simultaneously as part of a single erase operation). Furthermore, in some cases, a NAND memory cell can be erased before it can be rewritten with new data. Thus, for example, in some cases, a used page 175 may not be updated until the entire block 170 including the page 175 has been erased.

[0037] The system 100 may include any number of non-transitory computer-readable media that support volatile registers detecting power loss. For example, the host system 105, the memory system controller 115, or the memory device 130 may include or otherwise have access to one or more non-transitory computer-readable media that store instructions (e.g., firmware) to perform the functions attributed herein to the host system 105, the memory system controller 115, or the memory device 130. For example, if executed by the host system 105 (e.g., by the host system controller 106), by the memory system controller 115, or by the memory device 130 (e.g., by the local controller 135), such instructions may cause the host system 105, the memory system controller 115, or the memory device 130 to perform one or more associated functions as described herein.

[0038] The memory system 110 may receive a command to enter a low power mode from the host system 105. In response to receiving the command, the memory system 110 may store data associated with the memory system 110 in a register associated with the memory system 110. The register may be an example of a NAND trim register. In some cases, the register may be a volatile register. The memory system 110 may receive different commands to exit the low power mode from the host system 105 based on the stored data. In some cases, the memory system 110 may determine whether the data stored in the register contains one or more errors based on receiving the command to exit the low power mode. The memory system 110 may select the type of reset operation to be performed to exit the low power mode based on determining whether the data contains one or more errors. As part of the low power mode, normal maintenance operations may not have been applied to various aspects of the memory system (e.g., RAM or cache of the memory system 110). The information in those memories may have been corrupted, especially when the length of time that the memory system 110 is in a low power state becomes longer. If there are errors in the registers, the memory system 110 may select a hard reset operation to reload information from the NAND into some of those memories to ensure that the memory system 110 operates correctly. However, if there are no errors in the data in the registers, the memory system 110 may perform a soft reset operation that does not transfer as much data from the NAND to the cache and thereby takes less time, uses less power, and performs fewer read and write operations. The reset operation may be an example of a hard reset operation or a soft reset operation.

[0039] In some cases, the memory system 110 may enable a voltage detector of the memory system 110 to set an undervoltage voltage level, detect an undervoltage voltage level on a voltage rail of the system 100, detect an amount of power loss during a low power mode, or a combination thereof. After the memory system enters a sleep mode (e.g., a low power mode), the memory system 110 may check a register. If the amount of power loss during the low power mode meets (e.g., exceeds) a threshold, the memory system 110 may determine that the data stored in the register is corrupted (e.g., contains one or more errors). In such cases, the memory system 110 may perform a hard reset operation. If the amount of power loss during the low power mode fails to meet (e.g., is less than or equal to) a threshold, the memory system 110 may determine that the data stored in the register is not corrupted (e.g., does not contain one or more errors). In such cases, the memory system 110 may perform a soft reset operation. Performing a hard reset or a soft reset based on the data stored in the register may improve the performance of the overall memory system and the reliability of the reset operation.

[0040] Figure 2 An example of a state diagram 200 supporting volatile register detection of power loss according to examples as disclosed herein is illustrated. The state diagram 200 may include a plurality of different states of a memory system. For example, the state diagram may include a power-on state 205, an active state 220, an idle state 225, a pre-sleep state 230, a sleep state 235, a pre-power-off state 240, a power-off state 245, and a pre-activation state 250.

[0041] The idle state 225 may be an example of a memory system avoiding performing an operation of the memory system (e.g., a read, write, or erase operation). The memory system may transition from the idle state 225 to the active state 220. The active state 220 may be an example of a memory system performing a read, write, or erase operation. The memory system may enter a pre-sleep state 230 after exiting the active state 220. The pre-sleep state 230 may be an example of a memory system preparing to enter a sleep state 235. In such a case, the memory system may begin to avoid performing operations or perform operations at a reduced speed. In some examples, the memory system may transition from the pre-sleep state 230 to the sleep state 235. The sleep state 235 may be an example of a low power state.

[0042] The memory system may receive a command to enter the pre-power-off state 240 after the sleep state 235. The pre-power-off state 240 may be an example of a state in which the memory system prepares for the power-off state 245. In such a case, the memory system may begin to shut down (e.g., turn off) a portion of the memory system. The power-off state 245 may be an example of a state in which the memory system enters a shutdown mode. The memory system may enter the pre-activation state 250 after the pre-sleep state 230, the sleep state 235, the pre-power-off state 240, or the power-off state 245. The memory system may enter the pre-activation state 250 before entering the activation state 220. The pre-activation state 250 may be an example of a state in which the memory system begins to turn on a portion of the memory system that may be powered off in the power-off state 245 or may be in a sleep mode in the sleep state 235.

[0043] The memory system may receive a command to exit the active state 220 and enter the power-on state 205. To enter the power-on state 205, the memory system may perform a reset operation. The reset operation may mitigate the effects of an interruption or power loss during the power-on state 205. In such cases, the power-on state 205 may be an example of a state in which the memory system may perform an operation (e.g., a reset operation). For example, the power-on state may include a hard reset 210 and a soft reset 215. The memory system may use the reset command to exit a low power mode. The low power mode may be an example of an idle state 225, a pre-sleep state 230, a sleep state 235, a pre-power-off state 240, and a power-off state 245. The low power mode may have lower power consumption than the power-on state 205.

[0044] The hard reset 210 may be an example of a hard reset operation (e.g., FDh), and the soft reset 215 may be an example of a soft reset operation (e.g., FFh). The hard reset 210 may be an example of an operation that resets one or more settings that are not affected by the soft reset 215. The one or more settings may be examples of a power-on initialization state, data retrieval, an erase operation, or a combination thereof. In some cases, the hard reset 210 may be used to place a specific die (e.g., a logical unit (LUN)) in a condition that may be similar to a power-on initialization state. In some cases, the hard reset 210 may initialize some or all parameters and configurations of the target LUN to default values. The hard reset 210 may include information that retrieves information used by the memory system to operate the memory system (e.g., fine-tuning parameters among other types of information) from a ROM or more permanent storage device (e.g., NAND). In such cases, the hard reset 210 may restore the memory system to an initial state by erasing information stored in one or more caches of the memory system.

[0045] Soft reset 215 may be an example of an operation that avoids resetting one or more settings reset by hard reset 210. In some cases, soft reset 215 may be used to place a target into a known condition (but not necessarily a default condition) or with respect to an ongoing command sequence, or both. For example, some information transferred from ROM or more permanent memory (e.g., NAND) to one or more caches may not be transferred as part of a soft reset, thereby reducing the number of access operations performed compared to a hard reset. Soft reset 215 may include powering on the memory system during power-on state 205.

[0046] The memory system may undergo multiple hardware resets and power mode (e.g., state) changes. In some cases, the memory system may experience power cycles performed on the memory system, which may wear out the memory system over time due to read operations and write operations performed as part of the power cycles. In some instances, each power cycle may cause the memory system to experience read disturbances to the memory system's internal data, which may be fixed in internal physical blocks. During power cycling, power may be repeatedly removed from the memory system, thereby limiting the life of the memory system. In other instances, the memory system may undergo a power-on procedure (e.g., exiting the power-off state 245). During the power-on procedure, the memory system may experience increased hysteresis and latency due to the amount of data to be loaded from the memory system. In some cases, the memory system may load data from the NAND during the power-on procedure. For example, the memory system may load boot code during the power-on procedure.

[0047] The memory system may experience an undervoltage event, interruption, or power loss during a low power mode. The memory system may restart during a hardware reset (e.g., hard reset 210) and may not know the state or power state of the memory system. In some cases, the memory system may not know whether the memory may be affected by power loss when in a low power state. In such cases, the memory system may perform a hard reset 210. The hard reset 210 may shorten the life of the memory system by increasing the wear of the memory system and increasing the waiting time after exiting the low power mode. The memory system may avoid performing a soft reset 215 based on the memory system not knowing the potential power loss or interruption during the low power mode. In such cases, the memory system may not blindly (e.g., without knowing the data stored in the registers of the memory system) perform a soft reset 215. Specifically, the memory system may be configured to blindly (e.g., in the case of an undervoltage condition) perform a hard reset 210 operation instead of performing a soft reset 215 operation.

[0048] Techniques for improving wake-up latency and performance of a memory system are described, thereby improving the overall efficiency and operation of the memory system. For example, a memory system may receive a command to enter a low power mode. The memory system may store data (e.g., dummy data) in a register of the memory system in response to receiving the command. The memory system may receive a command to exit the low power mode. As part of exiting the low power mode, the memory system may determine whether the data (e.g., dummy data) stored in the register includes one or more errors. Based on the determination, the memory system may select which type of reset operation (e.g., hard reset 210 or soft reset 215) to use to exit the low power mode. For example, the memory system may perform a hard reset 210 in response to determining that the data includes one or more errors. The memory system may perform a soft reset 215 in response to determining that the data fails to include one or more errors.

[0049] In some cases, the memory system may be unaware of a power loss or interruption that may have occurred during a low power mode. In such cases, the memory system may enable a voltage detector to detect an undervoltage voltage level on a voltage rail of the memory system. The memory system may check the voltage detector to determine whether the memory system has experienced a power loss event or interruption, and perform a reset operation based on the determination.

[0050] If the register contains unchanged data (e.g., the data does not contain an error) and the voltage detector is not tripped, the memory system may exit the low power mode by performing a soft reset 215. If the register contains changed data (e.g., contains an error), the memory system may exit the low power mode by performing a hard reset 210. If the voltage detector is tripped, the memory system may exit the low power mode by performing a hard reset 210. If the register contains changed data (e.g., contains an error) and the voltage detector is tripped, the memory system may exit the low power mode by performing a hard reset 210. In such cases, the memory system may detect a power-on event (e.g., after a power loss) compared to a pass-through power-on state 205 (e.g., the memory device has not experienced a power loss).

[0051] In some examples, storing data in registers and performing a reset operation based on determining whether the stored data includes one or more errors can increase the reliability and security of the memory system, thereby allowing the memory system or other components to perform operations with improved speed, efficiency, and performance. By performing a reset operation based on the data, the memory system can experience reduced wake-up latency (e.g., the duration between exiting a low power mode and entering the powered-on state 205) and increased endurance of the memory system.

[0052] Figure 3An example of a flowchart 300 for supporting volatile register detection of power loss according to an example disclosed herein is illustrated. The operations of the flowchart 300 may be implemented by any device or component thereof as described herein. For example, the operations of the flowchart 300 may be implemented by any device or component thereof as described herein. Figure 1 The described memory system performs. Alternative examples of the following may be implemented, where some steps are performed in a different order or not performed at all. Some steps may additionally include additional features not mentioned below. Flowchart 300 illustrates a technique for a memory system to detect power loss using volatile registers.

[0053] Aspects of flowchart 300 may be implemented by a controller as well as other components. Additionally or alternatively, aspects of flowchart 300 may be implemented as instructions stored in a memory (e.g., firmware stored in a memory coupled to a memory system). For example, the instructions, when executed by a controller (e.g., memory system controller 115), may cause the controller to perform the operations of flowchart 300.

[0054] At 305, a first command may be received. For example, the host system may transmit a first command to enter a first power mode, the first power mode having lower power consumption than a second power mode. In such cases, the memory system may receive the first command from the host system. The first power mode may be an example of a sleep mode, a low power mode, an idle mode, or a combination thereof. The second power mode may be an example of an active mode, a power-on mode, a reset mode, or a combination thereof.

[0055] At 310, data may be stored. For example, the memory system may store data associated with the memory system in a register associated with the memory system. In such cases, the memory system may set the data into a NAND volatile trim register. In some examples, the memory system may determine that a voltage of the memory system meets a threshold in response to storing the data. For example, the memory system may detect an undervoltage voltage level on a voltage rail. In some cases, the memory system may detect a power loss associated with the memory system based on identifying that the voltage meets or exceeds a voltage threshold. The undervoltage voltage may be associated with a reduction in electrical power availability or a limitation on the electrical power availability in at least a portion of the memory system.

[0056] In some examples, the memory system may store data in registers associated with the memory system after performing a soft reset operation. For example, the memory system may store data after waking up (e.g., entering an active state or a powered-on state) after a soft reset operation. In some cases, the value of the data stored in the register may be hard-coded in ROM code, read from an eFUSE, or stored as a value in the register.

[0057] At 315, a first power mode may be entered. For example, the memory system may enter the first power mode in response to storing data. The memory system may enter a sleep mode, a low power mode, an idle mode, or a combination thereof based on storing data in a register. In some cases, the memory system may store data in a register after initialization to enter the first power mode, before entering the first power mode, or when (e.g., simultaneously) the memory system enters the first power mode. In some examples, entering the first power mode may be based on determining that a voltage of the memory system satisfies a threshold.

[0058] At 320, a second command may be received. For example, the host system may transmit a second command to exit the first power mode. In such cases, the memory system may receive the second command from the host system to exit the first power mode based on the stored data. The second command may be an example of a command to enter a power-on mode, an activation mode, a reset mode, or a combination thereof. In some cases, the memory system may receive the second command based on (e.g., in response to) entering the first power mode. In such cases, the memory system may receive the second command after entering the first power mode.

[0059] At 325, a determination may be made whether the data includes errors. For example, the memory system may determine whether the data stored in the register includes one or more errors (e.g., corrupted data). In some examples, the memory system may determine that the data includes one or more errors based on receiving the second command. In some examples, the memory system may determine that the data fails to include one or more errors (e.g., the data may not be corrupted) based on receiving the second command.

[0060] At 330, a power parameter may be determined. For example, the memory system may determine that a power parameter of the memory system fails to meet a threshold based on determining that the data fails to include one or more errors. In some examples, the memory system may determine that a voltage detector of the memory system may not have tripped. For example, the memory system may determine that the memory system has not lost enough power to perform a hard reset operation.

[0061] In other examples, the memory system may determine that a power parameter of the memory system meets a threshold based on determining that the data includes one or more errors. In some examples, the memory system may determine that a voltage detector of the memory system may be tripped. For example, the memory system may determine that the memory system consumes enough power to perform a hard reset operation.

[0062] At 335, a soft reset operation may be performed. In some cases, the memory system may select which type of reset operation (e.g., a soft reset operation or a hard reset operation) to perform. For example, the memory system may perform a reset operation to exit the first power mode based on determining whether the data stored in the register includes one or more errors based on receiving the second command. In such cases, the memory system may perform a reset operation based on determining whether the data stored in the register is corrupted. The memory system may exit the first power mode in response to performing the reset operation. For example, the memory system may perform a soft reset operation to avoid resetting one or more settings reset by a hard refresh operation based on determining that a power parameter fails to meet a threshold. In other examples, the memory system may perform a soft reset operation based on determining that the data fails to include an error.

[0063] At 340, a hard reset operation may be performed. In some cases, the memory system may select which type of reset operation (e.g., a soft reset operation or a hard reset operation) to perform. For example, the memory system may perform a reset operation to exit the first power mode based on determining whether the data stored in the register contains one or more errors based on receiving the second command. In such cases, the memory system may perform a reset operation based on determining whether the data stored in the register is corrupted. The memory system may exit the first power mode in response to performing the reset operation. In some cases, the memory system may perform a hard reset operation to reset one or more settings that are not affected by the soft refresh in response to determining that the data contains one or more errors. The memory system may perform a hard reset operation based on determining that the power parameter meets a threshold.

[0064] To perform a hard reset operation, the memory system may retrieve information from the memory for one or more settings that have been reset. For example, the memory system may retrieve information from the ROM during a power-on mode. The memory system may include one or more power cycles. In some examples, the power-on mode may be an example of a reset mode. During the power-on mode, the memory system may operate at a slower speed than during the power-on mode. To achieve a faster operating condition, the memory system may perform a reset operation and enter the power-on mode.

[0065] Figure 4 An example of a block diagram 400 is shown for supporting volatile registers to detect power loss according to examples disclosed herein. The memory system 420 may be as described in reference Figures 1 to 34. The memory system 420 or its various components may be examples of means for performing various aspects of volatile registers to detect power loss, as described herein. For example, the memory system 420 may include a command receiver 425, a storage component 430, an exit component 435, an error detector 440, or any combination thereof. Each of these components may communicate with each other, directly or indirectly (e.g., via one or more buses).

[0066] The command receiver 425 may be configured as or otherwise support means for receiving a first command from a host system to enter a first power mode, the first power mode having lower power consumption than a second power mode. The storage component 430 may be configured as or otherwise support means for storing data associated with the memory system in a register associated with the memory system. The exit component 435 may be configured as or otherwise support means for receiving a second command from the host system to exit the first power mode based at least in part on the stored data. The error detector 440 may be configured as or otherwise support means for performing a reset operation to exit the first power mode based at least in part on determining whether the data stored in the register contains one or more errors based at least in part on receiving the second command.

[0067] In some examples, command receiver 425 may be configured or otherwise support means for entering a first power mode based at least in part on the stored data, wherein receiving the second command is based at least in part on entering the first power mode.

[0068] In some examples, storage component 430 may be configured as or otherwise support means for retrieving from memory information of one or more settings that have been reset.

[0069] In some examples, storage component 430 may be configured as or otherwise support means for determining that a voltage of the memory system satisfies a threshold based at least in part on storing data, wherein entering the first power mode is based at least in part on determining that a voltage of the memory system satisfies the threshold. In some examples, storing data associated with the memory system in a register associated with the memory system occurs after performing a soft reset operation to enter the second power mode from the first power.

[0070] In some examples, exit component 435 can be configured as or otherwise support means for exiting the first power mode based at least in part on performing a reset operation.

[0071] In some examples, error detector 440 may be configured or otherwise support means for determining that the data includes one or more errors based at least in part on receiving the second command, wherein the reset operation includes a hard reset operation that resets one or more settings not affected by the soft refresh operation.

[0072] In some examples, error detector 440 may be configured as or otherwise support means for determining that the data fails to include one or more errors based at least in part on receiving the second command, wherein performing the reset operation is based at least in part on determining that the data fails to include one or more errors.

[0073] In some examples, error detector 440 may be configured as or otherwise support means for determining that a power parameter of the memory system fails to satisfy a threshold based at least in part on determining that the data fails to include one or more errors, wherein the reset operation includes a soft reset operation that avoids resetting one or more settings reset by the hard refresh operation, and wherein performing the soft reset operation is based at least in part on determining that the power parameter fails to satisfy the threshold.

[0074] In some examples, error detector 440 may be configured as or otherwise support means for determining that a power parameter of the memory system satisfies a threshold based at least in part on determining that the data includes one or more errors, wherein the reset operation includes a hard reset operation that resets one or more settings not affected by the soft refresh operation.

[0075] Figure 5 A flowchart illustrating a method 500 for supporting volatile registers to detect power loss according to an example disclosed herein is shown. The operations of the method 500 may be implemented by a memory system or components thereof as described herein. For example, the operations of the method 500 may be implemented by a memory system or components thereof as described herein. Figures 1 to 4 The described memory system performs. In some examples, the memory system may execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the memory system may use dedicated hardware to perform aspects of the described functions.

[0076] Aspects of method 500 may be implemented by a controller as well as other components. Additionally or alternatively, aspects of method 500 may be implemented as instructions stored in a memory (e.g., firmware stored in a memory coupled to memory system 110). For example, the instructions, when executed by a controller (e.g., memory system controller 115), may cause the controller to perform the operations of method 500.

[0077] At 505, a first command may be received. The method may include receiving a first command from a host system to enter a first power mode, the first power mode having lower power consumption than a second power mode. The operations of 505 may be performed according to examples as disclosed herein. In some examples, aspects of the operations of 505 may be as described in reference to Figure 4 The command receiver 425 described performs.

[0078] At 510, data may be stored. The method may include storing data associated with the memory system in a register associated with the memory system. The operations of 510 may be performed according to examples as disclosed herein. In some examples, aspects of the operations of 510 may be described in detail in reference to Figure 4 The storage component 430 is described as performing.

[0079] At 515, a second command may be received. The method may include receiving a second command from the host system to exit the first power mode based at least in part on the stored data. The operations of 515 may be performed according to examples as disclosed herein. In some examples, aspects of the operations of 515 may be described as described in reference to Figure 4 The described exit component 435 executes.

[0080] At 520, a reset operation may be performed. The method may include performing a reset operation to exit the first power mode based at least in part on determining whether the data stored in the register includes one or more errors based at least in part on receiving the second command. The operation of 520 may be performed according to examples as disclosed herein. In some examples, aspects of the operation of 520 may be described by reference to Figure 4 The described error detector 440 performs.

[0081] In some examples, an apparatus as described herein may perform one or more methods, such as method 500. The apparatus may include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: receiving a first command from a host system to enter a first power mode having lower power consumption than a second power mode; storing data associated with a memory system in a register associated with the memory system; receiving a second command from the host system to exit the first power mode based at least in part on the stored data; and performing a reset operation to exit the first power mode based at least in part on determining whether the data stored in the register includes one or more errors based at least in part on receiving the second command.

[0082] Some instances of method 500 and the apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for performing the following operations: determining that the data includes one or more errors based at least in part on receiving the second command, wherein the reset operation includes a hard reset operation to reset one or more settings that may not be affected by the soft refresh operation.

[0083] In some examples of the method 500 and apparatus described herein, performing a hard reset operation may include operations, features, circuitry, logic, means, or instructions for retrieving information of one or more settings that may be reset from a memory.

[0084] Some instances of method 500 and the apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for performing the following operations: determining that the data fails to include one or more errors based at least in part on receiving the second command, wherein performing the reset operation may be based at least in part on determining that the data fails to include one or more errors.

[0085] Some examples of method 500 and apparatus described herein may further include operations, features, circuit systems, logic, means, or instructions for determining that a power parameter of the memory system fails to satisfy a threshold based at least in part on determining that the data fails to include one or more errors, wherein the reset operation includes a soft reset operation that avoids resetting one or more settings that may be reset by a hard refresh operation, and wherein performing the soft reset operation may be based at least in part on determining that the power parameter fails to satisfy the threshold.

[0086] For example, the apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for performing the following operations: performing a hard reset operation may be based at least in part on determining that the power parameter fails to meet the threshold. In some cases, the apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for performing the following operations: performing a soft reset operation may be based at least in part on determining that the power parameter meets the threshold.

[0087] Some examples of the method 500 and apparatus described herein may further include storing data associated with the memory system in a register associated with the memory system occurs after entering the second power mode from the first power mode using a soft reset operation.

[0088] Some examples of method 500 and apparatus described herein may further include operations, features, circuit systems, logic, means, or instructions for performing the following operations: determining that a power parameter of the memory system satisfies a threshold based at least in part on determining that the data includes one or more errors, wherein the reset operation includes a hard reset operation to reset one or more settings that may not be affected by the soft refresh operation.

[0089] Some examples of method 500 and devices described herein may further include operations, features, circuit systems, logic, means, or instructions for entering a first power mode based at least in part on storing data, wherein receiving the second command may be based at least in part on entering the first power mode.

[0090] Some instances of method 500 and the apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for performing the following operations: determining that a voltage of the memory system satisfies a threshold based at least in part on the stored data, wherein entering the first power mode may be based at least in part on determining that the voltage of the memory system satisfies the threshold.

[0091] Some examples of the method 500 and apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for exiting the first power mode based at least in part on performing a reset operation.

[0092] It should be noted that the methods described above describe possible implementations, and that the operations and steps may be rearranged or otherwise modified, and other implementations are possible. Furthermore, parts from two or more of the methods may be combined.

[0093] The information and signals described herein may be represented using any of a variety of different techniques and technologies. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some figures may illustrate a signal as a single signal; however, the signal may represent a bus of signals, where the bus may have various bit widths.

[0094] The terms "electronic communication," "conductive contact," "connection," and "coupling" may refer to a relationship between components that supports the flow of signals between the components. Components are considered to be in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) if there is any conductive path between the components that can support the flow of signals between the components at any time. At any given time, the conductive paths between components that are in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) may be open or closed based on the operation of the device that includes the connected components. The conductive paths between the connected components may be direct conductive paths between the components, or the conductive paths between the connected components may be indirect conductive paths that may include intermediate components such as switches, transistors, or other components. In some examples, the flow of signals between the connected components may be interrupted for a period of time, for example, using one or more intermediate components such as switches or transistors.

[0095] The term "coupled" refers to the condition of moving from an open circuit relationship between components, in which signals are currently unable to communicate between the components via a conductive path, to a closed circuit relationship between the components, in which signals are able to communicate between the components via the conductive path. If a component, such as a controller, couples other components together, then the component initiates a change that allows signals to flow between the other components via conductive paths that previously did not permit signal flow.

[0096] The terms "if", "when", "based on", or "based at least in part on" are used interchangeably. In some instances, the terms "if", "when", "based on", or "based at least in part on" are interchangeable if they are used to describe a connection between conditional actions, conditional processes, or parts of processes.

[0097] The term "responsive to" may refer to a condition or action that occurs at least in part (if not completely) as a result of a prior condition or action. For example, a first condition or action may be performed, and a second condition or action may occur at least in part as a result of the prior condition or action occurring (whether directly after the first condition or action or after one or more other intermediate conditions or actions occur after the first condition or action).

[0098] In addition, the term "directly in response to" or "directly in response to" may refer to a condition or action that occurs as a direct result of a previous condition or action. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of a previous condition or action occurring independently of whether other conditions or actions occur. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of a previous condition or action occurring, so that no other intermediate conditions or actions occur between an earlier condition or action and the second condition or action, or a limited number of one or more intermediate steps or actions occur between an earlier condition or action and the second condition or action. Unless otherwise specified, any condition or action described herein as being "based on", "at least partially based on" or "in response to" some other steps, actions, events or conditions and performed may be performed additionally or alternatively (e.g., in alternative instances) "directly in response to" or "directly in response to" such other conditions or actions.

[0099] The devices including memory arrays discussed herein may be formed on a semiconductor substrate, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some examples, the substrate is a semiconductor wafer. In some other examples, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of a semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate may be controlled by doping with various chemicals including, but not limited to, phosphorus, boron, or arsenic. Doping may be performed during the initial formation or growth of the substrate, by ion implantation, or by any other doping method.

[0100] The switch component or transistor discussed herein may represent a field effect transistor (FET) and include a three-terminal device including a source, a drain, and a gate. The terminals may be connected to other electronic components by conductive materials such as metals. The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., most of the carriers are electrons), the FET may be referred to as an n-type FET. If the channel is p-type (i.e., most of the carriers are holes), the FET may be referred to as a p-type FET. The channel may be terminated by an insulating gate oxide. Channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, may make the channel conductive. If a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned on" or "activated". If a voltage less than the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned off" or "deactivated".

[0101] The descriptions set forth herein in conjunction with the accompanying drawings describe example configurations and do not represent all examples that may be implemented or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration" and is not "preferable" or "advantageous" over other examples. The specific embodiments include specific details to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some cases, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0102] In the drawings, similar components or features may have the same reference label. In addition, various components of the same type may be distinguished by following the reference label with a dash and a second label that distinguishes between the similar components. If only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label, regardless of the second reference label.

[0103] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored as one or more instructions or codes on a computer-readable medium or transmitted via a computer-readable medium. Other examples and implementations are within the scope of the present disclosure and the appended claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hard wiring, or a combination of any of these. The features implementing the functions may also be physically located at various locations, including being distributed so that parts of the functions are implemented at different physical locations.

[0104] For example, the various illustrative blocks and components described in connection with the disclosure herein may be implemented or performed using a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device designed to perform the functions described herein, discrete gate or transistor logic, discrete hardware components, or any combination thereof. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. A processor may be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0105] As used herein (including in the claims), "or" as used in a list of items (e.g., a list of items preceded by a phrase such as "at least one of" or "one or more of") indicates an inclusive list, so that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). In addition, as used herein, the phrase "based on" should not be interpreted as referring to a closed set of conditions. For example, an exemplary step described as "based on condition A" can be based on both condition A and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on."

[0106] Computer-readable media include both non-transitory computer storage media and communication media, and the communication media include any media that facilitates the transfer of computer programs from one place to another. Non-transitory storage media can be any available media that can be accessed by a general or special-purpose computer. By way of example and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disk (CD) ROM or other optical disk storage device, magnetic disk storage device or other magnetic storage device, or can be used to carry or store the desired program code components in the form of instructions or data structures and can be accessed by a general or special-purpose computer or a general or special-purpose processor. Any other non-transitory media. In addition, any connection can be appropriately referred to as computer-readable media. For example, if a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technologies such as infrared, radio and microwaves are used to transmit software from a website, server or other remote source, then coaxial cable, fiber optic cable, twisted pair, DSL or wireless technologies such as infrared, radio and microwaves are included in the definition of media. As used herein, disk and disc include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0107] The description herein is provided to enable one skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to one skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but is given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A device comprising: Memory system; as well as A control circuit is coupled to the memory system and configured to cause the device to perform the following operations: receiving a first command from a host system to enter a first power mode, the first power mode having lower power consumption than a second power mode; storing data associated with the memory system in a register associated with the memory system; receiving a second command from the host system to exit the first power mode based at least in part on storing the data; as well as A reset operation is performed to exit the first power mode based at least in part on determining whether the data stored in the register includes one or more errors based on receiving the second command.

2. The device according to claim 1, wherein the control circuit is further configured to cause the device to perform the following operations: The data is determined to include the one or more errors based at least in part on receiving the second command, wherein the reset operation comprises a hard reset operation that resets one or more settings not affected by a soft refresh operation.

3. The device according to claim 2, wherein: To perform the hard reset operation, the control circuit is configured to cause the device to perform the following operations: Information of the one or more settings that have been reset is retrieved from memory.

4. The device of claim 1, wherein the control circuit is further configured to cause the device to: A determination is made based at least in part on receiving the second command that the data fails to include the one or more errors, wherein performing the reset operation is based at least in part on determining that the data fails to include the one or more errors.

5. The device of claim 4, wherein the control circuit is further configured to cause the device to: A determination is made based at least in part on a determination that the data fails to include the one or more errors that a power parameter of the memory system fails to satisfy a threshold, wherein the reset operation comprises a soft reset operation that avoids resetting one or more settings reset by a hard refresh operation, and wherein performing the soft reset operation is based at least in part on a determination that the power parameter fails to satisfy the threshold.

6. The apparatus of claim 5, wherein storing the data associated with the memory system in the register associated with the memory system occurs after entering the second power mode from the first power mode using the soft reset operation.

7. The device of claim 1, wherein the control circuit is further configured to cause the device to: A power parameter of the memory system is determined to satisfy a threshold based at least in part on determining that the data includes the one or more errors, wherein the reset operation comprises a hard reset operation that resets one or more settings not affected by a soft refresh operation.

8. The device of claim 1, wherein the control circuit is further configured to cause the device to: The first power mode is entered based at least in part on storing the data, wherein receiving the second command is based at least in part on entering the first power mode.

9. The device of claim 8, wherein the control circuit is further configured to cause the device to: A determination is made based at least in part on storing the data that a voltage of the memory system satisfies a threshold, wherein entering the first power mode is based at least in part on determining that the voltage of the memory system satisfies the threshold.

10. The device of claim 1, wherein the control circuit is further configured to cause the device to: The first power mode is exited based at least in part on performing the reset operation.

11. A non-transitory computer-readable medium storing code, the code comprising instructions executable by a processor of an electronic device, causing the electronic device to perform the following operations: receiving a first command from a host system to enter a first power mode, the first power mode having lower power consumption than a second power mode; storing data associated with the memory system in a register associated with the memory system; receiving a second command from the host system to exit the first power mode based at least in part on storing the data; as well as A reset operation is performed to exit the first power mode based at least in part on determining whether the data stored in the register includes one or more errors based on receiving the second command.

12. The non-transitory computer-readable medium of claim 11, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: The data is determined to include the one or more errors based at least in part on receiving the second command, wherein the reset operation comprises a hard reset operation that resets one or more settings not affected by a soft refresh operation.

13. The non-transitory computer-readable medium of claim 12, wherein the instructions, when executed by the processor of the electronic device, cause the electronic device to perform the hard reset operation, and when executed by the processor of the electronic device, cause the electronic device to perform the following operations: Information of the one or more settings that have been reset is retrieved from memory.

14. The non-transitory computer-readable medium of claim 11, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: A determination is made based at least in part on receiving the second command that the data fails to include the one or more errors, wherein performing the reset operation is based at least in part on determining that the data fails to include the one or more errors.

15. The non-transitory computer-readable medium of claim 14, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: A determination is made based at least in part on a determination that the data fails to include the one or more errors that a power parameter of the memory system fails to satisfy a threshold, wherein the reset operation comprises a soft reset operation that avoids resetting one or more settings reset by a hard refresh operation, and wherein performing the soft reset operation is based at least in part on a determination that the power parameter fails to satisfy the threshold.

16. The non-transitory computer-readable medium of claim 15, wherein storing the data associated with the memory system in the register associated with the memory system occurs after entering the second power mode from the first power mode using the soft reset operation.

17. The non-transitory computer-readable medium of claim 11, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: A power parameter of the memory system is determined to satisfy a threshold based at least in part on determining that the data includes the one or more errors, wherein the reset operation comprises a hard reset operation that resets one or more settings not affected by a soft refresh operation.

18. The non-transitory computer-readable medium of claim 11, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: The first power mode is entered based at least in part on storing the data, wherein receiving the second command is based at least in part on entering the first power mode.

19. The non-transitory computer-readable medium of claim 18, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: A determination is made based at least in part on storing the data that a voltage of the memory system satisfies a threshold, wherein entering the first power mode is based at least in part on determining that the voltage of the memory system satisfies the threshold.

20. The non-transitory computer-readable medium of claim 11, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: The first power mode is exited based at least in part on performing the reset operation.

21. A method performed at a memory system, comprising: receiving a first command from a host system to enter a first power mode, the first power mode having lower power consumption than a second power mode; storing data associated with the memory system in a register associated with the memory system; receiving a second command from the host system to exit the first power mode based at least in part on storing the data; as well as A reset operation is performed to exit the first power mode based at least in part on determining whether the data stored in the register includes one or more errors based on receiving the second command.

22. The method of claim 21, further comprising: The data is determined to include the one or more errors based at least in part on receiving the second command, wherein the reset operation comprises a hard reset operation that resets one or more settings not affected by a soft refresh operation.

23. The method of claim 22, wherein performing the hard reset operation comprises: Information of the one or more settings that have been reset is retrieved from memory.

24. The method of claim 21, further comprising: A determination is made based at least in part on receiving the second command that the data fails to include the one or more errors, wherein performing the reset operation is based at least in part on determining that the data fails to include the one or more errors.

25. The method of claim 24, further comprising: A determination is made based at least in part on a determination that the data fails to include the one or more errors that a power parameter of the memory system fails to satisfy a threshold, wherein the reset operation comprises a soft reset operation that avoids resetting one or more settings reset by a hard refresh operation, and wherein performing the soft reset operation is based at least in part on a determination that the power parameter fails to satisfy the threshold.

Images