Method for interrupt routing control and interrupt controller for system on chip

Abstract

The application relates to the technical field of integrated chips, and discloses an interrupt routing control method for a system-level chip, which comprises the following steps: synchronously processing interrupt request signals sent by a plurality of interrupt sources to obtain a plurality of interrupt request signals in a to-be-processed state; determining a target interrupt request signal which needs to be processed in a next clock cycle from the plurality of interrupt request signals in the to-be-processed state; acquiring routing information of an interrupt source corresponding to the target interrupt request signal according to a preset interrupt chain table; and determining a target central processing unit and a target pin corresponding to the interrupt source sending the target interrupt request signal according to the routing information of the interrupt source. The application can meet the demand of a working scene in which the number of CPU interrupt pins is limited, and realizes dynamic configuration of high-concurrency interrupt routing. The application further discloses an interrupt controller.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated chip, for example, to an interrupt routing control method and an interrupt controller for a system on chip. BACKGROUND

[0002] At present, in the development process of a system on chip (SOC) of a vehicle level, a large number of peripherals are used, and a SOC chip often needs to undertake a large number of control and calculation tasks. In the process of executing a program instruction stream, when some unexpected situation occurs, the execution of the current program needs to be suspended, and a new program instruction stream needs to be processed, and after the processing is completed, the original suspended program instruction stream continues to run. The mechanism is an interrupt. The interrupt generated by the peripheral interrupt source is first sent to an interrupt controller, and then the interrupt controller transfers it to a central processing unit (CPU). The traditional interrupt routing mode is that one interrupt source corresponds to one CPU interrupt pin.

[0003] In the process of implementing the embodiments of the present disclosure, it is found that at least the following problems exist in the related art:

[0004] In the existing scheme, even if a multi-core architecture is used, the number of interrupt pins of the CPU is difficult to meet the needs of the peripheral interrupt source. When the number of concurrent interrupts is too large, the traditional mechanical routing mode of one interrupt source corresponding to one CPU interrupt pin is no longer applicable. SUMMARY

[0005] To provide a basic understanding of some aspects of the disclosed embodiments, the following brief summary is given. The summary is not an overall description of the application, nor is it intended to identify key / important elements or delineate the scope of the embodiments. It is only a prelude to the detailed description below.

[0006] The embodiments of the present disclosure provide an interrupt routing control method and an interrupt controller for a system on chip, which can meet the needs of a working scenario in which the number of CPU interrupt pins is tight, and realize dynamic configuration of high-concurrency interrupt routing.

[0007] In some embodiments, the interrupt routing control method comprises:

[0008] Synchronizing processing of interrupt request signals sent by a plurality of interrupt sources to obtain a plurality of interrupt request signals in a plurality of to-be-processed states;

[0009] Among the plurality of interrupt request signals in the plurality of to-be-processed states, a target interrupt request signal that needs to be processed at a next clock cycle is determined;

[0010] According to a preset interrupt linked list, routing information of an interrupt source corresponding to the target interrupt request signal is obtained.

[0011] Based on the routing information of the interrupt source, the target CPU and target pin corresponding to the interrupt source that issued the target interrupt request signal are determined.

[0012] In some embodiments, the interrupt controller includes:

[0013] The interrupt synchronization module is configured to synchronously process interrupt request signals from multiple interrupt sources to obtain multiple interrupt request signals in a pending state.

[0014] The interrupt arbitration module is configured to determine, from among the multiple interrupt request signals in pending states, the target interrupt request signal that needs to be processed in the next clock cycle.

[0015] The interrupt list module is configured to obtain the routing information of the interrupt source corresponding to the target interrupt request signal according to the preset interrupt list;

[0016] The interrupt mapping module is configured to determine the target CPU and target pin corresponding to the interrupt source that issued the target interrupt request signal, based on the routing information of the interrupt source.

[0017] Optionally, the interrupt arbitration module includes four arbitration sub-units, and the interrupt linked list module includes four linked list sub-units;

[0018] The arbitration subunit is configured to receive interrupt request signals of at least one pending state from interrupt sources within a fixed number range, and to determine, from the interrupt request signals of at least one pending state, the target interrupt request signal that needs to be processed in the next clock cycle.

[0019] The linked list subunit is configured to correspond to the arbitration subunit, so as to obtain the routing information of the interrupt source corresponding to the target interrupt request signal determined by each arbitration subunit according to the preset interrupt linked list.

[0020] Optionally, the interrupt controller further includes:

[0021] The first counter module is configured to count the number of interrupts for each interrupt source. When an interrupt request signal issued by any interrupt source is processed synchronously to form an interrupt request signal in a pending state, the number of interrupts for the interrupt source is incremented by 1. After the interrupt request signal in the pending state of any interrupt source is determined to be a target interrupt request signal, the number of interrupts for the interrupt source is decremented by 1.

[0022] The second counter module is configured to count the number of successful interrupt arbitrations for each interrupt source. After an interrupt request signal in the pending state of any interrupt source is determined to be a target interrupt request signal, the number of successful interrupt arbitrations for the interrupt source corresponding to the interrupt source is incremented by 1. After any target interrupt request signal is responded to by the central processing unit, the number of successful interrupt arbitrations for the interrupt source that issued the target interrupt request signal is decremented by 1.

[0023] Optionally, the interrupt controller further includes:

[0024] The third counter module is configured to count the number of times each pin of the central processing unit needs to be adjusted to a high position. When the central processing unit processes an interrupt event corresponding to any pin, the number of times the pin needs to be adjusted to a high position is reduced by 1. When the number of times the pin needs to be adjusted to a high position is 0, the pin is adjusted to a low position.

[0025] The interrupt routing control method and interrupt controller for system-on-a-chip provided in this disclosure can achieve the following technical effects:

[0026] By identifying the target interrupt request signal that needs to be processed in the next clock cycle from the multiple interrupt request signals in the pending state, interrupt requests are processed sequentially. The routing information of the interrupt source corresponding to the target interrupt request signal is obtained through the interrupt chain, realizing dynamic routing configuration between the interrupt source and the central processing unit. That is, multiple interrupt sources correspond to one pin of the central processing unit, which has the routing control function to handle high concurrency of multiple channels. It can meet the working scenario of handling a large number of peripheral interrupt sources when the number of interrupt pins of the central processing unit is insufficient.

[0027] The above general description and the description below are exemplary and illustrative only and are not intended to limit this application. Attached Figure Description

[0028] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations and drawings do not constitute a limitation on the embodiments. Elements having the same reference numerals in the drawings are shown as similar elements. The drawings are not to be scaled. And wherein:

[0029] Figure 1 This is a schematic diagram of an interrupt routing control method for a system-on-a-chip provided in this application;

[0030] Figure 2 This is a schematic diagram of another interrupt routing control method for system-on-a-chip provided in this application;

[0031] Figure 3 This is a schematic diagram of another interrupt routing control method for system-on-a-chip provided in this application;

[0032] Figure 4 This is a schematic diagram of another interrupt routing control method for system-on-a-chip provided in this application;

[0033] Figure 5 This is a schematic diagram of another interrupt routing control method for system-on-a-chip provided in this application;

[0034] Figure 6 This is a schematic diagram of another interrupt routing control method for system-on-a-chip provided in this application;

[0035] Figure 7 This is a schematic diagram of the architecture of an interrupt controller according to this application;

[0036] Figure 8 This is a schematic diagram of another interrupt controller architecture provided in this application;

[0037] Figure 9 This is an application illustration provided in this application. Detailed Implementation

[0038] To provide a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for illustrative purposes only and are not intended to limit the embodiments of this disclosure. In the following technical description, for ease of explanation, several details are used to provide a full understanding of the disclosed embodiments. However, one or more embodiments may still be implemented without these details. In other cases, well-known structures and interrupt controllers may be simplified in their depiction to simplify the drawings.

[0039] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this disclosure described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0040] Unless otherwise stated, the term "multiple" means two or more.

[0041] In this embodiment of the disclosure, the character " / " indicates that the objects before and after it are in an "or" relationship. For example, A / B means: A or B.

[0042] The term "and / or" describes an association between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or A and B.

[0043] The term "correspondence" can refer to an association or binding relationship. The correspondence between A and B means that there is an association or binding relationship between A and B.

[0044] Combination Figure 1 As shown, this disclosure provides an interrupt routing control method for a system-on-a-chip, including:

[0045] Step 101: Synchronize the interrupt request signals issued by multiple interrupt sources to obtain multiple interrupt request signals in pending status.

[0046] In the embodiments of this application, the interrupt controller of this application receives interrupt request signals from multiple peripheral interrupt sources, and outputs interrupt request signals in a pending state after synchronization processing. For example, a certain vehicle track-grade SOC chip has a total of 1024 interrupt sources (interrupt source 0 to interrupt source 1023). In extreme cases, it can issue 1024 interrupt request signals in parallel. Therefore, it is necessary to synchronize the 1024 interrupt sources and send out 1024 interrupt request signals.

[0047] Step 102: Among the multiple interrupt request signals in the pending state, determine the target interrupt request signal that needs to be processed in the next clock cycle.

[0048] In the embodiments of this application, the interrupt controller arbitrates multiple interrupt request signals in pending states and determines the target interrupt request signal that needs to be prioritized for processing in the next clock cycle based on the arbitration result.

[0049] Step 103: Obtain the routing information of the interrupt source corresponding to the target interrupt request signal according to the preset interrupt chain list.

[0050] In the embodiments of this application, an interrupt list needs to be pre-set before each dynamic configuration. The interrupt list is implemented based on static random-access memory (SRAM). The interrupt controller of this application obtains the routing information of the interrupt source corresponding to the target interrupt request signal by querying the interrupt list.

[0051] Step 104: Based on the routing information of the interrupt source, determine the target CPU and target pin corresponding to the interrupt source that issued the target interrupt request signal.

[0052] In the embodiments of this application, the interrupt controller of this application obtains the mapping relationship between the interrupt source that sends the target interrupt request signal and the central processing unit and its pins based on the routing information of the interrupt source, and then processes the interrupt event of the interrupt source through the central processing unit and its pins.

[0053] The interrupt routing control method for system-on-a-chip provided in this disclosure determines the target interrupt request signal to be processed in the next clock cycle from the multiple interrupt request signals in the pending state. This enables sequential processing of interrupt requests and obtains the routing information of the interrupt source corresponding to the target interrupt request signal through the interrupt list. This achieves dynamic routing configuration between the interrupt source and the central processing unit, where multiple interrupt sources correspond to one pin of the central processing unit. It has routing control function for handling high concurrency of multiple channels and can meet the working scenario of handling a large number of peripheral interrupt sources when the number of interrupt pins of the central processing unit is insufficient.

[0054] Optionally, combined Figure 2 As shown, determining at least one target interrupt request signal that needs to be processed in the next clock cycle from among the multiple interrupt request signals in pending states includes:

[0055] Step 201: Through the polling scheduling mechanism, determine the interrupt request signal with the highest priority pending status in the next clock cycle, and use it as the target interrupt request signal for successful arbitration.

[0056] In the embodiments of this application, the interrupt controller of this application adopts a round-robin scheduling mechanism to process the interrupt request signals of the pending state. The interrupt request signals are scheduled in a cyclic manner. In each clock cycle, the interrupt request signal of the pending state with the highest priority is arbitrated as the target interrupt request signal for successful arbitration, until the interrupt request signal of each pending state can be successfully arbitrated as the target interrupt request signal.

[0057] Step 202: Generate and output the arbitration enable signal and the number of the interrupt source that issued the target interrupt request signal.

[0058] In the embodiments of this application, after successful arbitration, the interrupt controller of this application simultaneously outputs an arbitration enable signal indicating successful arbitration, as well as the number of the interrupt source that issued the target interrupt request signal, such as any one of the numbers from interrupt source 0 to interrupt source 1023 mentioned above.

[0059] Step 203: Adjust the priority of the target interrupt request signal to the lowest level.

[0060] In the embodiments of this application, in order to ensure that the interrupt request signal of each pending state has an equal chance of being successfully arbitrated, the interrupt controller of this application needs to adjust the priority of the target interrupt request signal in subsequent arbitration to the lowest. The polling scheduling mechanism is mainly implemented through combinational logic circuits. As long as there is an interrupt request signal of a pending state, an arbitration result will be generated in the next clock cycle.

[0061] Thus, this application adopts an arbitration strategy with a polling scheduling mechanism to address the situation of multiple concurrent interrupts, thereby ensuring that each interrupt request signal can be responded to equally.

[0062] Optionally, combined Figure 3 As shown, the step of obtaining the routing information of the interrupt source corresponding to the target interrupt request signal according to the preset interrupt list includes:

[0063] Step 301: Based on the number of the interrupt source that issued the target interrupt request signal, obtain the memory structure corresponding to the number in the interrupt list.

[0064] Step 302: Obtain the mapping relationship between interrupt sources and central processing unit stored in the memory structure, as well as the mapping relationship between interrupt sources and interrupt pins.

[0065] In the embodiments of this application, the interrupt chain list includes multiple memory structures, i.e., nodes. The memory structures store the routing information of the interrupt source, i.e., the target central processing unit of the interrupt source and the target pin of the target central processing unit. Furthermore, the interrupt chain list involves error checking and correction code (ECC) verification. ECC verification is an encoding method used to detect and correct errors that occur during transmission to a certain extent, thereby ensuring the accuracy and reliability of the routing information of the interrupt request signal.

[0066] Optionally, combined Figure 4 As shown, determining the target CPU and target pin corresponding to the interrupt source that issued the target interrupt request signal based on the routing information of the interrupt source includes:

[0067] Step 401: Determine the target CPU corresponding to the target interrupt request signal based on the mapping relationship between the interrupt source and the CPU.

[0068] Step 402: Determine the target interrupt pin corresponding to the target interrupt request signal based on the mapping relationship between the interrupt source and the interrupt pin.

[0069] Step 403: Adjust the target interrupt pin of the target central processing unit to a high bit in response to the target interrupt request signal.

[0070] In the embodiments of this application, the interrupt controller determines the target CPU and target interrupt pin corresponding to the target interrupt request signal based on the mapping relationship between the interrupt source and the CPU, and adjusts the target interrupt pin of the target CPU to a high bit to respond to the target interrupt request signal, thereby realizing a dynamic mapping relationship between the CPU and the interrupt source.

[0071] Optionally, combined Figure 5 As shown, the method further includes:

[0072] Step 501: Count the number of interrupts that occurred and the number of successful interrupt arbitrations for each interrupt source.

[0073] Step 502: When an interrupt request signal from any interrupt source is processed synchronously to form an interrupt request signal in a pending state, the interrupt occurrence count corresponding to the interrupt source is increased by 1.

[0074] Step 503: After the interrupt request signal in the pending state of any interrupt source is determined to be the target interrupt request signal, the interrupt occurrence count corresponding to the interrupt source is reduced by 1, and the interrupt arbitration success count corresponding to the interrupt source is increased by 1.

[0075] Step 504: After any target interrupt request signal is responded to by the central processing unit, the number of successful interrupt arbitrations corresponding to the interrupt source that issued the target interrupt request signal is reduced by 1.

[0076] In the embodiments of this application, after the interrupt request signal of the peripheral interrupt source is synchronously processed to form an interrupt request signal in a pending state, the interrupt request signal in the pending state is simultaneously latched into the interrupt source status register for query by the central processing unit. Furthermore, the number of interrupt occurrences and the number of successful interrupt arbitrations for each interrupt source are counted. When an interrupt request signal from any interrupt source is synchronously processed to form an interrupt request signal in a pending state, the interrupt occurrence count corresponding to that interrupt source is incremented by 1. After an interrupt request signal in a pending state from any interrupt source is determined to be a target interrupt request signal, the interrupt occurrence count corresponding to that interrupt source is decremented by 1, and the number of successful interrupt arbitrations corresponding to that interrupt source is incremented by 1. After any target interrupt request signal is responded to by the central processing unit, the number of successful interrupt arbitrations corresponding to the interrupt source that issued the target interrupt request signal is decremented by 1. When the interrupt occurrence count corresponding to an interrupt source is 0, it indicates that there is no new interrupt request signal, and all interrupt request signals in the pending state are adjusted to low bits.

[0077] In this way, by designing a counter at the peripheral interrupt source end to record the number of interrupts initiated by each interrupt source and the number of times the arbitration succeeds, interrupt request signals that are not responded to in time can be protected for interrupt buffering.

[0078] Optionally, combined Figure 6 As shown, the method further includes:

[0079] Step 601: Count the number of times each pin of the central processing unit needs to be adjusted to a high bit.

[0080] Step 602: When the central processing unit processes an interrupt event corresponding to any pin, reduce the number of times the pin needs to be adjusted to a high bit by 1.

[0081] Step 603: If the number of times any pin needs to be adjusted to a high position is 0, adjust the pin to a low position.

[0082] In the embodiments of this application, each pin of the central processing unit is also designed with a counting function to accumulate the number of interrupt sources that need to be pulled high. For example, in the case of a four-way mapping relationship, the maximum number of interrupt pins that can be successfully activated at the same time is four. At the same time, each time the central processing unit enters the interrupt service function corresponding to the pin, the count is decremented by 1, indicating that an interrupt has been successfully processed. When the count is 0, the circuit adjusts the interrupt pin to a low bit, indicating that all interrupt requests have been processed.

[0083] It should be noted that although sufficient depth is set for the counter's counting function, subsequent interrupt request signals will still be lost when interrupt sources send interrupt request signals continuously and rapidly and the central processing unit cannot process them in time. In this case, the overflow flag can be adjusted to a high bit to alert the maintenance personnel.

[0084] In this way, by designing a counting function at the interrupt pin of the central processing unit, the number of times the interrupt pin of the central processing unit is set to record is recorded, so as to perform interrupt buffering and protect interrupt signals that are not responded to in time.

[0085] Furthermore, the actual interrupt handling process for application software is as follows: after entering the interrupt service function, the "clear interrupt pin" instruction is first issued, then all interrupt source status registers mapped to the interrupt pin are queried to obtain which interrupt sources triggered this interrupt, and finally the corresponding interrupt source handling function is entered in sequence. In the handling function, the "clear interrupt status register" instruction is issued until all interrupt source interrupt events are processed.

[0086] Combination Figure 7 As shown, this disclosure provides an interrupt controller, including:

[0087] The interrupt synchronization module 701 is configured to synchronize interrupt request signals from multiple interrupt sources to obtain multiple interrupt request signals in a pending state.

[0088] Interrupt arbitration module 702 is configured to determine, from the multiple pending interrupt request signals, the target interrupt request signal that needs to be processed in the next clock cycle.

[0089] The interrupt list module 703 is configured to obtain the routing information of the interrupt source corresponding to the target interrupt request signal according to the preset interrupt list;

[0090] Interrupt mapping module 704 is configured to determine the target CPU and target pin corresponding to the interrupt source that issued the target interrupt request signal based on the routing information of the interrupt source.

[0091] Optionally, the interrupt arbitration module includes four arbitration sub-units, and the interrupt linked list module includes four linked list sub-units;

[0092] The arbitration subunit is configured to receive interrupt request signals of at least one pending state from interrupt sources within a fixed number range, and to determine, from the interrupt request signals of at least one pending state, the target interrupt request signal that needs to be processed in the next clock cycle.

[0093] The linked list subunit is configured to correspond to the arbitration subunit, so as to obtain the routing information of the interrupt source corresponding to the target interrupt request signal determined by each arbitration subunit according to the preset interrupt linked list.

[0094] In order to avoid excessively long interrupt response time in extreme cases (such as when all interrupt sources issue interrupt signals simultaneously) and to balance the circuit implementation area, this application divides the interrupt sources into four groups. Similarly, the interrupt arbitration module and the interrupt list module are also composed of four functionally identical sub-units. Thus, the interrupt sources are grouped and arbitrated through the design concept of "serial-parallel conversion". The interrupt list is used to implement the design mechanism of dynamic configuration of interrupt routes by pre-setting routing information, so as to balance the circuit area and interrupt response time.

[0095] Optionally, the interrupt controller further includes:

[0096] The first counter module is configured to count the number of interrupts for each interrupt source. When an interrupt request signal issued by any interrupt source is processed synchronously to form an interrupt request signal in a pending state, the number of interrupts for the interrupt source is incremented by 1. After the interrupt request signal in the pending state of any interrupt source is determined to be a target interrupt request signal, the number of interrupts for the interrupt source is decremented by 1.

[0097] The second counter module is configured to count the number of successful interrupt arbitrations for each interrupt source. After an interrupt request signal in the pending state of any interrupt source is determined to be a target interrupt request signal, the number of successful interrupt arbitrations for the interrupt source corresponding to the interrupt source is incremented by 1. After any target interrupt request signal is responded to by the central processing unit, the number of successful interrupt arbitrations for the interrupt source that issued the target interrupt request signal is decremented by 1.

[0098] Optionally, the interrupt controller further includes:

[0099] The third counter module is configured to count the number of times each pin of the central processing unit needs to be adjusted to a high position. When the central processing unit processes an interrupt event corresponding to any pin, the number of times the pin needs to be adjusted to a high position is reduced by 1. When the number of times the pin needs to be adjusted to a high position is 0, the pin is adjusted to a low position.

[0100] Thus, this application establishes an interrupt buffer and overflow mechanism by designing the interrupt source terminal and the CPU interrupt pin terminal counter, thereby protecting the interrupt source under high concurrency interrupt conditions.

[0101] In one practical application of this application, combined with Figure 8 As shown, a certain automotive-grade SOC chip adopts a multi-core architecture with 5 CPUs (each CPU has 256 interrupt pins) and 1024 interrupt sources. Each CPU is required to be able to handle 1024 interrupts, and each interrupt source is allowed to initiate interrupts simultaneously. When the CPU is handling an interrupt, it is necessary to protect other unresponsive interrupts.

[0102] To this end, the interrupt controller of this application is configured with four arbitration subunits and four linked list subunits to respond to and process 1024 interrupt sources, for example, combined with Figure 9 As shown, both interrupt sources are mapped to interrupt pin 10 of CPU 3, and these two interrupt sources are assigned to groups 0 and 1 respectively. In the 4th clock cycle, both interrupt signals are successfully arbitrated simultaneously, the CPU counter is incremented by 2, the corresponding interrupt pin is set high, and the program enters the interrupt service function. In the 7th clock cycle, one interrupt signal is successfully arbitrated, and the CPU counter is incremented by 1. In the 14th, 17th, and 20th clock cycles, the interrupt events triggered by the interrupt sources are processed sequentially, the counter is cleared to zero in the 21st clock cycle, and then the CPU interrupt pin is adjusted to a low bit, exiting the interrupt service function.

[0103] This disclosure provides a storage medium storing computer-executable instructions configured to execute the above-described interrupt routing control method for a system-on-a-chip.

[0104] The aforementioned storage medium can be a transient computer-readable storage medium or a non-transitory computer-readable storage medium.

[0105] The technical solutions of this disclosure can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes one or more instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in this disclosure. The aforementioned storage medium can be a non-transitory storage medium, including: a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and other media capable of storing program code; it can also be a transient storage medium.

[0106] The foregoing description and accompanying drawings fully illustrate embodiments of this disclosure to enable those skilled in the art to practice them. Other embodiments may include structural, logical, electrical, procedural, and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the order of operation may vary. Parts and features of some embodiments may be included in or replace parts and features of other embodiments. Moreover, the terminology used in this application is for describing embodiments only and is not intended to limit the claims. As used in the description of embodiments and claims, the singular forms “a,” “an,” and “the” are intended to equally include the plural forms unless the context clearly indicates otherwise. Similarly, the term “and / or” as used in this application means including one or more of the associated listed items and all possible combinations thereof. Additionally, when used in this application, the term "comprise" and its variations "comprises" and / or "comprising" refer to the presence of stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. Without further limitations, an element defined by the phrase "comprises a..." does not exclude the presence of other identical elements in the process, method, or apparatus that includes said element. In this document, each embodiment may focus on the differences from other embodiments, and similar or identical parts between embodiments can be referred to mutually. For methods, products, etc., disclosed in the embodiments, if they correspond to the method section disclosed in the embodiments, the relevant parts can be referred to the description of the method section.

[0107] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of this disclosure. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, interrupt controllers, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0108] The methods and products disclosed in the embodiments herein (including but not limited to interrupt controllers, devices, etc.) can be implemented in other ways. For example, the interrupt controller embodiments described above are merely illustrative. For instance, the division of units may be merely a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces. The indirect coupling or communication connection of the interrupt controller or unit may be electrical, mechanical, or other forms. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to implement this embodiment according to actual needs. Furthermore, the functional units in the embodiments of this disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0109] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than that shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. In the descriptions corresponding to the flowcharts and block diagrams in the accompanying drawings, the operations or steps corresponding to different blocks may also occur in a different order than disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. Each block in a block diagram and / or flowchart, and combinations of blocks in a block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

Claims

1. An interrupt routing control method for system-on-a-chip, characterized in that, include: The interrupt request signals from multiple interrupt sources are processed synchronously to obtain multiple interrupt request signals in pending status. Among the multiple interrupt request signals in pending states, a target interrupt request signal that needs to be processed in the next clock cycle is determined; wherein, determining at least one target interrupt request signal that needs to be processed in the next clock cycle from the multiple interrupt request signals in pending states includes: determining the interrupt request signal of the pending state with the highest priority in the next clock cycle through a polling scheduling mechanism, as the target interrupt request signal for successful arbitration; generating and outputting an arbitration enable signal and the number of the interrupt source that issued the target interrupt request signal; and adjusting the priority of the target interrupt request signal to the lowest level; According to a preset interrupt list, the routing information of the interrupt source corresponding to the target interrupt request signal is obtained; specifically, this includes: obtaining the memory structure corresponding to the number of the interrupt source that issued the target interrupt request signal in the interrupt list; obtaining the mapping relationship between the interrupt source and the central processing unit, and the mapping relationship between the interrupt source and the interrupt pin stored in the memory structure; Based on the routing information of the interrupt source, the target CPU and target pin corresponding to the interrupt source that issued the target interrupt request signal are determined.

2. The interruption routing control method according to claim 1, characterized in that, The step of determining the target CPU and target pin corresponding to the interrupt source that issued the target interrupt request signal based on the routing information of the interrupt source includes: Based on the mapping relationship between interrupt sources and central processing units, determine the target central processing unit corresponding to the target interrupt request signal; Based on the mapping relationship between interrupt sources and interrupt pins, determine the target interrupt pin corresponding to the target interrupt request signal; Adjust the target interrupt pin of the target central processing unit to a high bit in response to the target interrupt request signal.

3. The interruption routing control method according to any one of claims 1 to 2, characterized in that, Also includes: Count the number of interrupts that occurred and the number of successful interrupt arbitrations for each interrupt source; When an interrupt request signal from any interrupt source is processed synchronously to form an interrupt request signal in a pending state, the interrupt occurrence count corresponding to the interrupt source is increased by 1. Once an interrupt request signal in the pending state of any interrupt source is determined to be the target interrupt request signal, the interrupt occurrence count corresponding to the interrupt source is reduced by 1, and the interrupt arbitration success count corresponding to the interrupt source is increased by 1. After any target interrupt request signal is responded to by the central processing unit, the number of successful interrupt arbitrations corresponding to the interrupt source that issued the target interrupt request signal is reduced by 1.

4. The interruption routing control method according to any one of claims 1 to 2, characterized in that, Also includes: Count the number of times each pin of the central processing unit needs to be adjusted to a high bit; When the central processing unit processes an interrupt event corresponding to any pin, the number of times the pin needs to be adjusted to a high bit is reduced by 1; If the number of times a pin needs to be adjusted to a high position is 0, adjust the pin to a low position.

5. An interrupt controller, characterized in that, include: The interrupt synchronization module is configured to synchronously process interrupt request signals from multiple interrupt sources to obtain multiple interrupt request signals in a pending state. An interrupt arbitration module is configured to determine, from among the interrupt request signals in the plurality of pending states, a target interrupt request signal that needs to be processed in the next clock cycle; wherein, determining at least one target interrupt request signal that needs to be processed in the next clock cycle from among the interrupt request signals in the plurality of pending states includes: determining, through a polling scheduling mechanism, the interrupt request signal of the pending state with the highest priority in the next clock cycle as the target interrupt request signal for successful arbitration; generating and outputting an arbitration enable signal and the number of the interrupt source that issued the target interrupt request signal; and adjusting the priority of the target interrupt request signal to the lowest level; The interrupt list module is configured to obtain routing information of the interrupt source corresponding to the target interrupt request signal according to a preset interrupt list; specifically, it includes: obtaining the memory structure corresponding to the number of the interrupt source that issued the target interrupt request signal in the interrupt list; obtaining the mapping relationship between the interrupt source and the central processing unit, and the mapping relationship between the interrupt source and the interrupt pin stored in the memory structure; The interrupt mapping module is configured to determine the target CPU and target pin corresponding to the interrupt source that issued the target interrupt request signal, based on the routing information of the interrupt source.

6. The interrupt controller according to claim 5, characterized in that, The interruption arbitration module includes four arbitration sub-units, and the interruption linked list module includes four linked list sub-units. The arbitration subunit is configured to receive interrupt request signals of at least one pending state from interrupt sources within a fixed number range, and to determine, from the interrupt request signals of at least one pending state, the target interrupt request signal that needs to be processed in the next clock cycle. The linked list subunit is configured to correspond to the arbitration subunit, so as to obtain the routing information of the interrupt source corresponding to the target interrupt request signal determined by each arbitration subunit according to the preset interrupt linked list.

7. The interrupt controller according to claim 5, characterized in that, Also includes: The first counter module is configured to count the number of interrupts for each interrupt source. When an interrupt request signal issued by any interrupt source is processed synchronously to form an interrupt request signal in a pending state, the number of interrupts for the interrupt source is incremented by 1. After the interrupt request signal in the pending state of any interrupt source is determined to be a target interrupt request signal, the number of interrupts for the interrupt source is decremented by 1. The second counter module is configured to count the number of successful interrupt arbitrations for each interrupt source. After an interrupt request signal in the pending state of any interrupt source is determined to be a target interrupt request signal, the number of successful interrupt arbitrations for the interrupt source corresponding to the interrupt source is incremented by 1. After any target interrupt request signal is responded to by the central processing unit, the number of successful interrupt arbitrations for the interrupt source that issued the target interrupt request signal is decremented by 1.

8. The interrupt controller according to claim 5, characterized in that, Also includes: The third counter module is configured to count the number of times each pin of the central processing unit needs to be adjusted to a high position. When the central processing unit processes an interrupt event corresponding to any pin, the number of times the pin needs to be adjusted to a high position is reduced by 1. When the number of times the pin needs to be adjusted to a high position is 0, the pin is adjusted to a low position.

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