Bad Block Scanning Circuit and Scanning Method Set in Solid State Drive Main Control Chip

Abstract

The present invention discloses a bad block scanning circuit and a scanning method disposed in a solid-state drive main control chip, relating to the technical field of solid-state drives. The solid-state drive includes a flash memory module and a main control chip. The main control chip includes a scanning circuit and a CPU. The flash memory module includes a plurality of factory blocks, and the factory blocks contain factory bad blocks. The scanning circuit includes: an interface module connected to the flash memory module for reading the factory blocks in the flash memory module; an NHOST module connected to the interface module and the CPU respectively for identifying factory bad blocks from the factory blocks read by the interface module and transmitting the factory bad block information to the CPU; an MSM module for controlling the working process of the scanning circuit, the CPU is connected to the MSM module, and the MSM module is connected to the NHOST module and the interface module respectively. In the process of card opening and mass production, the step of bad block scanning can be omitted in this application, shortening the time and improving the production efficiency.

Description

Technical Field

[0001] The present invention relates to the technical field of solid-state drives, and particularly to a bad block scanning circuit and a scanning method disposed in a main control chip of a solid-state drive. Background Art

[0002] In the production of SSD solid-state drives, the prior art has dedicated steps for bad block scanning, either a separate step for scanning factory bad blocks or a sub-step of the "card opening" process. After the bad blocks are scanned, they are written into the internal storage space of the SSD.

[0003] These steps consume corresponding production time or test time, and correspondingly reduce the production efficiency / test efficiency of the SSD solid-state drive. Summary of the Invention

[0004] An object of the present invention is to provide a bad block scanning circuit and a scanning method disposed in a main control chip of a solid-state drive to improve production efficiency.

[0005] To solve the above technical problems, the present invention adopts the following technical solutions:

[0006] A first aspect of an embodiment of the present invention provides a bad block scanning circuit disposed in a main control chip of a solid-state drive. The solid-state drive includes a flash memory module and a main control chip. The main control chip includes a scanning circuit and a CPU. The flash memory module includes a plurality of factory blocks, and the factory blocks contain factory bad blocks. The scanning circuit includes: an interface module connected to the flash memory module for reading the factory blocks in the flash memory module; an NHOST module respectively connected to the interface module and the CPU for identifying factory bad blocks from the factory blocks read from the interface module and transmitting the factory bad block information to the CPU; an MSM module for controlling the working process of the scanning circuit, the CPU is connected to the MSM module, and the MSM module is respectively connected to the NHOST module and the interface module.

[0007] In some embodiments, the scanning circuit further includes a UARTC module and a serial bus for communicating with the CPU. The CPU is connected to the UARTC module through the serial bus, and the UARTC module is respectively connected to the NHOST module and the MSM module.

[0008] In some embodiments, the scanning circuit further includes a RAM module for caching data, and the RAM module is disposed between the NHOST module and the UARTC module.

[0009] In some embodiments, the main control chip further includes a NANDC module for switching with the interface module, and the NANDC module is respectively connected to the flash memory module and the serial bus.

[0010] In some embodiments, the scanning circuit further includes a MUX module for switching the interface module and the NANDC module. The MUX module is respectively connected to the interface module, the NANDC module, and the flash memory module, and the MSM module is connected to control the MUX module.

[0011] A second aspect of the embodiments of the present invention provides a scanning method. The factory bad blocks include first-class factory bad blocks and second-class factory bad blocks. The scanning method includes: the interface module reads the factory blocks in the flash memory module and identifies the second-class factory bad blocks; the NHOST module identifies the first-class factory bad blocks from the factory blocks and transmits the information of the first-class factory bad blocks and the second-class factory bad blocks to the CPU; the CPU enters the information of the first-class factory bad blocks and the second-class factory bad blocks into the memory; when the CPU performs read / write / erase operations on the factory blocks, it avoids the bad blocks that are the same as the information in the memory.

[0012] In some embodiments, before the interface module reads the factory blocks in the flash memory module and identifies the second-class factory bad blocks, the method further includes: after the solid-state drive is installed and powered on for the first time, the solid-state drive automatically performs the above scanning method to scan the bad blocks of the solid-state drive.

[0013] In some embodiments, before the solid-state drive is installed and powered on for the first time and the solid-state drive automatically performs the above scanning method to scan the bad blocks of the solid-state drive, the method further includes: making different bad block marks for the first-class factory bad blocks and the second-class factory bad blocks respectively, so as to facilitate the NHOST module and the interface module to identify the first-class factory bad blocks and the second-class factory bad blocks.

[0014] In some embodiments, after the CPU avoids the bad blocks that are the same as the information in the memory when performing read / write / erase operations on the factory blocks, the method further includes: when performing read / write / erase operations on the flash memory module, if the write or erase operation fails, it is determined as a newly added bad block, and the information of the newly added bad block is transmitted to the CPU; the CPU enters the information of the newly added bad block into the memory to prevent accessing the newly added bad block again.

[0015] In some embodiments, when performing read / write / erase operations on the flash memory module, if a write or erase operation fails, it is determined as a newly added bad block, and the information of the newly added bad block is transmitted to the CPU. The method further includes: when performing read / write / erase operations on the flash memory module, the CPU accesses the flash memory through the NANDC and scans for the newly added bad blocks through the NANDC.

[0016] The bad block scanning circuit and scanning method provided in the main control chip of the solid-state drive according to the embodiments of the present invention have at least the following beneficial effects: When the SSD solid-state drive is first installed and used, after the first power-on, the SSD solid-state drive automatically performs a scan of the factory bad blocks internally and writes the factory bad blocks into the reserved area inside the SSD solid-state drive. This scanning takes only a few seconds to more than ten seconds and has no impact on the user experience. In this way, in the card opening and mass production steps of the SSD solid-state drive, the step of scanning the factory bad blocks can be omitted, improving the production efficiency of the SSD solid-state drive and saving the precious time occupied by the production line.

[0017] It should be understood that the above general description and the following detailed description are only exemplary and do not limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention, and those of ordinary skill in the art can obtain other drawings without creative efforts based on these drawings.

[0019] Figure 1 Schematic diagram of the connection structure of the scanning circuit according to the embodiment;

[0020] Figure 2 Flowchart of the scanning method according to the embodiment.

[0021] Explanation of the reference numerals in the drawings is as follows: 1, solid-state drive; 2, flash memory module; 3, main control chip; 4, scanning circuit; 5, CPU; 6, interface module; 7, NHOST module; 8, MSM module; 9, UARTC module; 10, serial bus; 11, RAM module; 12, NANDC module; 13, MUX module. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0022] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0023] In the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation of the present invention.

[0024] The terms "first", "second", "third" are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, the features defined with "first", "second", "third" may explicitly or implicitly include one or more of such features. In the description of the present invention, unless otherwise specified, the meaning of "a plurality" is two or more.

[0025] In the description of the present invention, it should be noted that unless otherwise clearly specified and limited, the terms "connected", "installed", "connected", "coupled" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the connection of two elements inside. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0026] Now, the exemplary embodiments will be described more fully with reference to the accompanying drawings. However, the exemplary embodiments can be implemented in various forms and should not be construed as limited to the examples set forth herein; rather, these exemplary embodiments are provided so that the present disclosure will be more complete and comprehensive, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus the repeated description thereof will be omitted.

[0027] The following further elaborates in detail the preferred embodiments of the present disclosure in conjunction with the Figures 1 to 2 accompanying drawings of this specification.

[0028] Please refer to Figure 1 .

[0029] According to some embodiments, the present application provides a scanning circuit for defective blocks of a solid-state drive main control chip. The solid-state drive 1 includes a flash memory module 2 and a main control chip 3 therein. The main control chip 3 includes a scanning circuit 4 and a CPU 5. The flash memory module 2 includes a plurality of factory blocks, and the factory blocks contain factory defective blocks. The scanning circuit 4 includes: an interface module 6, which is connected to the flash memory module 2 for reading the factory blocks in the flash memory module 2; an NHOST module 7, which is respectively connected to the interface module 6 and the CPU 5 for identifying factory defective blocks from the factory blocks read from the interface module 6 and transmitting the factory defective block information to the CPU 5; an MSM module 8 for controlling the working process of the scanning circuit 4, the CPU 5 is connected to the MSM module 8, and the MSM module 8 is respectively connected to the NHOST module 7 and the interface module 6.

[0030] Based on the above embodiments, the solid-state drive 1 is a substitute for a traditional mechanical hard disk. In a typical solid-state drive 1, its internal circuit includes a main control chip 3, DDR memory particles, a flash memory module 2, SPI Flash particles, etc.

[0031] The flash memory module 2 includes a plurality of NAND Flash memory arrays. The NAND Flash memory array is the main body inside the solid-state drive 1 for carrying stored data; the data in the NAND Flash will not be lost after the system power-off, and after power-on again, the data therein still exists. A memory with this characteristic is called a "non-volatile memory" in the industry.

[0032] The internal storage space of a typical NAND Flash memory chip is organized in the following way:

[0033] One NAND Flash memory package contains one or more LUNs;

[0034] One LUN contains one or more Planes;

[0035] One Plane contains a plurality of Blocks;

[0036] One Block contains many Pages;

[0037] One Page contains a plurality of Bytes.

[0038] Among them, Block means "block", Page means "page", and Byte means "byte".

[0039] There are three common operations for NAND Flash: read, write (i.e., programming), and erase (i.e., erasure). Generally speaking, read and write operations are both in units of Page, while erase operations are in units of Block.

[0040] There are always a small number of blocks inside NAND Flash. At the time of factory shipment, these blocks have inherent and irreparable defects and errors and cannot perform read / write / erase operations normally. These blocks are called "factory bad blocks", that is, Factory BadBlock, and users cannot use these blocks for data storage.

[0041] The addresses of factory bad blocks for each NAND Flash are random. In a typical case, among every 1000 Blocks, there may be less than ten factory bad blocks.

[0042] The reason why the solid-state drive 1 can store a large amount of user data depends on the NAND Flash memory particle array on the circuit board. Therefore, an important function of the solid-state drive 1 is bad block processing.

[0043] In the production of the existing solid-state drive 1, the existing technologies all have dedicated steps for bad block scanning. Either it is a separate step for scanning factory bad blocks, or it is a sub-step of the "card opening" process. After scanning out the bad blocks, they are written into the internal storage space of the solid-state drive 1.

[0044] These steps require corresponding production time or test time. Correspondingly, this reduces the production efficiency / test efficiency of the solid-state drive 1.

[0045] Therefore, this application provides a scanning circuit 4 for bad blocks of the main control chip 3 of the solid-state drive 1, as Figure 1 shown. It includes a main control chip 3, which is arranged inside the solid-state drive 1. The main control chip 3 includes a scanning circuit 4 and a CPU 5. The scanning circuit 4 includes: an interface module 6. The interface module 6 includes multiple PHY interfaces. The flash memory module 2 includes multiple NAND Flash memory arrays. The PHY interface and the NAND Flash memory array can be in a one-to-one relationship or a one-to-many relationship. The interface module 6 is connected to the flash memory module 2 to be used for reading the factory blocks in the flash memory module 2. Among them, the interface module 6 is the physical layer (i.e., phy layer) control logic of the NAND Flash module, used to implement the four basic Cycles of Command Cycle, Address Cycle, Data Input Cycle, and Data Output Cycle required in the NAND chip manual.

[0046] Further, the NHOST module 7 is respectively connected to the interface module 6 and the CPU 5, and is used to identify factory bad blocks from the factory blocks read by the interface module 6 and transmit the factory bad block information to the CPU 5. The CPU 5 stores the factory bad block information in the non-volatile memory. Among them, the NHOST module 7 is the main control end of the flash memory module 2. It schedules the interface module 6 and splices various operation processes such as read, write, erase, read ID, read Unique ID, and read Status with four basic Cycles. For example, a typical Page Read operation is spliced by a Command Cycle, an Address Cycle, and a Data Output Cycle.

[0047] Further, the CPU 5 is connected to the MSM module 8. The MSM module 8 is respectively connected to the NHOST module 7 and the interface module 6. When the CPU 5 performs read, write, and erase operations on the factory blocks, when encountering a factory bad block that is the same as the bad block information in the non-volatile memory, no read, write, and erase operations are performed.

[0048] Further, after long-term use of the solid-state drive 1, new bad blocks will appear. When the new bad blocks are identified, the CPU 5 stores the new bad blocks in the non-volatile memory to prevent access to the new bad blocks again next time.

[0049] After the scanning circuit 4 is arranged in the main control chip 3 of the solid-state drive 1, when the solid-state drive 1 is first installed and used, after the first power-on, the internal of the solid-state drive 1 automatically scans the factory bad blocks and writes the factory bad blocks into the reserved area inside the solid-state drive 1. This scanning only takes a few seconds to more than ten seconds and has no impact on the user experience. In this way, in the card opening and mass production steps of the solid-state drive 1, the step of scanning the factory bad blocks can be omitted, improving the production efficiency of the solid-state drive 1 and saving the precious time occupied by the production line.

[0050] According to some embodiments, the scanning circuit 4 further includes a UARTC module 9 for communicating with the CPU 5 and a serial bus 10. The CPU 5 is connected to the UARTC module 9 through the serial bus 10. The UARTC module 9 is respectively connected to the NHOST module 7 and the MSM module 8. Among them, the UARTC module 9 performs serial communication and communicates with the CPU 5 through the bus inside the SOC.

[0051] Based on the above embodiments, using the UARTC module 9, it can be connected to the serial bus 10 of the CPU 5; the serial port is a commonly used simple bus. In addition to the serial port, SPI bus, IIC bus, APB bus, AHB bus, AXI bus, etc. can also be used. Correspondingly, the UARTC module 9 needs to be replaced with modules named SPIC, IICC, APBC, AHBC, AXIC, etc.

[0052] According to some embodiments, the scanning circuit 4 further includes a RAM module 11 for caching data. The RAM module 11 is disposed between the NHOST module 7 and the UARTC module 9. After receiving information from the NHOST module 7, the RAM module 11 temporarily caches the data and then sends it to the CPU 5 through the UARTC module 9.

[0053] According to some embodiments, the main control chip 3 further includes a NANDC module 12 for switching with the interface module 6. The NANDC module 12 is respectively connected to the flash memory module 2 and the serial bus 10.

[0054] According to some embodiments, the scanning circuit 4 further includes a MUX module 13 for switching the interface module 6 and the NANDC module 12. The MUX module 13 is respectively connected to the interface module 6, the NANDC module 12, and the flash memory module 2. The MSM module 8 is connected to control the MUX module 13.

[0055] Based on the above embodiments, during the normal use of the user, when performing a new bad block scan, the NANDC module 12 controls the flash memory module 2, but the interface module 6 monitors the interface signals between the NANDC module 12 and the flash memory module 2. The access control interface of the flash memory module 2 is switched and controlled by the MUX module 13, and the MUX module 13 is controlled by the MSM module 8.

[0056] Please refer to Figure 2 。

[0057] According to some other embodiments, the present application provides a scanning method for scanning bad blocks of a solid-state drive 1. The method is applied to the scanning circuit 4 as described above. The factory bad blocks include the first type of factory bad blocks and the second type of factory bad blocks. The scanning method includes: Step 101, the interface module 6 reads the factory blocks in the flash memory module 2 and identifies the second type of factory bad blocks; Step 102, the NHOST module 7 identifies the first type of factory bad blocks from the factory blocks and transmits the information of the first type of factory bad blocks and the second type of factory bad blocks to the CPU 5; Step 103, the CPU 5 enters the information of the first type of factory bad blocks and the second type of factory bad blocks into the memory; Step 104, when the CPU 5 performs read, write, and erase operations on the factory blocks, it avoids the bad blocks that are the same as the information in the memory.

[0058] According to some embodiments, before Step 101 where the interface module 6 reads the factory blocks in the flash memory module 2 and identifies the second type of factory bad blocks, the method further includes: after the solid-state drive 1 is installed and powered on for the first time, the solid-state drive 1 automatically performs the scanning method as described above to scan the bad blocks of the solid-state drive 1.

[0059] According to some embodiments, before the solid-state drive 1 automatically performs the scanning method as described above to scan the bad blocks of the solid-state drive 1 after the solid-state drive 1 is installed and powered on for the first time, the method further includes: making different bad block marks for the first type of factory bad blocks and the second type of factory bad blocks respectively, so as to facilitate the NHOST module 7 and the interface module 6 to identify the first type of factory bad blocks and the second type of factory bad blocks.

[0060] Based on the above embodiments, the flash memory module 2 includes multiple NAND Flash arrays. A typical NAND Flash memory chip organizes its internal storage space in the following way:

[0061] One NAND Flash memory package contains one or more LUNs;

[0062] One LUN contains one or more Planes;

[0063] One Plane contains multiple Blocks;

[0064] One Block contains many Pages;

[0065] One Page contains multiple Bytes.

[0066] Among them, Block means "block", Page means "page", and Byte means "byte".

[0067] There are three common operations for NAND Flash: read, write (i.e., programming), and erase. Generally, read and write operations are performed in units of pages, while erase operations are performed in units of blocks. There are always a small number of blocks inside NAND Flash. At the time of factory shipment, these blocks have inherent and irreparable defects and errors and cannot be read / written / erased normally. These blocks are called "factory bad blocks", i.e., Factory Bad Block, and users cannot use these blocks for data storage.

[0068] The addresses of factory bad blocks for each NAND Flash are random. In a typical case, among every 1000 blocks, there may be less than ten factory bad blocks.

[0069] For convenient query, there are two common marking methods:

[0070] The first type of factory bad block:

[0071] Write a special character in the sixth byte of the spare area as the bad block mark. When a user hopes to query factory bad blocks, they need to read the sixth byte of each physical block in sequence to see if it is marked as a factory bad block to make a determination.

[0072] If this method is adopted, the mark of the factory bad block can actually be erased by the user; if a full-chip erase is performed, all the marks of the factory bad blocks will be lost.

[0073] During the production process, the chips are tested under strict environmental conditions to identify and confirm factory bad blocks; many of the "factory bad blocks" marked are actually in a critical state between "good" and "bad". If the chip operates in a relatively comfortable environmental condition, it is very likely to behave as a good block. After delivery to the user, it is very difficult for the user to reproduce such strict conditions. Therefore, after the user erases the mark of the factory bad block, if read / write / erase access is performed on the "factory bad block", these addresses are very likely to behave as normal good blocks.

[0074] Therefore, for this type of flash memory particle, after the user obtains the NAND Flash particle, they must first read out the factory bad blocks, save them separately, and then perform other read / write / erase operations; otherwise, once the factory bad block flag is erased, there will be no means to obtain the factory bad block information anymore.

[0075] The second type of factory bad block:

[0076] Mark each Block in a non-volatile manner. The user performs instruction operations on each Block of the entire chip one by one with a specific instruction sequence and reads the corresponding Status flag to know whether each Block is a factory bad block, and then constructs a list of factory bad blocks and enters it into the memory.

[0077] If this method is adopted, generally speaking, the bad block flag cannot be erased by the user. Even if a full-chip erase is performed, the flag of the factory bad block will not be lost. For this type of NAND Flash particle, even if the factory bad blocks are not read in advance, the factory bad block information can be read again at a later time.

[0078] Scan for factory bad blocks:

[0079] After the solid-state drive 1 is delivered to the user and the installation is completed, when it is powered on and booted for the first time, the entire disk is in a blank state at this time, and the factory bad blocks are scanned at this time.

[0080] For the first type of factory bad blocks, the interface module 6 reads the addresses where the bad block identifiers are located in each Block of the entire chip, and the NHOST module 7 determines whether they are factory bad blocks. If so, the addresses of the bad blocks are written into the RAM module 11 for caching, and then passed back to the CPU 5 through the UARTC module 9.

[0081] For the second type of factory bad blocks, the interface module 6 directly reads the status of each Block of the entire chip in a loop to know whether it is a factory bad block, writes the bad block information (i.e., the address of the bad block) into the RAM module, and then the UARTC module 9 passes it back to the CPU 5.

[0082] The first type of factory bad blocks and the second type of factory bad blocks generally do not appear in the same NAND Flash chip at the same time. Generally speaking, in a NAND Flash chip, either the marking method for the first type of factory bad blocks is used for detection, or the marking method for the second type of factory bad blocks is used for detection. For more comprehensive detection, in this application, when detecting, the first type of factory bad blocks and the second type of factory bad blocks are detected together. If there are no first type of factory bad blocks, the steps for detecting the first type of factory bad blocks are skipped. If there are no second type of factory bad blocks, the steps for detecting the second type of factory bad blocks are skipped.

[0083] According to some embodiments, after the CPU 5 avoids the bad blocks that are consistent with the information in the memory when performing read, write, and erase operations on the factory blocks, the method further includes: when performing read, write, and erase operations on the flash memory module 2, if the write or erase operation fails, it is determined as a newly added bad block, and the information of the newly added bad block is transmitted to the CPU 5; the CPU 5 enters the information of the newly added bad block into the memory to prevent accessing the newly added bad block again.

[0084] Based on the above embodiments, the lifespan of the flash memory module 2 is not infinite. It has its own service life, which has two aspects: 1. Endurance, that is, how many Program / Erase Cycles each Block can withstand, namely the P / E lifespan; 2. Retention, that is, how many years the data stored in the Flash can be retained.

[0085] During the use of the solid-state drive 1, as the number of read / write / erase operations increases, each Block will gradually approach the upper limit of its P / E lifespan. During this process, some Blocks may experience relatively severe degradation, and as a result, it may lead to failure to program (Program write failure), failure to erase (Erase failure), or read error (the error rate of reading data is relatively high, exceeding the ECC error correction capability range). When this situation occurs, the corresponding block is also called a "bad block", that is, a Bad Block. To distinguish it from the "factory bad blocks" that come with the chip when it leaves the factory, these bad blocks that appear during use are called "newly added bad blocks" or "used bad blocks".

[0086] Generally speaking, within the service life of the flash memory module 2, it is necessary to control that the number of newly added bad blocks does not exceed a certain proportion of the total chip capacity. For example, at most it does not exceed 2%; on this premise, combined with an appropriate bad block management algorithm, the flash memory module 2 can still be used normally.

[0087] The reason why the solid-state drive 1 can store a large amount of user data is the NAND Flash memory particle array on the circuit board. Therefore, an important function of the solid-state drive 1 is bad block processing, including:

[0088] Scanning the flash memory module 2, obtaining its factory bad block list, and recording it in the memory.

[0089] During the use of the solid-state drive 1, establishing, maintaining, and updating a newly added bad block list and recording it in the memory.

[0090] In the actual design scheme of the solid-state drive 1, the "factory bad block list" and the "newly added bad block list" may be combined into one, or may be maintained and managed separately.

[0091] During normal access to the flash memory module 2, the interface module 6 monitors the flash memory module 2 interface in real time. If it is found that the Status returned by the programming or erasing operation is Fail, it is determined as a newly added bad block. At this time, its Block address is written into the RAM module and later passed back to the CPU 5 by the UARTC.

[0092] According to some embodiments, when performing read, write, and erase operations on the flash memory module 2, if a write or erase operation fails, it is determined as a newly added bad block, and the information of the newly added bad block is transmitted to the CPU 5. The method further includes: when performing read, write, and erase operations on the flash memory module 2, the CPU 5 accesses the flash memory through the NANDC and scans for the newly added bad block through the NANDC.

[0093] Based on the above embodiments, another circuit form is as follows. The flash memory module 2 is alternately controlled by the NANDC module 12 and the interface module 6 in the main control chip 3:

[0094] When performing normal data access (ordinary read, write, and erase), the NANDC module 12 accesses the flash memory module 2;

[0095] When performing factory bad block scanning, the interface module 6 controls the flash memory module 2;

[0096] During normal use by the user, when performing newly added bad block scanning, the NANDC module 12 still controls the flash memory module 2, but the interface module 6 monitors the interface signals between the NANDC module 12 and the flash memory module 2;

[0097] The access control interface of the flash memory module 2 is switched and controlled by the MUX module 13, and the MUX module 13 is controlled by the MSM module 8.

[0098] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in a suitable manner in any one or more embodiments or examples.

[0099] Although the present disclosure has been described with reference to several exemplary embodiments, it should be understood that the terms used are illustrative and exemplary, rather than restrictive. Since the present disclosure can be embodied in many forms without departing from the spirit or essence of the invention, it should be understood that the above embodiments are not limited to any of the foregoing details, but should be broadly construed within the spirit and scope defined by the appended claims. Therefore, all changes and modifications falling within the scope of the claims or their equivalents should be covered by the appended claims.

Claims

1. A bad block scanning circuit disposed in a solid-state drive main control chip, characterized in that, the solid-state drive includes a flash memory module and a main control chip, the main control chip includes a scanning circuit and a CPU, the flash memory module includes a plurality of factory blocks, the factory blocks contain factory bad blocks, the factory bad blocks include first-class factory bad blocks and second-class factory bad blocks, and the scanning circuit includes: An interface module, which is connected to the flash memory module for reading the factory blocks in the flash memory module and identifying the second-class factory bad blocks; An NHOST module, which is respectively connected to the interface module and the CPU for identifying the first-class factory bad blocks from the factory blocks read by the interface module and transmitting the information of the factory bad blocks to the CPU; An MSM module for controlling the working process of the scanning circuit, the CPU is connected to the MSM module, and the MSM module is respectively connected to the NHOST module and the interface module; A UARTC module and a serial bus for communicating with the CPU, the CPU is connected to the UARTC module through the serial bus, and the UARTC module is respectively connected to the NHOST module and the MSM module; An NANDC module for switching and using with the interface module, the NANDC module is respectively connected to the flash memory module and the serial bus; A MUX module for switching the interface module and the NANDC module, the MUX module is respectively connected to the interface module, the NANDC module and the flash memory module, and the MSM module is connected to control the MUX module; After the solid-state drive is installed and powered on for the first time, the bad blocks of the solid-state drive are scanned.

2. The scanning circuit according to claim 1, characterized in that, the scanning circuit further includes a RAM module for caching data, and the RAM module is disposed between the NHOST module and the UARTC module.

3. A scanning method, which is applied to the scanning circuit according to claim 1, characterized in that, the factory bad blocks include first-class factory bad blocks and second-class factory bad blocks, and the scanning method includes: The interface module reads the factory blocks in the flash memory module and identifies the second-class factory bad blocks; The NHOST module identifies the first-class factory bad blocks from the factory blocks and transmits the information of the first-class factory bad blocks and the second-class factory bad blocks to the CPU; The CPU enters the information of the first-class factory bad blocks and the second-class factory bad blocks into the memory; When the CPU performs read / write / erase operations on the factory blocks, it avoids the bad blocks that are the same as the information in the memory.

4. The scanning method according to claim 3, characterized in that, before the interface module reads the factory blocks in the flash memory module and identifies the second-class factory bad blocks, the method further includes: After the solid-state drive is installed and powered on for the first time, the bad blocks of the solid-state drive are scanned.

5. The scanning method according to claim 4, characterized in that, After the solid-state drive is installed and powered on for the first time, before scanning for bad blocks on the solid-state drive, the method further includes: Making different bad block marks for the first type of factory bad blocks and the second type of factory bad blocks respectively, so as to facilitate the NHOST module and the interface module to identify the first type of factory bad blocks and the second type of factory bad blocks.

6. The scanning method according to claim 3, wherein, After the CPU avoids bad blocks that are consistent with the information in the memory when performing read, write, and erase operations on the factory blocks, the method further includes: When performing read, write, and erase operations on the flash memory module, if the write or erase operation fails, it is determined as a newly added bad block, and the information of the newly added bad block is transmitted to the CPU; The CPU enters the information of the newly added bad block into the memory to prevent accessing the newly added bad block again.

7. The scanning method according to claim 6, wherein, When performing read, write, and erase operations on the flash memory module, if the write or erase operation fails, it is determined as a newly added bad block, and the information of the newly added bad block is transmitted to the CPU, the method further includes: When performing read, write, and erase operations on the flash memory module, the CPU accesses the flash memory through the NANDC module and scans for the newly added bad blocks through the NANDC module.

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