Multiplexer under memory cell array

Abstract

This application relates to multiplexers under an array of memory cells. Sense amplifiers can be formed outside / horizontally adjacent to an array of vertical stacks of memory cells. A memory cell can be sensed via a multiplexer formed under the array, which is operable to couple a vertical sense line (to which the memory cell is coupled) to a horizontal sense line (to which the sense amplifier is coupled).

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to memory devices, and more particularly to multiplexers under memory cell arrays. BACKGROUND

[0002] Memory is typically implemented in electronic systems such as computers, cellular telephones, handheld devices, etc. There are many different types of memory, including volatile and non-volatile memory. Volatile memory can require power to maintain its data, and can include random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), and synchronous dynamic random access memory (SDRAM). Non-volatile memory can provide persistent data by retaining stored data when unpowered, and can include NAND flash memory, NOR flash memory, nitride read-only memory (NROM), phase change memory (e.g., phase change random access memory), resistive memory (e.g., resistive random access memory), cross point memory, ferroelectric random access memory (FeRAM), etc.

[0003] As design rules shrink, less semiconductor space is available for fabricating memory including DRAM arrays. A respective memory cell for a DRAM can include an access device (e.g., a transistor) having first and second source / drain regions separated by a channel region. A gate can be opposite the channel region and separated from the channel region by a gate dielectric. An access line, sometimes referred to in the art as a word line, is electrically connected to the gate of a DRAM cell. The DRAM cell can include a storage node such as a capacitor cell, which is coupled to a sense line, sometimes referred to in the art as a digit line, through the access device. The access device can be activated (e.g., to select a cell) through the access line coupled to the access transistor. The capacitor can store a charge corresponding to a data value (e.g., a logic "1" or "0") for the respective cell. SUMMARY

[0004] According to one embodiment of the present disclosure, a memory device (651) for sensing memory cells (110; 210-1,..., 210-16; 310-1,..., 310-4; 410-1,..., 410-(Q+7)) is provided. The memory device (651) includes an array (101-1, 101-2,..., 101-N; 653) of memory cells including a plurality of vertically stacked tiers (430-1,..., 430-P) of memory cells, a respective plurality of horizontal access lines (107-1,..., 107-B; 207-1,..., 207-16; 407-1,..., 407-4) coupled to each of the plurality of tiers, and a plurality of vertical sense lines (103-1,..., 103-A; 203-1,..., 203-10; 303-1,..., 303-4; 403-1,..., 403-8) coupled to each of the plurality of tiers. The memory device (651) further includes a semiconductor below the array including a plurality of multiplexers (232-1,..., 232-16; 332-1,..., 332-4; 432-1,..., 432-4) each coupled to a respective vertical sense line of the plurality of vertical sense lines and to a respective horizontal sense line (222-1-1, 222-1-2,..., 222-4-1, 222-4-2; 322-1-1, 322-1-2,..., 322-4-1, 322-4-2; 422-1, 422-2). The memory device (651) also includes a plurality of sense amplifiers (226-1,..., 226-4; 326-1,..., 326-4) each coupled to a respective pair of horizontal sense lines (222-1-1, 222-1-2,..., 222-4-1, 222-4-2; 322-1-1, 322-1-2,..., 322-4-1, 322-4-2; 422-1, 422-2).

[0005] According to another embodiment of the present disclosure, a memory device (651) for sensing memory cells (110; 210-1,..., 210-16; 310-1,..., 310-4; 410-1,..., 410-(Q+7)) is provided. The memory device (651) includes: an array of memory cells (101-1, 101-2,..., 101-N; 653) including a plurality of vertically stacked tiers (430-1,..., 430-P) of memory cells coupled to a plurality of horizontal access lines (107-1,..., 107-B; 207-1,..., 207-16; 407-1,..., 407-4) and coupled to a plurality of vertical sense lines (103-1,..., 103-A; 203-1,..., 203-10; 303-1,..., 303-4; 403-1,..., 403-8). The memory device (651) further includes: semiconductor circuitry formed below the array including: a plurality of multiplexers (232-1,..., 232-16; 332-1,..., 332-4; 432-1,..., 432-4) formed below the plurality of vertically stacked tiers of memory cells, each of the plurality of multiplexers coupled to a respective one of the plurality of vertical sense lines; and a plurality of pairs of horizontal sense lines (222-1-1, 222-1-2,..., 222-4-1, 222-4-2; 322-1-1, 322-1-2,..., 322-4-1, 322-4-2; 422-1, 422-2) coupled to the plurality of multiplexers. The memory device (651) also includes: semiconductor circuitry formed outside the array including a plurality of sense amplifiers (226-1,..., 226-4; 326-1,..., 326-4), each coupled to a respective one of the plurality of pairs of horizontal sense lines. The memory device (651) further includes: control circuitry (652) configured to cause a first portion of the plurality of multiplexers to electrically couple a first portion of the plurality of vertical sense lines to a first one of each of the plurality of pairs of horizontal sense lines for sensing the memory cells coupled to a first horizontal access line (107-1,..., 107-B; 207-1,..., 207-16; 407-1,..., 407-4) of the plurality of horizontal access lines, wherein the first portion of the plurality of vertical sense lines is coupled to the first horizontal access line of the plurality of horizontal access lines.

[0006] According to yet another embodiment of the present disclosure, a method of sensing a memory cell (110; 210-1,..., 210-16; 310-1,..., 310-4; 410-1,..., 410-(Q+7)) in a sensing array (101-1, 101-2,..., 101-N; 653) is provided. The method includes activating a particular horizontal access line (107-1,..., 107-B; 207-1,..., 207-16; 407-1,..., 407-4) coupled to a memory cell among a respective plurality of horizontal access lines (107-1,..., 107-B; 207-1,..., 207-16; 407-1,..., 407-4) of each of a plurality of vertical stack layers (430-1,..., 430-P) coupled to the memory cell. The method also includes electrically coupling, via a first multiplexer (232-1,..., 232-16; 332-1,..., 332-4; 432-1,..., 432-4) in a semiconductor under the array, a first vertical sense line (103-1,..., 103-A; 203-1,..., 203-10; 303-1,..., 303-4; 403-1,..., 403-8) to a first horizontal sense line (222-1-1, 222-1-2,..., 222-4-1, 222-4-2; 322-1-1, 322-1-2,..., 322-4-1, 322-4-2; 422-1, 422-2), where the first vertical sense line is coupled to the memory cell. The method further includes electrically coupling, via a second multiplexer (232-1,..., 232-16; 332-1,..., 332-4; 432-1,..., 432-4) in the circuit, a second vertical sense line (103-1,..., 103-A; 203-1,..., 203-10; 303-1,..., 303-4; 403-1,..., 403-8) to a second horizontal sense line (222-1-1, 222-1-2,..., 222-4-1, 222-4-2; 322-1-1, 322-1-2,..., 322-4-1, 322-4-2; 422-1, 422-2), where the second vertical sense line is not coupled to the memory cell. The method further includes sensing the memory cell with a differential sense amplifier coupled to the first horizontal sense line and the second horizontal sense line, where the differential sense amplifier is horizontally adjacent to the plurality of vertical stack layers of memory cells. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1is a schematic illustration of a portion of a vertical three-dimensional (3D) memory according to a number of embodiments of the present disclosure.

[0008] Figure 2A is a first plan view of a portion of a 3D memory according to a number of embodiments of the present disclosure.

[0009] Figure 2B is a second plan view of a portion of a 3D memory according to a number of embodiments of the present disclosure.

[0010] Figure 2C is a third plan view of a portion of a 3D memory according to a number of embodiments of the present disclosure.

[0011] Figure 3 is a top view of a portion of a vertical 3D memory according to a number of embodiments of the present disclosure.

[0012] Figure 4 is a diagram of a portion of a vertical 3D memory according to a number of embodiments of the present disclosure.

[0013] Figure 5 is a schematic illustration of a vertical sense line multiplexer according to a number of embodiments of the present disclosure.

[0014] Figure 6 is a block diagram of an apparatus according to a number of embodiments of the present disclosure. DETAILED DESCRIPTION

[0015] Embodiments of the present disclosure describe multiplexers below an array of memory cells. A vertical three-dimensional (3D) memory (e.g., 3D-DRAM) according to a number of embodiments of the present disclosure can include an array of memory cells composed of vertically stacked layers of memory cells. The memory cells are controlled and / or accessed via vertical sense lines running through the layers of memory cells and horizontal access lines running within respective layers of memory cells. The horizontal access lines can be coupled to a number of access line drivers via a staircase connection, which in turn provides power to a subset of the vertical sense lines via respective horizontal access lines. The vertical sense lines can be coupled to respective horizontal sense lines formed below the array. The horizontal sense lines can be coupled to respective sense amplifiers external to the array. The vertical sense lines can each be coupled to respective horizontal sense lines via respective multiplexers that allow individual vertical sense lines to be activated and / or deactivated for read and write operations, among other operations.

[0016] Embodiments of the disclosure provide simplified circuitry formed below an array of memory cells (e.g., an array of vertical stacks of memory cells). In at least one embodiment, the circuitry formed below the array can be simplified by not including a sense amplifier, which can instead be located outside of and / or horizontally adjacent to the array. Such simplified circuitry can occupy less space below the array, which will make more vertical space available for forming memory cells within the array. Accordingly, embodiments of the disclosure can increase the cell storage density (e.g., the number of memory cells within a particular space / volume) of an array of vertical stacks of memory cells.

[0017] As used herein, the singular forms “a,” “an,” and “the” include singular and plural referents unless the context clearly dictates otherwise. Additionally, the word “may” is used herein in a permissive sense (i.e., meaning having the potential to), rather than in a mandatory sense (i.e., meaning must). The term “include” and its derivatives mean “including, but not limited to.” The term “coupled” means directly or indirectly connected.

[0018] The figures herein follow a numbering convention in which the first digit or digits correspond to the figure number and the remaining digits, if any, correspond to the numbering of the elements within the figure. Similar elements or components between different figures can be designated by like reference numerals. For example, 103 can represent an element “03” in Figure 1 , and similar elements can be represented as 203 in Figure 2B and 2C . Similar elements between different figures can also be identified by like reference numerals without a hyphen and a following number or letter. For example, elements 103-1, 103-2, 103-A in Figure 1 may be collectively referred to as 103. As used herein, designators “A,” “B,” “Q,” “P,” and “N,” particularly with respect to reference numerals in the drawings, indicate that a number of the particular feature so designated can be included. As will be appreciated, as various embodiments of the present disclosure can include, inter alia, elements of the drawings shown in the figures, additional embodiments of the present disclosure can be provided without the elements. Additionally, as will be appreciated, the proportions and relative scales of the various elements in the figures are intended to be illustrative only and should not be taken as limiting.

[0019] Figure 1 is a schematic illustration of a portion of a vertical 3D memory in accordance with several embodiments of the present disclosure. Figure 1 is a circuit diagram illustrating a cell array of a portion of a 3D semiconductor memory device in accordance with embodiments of the present disclosure. Figure 1The array of cells can have a plurality of sub-array of cells 101-1, 101-2,..., 101-N. The sub-array of cells 101-1, 101-2,..., 101-N can have various configurations. For example, the sub-array of cells 101-1, 101-2,..., 101-N can be arranged along a second direction (D2) 105. Each of the sub-array of cells 101-2 can include a plurality of access lines 107-1, 107-2,..., 107-B (also referred to as word lines). In addition, each of the sub-array of cells 101-2 can include a plurality of sense lines 103-1, 103-2,..., 103-A (which can also be referred to as bit lines, data lines, or digit lines). In Figure 1 , the access lines 107-1, 107-2,..., 107-B are shown extending in a first direction (D1) 109, and the sense lines 103-1, 103-2,..., 103-A are shown extending in a third direction (D3) 111; however, embodiments are not so limited. The first direction (D1) 109 and the second direction (D2) 105 can be considered to be in a horizontal (“X-Y”) plane. The third direction (D3) 111 can be considered to be in a vertical (“Z”) plane. Thus, in accordance with several embodiments described herein and as illustrated in Figure 1 , the sense lines 103-1, 103-2,..., 103-A extend in a vertical direction (third direction (D3) 111); however, embodiments are not so limited. For example, in accordance with several embodiments described herein, the sense lines 103-1, 103-2,..., 103-A can extend in a horizontal direction (direction (D1) 109).

[0020] As noted, embodiments are not limited to Figure 1 schematic illustration. One or more embodiments provide that the sense lines 103-1, 103-2,..., 103-A can extend in the first direction (D1) 109, and the access lines 107-1, 107-2,..., 107-B can extend in the third direction (D3) 111. Thus, one or more embodiments provide that the sense lines 103-1, 103-2,..., 103-A can extend in a horizontal direction, and the access lines 107-1, 107-2,..., 107-B extend in a vertical direction.

[0021] Memory cells 110 can include access devices (e.g., transistors) and storage nodes located at the intersection of each access line 107-1, 107-2,..., 107-B and each sense line 103-1, 103-2,..., 103-A. The memory cells can be written to or read from using the access lines 107-1, 107-2,..., 107-B and the sense lines 103-1, 103-2,..., 103-A. As shown, the access lines 107-1, 107-2,..., 107-B can electrically interconnect the memory cells along the horizontal rows of each subarray of cells 101-1, 101-2,..., 101-N, and the sense lines 103-1, 103-2,..., 103-A can electrically interconnect the memory cells along the vertical columns of each subarray of cells 101-1, 101-2,..., 101-N. One memory cell 110 can be located between one access line 107-2 and one sense line 103-2. Each memory cell can be uniquely addressed by a combination of the access lines 107-1, 107-2,..., 107-B and the sense lines 103-1, 103-2,..., 103-A. Figure 1

[0022] The access lines 107-1, 107-2,..., 107-B can be or include electrically conductive patterns (e.g., metal lines) disposed on and spaced apart from a substrate. As shown, the access lines 107-1, 107-2,..., 107-B can extend in a first direction (D1) 109. The access lines 107-1, 107-2,..., 107-B in one subarray of cells 101-2 can be spaced apart from each other in a vertical direction (third direction (D3) 111). However, embodiments are not limited in this regard. Figure 1

[0023] The sense lines 103-1, 103-2,..., 103-A can be or include electrically conductive patterns (e.g., metal lines) that extend in a vertical direction (third direction (D3) 111) relative to the substrate as shown. The sense lines in one subarray of cells 101-2 can be spaced apart from each other in the first direction (D1) 109. However, embodiments are not limited in this regard. Figure 2A

[0024] ​​​The gates of the memory cells 110 can be connected to the access lines 107-2, and the first conductive nodes (e.g., first source / drain regions) of the access devices (e.g., transistors) of the memory cells 110 can be connected to the sense lines 103-2. Each of the memory cells 110 can be connected to a storage node (e.g., a capacitor). The second conductive nodes (e.g., second source / drain regions) of the access devices (e.g., transistors) of the memory cells 110 can be connected to the storage nodes (e.g., capacitors). While first and second source / drain region references are used herein to refer to two separate and distinct source / drain regions, the source / drain regions that are not referred to as the “first” and / or “second” source / drain regions are not meant to have some unique meaning. It is only meant that one of the source / drain regions is connected to the sense line 103-2 and the other can be connected to the storage node.

[0025] Figure 2A is a first view of a portion of a 3D memory in accordance with several embodiments of the disclosure. Figure 2A The views in show a portion of a 3D memory, including a cross-sectional view of a bottom portion of the 3D memory including horizontal sense lines 222 and sense amplifiers 226 and a cross-sectional view of another bottom portion of the 3D memory including memory cells 210 and horizontal access lines 207. Figure 1 The portion of the 3D memory shown in is shown in a first direction 209 (D1) and a second direction 205 (D2) that respectively correspond to the first direction 109 (D1) and the second direction 105 (D2) as described in connection with Figure 2A

[0026] Figure 2A The memory cells 210 coupled to the horizontal access lines 207 are illustrated, respectively. For example, memory cells 210-1, 210-2, 210-3, 210-4 are coupled to horizontal access line 207-1; memory cells 210-5, 210-6, 210-7, 210-8 are coupled to horizontal access line 207-2; memory cells 210-9, 210-10, 210-11, 210-12 are coupled to horizontal access line 207-3; and memory cells 210-13, 210-14, 210-15, 210-16 are coupled to horizontal access line 207-4. Figure 2A ​Pairs of horizontal sense lines 222, which are formed outside (and / or positioned horizontally adjacent to) the array of vertical stacks of memory cells, are illustrated as being coupled to sense amplifiers 226, respectively. For example, the pair of horizontal sense lines 222-1 (horizontal sense lines 222-1-1 and 222-1-2) are coupled to sense amplifier 226-1; the pair of horizontal sense lines 222-2 (horizontal sense lines 222-2-1 and 222-2-2) are coupled to sense amplifier 226-2; the pair of horizontal sense lines 222-3 (horizontal sense lines 222-3-1 and 222-3-2) are coupled to sense amplifier 226-3; and the pair of horizontal sense lines 222-4 (horizontal sense lines 222-4-1 and 222-4-2) are coupled to sense amplifier 226-4.

[0027] Furthermore, memory cells 210 are coupled to horizontal sense lines 222 via respective multiplexers 232. For example, memory cells 210-4 and 210-12 are coupled to horizontal sense line 222-1-1 via multiplexers 232-1 and 232-3, respectively; memory cells 210-8 and 210-16 are coupled to horizontal sense line 222-1-2 via multiplexers 232-2 and 232-4, respectively; memory cells 210-3 and 210-11 are coupled to horizontal sense line 222-2-1 via multiplexers 232-11 and 232-5, respectively; memory cells 210-7 and 210-15 are coupled to horizontal sense line 222-2-2 via multiplexers 232-12 and 232-6, respectively; memory cells 210-2 and 210-10 are coupled to horizontal sense line 222-3-1 via multiplexers 232-13 and 232-7, respectively; memory cells 210-6 and 210-14 are coupled to horizontal sense line 222-3-2 via multiplexers 232-14 and 232-8, respectively; memory cells 210-1 and 210-9 are coupled to horizontal sense line 222-4-1 via multiplexers 232-15 and 232-9, respectively; and memory cells 210-5 and 210-13 are coupled to horizontal sense line 222-4-2 via multiplexers 232-16 and 232-10, respectively.

[0028] Each horizontal access line 207 is coupled to a respective horizontal access line driver 228, which can be referred to in the art as a sub-word line driver. Although illustrated as a single element, horizontal access line driver 228 can include multiple horizontal access line drivers and each of the drivers can be coupled to a respective horizontal access line 207. Horizontal access line driver 228 can be coupled to a power supply, such as a positive power supply.

[0029] As Figure 2AFurther shown, horizontal access lines extend in direction 209 (Dl) and pairs of horizontal sense lines 222 extend in direction 205 (D2). While Figure 2B not shown in FIGS. 1-3 (but shown in Figure 2C and Figure 2B ), the pairs of horizontal sense lines 222 are further coupled to vertical sense lines 203 extending in direction 211, respectively.

[0030] Figure 2B is a second plan view of a portion of a 3D memory in accordance with several embodiments of the present disclosure. Figure 1 The plan view in FIG. 4 shows a cross-section of a portion of a 3D memory in third direction 211 (D3) and second direction 205 (D2) corresponding to third direction 111 (Dl) and second direction 105 (D2) shown in FIG. 3, respectively. Figure 2B

[0031] As shown in FIG. 5, vertical stack memory cells 210 are coupled to vertical sense lines 203-1 through 203-4, respectively. For example, memory cells including memory cell 210-4 (and those memory cells vertically stacked on memory cell 210-4) are coupled to vertical sense line 203-1; memory cells including memory cell 210-8 (and those memory cells vertically stacked on memory cell 210-8) are coupled to vertical sense line 203-2; memory cells including memory cell 210-12 (and those memory cells vertically stacked on memory cell 210-12) are coupled to vertical sense line 203-3; and memory cells including memory cell 210-16 (and those memory cells vertically stacked on memory cell 210-16) are coupled to vertical sense line 203-4. Figure 2B As shown in FIG. 6, memory cells 210 are coupled to respective horizontal access lines 207. For example, memory cells 210-4, 210-8, 210-12, and 210-16 are coupled to horizontal access lines 207-1, 207-2, 207-3, and 207-4, respectively.

[0032] Figure 2B Further shown, memory cells 210 are coupled to respective horizontal access lines 207. For example, memory cells 210-4, 210-8, 210-12, and 210-16 are coupled to horizontal access lines 207-1, 207-2, 207-3, and 207-4, respectively.

[0033] Figure 2B Further shown, multiplexers 232 are coupled to respective pairs of horizontal sense lines and formed below the array of vertically stacked memory cells. As shown in FIG. 7, multiplexers 232-1 through 232-3 are coupled to horizontal sense lines 222-1-1 (similar to horizontal sense lines 222-1-1 shown in FIG. 6). While Figure 2A Figure 2B Figure 6 ​​​​The multiplexers 232-2 and 232-4 are coupled to different ones of the pair, such as the horizontal sense line 222-1-2, although not shown in detail. In addition, the multiplexers 232-1, 232-2, 232-3, and 232-4 are coupled to the vertical sense lines 203-1, 203-2, 203-3, and 203-4, respectively. Control circuitry (e.g., Figure 2C The control circuitry 652, shown, can cause the multiplexers 232 to electrically couple / de-couple the vertical sense lines 203 to / from the respective horizontal sense lines 222. For example, the multiplexers 232-1 and 232-3 are operable to electrically couple / de-couple the vertical sense lines 203-1 and 203-3 to / from the horizontal sense lines 222-1-1.

[0034] Figure 2C is a third plan view of a portion of a 3D memory in accordance with several embodiments of the present disclosure. Figure 1 The plan views in are shown in the third direction 211 (D3) and the first direction 209 (D1) corresponding to the third direction 111 (D3) and the first direction 109 (D1), respectively, as described in connection with Figure 2C The cross-section of a portion of the 3D memory is shown in the third direction 211 (D3) and the first direction 209 (D1) corresponding to the third direction 111 (D3) and the first direction 109 (D1), respectively, as described in connection with

[0035] As illustrated in Figure 2C The vertically stacked memory cells 210 are coupled to the horizontal access lines 207 and the vertical sense lines 203, respectively, as illustrated in For example, the memory cells 210-12, 210-11, 210-10, and 210-9 (and those vertically stacked on the memory cells 210-12, 210-11, 210-10, and 210-9) are coupled to one of the horizontal access lines (e.g., the horizontal access line 207-3) and to the vertical sense lines 203-3, 203-5, 203-7, and 203-9, respectively. In addition, for example, the memory cells 210-16, 210-15, 210-14, and 210-13 (and those vertically stacked on the memory cells 210-16, 210-15, 210-14, and 210-13) are coupled to the horizontal access line 207-4 and to the vertical sense lines 203-4, 203-6, 203-8, and 203-10, respectively. As Figure 2C Further shown, the horizontal access lines 207, including the horizontal access line 207-4 and those vertically stacked on the horizontal access line 207-4, and the horizontal access line drivers 228 are coupled via the stepped connections 215.

[0036] In addition, as Figure 3As shown in FIG. 2, vertical sense lines 203-3 through 203-10 are coupled to multiplexers 232-3, 232-4, 232-5, 232-6, 232-7, 232-8, 232-9, and 232-10, respectively. For example, vertical sense lines 203-3 and 204-4 are coupled to multiplexers 232-3 and 232-4, respectively; vertical sense lines 203-5 and 203-6 are coupled to multiplexers 232-5 and 232-6, respectively; vertical sense lines 203-7 and 203-8 are coupled to multiplexers 232-7 and 232-8, respectively; and vertical sense lines 203-9 and 203-10 are coupled to multiplexers 232-9 and 232-10, respectively.

[0037] Each multiplexer is operable to couple / decouple a vertical sense line 203 to / from a respective horizontal sense line 222. For example, multiplexer 232-3 is operable to couple vertical sense line 203-3 to / from one of the pair of horizontal sense lines 222-1-1; multiplexer 232-4 is operable to couple vertical sense line 203-4 to / from the other of the pair of horizontal sense lines 222-1-2; multiplexer 232-5 is operable to couple vertical sense line 203-5 to / from one of the pair of horizontal sense lines 222-2-1; multiplexer 232-6 is operable to couple vertical sense line 203-6 to / from the other of the pair of horizontal sense lines 222-2-2; multiplexer 232-7 is operable to couple vertical sense line 203-7 to / from one of the pair of horizontal sense lines 222-3-1; multiplexer 232-8 is operable to couple vertical sense line 203-8 to / from the other of the pair of horizontal sense lines 222-3-2; multiplexer 232-9 is operable to couple vertical sense line 203-9 to / from one of the pair of horizontal sense lines 222-4-1; and multiplexer 232-10 is operable to couple vertical sense line 203-10 to / from the other of the pair of horizontal sense lines 222-4-2.

[0038] Figure 3 is a top-down view of a portion of vertical 3D memory 321 in accordance with several embodiments of the present disclosure. Figure 4 The illustrated memory cells 310 represent memory cells located on the same layer (e.g., in conjunction with Figure 3 the illustrated one of layers 430).

[0039] Figure 3The memory cells 310 shown are coupled to vertical sensing lines 303. For example, memory cells 310-1, 310-2, 310-3, and 310-4 are coupled to vertical sensing lines 303-1, 303-2, 303-3, and 303-4, respectively, which are further coupled to multiplexers 332-1, 332-2, 332-3, and 332-4, respectively. Although in Figure 6 Not shown, but memory cells 310-1, 310-2, 310-3, and 310-4 are coupled to the same horizontal access line 307. Memory cells 310 coupled to the same horizontal access line 307 can be accessed together as cells. For example, control circuitry (e.g., Figure 3 The control circuit 652 shown can cause multiplexers 332-1 to 332-4 to electrically couple the corresponding vertical sensing lines (to which memory cells 310-1 to 310-4 are coupled) to one of each pair of horizontal sensing lines, such as horizontal sensing lines 322-1-1, 322-2-1, 322-3-1 and 322-4-1, to allow access to memory cells 310-1 to 310-4.

[0040] like Figure 6 As further shown, each pair of horizontal sensing lines 322 is coupled to a corresponding sensing amplifier 326, which is formed outside (and / or horizontally adjacent to) the array of vertically stacked layers of memory cells. For example, the pairs of horizontal sensing lines 322-1-1 and 322-1-2 are coupled to sensing amplifier 326-1; the pairs of horizontal sensing lines 322-2-1 and 322-2-2 are coupled to sensing amplifier 326-2; the pairs of horizontal sensing lines 322-3-1 and 322-3-2 are coupled to sensing amplifier 326-3; and the pairs of horizontal sensing lines 322-4-1 and 322-4-2 are coupled to sensing amplifier 326-4. The sensing amplifier 326 may be a differential sensing amplifier and is configured to measure (sensing the data state of the memory cell) the differential voltage between the two horizontal sensing lines of the corresponding pair. For example, in order to sense the data state of memory cell 310-1, a control circuit (e.g., Figure 4 The control circuit 652 shown causes multiplexers 332-1 and 332-5 to electrically couple vertical sensing lines 303-1 and 303-5 to horizontal sensing lines 322-1-1 and 322-1-2, respectively, activates the access line driver coupled to memory cell 310-1, and causes sensing amplifier 326-1 to sense the differential voltage between horizontal sensing lines 322-1-1 and 322-1-2. Figure 3 Further details describe how the sensing amplifier 326 and the multiplexer 332 operate relative to the horizontal sensing line 322.

[0041] While embodiments are not so limited, vertical sense lines, such as vertical sense line 303, can be spaced apart from each other by a particular distance, such as 695 nanometers (nm), for example. Further, horizontal sense lines of each pair can be spaced apart from each other by a particular size, such as 60 nm, and a pair of horizontal sense lines can be spaced apart from horizontal sense lines of a different pair by 60 nm, although embodiments are not so limited.

[0042] Sense amplifiers 326 can be coupled to either of the two ends of a pair of horizontal sense lines 322. For example, sense amplifiers 326-1 and 326-3 are coupled to one end of pairs of horizontal sense lines 322-1 and 322-3, respectively, while sense amplifiers 326-2 and 326-4 are coupled to the opposite end of pairs of horizontal sense lines 322-2 and 322-4, respectively, as illustrated in Figure 2B While embodiments are not so limited, a sense amplifier, such as at least one of sense amplifiers 336, can run 4.6 micrometers (pm) in a D2 direction (e.g., a second direction (D2) 205 as illustrated in Figure 2A While embodiments are not so limited, a sense amplifier, such as at least one of sense amplifiers 336, can run 4.6 micrometers (pm) in a D2 direction (e.g., a second direction (D2) 205 as illustrated in Figure 3 While embodiments are not so limited, a sense amplifier, such as at least one of sense amplifiers 336, can run 4.6 micrometers (pm) in a D2 direction (e.g., a second direction (D2) 205 as illustrated in Figure 4 While not illustrated in

[0043] Figure 4 is a diagram of a portion of a vertical 3D memory according to several embodiments of the present disclosure. Figures 1 to 3 The illustrated vertical 3D memory is similar to the memory shown in Figure 4 but shown from a different perspective and with a different level of detail. A portion of a plurality of vertically stacked layers 430-1, 430-2,... 430-P of memory cells in an array is shown. Layers 430 are vertically stacked in a third direction 411 (D3). A plurality of vertical sense lines, such as vertical sense lines 403-1 through 403-8, also run through layers 430 in the third direction 411 (D3). Each vertical sense line 403 is coupled to one memory cell 410 in each layer 430.

[0044] Each layer 430-1, 430-2,... 430-P can include memory cells coupled to respective horizontal access lines that each run along a first direction 409 (D1) parallel to each other. As an example, as Figure 4As illustrated in the middle, tier 430-1 includes memory cells 410-1 and 410-5 (coupled to horizontal access line 407-1 and vertical sense lines 403-1 and 403-5, respectively), and memory cells 410-2 and 410-6 (coupled to horizontal access line 407-2 and vertical sense lines 403-2 and 403-6, respectively), memory cells 410-3 and 410-7 (coupled to horizontal access line 407-3 and vertical sense lines 403-3 and 403-7, respectively), and memory cells 410-4 and 410-8 (coupled to horizontal access line 407-4 and vertical sense lines 403-4 and 403-8, respectively). Similarly, tier 430-2 can include memory cells 410-9 and 410-13 (coupled to the same horizontal access line and vertical sense lines 403-1 and 403-5, respectively), 410-10 and 410-14 (coupled to the same horizontal access line and vertical sense lines 403-2 and 403-6, respectively), 410-11 and 410-15 (coupled to the same horizontal access line and vertical sense lines 403-3 and 403-7, respectively), and 410-12 and 410-16 (coupled to the same horizontal access line and vertical sense lines 403-4 and 403-8, respectively). Similarly, tier 430-P can include 410-Q and 410-(Q+4) (coupled to the same horizontal access line and vertical sense lines 403-1 and 403-5, respectively), 410-(Q+1) and 410-(Q+5) (coupled to the same horizontal access line and vertical sense lines 403-2 and 403-6, respectively), 410-(Q+2) and 410-(Q+6) (coupled to the same horizontal access line and vertical sense lines 403-3 and 403-7, respectively), and 410-(Q+3) and 410-(Q+7) (coupled to the same horizontal access line and vertical sense lines 403-4 and 403-8, respectively), as Figure 4 illustrated in the middle. Further, each tier 430 intersects a plurality of vertical sense lines 403 running in a third direction 411 (D3).

[0045] As Figure 4 further illustrated, vertical sense lines 403-1 through 403-4 are coupled to respective ones of a pair of horizontal sense lines 422-1 and 422-2 via respective multiplexers 432-1 through 432-4 formed below the vertically stacked memory cell array. For example, as Figure 4 illustrated in the middle, vertical sense lines 403-1 and 403-3 are coupled to horizontal sense line 422-1 via multiplexers 432-1 and 432-3, respectively, and vertical sense lines 403-2 and 403-4 are coupled to horizontal sense line 422-2 via multiplexers 432-2 and 432-4, respectively. As Figure 4As shown, the vertical sensing line 403 comprises alternating vertical sensing lines along the pair of horizontal sensing lines 422.

[0046] Multiplexer 432-1 is operable to electrically couple vertical sensing line 403-1 to / decouple horizontal sensing line 422-1 (making one of memory cells 410-1, 410-9, and 410-Q accessible); multiplexer 432-2 is operable to electrically couple vertical sensing line 403-2 to / decouple horizontal sensing line 422-2 (making one of memory cells 410-2, 410-10, and 410-(Q+1) accessible); multiplexer Device 432-3 is operable to electrically couple vertical sensing line 403-3 to / from horizontal sensing line 422-1 (making one of memory cells 410-3, 410-11, and 410-(Q+2) accessible); and multiplexer 432-4 is operable to electrically couple vertical sensing line 403-4 to / from horizontal sensing line 422-2 (making one of memory cells 410-4, 410-12, and 410-(Q+3) accessible).

[0047] As described herein, each multiplexer is operable to electrically couple a vertical sensing line to / from a corresponding horizontal sensing line. Although Figure 3 Not shown in the diagram, but a pair of horizontal sensing lines 422-1 and 422-2 can be coupled to a sensing amplifier (e.g., Figure 6 The sensing amplifier 326 shown. In order to sense the memory cell, the control circuit (e.g., Figure 2C The control circuit 652 shown can cause two multiplexers adjacent to each other and coupled to a pair of horizontal sensing lines 422 to electrically couple one vertical sensing line (to which the memory cell to be sensed) to one of the pair of horizontal sensing lines and to electrically couple another vertical sensing line to a different one of the pair of horizontal sensing lines. For example, to sense memory cell 410-1, the control circuit can cause multiplexer 432-1 to electrically couple vertical sensing line 403-1 to horizontal sensing line 422-1, and multiplexer 432-2 to electrically couple vertical sensing line 403-2 to horizontal sensing line 422-1, while causing the remaining multiplexers 432-3 and 432-4 to decouple the remaining vertical sensing lines (e.g., vertical sensing lines 403-3 and 403-4) from the corresponding horizontal sensing lines 422-1 and 422-2. The control circuit can further activate the access line driver (e.g., in conjunction with...) Figure 5 The access line driver 228 shown provides a positive power supply to the horizontal access line 407-1, which in turn provides a differential voltage (e.g., the voltage difference between the vertical sensing lines 403-1 and 403-2) to the sensing amplifier via the horizontal sensing lines 422-1 and 422-2.

[0048] Figure 4 is a schematic illustration of a vertical sense line multiplexer 532 according to a number of embodiments of the present disclosure. The multiplexer 532 can be formed below a memory cell array including a plurality of vertical stacks of memory cells, e.g., as shown in Figure 4 The array can include a plurality of vertical sense lines coupled to the layers of memory cells, e.g., the vertical sense lines 403 shown in Figure 4 Each vertical sense line can be coupled to a respective multiplexer. For a set of vertical sense lines, the respective multiplexers are to select and / or deselect (electrically couple / decouple) the vertical sense lines to / from a horizontal sense line, e.g., the horizontal sense line 422 shown in Figure 6

[0049] The multiplexer 532 can include a first transistor 549-1 and a second transistor 549-2. The first transistor 549-1 can have a first terminal 545-1 coupled to a vertical sense line 503 and a first terminal 545-2 of the second transistor 549-2. The first transistor 549-1 can have a second terminal 525-1 coupled to a horizontal sense line 522. The second transistor 549-2 can have a second terminal 525-2 coupled to a vertical channel 547 (e.g., “DVC2”).

[0050] The multiplexer 532 can be configured such that deactivation of the first transistor 549-1 and activation of the second transistor 549-2 causes the respective vertical sense line 503 to be electrically coupled to the vertical channel 547. To deactivate the first transistor 549-1 or the second transistor 549-2, a first signal (“Vss”) can be applied to a gate 541-1 of the first transistor 549-1 or a gate 541-2 of the second transistor 549-2. To activate the first transistor 549-1, a second signal (“VEQ”) can be applied to the gate 541-1 of the first transistor 549-1. To activate the second transistor 549-2, a third signal (“Vdd”) can be applied to the gate 541-2 of the second transistor 549-2. The multiplexer 532 can be configured such that activation of the first transistor 549-1 and deactivation of the second transistor 549-2 causes the respective vertical sense line 503 to be electrically coupled to the horizontal sense line 522.

[0051] ​In at least one embodiment, the first transistor 549-1 and the second transistor 549-2 comprise n-type metal-oxide-semiconductor (NMOS) transistors. The multiplexer 532 may be formed as a semiconductor below the array circuit, sometimes referred to as an array-below complementary metal-oxide-semiconductor (cMOS) (CuA) circuit. However, for embodiments in which both transistors of the multiplexer 532 are nMOS transistors, the circuit may be referred to as an array-below nMOS circuit. The multiplexer 532 formed as an array-below nMOS occupies less space compared to the case where the multiplexer 532 is formed as an array-below cMOS. According to at least one embodiment of this disclosure, the multiplexer 532 formed as an array-below nMOS can be directly coupled below the corresponding vertical sensing line 503, such that each vertical sensing line 503 in the array can have an nMOS multiplexer 532 formed below it without sacrificing the space that would otherwise be required if a cMOS multiplexer were used. The use of cMOS multiplexers is not feasible for a given feature width in current manufacturing processes because cMOS multiplexers cannot fit within a given size.

[0052] Figure 6 This is a block diagram of an apparatus according to several embodiments of the present disclosure. Figure 6 This is a block diagram of a device in the form of a computing system 650 including a memory device 651, according to several embodiments of the present disclosure. As used herein, for example, the memory device 651, the memory array 653, and / or the host 602 may also be considered as a "device". According to an embodiment, according to the embodiment described herein, the memory device 651 may include at least one memory array 653 having memory cells formed with digital lines and body contact areas.

[0053] In this example, system 650 includes host 602 coupled to memory device 651 via interface 654. Interface 654 can pass control, address, data, and other signals between memory device 651 and host 602. The interface can include a command bus (e.g., coupled to control circuitry 652), an address bus (e.g., coupled to address circuitry 606), and a data bus (e.g., coupled to input / output (I / O) circuitry 657). In some embodiments, the command bus and address bus can comprise a common command / address bus. In some embodiments, the command bus, address bus, and data bus can be part of a common bus. The command bus can pass signals between host 602 and control circuitry 652, such as a clock signal for timing, a reset signal, a chip select, parity information, alerts, etc. The address bus can pass signals between host 602 and address circuitry 606, such as a logical address for a rank of memory in memory array 653 for a memory operation. Interface 654 can be a physical interface that employs a suitable protocol. This protocol can be custom or proprietary, or the interface can employ a standardized protocol, such as Peripheral Component Interconnect Express (PCIe), Gen-Z interconnect, Cache Coherent Interconnect for Accelerators (CCIX), etc. In some cases, control circuitry 652 is a register clock driver (RCD), such as an RCD employed on an RDIMM or LRDIMM.

[0054] Computing system 650 can be a personal laptop computer, a desktop computer, a digital camera, a cellular telephone, a memory card reader, or an Internet of Things (IoT) enabled device, among various other types of systems. Host 602 can include a number of processing resources (e.g., one or more processors, microprocessors, or some other type of controlling circuitry) capable of accessing memory 651. System 650 can include separate integrated circuits, or both host 602 and memory device 651 can be on the same integrated circuit. For example, host 602 can be a system controller of a memory system that includes a plurality of memory devices 651, with system controller 652 providing access to respective memory devices 651 by another processing resource such as a central processing unit (CPU).

[0055] In Figure 6In the example shown, host 602 is responsible for executing an operating system (OS) and / or various applications (e.g., processes) that can be loaded onto the host (e.g., from memory device 651 via controller 652). The OS and / or various applications can be loaded from memory device 651 by providing access commands from host 602 to access data comprising the OS and / or various applications to memory device 651. Host 602 can also access the data utilized by the OS and / or various applications by providing access commands to retrieve the data for execution of the OS and / or various applications to memory device 651.

[0056] For clarity, system 650 has been simplified to focus on features relevant to the present disclosure. Memory array 653 can be a DRAM array including at least one memory cell having digit lines and body contact regions formed according to the techniques described herein. For example, memory array 653 can be an unmasked DL 4F2 array, such as a 3D-DRAM memory array. Array 653 can include memory cells arranged in rows coupled by access lines (which can be referred to herein as word lines or select lines) and columns coupled by sense lines (which can be referred to herein as digit lines or data lines). While a single array 653 is shown in ​ While a single array 653 is shown in

[0057] Memory device 651 includes address circuitry 606 to latch address signals provided by interface 654. The interface can include a physical interface employing suitable protocols (e.g., a data bus, an address bus, and a command bus, or a combined data / address / command bus). Such protocols can be custom or proprietary, or interface 654 can employ standardized protocols, such as Peripheral Component Interconnect Express (PCIe), Gen-Z, CCIX, etc. Row decoder 608 and column decoder 612 receive and decode address signals to access memory array 653. Data can be read from memory array 653 by sensing voltage and / or current changes on the sense lines using sense circuitry 655. Sense circuitry 655 can include, for example, sense amplifiers that can read and latch a page (e.g., a row) of data from memory array 653. I / O circuitry 657 can be used for bidirectional data communication between host 602 and memory device 651 via interface 654. Read / write circuitry 613 is used to write data to and read data from memory array 653. As an example, circuitry 613 can include various drivers, latching circuitry, etc.

[0058] The control circuit 652 decodes signals provided by the host 602. The signals can be commands provided by the host 602. These signals can include chip enable signals, write enable signals, and address latch signals used to control the operations performed on the memory array 653, including data read, data write, and data erase operations. In various embodiments, the control circuit 652 is responsible for executing instructions from the host 602. The control circuit 652 can comprise a state machine, a sequencer, and / or some other type of control circuit, which can be implemented in hardware, firmware, or software, or any combination of the three. In some instances, the host 602 can be a controller that is external to the memory device 651. For example, the host 602 can be a memory controller coupled to a processing resource of a computing device.

[0059] The term semiconductor may, for example, refer to a material, wafer, or substrate, and includes any base semiconductor structure. "Semiconductor" should be understood as including silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin-film transistor (TFT) technology, doped and undoped semiconductors, epitaxial semiconductors supported by base semiconductor structures, as well as other semiconductor structures. Furthermore, when reference is made to a semiconductor in the preceding description, previous process steps can have been utilized to form regions / junctions in the base semiconductor structure, and the term semiconductor can include the underlying material as well as the regions / junctions formed over the base semiconductor structure.

[0060] It should be recognized that the term vertical accounts for variations from "exact" vertical due to normal manufacturing, measurement, and / or assembly variations, and one of ordinary skill in the art would understand the meaning of the term "vertical." For example, vertical can correspond to the z-direction. As used herein, when a particular element is "adjacent" to another element, the particular element can cover the other element, can be above the other element, or lateral to the other element, and / or can be in direct physical contact with the other element. For example, lateral can refer to a horizontal direction (e.g., a y-direction or an x-direction) that can be perpendicular to the z-direction.

[0061] While specific embodiments have been shown and described in the present disclosure, it will be appreciated that a person of ordinary skill in the art will know that arrangements calculated to achieve the same results can be substituted for the specific embodiments shown. The present disclosure is intended to cover modifications or variations of various embodiments of the disclosure. It should be understood that the above description is an illustration and not a limitation. Combinations of the above embodiments, and other embodiments not specifically described herein, will be apparent to a person of ordinary skill in the art upon attaining a full understanding of the above description. The scope of various embodiments of the present disclosure includes other applications that can use the above structures and methods. The scope of various embodiments of the present disclosure should, therefore, be determined not with reference to the above description, but should instead be determined with reference to the appended claims, along with the full range of equivalents to which such claims are entitled.

Claims

1. A method for sensing memory cells (110; 210-1, ..., 210-16; 310-1, ..., 310-4); A memory device (651) comprising 410-1, ..., 410-(Q+7)), comprising: A memory cell array (101-1, 101-2, ..., 101-N; 653), comprising: Multiple vertically stacked layers of memory cells (430-1, ..., 430-P); Correspondingly, multiple horizontal access lines (107-1, ..., 107-B; 207-1, ..., 207-16; 407-1, ..., 407-4) are coupled to each of the multiple vertically stacked layers; and Multiple vertical sensing lines (103-1, ..., 103-A; 203-1, ..., 203-10; 303-1, ..., 303-4; 403-1, ..., 403-8) are coupled to each of the multiple vertically stacked layers; The semiconductor below the array includes a plurality of multiplexers (232-1, ..., 232-16; 332-1, ..., 332-4; ​​432-1, ..., 432-4), each of which is coupled to a corresponding vertical sensing line and to a corresponding horizontal sensing line (222-1-1, 222-1-2, ..., 222-4-1, 222-4-2; 322-1-1, 322-1-2, ..., 322-4-1, 322-4-2; 422-1, 422-2); and Multiple sensing amplifiers (226-1, ..., 226-4; 326-1, ..., 326-4) are each coupled to a corresponding pair of horizontal sensing lines (222-1-1, 222-1-2, ..., 222-4-1, 222-4-2; 322-1-1, 322-1-2, ..., 322-4-1, 322-4-2; 422-1, 422-2); Each of the plurality of multiplexers includes a corresponding pair of transistors (549-1, 549-2); and The transistors of the corresponding pairs are configured such that: Activation of the first of the corresponding pair of transistors causes the corresponding vertical sensing line to be electrically coupled to the corresponding horizontal sensing line; and Activation of the second of the corresponding pair of transistors causes the corresponding vertical sensing line to be electrically decoupled from the corresponding horizontal sensing line.

2. The memory device according to claim 1, wherein: The first horizontal sensing line of the corresponding pair is coupled to the first subgroup of the plurality of vertical sensing lines via the first subgroup of the plurality of multiplexers; as well as The second horizontal sensing line of the corresponding pair is coupled to the second subgroup of the plurality of vertical sensing lines via the second subgroup of the plurality of multiplexers.

3. The memory device of claim 2, wherein the first subgroup and the second subgroup of vertical sensing lines comprise alternating vertical sensing lines along the horizontal sensing lines of the respective pair.

4. The memory device according to any one of claims 1 to 3, wherein: Each of the plurality of vertical sensing lines is coupled to a different memory cell (110; 210-1, ..., 210-16; 310-1, ..., 310-4; 410-1, ..., 410-(Q+7)) in each of the plurality of vertically stacked layers; and The plurality of sensing amplifiers includes differential sensing amplifiers.

5. The memory device according to any one of claims 1 to 3, wherein each of the plurality of multiplexers comprises an n-type metal-oxide-semiconductor nMOS transistor.

6. The memory device according to any one of claims 1 to 3, wherein the plurality of sense amplifiers are horizontally adjacent to the memory cell array.

7. A method for sensing memory cells (110; 210-1, ..., 210-16; 310-1, ..., 310-4); A memory device (651) comprising 410-1, ..., 410-(Q+7)), comprising: An array memory cell (101-1, 101-2, ..., 101-N; 653) includes multiple vertically stacked layers (430-1, ..., 430-P) of memory cells, the multiple vertically stacked layers of memory cells being coupled to multiple horizontal access lines (107-1, ..., 107-B; 207-1, ..., 207-16; 407-1, ..., 407-4) and coupled to multiple vertical sensing lines (103-1, ..., 103-A; 203-1, ..., 203-10; 303-1, ..., 303-4; 403-1, ..., 403-8); The semiconductor circuit formed beneath the array includes: Multiple multiplexers (232-1, ..., 232-16; 332-1, ..., 332-4; ​​432-1, ..., 432-4) are formed below the multiple vertically stacked layers of the memory cells, each of the multiple multiplexers being coupled to a corresponding one of the multiple vertical sensing lines; and Multiple pairs of horizontal sensing lines (222-1-1, 222-1-2, ..., 222-4-1, 222-4-2; 322-1-1, 322-1-2, ..., 322-4-1, 322-4-2; 422-1, 422-2) are coupled to the multiple multiplexers; A semiconductor circuit formed outside the array includes a plurality of sense amplifiers (226-1, ..., 226-4; 326-1, ..., 326-4), each of the plurality of sense amplifiers being coupled to a corresponding one of the plurality of pairs of horizontal sense lines; and A control circuit (652) is configured to cause a first portion of the plurality of multiplexers to electrically couple a first portion of the plurality of vertical sensing lines to the first of each of the plurality of pairs of horizontal sensing lines in order to sense the memory cells coupled to the first horizontal access lines (107-1, ..., 107-B; 207-1, ..., 207-16; 407-1, ..., 407-4) of the plurality of horizontal access lines, wherein the first portion of the plurality of vertical sensing lines is coupled to the first horizontal access line of the plurality of horizontal access lines; Each of the plurality of multiplexers includes a corresponding pair of transistors; and The transistors of the corresponding pairs are configured such that: Activation of the first of the corresponding pair of transistors causes the corresponding vertical sensing line to be electrically coupled to the corresponding horizontal sensing line; and Activation of the second of the corresponding pair of transistors causes the corresponding vertical sensing line to be electrically decoupled from the corresponding horizontal sensing line.

8. The memory device of claim 7, wherein the control circuitry is configured such that a second portion of the plurality of multiplexers electrically decouples a second portion of the plurality of vertical sensing lines from the first of each of the plurality of pairs of horizontal sensing lines, wherein the second portion of the plurality of vertical sensing lines is not coupled to the first horizontal access line of the plurality of horizontal access lines.

9. The memory device according to claim 7, wherein: The second portion of the plurality of vertical sensing lines is coupled to the second of each of the plurality of pairs of horizontal sensing lines; and The control circuit is configured such that the second portion of the plurality of multiplexers electrically couples the second portion of the plurality of vertical sensing lines to the second of each of the plurality of pairs of horizontal sensing lines, wherein: Each of the second portions of the plurality of vertical sensing lines is respectively adjacent to a corresponding location in the first portion of the plurality of vertical sensing lines; and The second portion of the plurality of vertical sensing lines is not coupled to the first horizontal sensing line among the plurality of pairs of horizontal sensing lines.

10. The memory device according to claim 9, wherein: The third portion of the plurality of multiplexers is coupled to the second of each of the plurality of pairs of horizontal sensing lines and the remainder of the plurality of vertical sensing lines; and The control circuit is configured such that the third portion of the plurality of multiplexers decouples the remaining portions of the plurality of vertical sensing lines from the second electrical connection in each of the plurality of pairs of horizontal sensing lines.

11. The memory device according to claim 7, wherein: Each of the plurality of horizontal sensing lines is coupled to a corresponding one of the plurality of access line drivers (228); and The control circuit is configured to activate the first of the plurality of access line drivers coupled to the first horizontal sensing line in order to sense the memory cell.

12. The memory device of claim 11, wherein the control circuitry is configured to deactivate the remaining one of the plurality of access line drivers not coupled to the first horizontal sensing line.

13. The memory device according to any one of claims 7 to 12, wherein a first portion of the plurality of multiplexers is coupled to the first of each of the plurality of pairs of horizontal sensing lines, and a second portion of the plurality of multiplexers is coupled to the second of each of the plurality of pairs of horizontal sensing lines.

14. The memory device according to any one of claims 7 to 12, wherein a first portion of the plurality of sense amplifiers is coupled to a first end of the plurality of pairs of horizontal sense lines, and a second portion of the plurality of sense amplifiers is coupled to a second end of the plurality of pairs of horizontal sense lines opposite to the first end.

15. The memory device according to any one of claims 7 to 12, further comprising a plurality of sub-access line drivers (228), wherein: A first portion of the plurality of sub-access line drivers is coupled to a first end of the plurality of horizontal access lines; and The second portion of the plurality of sub-access line drivers is coupled to the second end of the plurality of horizontal access lines opposite to the first end.

16. A memory cell (110; 210-1, ..., 210-16; 310-1, ..., 310-4) in a sensing array (101-1, 101-2, ..., 101-N; 653); The method of 410-1, ..., 410-(Q+7)) includes: In each of the plurality of vertical stacked layers (430-1, ..., 430-P) coupled to a memory cell, a particular horizontal access line (107-1, ..., 107-B; 207-1, ..., 207-16; 407-1, ..., 407-4) coupled to the memory cell is activated; The first vertical sensing lines (103-1, ..., 103-A; 203-1, ..., 203-10; 303-1, ..., 303-4; 432-1, ..., 432-4) are electrically coupled to the first horizontal sensing lines (222-1-1, 222-1-2, ..., 222-4-1, 222-4-2; 322-1-1, 322-1-2, ..., 322-4-1, 322-4-2; 422-1, 422-2) via a first multiplexer (232-1, ..., 232-16; 332-1, ..., 332-4; ​​432-1, ..., 432-2) in the semiconductor below the array, wherein the first vertical sensing lines are coupled to the memory cells; The second vertical sensing lines (103-1, ..., 103-A; 203-1, ..., 203-10; 303-1, ..., 303-4; 432-1, ..., 432-4) are electrically coupled to the second horizontal sensing lines (222-1-1, 222-1-2, ..., 222-4-1, 222-4-2; 322-1-1, 322-1-2, ..., 322-4-1, 322-4-2; 422-1, 422-2) via a second multiplexer (232-1, ..., 232-16; 332-1, ..., 332-4; ​​432-1, ..., 432-2), wherein the second vertical sensing lines are not coupled to the memory cells; as well as The memory cell is sensed using a differential sensing amplifier coupled to the first horizontal sensing line and the second horizontal sensing line, wherein the differential sensing amplifier is horizontally adjacent to the plurality of vertically stacked layers of the memory cell; Each of the first multiplexer and the second multiplexer includes a corresponding pair of transistors; and The transistors of the corresponding pairs are configured such that: Activation of the first of the corresponding pair of transistors causes the corresponding vertical sensing line to be electrically coupled to the corresponding horizontal sensing line; and Activation of the second of the corresponding pair of transistors causes the corresponding vertical sensing line to be electrically decoupled from the corresponding horizontal sensing line.

17. The method of claim 16, further comprising: Activate the access line driver (228) coupled to the first horizontal sensing line; as well as Deactivate the access line driver (228) coupled to the second horizontal sensing line.

18. The method of claim 16, further comprising, before sensing the memory cell: Electrically decouple at least one other vertical sensing line from the first horizontal sensing line; and At least one other vertical sensing line is electrically decoupled from the second horizontal sensing line.

19. The method according to any one of claims 16 to 18, wherein electrically coupling the first vertical sensing line to the first horizontal sensing line via the first multiplexer comprises applying a signal to the gate (541-1, 541-2) of a pair of transistors (549-1, 549-2) including the first multiplexer.

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