Storage device and method of operating a storage device

Abstract

A storage device includes a non-volatile memory device and a memory controller that controls the non-volatile memory device. The non-volatile memory device includes an array of storage cells. The array of storage cells includes a normal cell region, a parity cell region, and a redundant cell region. A first bit line is connected to the normal cell region and the parity cell region, and a second bit line is connected to the redundant cell region. The memory controller includes an error-correcting code (ECC) engine to generate parity data. The memory controller stores user data in the normal cell region, controls the non-volatile memory device to perform a column repair on a first defective bit line in the first bit line, allocates an additional column address to the first defective bit line and the second bit line, and stores at least a portion of the parity data in a region corresponding to the additionally allocated column address.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application 10-2021-0017619, filed on February 8, 2021, with the Korean Intellectual Property Office (KIPO), the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] The example embodiments generally relate to storage devices, and more specifically to storage devices and methods of operating storage devices. Background Technology

[0004] Semiconductor memory devices are classified into volatile memory and non-volatile memory. Data stored in volatile memory is lost when power is turned off. Data stored in non-volatile memory is retained even after power is turned off. Flash memory devices are an example of non-volatile memory devices. Flash memory devices have large storage capacity, relatively high noise immunity, and low power consumption. Therefore, flash memory devices are used in a variety of fields. For example, mobile systems such as smartphones or tablet PCs can use flash memory as a storage medium.

[0005] The storage capacity of semiconductor memory devices increases with advancements in manufacturing processes. However, as the integration density of semiconductor memory devices increases, the number of defective memory cells increases, and the yield of semiconductor memory devices decreases. Defective memory cells can be repaired using redundant memory cells or by performing error-correcting code (ECC) operations. The yield and performance of semiconductor memory devices can depend on the efficiency of this repair scheme. Summary of the Invention

[0006] At least one exemplary embodiment provides a storage device that can improve the availability of redundant cell regions and improve the error correction efficiency of an error correction code (ECC) engine.

[0007] At least one exemplary embodiment provides a method for operating a storage device that can improve the availability of redundant cell regions and improve the error correction efficiency of the ECC engine.

[0008] According to an example embodiment, the storage device includes a non-volatile storage device and a memory controller for controlling at least one non-volatile storage device. The non-volatile storage device includes a cell array, page buffer circuitry, and an address decoder. The cell array includes a normal cell region, a parity cell region, and a redundant cell region associated with repairing defective columns in the normal cell region and the parity cell region. The cell array includes a plurality of non-volatile memory cells coupled to a first bit line and a second bit line. The first bit line is connected to the normal cell region and the parity cell region. The second bit line is connected to the redundant cell region. The page buffer circuitry is connected to the cell array via the first and second bit lines. The address decoder is connected to the cell array via a plurality of word lines. The memory controller includes an error correction code (ECC) engine that generates parity data by performing ECC encoding on user data to be stored in the normal cell region. The memory controller stores user data in a normal cell area, controls a non-volatile memory device to perform column repair on a first defective bit line in the first bit line, assigns additional column addresses to the first defective bit line and the second bit line, and stores at least a portion of the parity data in an area corresponding to the additionally assigned column addresses.

[0009] According to an example embodiment, a method for operating a storage device is provided, the storage device including a non-volatile storage device and a memory controller for controlling the non-volatile storage device. According to the method, parity data is generated by an error correction code (ECC) engine in the memory controller by performing ECC encoding on user data to be stored in a normal cell region of a memory cell array of the non-volatile storage device, the memory cell array including a normal cell region, a parity cell region, and a redundant cell region associated with repairing defective columns in the normal cell region and the parity cell region. Column repair is performed on a first defective bit line in the first bit line connected to the normal cell region and the parity cell region. The memory controller assigns additional column addresses to the first defective bit line and a second bit line connected to the redundant cell region. The non-volatile storage device stores at least a portion of the parity data in the region corresponding to the additionally assigned column address.

[0010] According to an example embodiment, the storage device includes a non-volatile storage device and a memory controller for controlling the non-volatile storage device. The non-volatile storage device includes a cell array, page buffer circuitry, and an address decoder. The cell array includes a normal cell region, a parity cell region, and a redundant cell region associated with repairing defective columns in the normal cell region and the parity cell region. The cell array includes a plurality of non-volatile memory cells coupled to a first bit line and a second bit line. The first bit line is connected to the normal cell region and the parity cell region. The second bit line is connected to the redundant cell region. The page buffer circuitry is connected to the cell array via the first and second bit lines. The address decoder is connected to the cell array via a plurality of word lines. The memory controller includes an error correction code (ECC) engine that generates parity data by performing ECC encoding on user data to be stored in the normal cell region. The memory controller stores user data in the normal cell region, controls the non-volatile storage device to perform column repair on a first defective bit line in the first bit line, assigns additional column addresses to the first defective bit line and the second bit line, and stores at least a portion of the parity data in the region corresponding to the additionally assigned column addresses. The non-volatile memory device also includes control circuitry. The control circuitry controls the page buffer circuitry to perform column repair on a first defective bit line, associated with a given defective column. The control circuitry skips column repair on at least a portion of a second defective bit line, stores the defective column address information of said portion of the second defective bit line in an information block, and provides the defective column address information to the memory controller in response to a request from the memory controller. The ECC engine selectively uses the defective column address information and performs ECC decoding on user data read from at least one non-volatile memory device based on parity data from the non-volatile memory device.

[0011] Therefore, the non-volatile storage device stores the column address of the unrepaired defective bit line in the normal cell region as defective column address information in the information block. The memory controller assigns additional column addresses to the repaired bit line and a second bit line, which is coupled to a redundant cell region associated with the repaired defective bit line in the normal cell region. The non-volatile storage device stores a portion of the parity data in the region corresponding to the additionally assigned column address. The ECC engine in the memory controller performs ECC decoding on the user data based on the defective column address information and the parity data with the added bits. Thus, the storage device can improve error correction efficiency and provide availability of redundant cell regions. Attached Figure Description

[0012] The illustrative, non-limiting exemplary embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0013] Figure 1 This is a block diagram illustrating an electronic device according to an example embodiment.

[0014] Figure 2 This illustrates an example embodiment. Figure 1 A block diagram of the storage device.

[0015] Figure 3 This illustrates an example embodiment. Figure 2 A block diagram of the memory controller in a storage device.

[0016] Figure 4 This illustrates an example embodiment. Figure 3 A block diagram of an example ECC engine in a memory controller.

[0017] Figure 5 This illustrates an example embodiment. Figure 2 A block diagram of a non-volatile storage device in a storage device.

[0018] Figure 6 It shows Figure 5 A block diagram of the storage cell array.

[0019] Figure 7 It shows Figure 6 A circuit diagram of one of the memory blocks in the memory.

[0020] Figure 8 It shows Figure 7 An example of the structure of a string of cells in a storage block.

[0021] Figure 9 This illustrates an example embodiment. Figure 5 A block diagram of the control circuit in a non-volatile storage device.

[0022] Figure 10 This illustrates an example embodiment. Figure 5 Block diagram of a voltage generator in a non-volatile storage device.

[0023] Figure 11 This illustrates an example embodiment. Figure 5 A block diagram of an example of a memory cell array in a non-volatile storage device.

[0024] Figure 12A It shows when Figure 12A The graph shows the threshold voltage distribution of the memory cells when the memory cell array includes 3-bit three-level cells.

[0025] Figure 12B It shows Figure 12AThe graph shows the change in the threshold voltage of the memory cell.

[0026] Figure 13 This is a diagram illustrating the operation of determining the level of the read voltage required for error correction according to an example embodiment.

[0027] Figure 14 An example of ECC decoding of a storage device according to an example embodiment is shown.

[0028] Figure 15 and Figure 16 This is used to illustrate the operation of storing defective column address information in an information block according to an example embodiment.

[0029] Figure 17 An example embodiment is shown. Figure 2 Example operation of storage devices.

[0030] Figures 18 to 20 This is a flowchart illustrating a programming operation that assigns additional column addresses to defective bit lines in response to a memory controller, according to an example embodiment.

[0031] Figure 21 and Figure 22 This is a diagram illustrating the operation of a storage device according to an example embodiment.

[0032] Figure 23 This is a cross-sectional view of a non-volatile storage device according to an example embodiment.

[0033] Figure 24 This is a block diagram illustrating a storage device including a non-volatile storage device according to an example embodiment. Detailed Implementation

[0034] The inventive concept will be described more fully below with reference to the accompanying drawings, in which some exemplary embodiments are shown.

[0035] Figure 1 This is a block diagram illustrating an electronic device according to an example embodiment.

[0036] Reference Figure 1 The electronic device 10 includes a host 20 (e.g., a host device) and a storage device (or memory system) 30. The storage device 30 may include a memory controller (or storage controller) 100 and at least one non-volatile storage device 200. The host 20 can control the overall operation of the storage device 30.

[0037] The non-volatile storage device 200 can be implemented using NAND flash memory.

[0038] The memory controller 100 can exchange signals such as commands, addresses, and data with the host 20. The memory controller 100 can write data to the non-volatile memory device 200 and read data from the non-volatile memory device 200 according to commands from the host 20.

[0039] Figure 2 This illustrates an example embodiment. Figure 1 A block diagram of the storage device.

[0040] Reference Figure 2 The storage device 30 includes a memory controller 100 and at least one non-volatile storage device 200.

[0041] In the example embodiment, each of the memory controller 100 and at least one non-volatile memory device 200 may be provided in the form of a chip, package, or module. Alternatively, the memory controller 100 and at least one non-volatile memory device 200 may be packaged using one of the following: package-on-package (PoP), ball grid array (BGA), chip-scale package (CSP), plastic leaded chip carrier (PLCC), plastic dual in-line package (PDIP), disk-packaged die, wafer-level die, chip-on-board (COB), ceramic dual in-line package (CERDIP), plastic metric quad flat package (MQFP), small outline package (SOIC), compact small outline package (SSOP), thin small outline package (TSOP), thin quad flat package (TQFP), system-in-package (SIP), multi-chip package (MCP), wafer-level fabrication package (WFP), wafer-level processing stacked package (WSP), etc.

[0042] The non-volatile memory device 200 can perform erase, program, or write operations under the control of the memory controller 100. The non-volatile memory device 200 receives commands (CMD), address (ADDR), user data (DATA), and parity data (PRT) from the memory controller 100 via input / output lines to perform these operations. Furthermore, the non-volatile memory device 200 receives control signals (CTRL) from the memory controller 100 via control lines. Additionally, the non-volatile memory device 200 receives power (PWR) from the memory controller 100 via power lines.

[0043] The non-volatile storage device 200 can store the column address of the column in the information block where the error occurs repeatedly as the defective column address. The non-volatile storage device 200 can provide the memory controller 100 with the defective column address DCAI associated with a given defective column.

[0044] The memory cells of the non-volatile memory device 200 may have physical characteristics where the threshold voltage distribution varies due to factors such as programming elapsed time, temperature, programming interference, or read interference. For example, due to the aforementioned reasons, the data stored in the non-volatile memory device 200 may become erroneous. The memory controller 100 utilizes various error correction techniques to correct such errors. For example, the memory controller 100 includes an error correction code (ECC) engine 120 and a processor 110 for controlling the ECC engine 120.

[0045] During a read operation, the memory controller 100 can read data stored in the first page of the non-volatile memory device 200 using a default read voltage set. The default read voltage set may include predetermined read voltages. The ECC engine 120 can detect and correct errors included in the data read from the non-volatile memory device 200. In the example embodiment, the ECC engine 120 is implemented in hardware.

[0046] The data read during a read operation may contain more error bits than the ECC engine 120 can correct. In this case, the ECC engine 200 cannot correct the data, which can be referred to as an "Uncorrectable Error Correction Code (UECC) error". Data with a UECC error can be referred to as "UECC data".

[0047] For example, when data read using the default read voltage set includes a UECC error, processor 110 can adjust the read voltage set of non-volatile memory device 200. Memory controller 100 sends address ADDR, command CMD, and control signal CTRL, causing non-volatile memory device 200 to perform a read operation using the adjusted read voltage set.

[0048] The adjusted set of read voltages can be included in the control signal CTRL or the command CMD. The ECC engine 120 can detect and correct errors in the data read using the adjusted set of read voltages. For example, information indicating the values ​​of a set of voltages included in the adjusted set of read voltages can be included in the control signal CTRL or the command CMD.

[0049] In an example embodiment, processor 110 adjusts the read voltage set a predetermined number of times, and ECC engine 120 detects and corrects errors in data read using the adjusted read voltage set. For example, memory controller 100 may repeat the execution of a set of operations for adjusting the read voltage set a predetermined number of times, reading data using the adjusted read voltage set, and correcting errors in the read data.

[0050] When an error in reading data is corrected during the iteration of this set of operations, the memory controller 100 can output the corrected data to the host 20. For example, when iterating read operations under the control of the processor 110, the read data or a specific page of the read data is stored in... Figure 3 The buffer 130 is located in the buffer 130. The buffer 130 may be static random access memory (SRAM).

[0051] When an error in reading data after an iteration of the set of operations is not corrected (i.e., when a UECC error occurs), the memory controller 100 can determine the starting voltage set for performing the valleysearch operation based on the data stored in the buffer 130.

[0052] In the example embodiment, the iteration of adjusting the read voltage set and reading data using the adjusted read voltage set can be omitted.

[0053] When errors in the read data are not corrected after a read operation based on a default read voltage set or after iterations of that set of operations, the processor 110 can select a programming state that includes the highest error bit rate from the data stored in the buffer 130, and can determine the read voltage corresponding to the selected programming state as the starting voltage set. The processor 110 can perform a valley search operation based on the determined starting voltage set to determine the optimal read level voltage, and can perform a recovery read operation on the read data based on the optimal read level voltage.

[0054] To determine the optimal read voltage level, the processor 110 can set a search region defined by the start read voltage and the end read voltage. It can determine whether the search region belongs to the reference region. If the search region does not belong to the reference region, the search region can be changed. If the search region belongs to the reference region, a new read voltage can be searched to determine the optimal read voltage level.

[0055] Processor 110 can control ECC engine 120 to perform hard-decision decoding or soft-decision decoding on the read data. Processor 110 can control ECC engine 120 to perform hard-decision decoding on the read data based on a default set of read voltages. Alternatively, ECC engine 120 can perform soft-decision decoding on the read data based on a soft-decision read voltage that is offset from the hard-decision read voltage used in hard-decision decoding.

[0056] ECC engine 120 can generate parity data PRT, including first parity data and second parity data, by performing ECC encoding on user data to be stored in the memory cell array of non-volatile storage device 200. Memory controller 100 can store at least a portion of the parity data PRT in an area corresponding to the repair column and in a redundant cell area of ​​the memory cell array.

[0057] ECC Engine 120 can perform hard-decision decoding using the first parity data, and can perform soft-decision decoding using the defective column address information DCAI, the first parity data, and the second parity data.

[0058] Figure 3 This illustrates an example embodiment. Figure 2 A block diagram of the memory controller in a storage device.

[0059] Reference Figure 2 and Figure 3 The memory controller 100 includes a processor 110, an ECC engine 120, a buffer 130, a random number generator 140, a host interface 150, a read-only memory (ROM) 160, and a non-volatile memory interface 170, which are connected via a bus 105.

[0060] Processor 110 can control the overall operation of memory controller 100. Buffer 130 can store defective column address information DCAI provided from non-volatile memory device 200, and can provide defective column address information DCAI to ECC engine 120. ROM 160 can store various information used by memory controller 100 in firmware form.

[0061] ECC Engine 120 can generate Parity Data PRT, perform hard-decision decoding by using the first parity data of the Parity Data PRT, and perform soft-decision decoding by using Defect Column Address Information DCAI, the first parity data of the Parity Data PRT, and the second parity data.

[0062] Randomization generator 140 can randomize data to be stored in non-volatile storage device 200. For example, randomization generator 140 can randomize data to be stored in non-volatile storage device 200 via word lines.

[0063] Randomization generator 140 can process data such that the programming states of the memory cells connected to a word line have the same ratio. For example, if the memory cells connected to a word line are quad-level cells (QLCs) (each QLC stores 4 bits of data), each of the memory cells can have an erase state and one of the first to fifteenth programming states. In this case, randomization generator 140 can randomize the data such that the number of memory cells with erase states and the number of memory cells with the first to fifteenth programming states in the memory cells connected to a word line can be substantially the same. For example, the memory cells storing randomized data have the same number of programming states. Randomization generator 140 can derandomize data read from non-volatile storage devices.

[0064] Randomization generator 140 can randomize page data. For ease of understanding, the ideal operation of randomization generator 140 has been described. However, this disclosure is not limited thereto. For example, randomization generator 140 can randomize data such that in a memory cell connected to a word line, the number of memory cells having an erase state and the number of memory cells having a first programming state through a fifteenth programming state can each be approximately the same value. For example, the memory cells storing randomized data have a similar number of programming states.

[0065] The memory controller 100 can communicate with the host 20 via the host interface 150. For example, the host interface 150 can support communication protocols such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC, Peripheral Component Interconnect (PCI), PCI-express, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Mobile Industry Processor Interface (MIPI), Non-Volatile Memory Express (NVMe), Universal Flash Memory (UFS), etc. The memory controller 100 can communicate with the non-volatile storage device 200 via the non-volatile memory interface 170.

[0066] Figure 4 This illustrates an example embodiment. Figure 3 A block diagram of an example ECC engine in a memory controller.

[0067] Reference Figure 4 The ECC engine 120 includes an ECC encoder 121 (e.g., encoder circuitry), an ECC decoder 123 (e.g., ECC decoder circuitry), and a memory 125, and the memory 125 can store ECC 127.

[0068] ECC encoder 121 can generate parity data PRT, including first parity data PRT1 and second parity data PRT2, by performing ECC encoding on user data based on ECC 127. First parity data PRT1 can be used to correct errors in read data after column repair is performed on the data by non-volatile storage device 200, while second parity data PRT2 can be used together with first parity data PRT1 to correct errors in data where column repair is skipped or in data where soft-decision decoding is performed by non-volatile storage device 200.

[0069] Furthermore, the ECC encoder 121 can adjust the number of bits in the second parity data PRT2 generated during ECC encoding based on the defect column address information DCAI. For example, the ECC encoder 121 can increase or decrease the number of bits in the second parity data PRT2 based on the number of defect bit lines specified by the defect column address information DCAI. When the ECC encoder 121 performs ECC encoding, it can increase or decrease the number of bits in the second parity data PRT2 by using part or all of ECC 127.

[0070] During a read operation, the ECC decoder 123 can receive user data DATA and parity data PRT including first parity data PRT1 and second parity data PRT2 from the non-volatile storage device 200, receive defect column address information DCAI from the buffer 130, perform hard-decision decoding on user data DATA using the first parity data PRT1, perform soft-decision decoding on user data DATA using the defect column address information DCAI, the first parity data PRT1 and the second parity data PRT2, and provide the processor 110 with a decoding result signal DRS indicating the decoding result.

[0071] Figure 5 This illustrates an example embodiment. Figure 2 A block diagram of a non-volatile storage device in a storage device.

[0072] Reference Figure 5 The non-volatile storage device 200 includes a memory cell array 300, an address decoder 430, a page buffer circuit 410, a data input / output circuit 420, a control circuit 500, and a voltage generator 700.

[0073] The memory cell array 300 can be coupled to the address decoder 430 via the serial select line SSL, multiple word lines WL, and the ground select line GSL. Additionally, the memory cell array 300 can be coupled to the page buffer circuit 410 via multiple bit lines BL.

[0074] The memory cell array 300 may include multiple memory cells coupled to multiple word lines WL and multiple bit lines BL.

[0075] In an example embodiment, the memory cell array 300 may be a three-dimensional memory cell array formed on a substrate in a three-dimensional structure (or a vertical structure). In this case, the memory cell array 300 may include vertically oriented vertical cell strings, such that at least one memory cell is located above another memory cell.

[0076] Figure 6 It shows Figure 5 A block diagram of the storage cell array.

[0077] Reference Figure 6 The storage cell array 300 may include a plurality of storage blocks BLK1 to BLKz (z is an integer greater than 2) extending along a first direction to a third direction D1, D2, and D3. In an embodiment, storage blocks BLK1 to BLKz are formed by... Figure 4 The address decoder 430 is selected. For example, the address decoder 430 can select the storage block BLK corresponding to the block address among storage blocks BLK1 to BLKz.

[0078] Figure 7 It shows Figure 6 A circuit diagram of one of the memory blocks in the memory.

[0079] Figure 7 The memory block BLKi can be formed on the substrate in a three-dimensional (or vertical) structure. For example, multiple strings of memory cells included in the memory block BLKi can be formed along a direction PD perpendicular to the substrate.

[0080] Reference Figure 7 The memory block BLKi may include memory cell strings NS11 to NS33 coupled between bit lines BL1, BL2, and BL3 and the common source line CSL. Each of the memory cell strings NS11 to NS33 may include a string select transistor SST, multiple memory cells MC1 to MC8, and a ground select transistor GST. Figure 7 In the example, each of the storage cell strings NS11 to NS33 is shown as comprising eight storage cells MC1 to MC8. However, the example embodiment is not limited thereto. In some example embodiments, each of the storage cell strings NS11 to NS33 may include any number of storage cells.

[0081] The serial select transistor SST can be connected to the corresponding serial select lines SSL1 to SSL3. Multiple memory cells MC1 to MC8 can be connected to their respective word lines WL1 to WL8. The ground select transistor GST can be connected to the corresponding ground select lines GSL1 to GSL3. The serial select transistor SST can be connected to the corresponding bit lines BL1, BL2, and BL3, and the ground select transistor GST can be connected to the common source line CSL.

[0082] Word lines of the same height (e.g., WL1) can be connected together, and ground select lines GSL1 to GSL3 and string select lines SSL1 to SSL3 can be separated. Figure 7 In the example, memory block BLKi is shown coupled to eight word lines WL1 to WL8 and three bit lines BL1 to BL3. However, the example embodiment is not limited to this. In some example embodiments, memory cell array 300 may be coupled to any number of word lines and bit lines.

[0083] Figure 8 It shows Figure 7 An example of the structure of a string of cells in a storage block.

[0084] Reference Figure 7 and Figure 8 The columnar object PL is disposed on the substrate SUB in the unit string NS11, such that the columnar object PL extends in a direction perpendicular to the substrate SUB to contact the substrate SUB. Figure 8 Each of the ground select line GSL1, word lines WL1 to WL8, and string select line SSL shown can be formed of a conductive material (e.g., a metallic material) parallel to the substrate SUB. The pillar PL can be in contact with the substrate SUB through the conductive material forming the string select line SSL, word lines WL1 to WL8, and ground select line GSL.

[0085] The cross-sectional view taken along line AA′ is also shown in Figure 8 In this embodiment, a cross-sectional view of the first memory cell MC1 corresponding to the first word line WL1 is shown. The cylindrical member PL may include a cylindrical body BD. An air gap AG may be defined inside the body BD.

[0086] The substrate BD may include P-type silicon and may be the region where the channel will be formed. The pillar PL may also include a cylindrical tunnel insulating layer TI surrounding the substrate BD and a cylindrical charge trapping layer CT surrounding the tunnel insulating layer TI. A barrier insulating layer BI may be disposed between the first word line WL and the pillar PL. The substrate BD, tunnel insulating layer TI, charge trapping layer CT, barrier insulating layer BI, and first word line WL may constitute a charge trapping transistor formed along a direction perpendicular to the substrate SUB or the upper surface of the substrate SUB. The string select transistor SST, ground select transistor GST, and other memory cells may have the same structure as the first memory cell MC1.

[0087] Return to reference Figure 5 The control circuit 500 can receive command (signal) CMD and address (signal) ADDR from the memory controller 100, and can control the erase cycle, programming cycle, and read operation of the non-volatile memory device 200 based on the command signal CMD and the address signal ADDR. The programming cycle may include programming operations and programming verification operations. The erase cycle may include erase operations and erase verification operations.

[0088] For example, control circuit 500 can generate control signal CTL for controlling voltage generator 700 and control signal PCTL for controlling page buffer circuit 410 based on command signal CMD, and generate row address R_ADDR and column address C_ADDR based on address signal ADDR. Control circuit 500 can provide row address R_ADDR to address decoder 430 and column address C_ADDR to data input / output circuit 420.

[0089] Address decoder 430 can be coupled to memory cell array 300 via serial select line SSL, multiple word lines WL, and ground select line GSL. During programming or reading operations, address decoder 430 can determine one of the multiple word lines WL as the selected word line based on row address R_ADDR, and determine the remaining word lines in the multiple word lines WL as unselected word lines.

[0090] Voltage generator 700 can generate word line voltage VWL for the operation of non-volatile memory device 200 based on control signal CTL from control circuit 500. Voltage generator 700 can receive power PWR from memory controller 100. Word line voltage VWL can be applied to multiple word lines WL via address decoder 430.

[0091] For example, during an erase operation, voltage generator 700 can apply an erase voltage to the well of the memory block and can also apply a ground voltage to all word lines of the memory block. During an erase verification operation, voltage generator 700 can apply an erase verification voltage to all word lines of the memory block or apply the erase verification voltage sequentially to each word line.

[0092] For example, during programming operations, voltage generator 700 can apply a programming voltage to the selected word line and a programming pass voltage to the unselected word line. Furthermore, during programming verification operations, voltage generator 700 can apply a programming verification voltage to the selected word line and a verification pass voltage to the unselected word line.

[0093] Furthermore, during the default read operation, voltage generator 700 can apply a default read voltage to the selected word line and can also apply a read pass voltage to unselected word lines. During the resume read operation, voltage generator 700 can apply an optimal read level voltage to the selected word line.

[0094] Although not shown, voltage generator 700 can apply a disable voltage to the defective bit line, thereby preventing the memory cell coupled to the bit line from being programmed.

[0095] Page buffer circuitry 410 can be coupled to memory cell array 300 via multiple bit lines BL. Page buffer circuitry 410 may include multiple page buffers. In some example embodiments, one page buffer is connected to one bit line. In some example embodiments, one page buffer is connected to two or more bit lines.

[0096] Page buffer circuit 410 can temporarily store data to be programmed in the selected page or data read from the selected page.

[0097] Data input / output circuit 420 can be coupled to page buffer circuit 410 via data line DL. During programming operations, data input / output circuit 420 can receive user data DATA and parity data PRT from memory controller 100, and provide user data DATA and parity data PRT to page buffer circuit 410 based on column address C_ADDR received from control circuit 500. During read operations, data input / output circuit 420 can provide user data DATA and parity data PRT stored in page buffer circuit 410 to memory controller 100 based on column address C_ADDR received from control circuit 500.

[0098] Figure 9 This illustrates an example embodiment. Figure 5 A block diagram of the control circuit in a non-volatile storage device.

[0099] Reference Figure 9 The control circuit 500 includes a command decoder 510, an address buffer 520, and a control signal generator 530.

[0100] Command decoder 510 can decode command CMD to generate decoded command D_CMD, and can provide the decoded command D_CMD to control signal generator 530. Address buffer 520 can receive address signal ADDR, can provide row address R_ADDR to address decoder 430, and can provide column address C_ADDR to data input / output circuit 420. Row address R_ADDR and column address C_ADDR can be determined based on address signal ADDR.

[0101] The control signal generator 530 can receive a decoded command D_CMD, generate a control signal CTL based on the operation guided by the decoded command D_CMD, and provide the control signal CTL to the voltage generator 700. Furthermore, the control signal generator 530 can generate a control signal PCTL based on the operation guided by the decoded command D_CMD, and provide the control signal PCTL to the page buffer circuit 410.

[0102] Figure 10 This illustrates an example embodiment. Figure 5 Block diagram of a voltage generator in a non-volatile storage device.

[0103] Reference Figure 10 The voltage generator 700 includes a high-voltage generator 710 and a low-voltage generator 730. The voltage generator 700 may also include a negative voltage generator 750.

[0104] The high-voltage generator 710 can respond to the first control signal CTL1 to generate a programming voltage PGM, a programming pass voltage VPPASS, a verification pass voltage VVPASS, a read pass voltage VRPASS, and an erase voltage VERS according to the operation guided by the command CMD. Although not shown, the high-voltage generator 710 can generate an inhibit voltage. The programming voltage PGM is applied to the selected word line, the programming pass voltage VPPASS, the verification pass voltage VVPASS, and the read pass voltage VRPASS can be applied to unselected word lines, and the erase voltage VERS can be applied to the well of the memory block. The first control signal CTL1 may include multiple bits indicating the operation guided by the command CMD. The programming voltage PGM may correspond to a programming pulse.

[0105] The low-voltage generator 730 can generate a programming verification voltage VPV, a read voltage VRD, an erase verification voltage VER, and an optimal read level voltage VORD in response to a second control signal CTL2, according to an operation guided by the command CMD. The programming verification voltage VPV, read voltage VRD, optimal read level voltage VORD, and erase verification voltage VER can be applied to selected word lines according to the operation of the non-volatile memory device 200. The second control signal CTL2 may include multiple bits indicating the operation guided by the command CMD.

[0106] In response to the third control signal CTL3, the negative voltage generator 750 can generate a programming verification voltage VPV', a read voltage VRD', and an erase verification voltage VER' with negative levels, according to the operation guided by the command CMD. The third control signal CTL3 may include multiple bits indicating the operation guided by the command CMD.

[0107] Figure 11 This illustrates an example embodiment. Figure 5 A block diagram of an example of a memory cell array in a non-volatile storage device.

[0108] Reference Figure 11 The storage cell array 300a includes multiple storage blocks BLK1 to BLKz. Each of the multiple storage blocks BLK1 to BLKz may include multiple pages PAG1 to PAGq (q is an integer equal to or greater than 2).

[0109] The storage cell array 300a may include a normal cell area NCA for storing user data DATA, a parity cell area PCA for storing first parity data PRT1, and a redundant cell area RCA for repairing defective columns in the normal cell area NCA and the parity cell area PCA. In an example embodiment, a portion of the redundant cell area RCA is used to repair defective columns, while another portion of the redundant cell area RCA is used to store second parity data PRT2 of the parity data PRT. In an example embodiment, the redundant cell area RCA is used to store the second parity data PRT2.

[0110] The storage cells of the Normal Cell Area (NCA) and Parity Cell Area (PCA) can be coupled to the first bit lines BL1 to BLn, and the storage cells of the Redundant Cell Area (RCA) can be coupled to the second bit lines RBL1 to RBLm. In this embodiment, n is an integer equal to or greater than 4, and m is an integer equal to or greater than 2 and less than n.

[0111] Each page in the Normal Cell Area (NCA) and Parity Cell Area (PCA) may include multiple sectors SEC1 to SECk, and each page in the Redundant Cell Area (RCA) may include multiple redundant sectors RSEC1 to RSECg. In the embodiment, k is an integer equal to or greater than 3, and g is an integer equal to or greater than 2. When at least one of the multiple sectors SEC1 to SECk (e.g., sector SEC2) contains a defective column, the control circuit 500 can perform column repair by replacing sector SEC2 with redundant sector RSEC1. The non-volatile storage device 200 can perform column repair on a sector-by-sector basis.

[0112] The storage controller 100 can control the non-volatile storage device 200 to perform column repair on first defective bit lines BL1 to BLn that are defective in the normal cell region NCA and the parity cell region PCA. Additional column addresses can be assigned to the first defective bit lines and second bit lines RBL1 to RBLm. Second parity data PRT2 can be stored in the region corresponding to the additionally assigned column addresses, and the ECC engine 120 can perform ECC decoding by further using the second parity data PRT2. In an embodiment, the non-volatile storage device 200 may not perform column repair or may skip column repair on the second bit lines RBL1 to RBLm in the redundant cell region RCA. Defective bit lines coupled to defective columns may include first defective bit lines that perform column repair and second defective bit lines that do not perform column repair or may skip column repair.

[0113] Storage block BLK1 can correspond to information block and can store defect column address information DCAI.

[0114] Figure 12A It shows when Figure 5 The graph shows the threshold voltage distribution of the memory cells when the memory cell array includes 3-bit three-level cells.

[0115] Reference Figure 12A The horizontal axis represents the threshold voltage Vth, and the vertical axis represents the number of memory cells. When each memory cell is a 3-bit three-level cell programmed to store 3 bits, the memory cell can have an erase state E and one of the first programming states P1 to the seventh programming state P7. When the memory cell is a multi-level cell, unlike a single-level cell, small changes in the threshold voltage Vth can cause large problems due to the small intervals between the threshold voltage distributions.

[0116] The voltage level of the first read voltage Vr1 lies between the distribution of memory cells in the erase state E and the distribution of memory cells in the first program state P1. The voltage level of each of the second read voltages Vr2 to the seventh read voltage Vr7 lies between the distribution of memory cells in adjacent program states.

[0117] In the example embodiment, assuming a first read voltage Vr1 is applied, data "1" can be stored when the memory cell is turned on, and data "0" can be stored when the memory cell is turned off. However, this disclosure is not limited to this, and in other example embodiments, assuming a first read voltage Vr1 is applied, data "0" can be stored when the memory cell is turned on, and data "1" can be stored when the memory cell is turned off. Therefore, the logic level of the data can vary.

[0118] Figure 12B It shows Figure 12A The graph shows the change in the threshold voltage of the memory cell.

[0119] Reference Figure 12B The memory cells, respectively programmed into erase state E and first programming states P1 to seventh programming states P7, can have the following characteristics depending on the reading environment: Figure 12B The distribution of changes is shown. In Figure 12B In the diagram, the memory cells in the shaded area may have read errors, thereby reducing the reliability of non-volatile memory devices.

[0120] For example, when a read operation is performed on a memory device using a first read voltage Vr1, although the memory cell included in the shaded area is programmed to the first programmed state P1, the memory cell can be determined to have an erased state E due to the decrease in the threshold voltage Vth. Therefore, errors may occur during the read operation, thereby reducing the reliability of the non-volatile memory device.

[0121] When reading data from non-volatile storage device 200, the raw bit error rate (RBER) can vary depending on the voltage level of the read voltage. The optimal or alternative, desired voltage level for the read voltage can be determined based on the distribution pattern of the memory cell MCELs. Therefore, due to changes in the distribution of memory cells, the optimal or alternative, desired voltage level for the read voltage required to read data from the non-volatile storage device may change. Therefore, in order to quickly determine the optimal or alternative, desired voltage level for the read operation by taking into account the read environment of the non-volatile storage device, defensive code can be selectively executed.

[0122] Figure 13 This is a diagram illustrating the operation of determining the level of the read voltage used for error correction according to an example embodiment.

[0123] Reference Figure 13 The data states programmed into the memory cells must be separated from adjacent data states Si and Si+1 by a predetermined, or alternative, desired voltage interval to ensure sufficient read margin. When forming the threshold voltage distribution marked by dashed lines, a hard-decision read voltage V may be required for hard-decision decoding HD. H And may require the soft-decision read voltage V for soft-decision decoding operations SD1 and SD2. S1 and V S2 Therefore, the processor 110 can determine the level of the read voltage for hard or soft decision.

[0124] The ECC engine 120 can perform error correction operations by using a read voltage with a defined level (e.g., a defined read voltage level) for hard or soft decision.

[0125] When the ECC engine 120 performs error correction operations by using the read voltage for soft decision, the ECC engine 120 can enhance error correction capability when a defective memory cell (a 1-error in which a bit value indicating 0 is mistakenly read as 1) indicated by reference numeral 761 is not detected as an error.

[0126] The ECC engine 120 does not determine the memory cell as defective based on the defective column address information of the bit line coupled to the defective memory cell with 1-error, but can perform error correction operation by using the read voltage for soft decision.

[0127] Figure 14 An example of ECC decoding of a storage device according to an example embodiment is shown.

[0128] Reference Figure 14 The figure illustrates a memory cell coupled to a word line, a first bit line, and a second bit line. Reference numeral 771 indicates a defective memory cell 771 with a 1-error, where a bit value indicating a 0 is incorrectly read as a 1. Reference numeral 772 indicates a defective memory cell with a 0-error, where a bit value indicating a 1 is incorrectly read as a 0.

[0129] As shown by reference numeral 781 in the figure, the comparative non-volatile storage device performs column repair by replacing (REP) the sectors in the normal cell region NCA, including defective memory cells 771 and 772, with redundant sectors in the redundant cell region RCA.

[0130] According to the example embodiment of the non-volatile storage device 200, instead of replacing (REP) the sectors including defective storage cells 771 and 772 in the normal cell area NCA with redundant sectors in the redundant cell area RCA, the first parity data PRT1 and the second parity data PRT2 are stored in the parity cell area PCA and the redundant cell area RCA, and the ECC engine 120 in the memory controller 100 performs ECC decoding on the user data DATA by using the first parity data PRT1, the second parity data PRT2 and the defective column address information of the defective storage cells 771 and 772 to correct errors in the user data DATA, as shown by reference numeral 783.

[0131] Figure 15 and Figure 16 This is used to illustrate the operation of storing defective column address information in an information block according to an example embodiment.

[0132] exist Figure 15 In the figure, reference numeral 786 indicates the threshold voltage distribution of a normal memory cell, reference numeral 787 indicates the threshold voltage distribution of a defective memory cell with a 0-error, and reference numeral 788 indicates the threshold voltage distribution of a defective memory cell with a 1-error.

[0133] Reference Figure 15 and Figure 16 In order to detect defective memory cells with 0-errors and 1-errors, the control circuit 500 programs solid-state data including bit values ​​of 0 in the first memory block of the normal cell array NCA during the test sequence of the non-volatile memory device 200 (operation S110). For example, the control circuit 500 can program all 0s in the first memory block.

[0134] Control circuit 500 can determine that a storage cell with an output bit value of 1 has a 1-error by applying a first test read voltage VTr1 to the first word line of the first block (i.e., the information block) (operation S120). In an embodiment, the voltage level of the first test read voltage VTr1 is less than the threshold voltage of the programming storage cell in the first storage block. Control circuit 500 can determine that a storage cell with an output bit value of 0 has a 0-error by applying a second test read voltage VTr2 to the first word line of the first block (operation S130). In an embodiment, the voltage level of the second test read voltage VTr2 is greater than the threshold voltage of the programming storage cell in the first storage block.

[0135] The control circuit 500 can, during the test sequence, divide the second defect bit line into a first group of defect bit lines with 1-errors and a second group of defect bit lines with 0-errors based on the error attributes of the second defect bit line, and can store the column addresses of the first group of defect bit lines and the second group of defect bit lines in the database. Figure 11 The defect column address information DCAI is stored in the first storage block (information block) BLK1. The control circuit 500 can store the defect column address information DCAI in the first storage block (information block) BLK1 based on programming and reading operations performed on the first storage block in the normal cell area during the test sequence of the non-volatile storage device 200.

[0136] In addition, the control circuit 500 can Figure 15 The pattern is stored in the information block. A defective memory cell with a 1-error is detected by applying a first test read voltage VTr1, and a defective memory cell with a 0-error is detected by applying a second test read voltage VTr2. The defective column address information DCAI can be provided based on the output data in response to the first test read voltage VTr1 and the second test read voltage VTr2.

[0137] Figure 17 An example embodiment is shown. Figure 2 Example operation of storage devices.

[0138] Reference Figure 17 The figure shows a memory cell coupled to a word line, a first bit line, and a second bit line. Reference numeral 791 indicates a defective memory cell 791 with a 1-error, while reference numeral 792 indicates a defective memory cell 792 with a 0-error.

[0139] exist Figure 17 In this context, it is assumed that the parity check unit area PCA stores the first parity check data PRT1.

[0140] As shown by reference numeral 793 in the figure, the comparative non-volatile storage device performs column repair by replacing (REP1) sectors SECb in the normal cell region NCA, including defective memory cells 791 with 1-errors and defective memory cells 792 with 0-errors, with redundant sectors in the redundant cell region RCA.

[0141] In the storage device 30 according to the example embodiment, the memory controller 100 uses the redundant cell region RCA to perform column repair, assigns additional column addresses to the repair column and the redundant cell region RCA, and stores second parity data PRT2 in the repair column and the redundant cell region RCA.

[0142] The control circuit 500 performs column repair by replacing (REP2) a portion of the redundant cell region RCA with a sector SECb in the normal cell region NCA, which includes defective memory cells 791 with 1-errors and defective memory cells 792 with 0-errors. The ECC decoder 122 performs hard-decision decoding on the user data DATA for column repair based on the first parity data PRT1, and performs soft-decision decoding on the user data DATA for column repair based on the first parity data PRT1, the second parity data PRT2, and the defective column address information DCAI, as shown by reference numeral 794.

[0143] Figures 18 to 20 This is a flowchart illustrating a programming operation that assigns additional column addresses to defective bit lines in response to a memory controller, according to an example embodiment.

[0144] Reference Figures 5 to 11 , Figure 15 and Figure 18 In response to the memory controller 100 assigning an additional column address to the defect bit line, the control circuit 500 receives a programming command from the memory controller 100 (operation S210), and the control circuit 500 reads the defect column address information DCAI from the storage block BLK1 of the storage information block in response to the programming command (operation S220).

[0145] The control circuit 500 controls the page buffer circuit 410 to disable the second defect bit line with 1-error and 0-error by applying a disable voltage based on the read defect column address information DCAI (operation S230), and controls the address decoder 430 to apply a first programming pulse to the target word line associated with the programming command (operation S240). Figure 18 The control circuit 500 is shown to disable the second defect bit line with 1-error and 0-error and perform a programming operation.

[0146] Reference Figures 5 to 11 , Figure 15 and Figure 19 In response to the memory controller 100 assigning an additional column address to the defective bit line, the control circuit 500 receives a programming command from the memory controller 100 (operation S310), and the control circuit 500 performs a verification operation to detect a second defective bit line with a 0- error (operation S320).

[0147] The control circuit 500 controls the page buffer circuit 410 to disable the second defective bit line with a 0- error based on the verification operation (operation S330), controls the address decoder 430 to apply a first programming pulse to the target word line associated with the programming command (operation S340), and controls the address decoder 430 to apply a first programming verification voltage to the target word line (operation S350). Figure 19 The control circuit 500 is shown to disable the second defective bit line with a 0- error and perform a programming operation.

[0148] Reference Figures 5 to 11 , Figure 15 and Figure 20 In response to the memory controller 100 assigning an additional column address to a defective bit line, the control circuit 500 receives a programming command from the memory controller 100 (operation S410), the control address decoder 430 applies a first programming pulse to the target word line associated with the programming command, and the control address decoder 430 applies a first programming verification voltage and an error verification pulse to the target word line to detect a first programming state based on the first programming pulse and a second defective bit line with a 0- error (operation S430).

[0149] The control circuit 500 controls the page buffer circuit 410 to disable the second defective bit line with a 0- error based on the verification operation (operation S440), and controls the address decoder 430 to apply the second programming pulse to the target word line (operation S450). Figure 20 The control circuit 500 is shown to disable the second defective bit line with a 0- error and perform a programming operation.

[0150] Figure 21 and Figure 22 This is a diagram illustrating the operation of a storage device according to an example embodiment.

[0151] Reference Figures 2 to 16 , Figure 21 and Figure 22 A method is provided for operating a storage device, including a non-volatile storage device 200 and a memory controller 100, to control the non-volatile storage device 200.

[0152] According to this method, during the test sequence of the non-volatile storage device 200, the non-volatile storage device 200 stores the column address of the defect bit line with 1-error and 0-error in the information block as defect column address information DCAI (operation S503).

[0153] The memory controller 100 sends a request to obtain the defective column address information DCAI to the non-volatile storage device 200 (operation S505), and the non-volatile storage device 200, in response to the request, transmits the defective column address information DCAI to the memory controller 100 (operation S507). The memory controller 100 may store the defective column address information DCAI in the buffer 130.

[0154] The ECC engine 120 of the memory controller 100 generates parity data PRT by performing ECC encoding on user data DATA in the normal cell region NCA of the memory cell array 300 to be stored in the non-volatile storage device 200 (operation S510). The memory cell array 300 includes the normal cell region NCA, the parity cell region PCA, and the redundant cell region RCA associated with repairing defective columns in the normal cell region NCA and the parity cell region PCA.

[0155] The memory controller 100 assigns additional column addresses to the first defective bit line and the second bit line (operation S520), and the non-volatile storage device 200 stores a portion of the parity data PRT in the region corresponding to the additionally assigned column address (operation S530). Column repair is performed on the first defective bit line in the first bit line connected to the normal cell region NCA and the parity cell region PCA, and the second bit line is connected to the redundant cell region RCA.

[0156] The ECC engine 120 of the memory controller 100 receives user data DATA and parity data PRT from the non-volatile storage device 200, and performs ECC decoding on the user data DATA based on the parity data PRT and defect column address information DCAI.

[0157] Figure 23 This is a cross-sectional view of a non-volatile storage device according to an example embodiment.

[0158] Reference Figure 23 The non-volatile memory device or memory device 2000 may have a chip-to-chip (C2C) structure. A C2C structure can refer to a structure formed by: fabricating / manufacturing an upper chip including a memory cell region or cell region CELL on a first wafer, fabricating / manufacturing a lower chip including a peripheral circuit region PERI on a second wafer separate from the first wafer, and then bonding the upper and lower chips together. Here, the bonding process may include a method of electrically connecting bonding metal formed on the topmost metal layer of the upper chip and bonding metal formed on the topmost metal layer of the lower chip. In some example embodiments, copper-to-copper bonding is used when the bonding metal may include copper (Cu). However, the example embodiments are not limited to this. In some example embodiments, the bonding metal may also be formed of aluminum (Al) and / or tungsten (W).

[0159] Each of the peripheral circuit region PERI and cell region CELL of the storage device 2000 may include an external pad bonding region PA, a word line bonding region WLBA, and a bit line bonding region BLBA.

[0160] The Peripheral Circuit Region (PERI) may include: a first substrate 2210; an interlayer insulating layer 2215; a plurality of circuit elements 2220a, 2220b, and 2220c formed on the first substrate 2210; first metal layers 2230a, 2230b, and 2230c connected to the plurality of circuit elements 2220a, 2220b, and 2220c; and second metal layers 2240a, 2240b, and 2240c formed on the first metal layers 2230a, 2230b, and 2230c, respectively. In some example embodiments, the first metal layers 2230a, 2230b, and 2230c may be formed of tungsten, which has a relatively high resistivity, and the second metal layers 2240a, 2240b, and 2240c may be formed of copper, which has a relatively low resistivity.

[0161] exist Figure 23 In the example embodiment shown, although only the first metal layers 2230a, 2230b, and 2230c and the second metal layers 2240a, 2240b, and 2240c are shown and described, the example embodiment is not limited thereto, and one or more additional metal layers may be formed on the second metal layers 2240a, 2240b, and 2240c. At least a portion of the one or more additional metal layers formed on the second metal layers 2240a, 2240b, and 2240c may be formed of aluminum or the like, which has a lower resistivity than copper, the copper used to form the second metal layers 2240a, 2240b, and 2240c.

[0162] An interlayer insulating layer 2215 may be disposed on a first substrate 2210 and cover a plurality of circuit elements 2220a, 2220b, and 2220c, first metal layers 2230a, 2230b, and 2230c, and second metal layers 2240a, 2240b, and 2240c. The interlayer insulating layer 2215 may include an insulating material such as silicon oxide or silicon nitride.

[0163] The lower bonding metals 2271b and 2272b can be formed on the second metal layer 2240b in the word line bonding area (WLBA). In the WLBA, the lower bonding metals 2271b and 2272b in the peripheral circuit area (PERI) can be electrically bonded to the upper bonding metals 2371b and 2372b in the cell area (CELL). The lower bonding metals 2271b and 2272b, as well as the upper bonding metals 2371b and 2372b, can be formed of aluminum, copper, tungsten, or the like. Furthermore, the upper bonding metals 2371b and 2372b in the cell area (CELL) can be referred to as first metal pads, while the lower bonding metals 2271b and 2272b in the peripheral circuit area (PERI) can be referred to as second metal pads.

[0164] A cell region (CELL) may include at least one memory block. The cell region (CELL) may include a second substrate 2310 and a common source line 2320. On the second substrate 2310, a plurality of word lines 2331, 2332, 2333, 2334, 2335, 2336, 2337, and 2338 (e.g., 2330) may be stacked in a direction D3 (e.g., the Z-axis direction) perpendicular to the upper surface of the second substrate 2310. At least one string select line and at least one ground select line may be arranged above and below the plurality of word lines 2330, respectively, and the plurality of word lines 2330 may be disposed between the at least one string select line and the at least one ground select line.

[0165] In the bit line bonding region BLBA, the channel structure CH may extend along a third direction D3 perpendicular to the upper surface of the second substrate 2310 and pass through a plurality of word lines 2330, at least one string select line, and at least one ground select line. The channel structure CH may include a data storage layer, a channel layer, a buried insulating layer, etc., and the channel layer may be electrically connected to the first metal layer 2350c and the second metal layer 2360c. In some example embodiments, the first metal layer 2350c may be a bit line contact, and the second metal layer 2360c may be a bit line. In some example embodiments, the bit line 2360c may extend along a second direction D2 (e.g., the Y-axis direction) parallel to the upper surface of the second substrate 2310.

[0166] exist Figure 23 In some example embodiments shown, the area where the channel structure CH, bit line 2360c, etc., are arranged can be defined as a bit line bonding area BLBA. In the bit line bonding area BLBA, bit line 2360c can be electrically connected to circuit element 2220c providing page buffer 2393 in the peripheral circuit area PERI. Bit line 2360c can be connected to upper bonding metals 2371c and 2372c in the cell area CELL, and the upper bonding metals 2371c and 2372c can be connected to lower bonding metals 2271c and 2272c, which are connected to circuit element 2220c of page buffer 2393.

[0167] In the word line bonding area (WLBA), a plurality of word lines 2330 may extend along a first direction D1 (e.g., the X-axis direction) parallel to the upper surface of the second substrate 2310 and perpendicular to the second direction D2, and may be connected to a plurality of cell contact plugs 2341, 2342, 2343, 2344, 2345, 2346, and 2347 (e.g., 2340). The plurality of word lines 2330 and the plurality of cell contact plugs 2340 may be connected to each other in pads provided by at least a portion of the plurality of word lines 2330 extending at different lengths along the first direction D1. A first metal layer 2350b and a second metal layer 2360b may be sequentially connected to the upper portion of the plurality of cell contact plugs 2340, which are connected to the plurality of word lines 2330. Multiple cell contact plugs 2340 can be connected to the peripheral circuit area PERI via the upper bonding metals 2371b and 2372b of the cell area CELL in the word line bonding area WLBA and the lower bonding metals 2271b and 2272b of the peripheral circuit area PERI.

[0168] Multiple unit contact plugs 2340 may be electrically connected to circuit elements 2220b forming the line decoder 2394 in the peripheral circuitry region PERI. In some example embodiments, the operating voltage of the circuit elements 2220b forming the line decoder 2394 may be different from the operating voltage of the circuit elements 2220c forming the page buffer 2393. In some example embodiments, the operating voltage of the circuit elements 2220c forming the page buffer 2393 may be greater than the operating voltage of the circuit elements 2220b forming the line decoder 2394.

[0169] A common source line contact plug 2380 may be disposed in the external pad bonding region PA. The common source line contact plug 2380 may be formed of a conductive material such as metal, metal compound, or polysilicon, and may be electrically connected to the common source line 2320. A first metal layer 2350a and a second metal layer 2360a may be sequentially stacked on top of the common source line contact plug 2380. In some example embodiments, the region where the common source line contact plug 2380, the first metal layer 2350a, and the second metal layer 2360a are disposed may be defined as the external pad bonding region PA.

[0170] Input / output pads 2205 and 2305 may be disposed in the external pad bonding area PA. A lower insulating film 2201 covering the lower surface of the first substrate 2210 may be formed below the first substrate 2210, and the first input / output pad 2205 may be formed on the lower insulating film 2201. The first input / output pad 2205 may be connected to at least one of a plurality of circuit elements 2220a, 2220b, and 2220c disposed in the peripheral circuit area PERI via a first input / output contact plug 2203, and may be separated from the first substrate 2210 via the lower insulating film 2201. Alternatively or additionally, a side insulating film may be disposed between the first input / output contact plug 2203 and the first substrate 2210 to electrically isolate the first input / output contact plug 2203 from the first substrate 2210.

[0171] An upper insulating film 2301 covering the upper surface of the second substrate 2310 may be formed on the second substrate 2310, and a second input / output pad 2305 may be disposed on the upper insulating layer 2301. The second input / output pad 2305 may be connected to at least one of a plurality of circuit elements 2220a, 2220b, and 2220c disposed in the peripheral circuit region PERI via a second input / output contact plug 2303. In some example embodiments, the second input / output pad 2305 is electrically connected to circuit element 2220a.

[0172] According to an embodiment, the second substrate 2310 and the common source line 2320 are not disposed in the region where the second input / output contact plug 2303 is disposed. Furthermore, in an embodiment, the second input / output pad 2305 does not overlap with the word line 2330 in the third direction D3. The second input / output contact plug 2303 may be spaced apart from the second substrate 2310 in a direction parallel to the upper surface of the second substrate 2310, and may pass through the interlayer insulating layer 2315 of the cell region CELL to connect to the second input / output pad 2305.

[0173] According to embodiments, a first input / output pad 2205 and a second input / output pad 2305 may be selectively formed. In some example embodiments, the storage device 2000 may include only the first input / output pad 2205 disposed on the first substrate 2210 or the second input / output pad 2305 disposed on the second substrate 2310. Alternatively, the non-volatile storage device 200 may include the first input / output pad 2205 and the second input / output pad 2305.

[0174] In each of the external pad bonding area PA and bit line bonding area BLBA included in the cell region CELL and the peripheral circuit region PERI respectively, the metal pattern set on the top metal layer can be set as a dummy pattern (e.g., an electrically passive pattern), or the top metal layer may not exist.

[0175] In the external pad bonding area PA, the non-volatile memory device 2000 may include a lower metal pattern 2273a corresponding to an upper metal pattern 2372a formed in the uppermost metal layer of the cell region CELL, and having the same or similar cross-sectional shape as the upper metal pattern 2372a of the cell region CELL, so as to be interconnected with each other in the uppermost metal layer of the peripheral circuit region PERI. In an embodiment of the peripheral circuit region PERI, the lower metal pattern 2273a formed in the uppermost metal layer of the peripheral circuit region PERI is not connected to a contact. Similarly, in the external pad bonding area PA, an upper metal pattern 2372a may be formed in the uppermost metal layer of the cell region CELL, corresponding to the lower metal pattern 2273a formed in the uppermost metal layer of the peripheral circuit region PERI, and having the same shape as the lower metal pattern 2273a of the peripheral circuit region PERI.

[0176] Lower bonding metals 2271b and 2272b can be formed on the second metal layer 2240b in the word line bonding region WLBA. In the word line bonding region WLBA, the lower bonding metals 2271b and 2272b of the peripheral circuit region PERI can be electrically connected to the upper bonding metals 2371b and 2372b of the cell region CELL via copper-to-copper bonding.

[0177] Furthermore, in the bit line bonding region BLBA, an upper metal pattern 2392 can be formed in the uppermost metal layer of the cell region CELL. This upper metal pattern 2392 corresponds to the lower metal pattern 2252 formed in the uppermost metal layer of the peripheral circuit region PERI, and has the same or similar cross-sectional shape as the lower metal pattern 2252 of the peripheral circuit region PERI. In an embodiment, contacts may not be formed on the upper metal pattern 2392 formed in the uppermost metal layer of the cell region CELL.

[0178] In some example embodiments, a reinforcing metal pattern with the same or similar cross-sectional shape as the metal pattern formed in the uppermost metal layer of one of the cell region (CELL) and the peripheral circuit region (PERI) can be formed in the uppermost metal layer of the other. In some embodiments, contacts may not be formed on the reinforcing metal pattern.

[0179] Word line voltage can be applied to at least one memory block in the cell region CELL via the lower bonding metals 2271b and 2272b in the peripheral circuit region PERI and the upper bonding metals 2371b and 2372b in the cell region CELL.

[0180] Figure 24 This is a block diagram illustrating a storage device including a non-volatile storage device according to an example embodiment.

[0181] Reference Figure 24 The storage device 3000 includes a plurality of non-volatile storage devices 3100 and a controller 3200. In some example embodiments, the storage device 3000 may be an embedded multimedia card (eMMC), universal flash memory (UFS), a solid-state drive (SSD).

[0182] The controller 3200 can be connected to the non-volatile memory device 3100 via multiple channels CCH1, CCH2, CCH3...CCHk (k is a positive integer). The controller 3200 may include one or more processors 3210, buffer memory 3220, error correction code (ECC) engine 3230, host interface 3250, and non-volatile memory (NVM) interface 3260.

[0183] Buffer memory 3220 can store data for drive controller 3200. ECC engine 3230 can calculate error correction code values ​​for the data to be programmed during programming operations and can use these error correction code values ​​to correct errors in the read data during read operations. In data recovery operations, ECC engine 3230 can correct errors in data recovered from non-volatile storage device 3100. ECC engine 3230 can be... Figure 4 The ECC engine 120 is implemented. Therefore, the ECC engine 3230 can receive parity data, including first parity data and second parity data, from each of the non-volatile storage devices 3100, can perform hard-decision decoding on user data based on the first parity data, and can perform hard-decision decoding on user data based on the first parity data, the second parity data, and defect column address information.

[0184] The host interface 3250 can provide an interface with external devices. The non-volatile memory interface 3260 can provide an interface with the non-volatile memory device 3100.

[0185] Each non-volatile storage device 3100 may correspond to the aforementioned non-volatile storage device according to the example embodiment, and may optionally be supplied with an external high voltage VPP.

[0186] Various package types or package configurations can be used to package non-volatile storage devices or storage devices according to the example embodiments.

[0187] This disclosure can be applied to a variety of electronic devices, including non-volatile storage devices. For example, this disclosure can be applied to mobile phones, smartphones, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, camcorders, personal computers (PCs), server computers, workstations, laptop computers, digital televisions, set-top boxes, portable game consoles, navigation systems, etc.

[0188] The foregoing is illustrative of exemplary embodiments and should not be construed as limiting them. Although some exemplary embodiments have been described, those skilled in the art will readily understand that various modifications can be made to the exemplary embodiments without departing from the essence of this disclosure. Therefore, all such modifications are intended to be included within the scope of this disclosure as defined in the claims.

Claims

1. A storage device, comprising: Non-volatile storage devices, including: A storage cell array includes a normal cell region, a parity cell region, and a redundant cell region associated with repairing defective columns in the normal cell region and the parity cell region. The storage cell array includes a plurality of non-volatile storage cells coupled to a first bit line and a second bit line, the first bit line being connected to the normal cell region and the parity cell region, and the second bit line being connected to the redundant cell region. The page buffer circuit is connected to the memory cell array via the first bit line and the second bit line; and The address decoder is connected to the memory cell array via multiple word lines, and A memory controller is configured to control the non-volatile memory device. The memory controller includes an error correction code (ECC) engine, which is configured to generate parity data, including first parity data and second parity data, by performing ECC encoding on user data to be stored in the normal cell area. The memory controller is configured as follows: The user data is stored in the normal cell area. The non-volatile memory device is controlled to perform column repair on a first defective bit line in the first bit line, each of the first defective bit lines being associated with a given one in the defective column. Assign additional column addresses to the first defect bit line and the second bit line, and At least a portion of the parity data is stored in a region corresponding to an additionally allocated column address, and The non-volatile storage device further includes a control circuit configured to store the first parity check data in the parity check unit area and to store the second parity check data in the redundancy unit area.

2. The storage device according to claim 1, wherein, The control circuit is configured to control the page buffer circuit to perform column repair on the first defect bit line in the defect bit lines, each of the defect bit lines having a given defect column. The control circuit is configured to skip the column repair for at least a portion of the second defect bit line in the defect bit line, and is configured to store the defect column address information of the portion of the second defect bit line in an information block. The storage cell array comprises multiple cell strings stacked vertically on a substrate.

3. The storage device according to claim 2, wherein: The control circuit is configured to divide the second defect bit line into a first group of defect bit lines and a second group of defect bit lines based on the error attributes of the second defect bit line. The first set of defective bit lines has a 1-error, which indicates that a bit value of 0 was incorrectly read as a bit value of 1, and The second set of defective bit lines has a 0-error, which indicates that a bit value of 1 was incorrectly read as a bit value of 0.

4. The storage device according to claim 3, wherein, The control circuit is configured to store the defect column address information in the information block based on programming and reading operations performed on the information block in the normal cell region during a test sequence of the non-volatile storage device.

5. The storage device according to claim 4, wherein, The control circuit is configured as follows: The information block is programmed with data including all zero bit values; The storage cell that outputs a 1-bit value has the 1-error is determined by applying a first test read voltage to the first word line of the information block in the word line, wherein the level of the first test read voltage is less than the threshold voltage of the programming storage cell in the information block; as well as The storage cell that determines the bit value of the output 0 has the 0-error by applying a second test read voltage to the first word line of the information block, wherein the level of the second test read voltage is greater than the threshold voltage of the programming storage cell in the information block.

6. The storage device according to claim 2, in, The control circuit is configured to provide the defect column address information to the memory controller in response to a request from the memory controller. The memory controller further includes: A buffer is configured to store the defect column address information; and The processor is configured to control the ECC engine. The ECC engine includes: Memory used to store ECC; An ECC encoder is configured to perform ECC encoding on the user data based on the ECC to generate the parity data; and The ECC decoder is configured to selectively use the defect column address information and is configured to perform ECC decoding on the user data read from the non-volatile storage device based on the parity data read.

7. The storage device according to claim 6, wherein: The control circuit is configured to: perform column repair on a portion of the first defective bit line using at least one redundant bit line in the redundant cell region; and The ECC decoder is configured to perform hard-decision decoding on the user data read using the default read voltage by using the first parity data.

8. The storage device according to claim 7, wherein, The ECC engine is configured to: in response to user data with errors, perform soft-decision decoding on the user data using a soft-decision read voltage, the first parity data, the second parity data, and the defect column address information, wherein the soft-decision read voltage is offset relative to the hard-decision read voltage used in the hard-decision decoding.

9. The storage device according to claim 6, in, The storage device includes multiple non-volatile storage devices, and The buffer is configured to store the defect column address information associated with each of the plurality of non-volatile storage devices.

10. The storage device according to claim 2, wherein, In response to the memory controller assigning the additional column address to the defective bit line, The control circuit is configured as follows: In response to a programming command from the memory controller, the defect column address information is read from the information block; The page buffer circuit is controlled to disable the second defect bit line based on the read defect column address information; as well as The address decoder is controlled to apply a first programming pulse to the target word line associated with the programming command in the word line.

11. The storage device according to claim 2, wherein, In response to the memory controller assigning the additional column address to the defective bit line, The control circuitry is configured to control the address decoder in response to a programming command from the memory controller, such that the address decoder applies a verification voltage to the target word line associated with the programming command in the word line. The verification voltage is used to detect a first-type defect bit line with a 0-error, where the bit value indicating a 1 error is incorrectly read as a 0 bit value.

12. The storage device according to claim 11, wherein, The control circuit is configured as follows: The page buffer circuit is controlled to prevent voltage from being applied to the first type of defect bit line; as well as The address decoder is controlled to apply a first programming pulse to the target word line and a first programming verification voltage to the target word line.

13. The storage device according to claim 2, wherein, In response to the memory controller assigning the additional column address to the defective bit line, The control circuit is configured as follows: The address decoder is controlled to apply a first programming pulse to the target word line associated with the programming command in the word line; as well as The address decoder is controlled to apply a first programming verification voltage and an error verification pulse to the target word line to detect a first programming state based on the first programming pulse and a first type defect bit line with a 0-error, wherein the bit value indicating a 0-error is incorrectly read as a 0 bit value.

14. The storage device according to claim 13, wherein, The control circuit is configured as follows: The page buffer circuit is controlled to prevent voltage from being applied to the first type of defect bit line; as well as The address decoder is controlled to apply a second programming pulse to the target word line, the voltage level of the second programming pulse being greater than the voltage level of the first programming pulse.

15. The storage device according to claim 1, wherein, The non-volatile storage device further includes: A voltage generator is configured to generate word line voltages based on control signals; and... The address decoder is coupled to the memory cell array via the word line, and the address decoder is configured to transmit the word line voltage to the memory cell array based on the row address. The page buffer circuit is coupled to the memory cell array via the first bit line and the second bit line, and the page buffer circuit is configured to store the user data and the parity data in the memory cell array; and The control circuit is configured to control the voltage generator, the address decoder, and the page buffer circuit based on commands and addresses received from the memory controller.

16. The storage device according to claim 1, wherein, The non-volatile storage device includes: The storage cell region includes the storage cell array and the first metal pad; and The peripheral circuit region includes a second metal pad, which is vertically connected to the memory cell region via the first and second metal pads. The peripheral circuit region includes: A voltage generator is configured to generate word line voltages based on control signals; The address decoder is coupled to the memory cell array via the word line, and the address decoder is configured to transmit the word line voltage to the memory cell array based on the row address. The page buffer circuit is coupled to the memory cell array via the first bit line and the second bit line, and the page buffer circuit is configured to store the user data and the parity data in the memory cell array; and The control circuit is configured to control the voltage generator, the address decoder, and the page buffer circuit based on commands and addresses received from the memory controller.

17. A method of operating a storage device, the storage device comprising a non-volatile storage device and a memory controller, the memory controller being configured to control the non-volatile storage device, the method comprising: The error correction code (ECC) engine in the memory controller generates parity data, including first parity data and second parity data, by performing ECC encoding on user data in the normal cell area of ​​the memory cell array to be stored in the non-volatile storage device. The memory cell array includes the normal cell area, the parity cell area, and the redundant cell area associated with repairing defective columns in the normal cell area and the parity cell area. Perform column repair on the first defective bit line in the first bit line connected to the normal cell region and the parity check cell region; The memory controller assigns additional column addresses to the first defective bit line and the second bit line connected to the redundant cell region; as well as At least a portion of the parity data is stored by the non-volatile storage device in a region corresponding to an additionally allocated column address. The first parity check data is stored in the parity check unit area, and the second parity check data is stored in the redundancy unit area.

18. The method of claim 17, further comprising: The control circuitry of the non-volatile memory device repairs at least a portion of the second defect bit line in the defect bit line by skipping the column. The control circuit stores the defect column address information of the portion of the second defect bit line in an information block; as well as ECC decoding is performed on the user data read from the non-volatile storage device by selectively using the defect column address from the non-volatile storage device and based on the parity data from the non-volatile storage device.

19. A storage device, comprising: Non-volatile storage devices, including: A storage cell array includes a normal cell region, a parity cell region, and a redundant cell region associated with repairing defective columns in the normal cell region and the parity cell region. The storage cell array includes a plurality of non-volatile storage cells coupled to a first bit line and a second bit line, the first bit line being connected to the normal cell region and the parity cell region, and the second bit line being connected to the redundant cell region. The page buffer circuit is connected to the memory cell array via the first bit line and the second bit line; and The address decoder is coupled to the memory cell array via multiple word lines, and A memory controller is configured to control the non-volatile memory device. The memory controller includes an error correction code (ECC) engine, which is configured to generate parity data, including first parity data and second parity data, by performing ECC encoding on user data to be stored in the normal cell area. The memory controller is configured as follows: The user data is stored in the normal cell area. The non-volatile memory device is controlled to perform column repair on the first defective bit line in the first bit line. Assign additional column addresses to the first defect bit line and the second bit line, and At least a portion of the parity data is stored in a region corresponding to an additionally allocated column address. The non-volatile storage device further includes: A control circuit is configured to control the page buffer circuit to perform column repair on the first defect bit line in the defect bit lines, each of the defect bit lines being associated with a given one in the defect column. The control circuit is configured to skip column repair for at least a portion of the second defect bit line in the defect bit line, to store defect column address information of the portion of the second defect bit line in an information block, and to provide the defect column address information to the memory controller in response to a request from the memory controller. The control circuit is configured to store the first parity check data in the parity check unit area and to store the second parity check data in the redundancy unit area. The ECC engine is configured to selectively use the defect column address information and to perform ECC decoding on the user data read from the non-volatile storage device based on the parity data from the non-volatile storage device.

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