Semiconductor structure and its formation method

Abstract

This invention provides a semiconductor structure and a method for forming the same. The method includes: providing a substrate on which a gate structure and a sidewall are formed, and a lightly doped region is formed within the substrate at the bottom of the sidewall; forming a self-aligned metal silicide barrier layer; etching the self-aligned metal silicide barrier layer within the self-aligned metal silicide formation region, leaving a portion of the self-aligned metal silicide barrier layer at the corner formed by the sidewall and the substrate to form an isolation structure, the isolation structure being located at the bottom of the sidewall sidewall, and the longitudinal section of the isolation structure being triangular; forming a metal layer; and heat-treating the substrate to cause the metal layer to react with the substrate to form a self-aligned metal silicide layer. The isolation structure creates a gap between the self-aligned metal silicide layer on the substrate and the lightly doped region, thereby reducing the on-resistance, improving device efficiency, and enhancing device reliability.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] As the feature size (CD) of semiconductor devices continues to shrink, the contact resistance between semiconductor devices such as MOS field-effect transistors and the upper interconnect structure has an increasingly significant impact on device performance. A common method to reduce contact resistance in the existing technology is to form self-aligned metal silicides on the contact electrodes of the device.

[0003] In the fabrication of semiconductor devices, some devices require a self-aligned metal silicide process, while others require a non-salicide process. For devices requiring a non-salicide process, the properties of self-aligned metal silicides are utilized by covering the device with a material that does not react with metal. This material used to cover devices requiring non-salicide processes is called a self-aligned metal silicide barrier (SAB).

[0004] Figures 1 to 4 This is a schematic diagram of the structural steps in an existing method for forming self-aligned metal silicides. The existing method for forming self-aligned metal silicides includes the following steps:

[0005] First, such as Figure 1 As shown, a substrate 10 is provided, on which a gate structure 11 is formed. The gate structure 11 includes a gate dielectric layer 11a and a polysilicon gate 11b stacked sequentially. A sidewall 12 is formed on the sidewall of the gate structure 11, and the sidewall 12 includes an oxide layer 12a and a nitride layer 12b. Lightly doped regions 13 and 14 are formed in the substrate 10 at the bottom of the sidewall 12, and heavily doped regions 15 and 16 are formed in the substrate on the side of the sidewall 12 away from the gate structure 11. The heavily doped region 15 is adjacent to the lightly doped region 13, and the heavily doped region 16 is adjacent to the lightly doped region 14. The lightly doped regions 13 and 14 serve as lightly doped LDD regions, and the heavily doped regions 15 and 16 serve as source or drain doped regions, respectively.

[0006] Next, as Figure 2As shown, a self-aligned metal silicide barrier layer 17 is formed, which covers the substrate 10, the gate structure 11, and the sidewall 12. The substrate 10 includes a non-self-aligned metal silicide formation region and a self-aligned metal silicide formation region. The self-aligned metal silicide barrier layer 17 on the non-self-aligned metal silicide formation region is retained, and the self-aligned metal silicide barrier layer 17 on the self-aligned metal silicide formation region is removed. Figure 1-4 The non-self-aligned metal silicide formation region is not shown; only the self-aligned metal silicide formation region is shown. The self-aligned metal silicide barrier layer 17 is typically removed completely using a combination of dry and wet etching.

[0007] Next, as Figure 3 As shown, a metal layer 18 is formed. Figure 3 Only the self-aligned metal silicide formation region is shown, therefore the self-aligned metal silicide barrier layer 17 has been removed, and the metal layer 18 covers the substrate 10, the gate structure 11 and the sidewall 12.

[0008] Next, please continue to refer to... Figure 3 As shown, the substrate 10 is heat-treated, and the metal layer 18 reacts with the contacting silicon to form a self-aligned metal silicide layer 19. The metal layer 18 that does not form the self-aligned metal silicide layer 19 is removed by self-alignment. The self-aligned metal silicide layer 19 is located on the surface of the substrate 10 and the top surface of the gate structure 11.

[0009] Please refer to Figure 3 and Figure 4 As shown, during the formation of the self-aligned metal silicide layer 19, the metal elements in the metal layer 18 not only diffuse longitudinally into the substrate 10, but also diffuse laterally within the substrate 10, causing the self-aligned metal silicide layer 19 formed on the surface of the substrate 10 to diffuse into the lightly doped regions 13 and 14 below the sidewalls 12 (e.g., Figure 4 The virtual coil (in the middle) forms a non-ohmic contact with the lightly doped regions 13 and 14, which increases the on-resistance (Rdson), resulting in reduced device efficiency and decreased device reliability. Summary of the Invention

[0010] The purpose of this invention is to provide a semiconductor structure and a method for forming the same, such that there is a gap between the self-aligned metal silicide layer formed on the substrate and the lightly doped region, thereby reducing the on-resistance, improving device efficiency, and enhancing device reliability.

[0011] To address the aforementioned technical problems, the present invention provides a method for forming a semiconductor structure, comprising the following steps:

[0012] A substrate is provided on which a gate structure and a sidewall covering the sidewall of the gate structure are formed, and a lightly doped region is formed in the substrate at the bottom of the sidewall.

[0013] A self-aligned metal silicide barrier layer is formed, the self-aligned metal silicide barrier layer covering the substrate, the gate structure and the sidewall;

[0014] The self-aligned metal silicide barrier layer within the self-aligned metal silicide formation region is etched, and the remaining portion of the self-aligned metal silicide barrier layer at the corner formed by the sidewall and the substrate forms an isolation structure. The isolation structure is located at the bottom of the sidewall of the sidewall, and the longitudinal section of the isolation structure is triangular.

[0015] A metal layer is formed, the metal layer covering the substrate, the gate structure, the sidewalls, and the isolation structure; and,

[0016] The substrate is heat-treated to react with the metal layer to form a self-aligned metal silicide layer. The isolation structure provides a gap between the self-aligned metal silicide layer on the substrate and the lightly doped region.

[0017] Optionally, the self-aligned metal silicide barrier layer is a superposition layer of silicon oxide and silicon nitride or a silicon-rich oxide layer.

[0018] Optionally, the self-aligned metal silicide barrier layer within the self-aligned metal silicide formation region is dry-etched to form the isolation structure.

[0019] Optionally, the dry etching process comprises three stages. In the first stage, the etching gas contains CH3F, CH4, and Ar, with a pressure between 50 mtorr and 200 mtorr, a power between 700 W and 900 W, and an etching time between 1 min and 2 min. In the second stage, etching is performed using an endpoint measurement method, with the etching gas containing CH3F, CH4, and Ar, a pressure between 50 mtorr and 200 mtorr, and a power between 400 W and 600 W. In the third stage, the etching gas contains CH2F3 or CH3F, with a pressure between 30 mtorr and 100 mtorr, a power between 200 W and 400 W, and an etching time between 5 s and 15 s.

[0020] Optionally, a photoresist pattern formed by photolithography defines the self-aligned metal silicide formation region, the photoresist pattern covering the non-self-aligned metal silicide formation region and exposing the self-aligned metal silicide formation region.

[0021] Optionally, after forming the isolation structure and before forming the metal layer, the method further includes: removing the photoresist pattern.

[0022] Optionally, a heavily doped region is further formed in the substrate on the side of the sidewall away from the gate structure, the heavily doped region being adjacent to the lightly doped region.

[0023] Optionally, the step of forming the gate structure, the sidewalls, the lightly doped region, and the heavily doped region on the substrate includes:

[0024] A gate structure is formed on the substrate;

[0025] The substrate is subjected to a first ion implantation using the gate structure as a mask to form a temporary doped region.

[0026] A sidewall is formed on the side of the gate structure;

[0027] Using the gate structure and the sidewall as a mask, a second ion implantation is performed on the substrate to form a heavily doped region within the temporary doped region. The area within the temporary doped region where the heavily doped region is not formed is designated as the lightly doped region.

[0028] Optionally, the doping depth of the heavily doped region is greater than that of the lightly doped region, and the self-aligned metal silicide layer is located within the surface of the heavily doped region and has a gap between it and the lightly doped region.

[0029] Accordingly, the present invention also provides a semiconductor structure, comprising:

[0030] A substrate, a gate structure located on the substrate and a sidewall covering the sidewall of the gate structure, wherein a lightly doped region is formed in the substrate at the bottom of the sidewall;

[0031] An isolation structure located at the corner formed by the side wall and the base, the isolation structure being located at the bottom of the side wall of the side wall, and the longitudinal section of the isolation structure being triangular;

[0032] A self-aligned metal silicide layer is located within the surface of the substrate, and there is a gap between the self-aligned metal silicide layer and the lightly doped region.

[0033] In the semiconductor structure and its formation method provided by the present invention, the self-aligned metal silicide barrier layer in the self-aligned metal silicide formation region is etched, and the remaining portion of the self-aligned metal silicide barrier layer at the corner formed by the sidewall and the substrate forms an isolation structure. When the metal layer is subsequently formed and heat-treated, the metal elements in the metal layer will also diffuse laterally during longitudinal diffusion. However, the presence of the isolation structure prolongs the lateral diffusion path, and the metal elements can only diffuse to the bottom of the isolation structure and cannot further diffuse to the bottom of the sidewall. This results in a gap between the self-aligned metal silicide layer and the lightly doped region, thereby reducing the on-resistance, improving device efficiency, and improving device reliability.

[0034] In addition, dry etching of the self-aligned metal silicide barrier layer saves the wet etching step compared with existing technologies, simplifies the process, and reduces production costs. Attached Figure Description

[0035] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention.

[0036] Figure 1-4 This is a schematic diagram of the steps in the existing method for forming self-aligned metal silicides.

[0037] Figure 5 This is a flowchart of a method for forming a semiconductor structure according to an embodiment of the present invention.

[0038] Figure 6-10 This is a schematic diagram of the steps in a method for forming a semiconductor structure according to an embodiment of the present invention.

[0039] Figures 1 to 4 middle:

[0040] 10-Substrate; 11-Gate structure; 11a-Gate dielectric layer; 11b-Polysilicon gate; 12-Sidewall; 12a-Oxide layer; 12b-Nitride layer; 13-Lightly doped region; 14-Lightly doped region; 15-Heavily doped region; 16-Heavily doped region; 17-Self-aligned metal silicide barrier layer; 18-Metal layer; 19-Self-aligned metal silicide layer.

[0041] Figures 6 to 10 middle:

[0042] 100 - Substrate; 110 - Gate structure; 110a - Gate dielectric layer; 110b - Polysilicon gate; 120 - Sidewall; 120a - Oxide layer; 120b - Nitride layer; 130 - Lightly doped region; 140 - Lightly doped region; 150 - Heavily doped region; 160 - Heavily doped region; 170 - Self-aligned metal silicide barrier layer; 180 - Isolation structure; 190 - Metal layer; 200 - Self-aligned metal silicide layer. Detailed Implementation

[0043] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.

[0044] As used in this invention, the singular forms “a,” “an,” and “the” include plural objects; the term “or” is generally used to mean “and / or”; the term “a number” is generally used to mean “at least one”; and the term “at least two” is generally used to mean “two or more”. Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as “first,” “second,” or “third” may explicitly or implicitly include one or at least two of that feature, unless otherwise expressly indicated.

[0045] Figure 5 This is a flowchart of a method for forming a semiconductor structure according to an embodiment of the present invention. Figure 5 As shown, the method for forming a semiconductor structure provided in this embodiment includes the following steps:

[0046] S01: A substrate is provided, on which a gate structure and a sidewall covering the sidewall of the gate structure are formed, and a lightly doped region is formed in the substrate at the bottom of the sidewall;

[0047] S02: Form a self-aligned metal silicide barrier layer, the self-aligned metal silicide barrier layer covering the substrate, the gate structure and the sidewall;

[0048] S03: Etch the self-aligned metal silicide barrier layer within the self-aligned metal silicide formation region, leaving the remaining portion of the self-aligned metal silicide barrier layer at the corner formed by the sidewall and the substrate to form an isolation structure, the longitudinal section of which is triangular.

[0049] S04: Form a metal layer that covers the substrate, the gate structure, the sidewalls, and the isolation structure;

[0050] S05: The substrate is heat-treated to react with the metal layer to form a self-aligned metal silicide layer, and the isolation structure provides a gap between the self-aligned metal silicide layer on the substrate and the lightly doped region.

[0051] Figures 6-10 This is a schematic diagram of the steps in a method for forming a semiconductor structure according to an embodiment of the present invention. The following will be discussed in conjunction with... Figure 5 and Figures 6-10 A method for forming a semiconductor structure according to an embodiment of the present invention will be described in detail.

[0052] In step S01, please refer to Figure 6 As shown, a substrate 100 is provided, on which a gate structure 110 and a sidewall 120 covering the sidewall of the gate structure 110 are formed, and lightly doped regions 130 and 140 are formed in the substrate at the bottom of the sidewall 120.

[0053] The substrate 100 can be any suitable substrate well known to those skilled in the art, such as at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI). In this embodiment, the substrate 100 is preferably made of silicon.

[0054] The gate structure 110 includes a gate dielectric layer 110a and a polysilicon gate 110b stacked sequentially. The gate dielectric layer 110a is preferably made of silicon oxide, and the polysilicon gate 110b is made of polysilicon. The sidewall 120 includes an oxide layer 120a and a nitride layer 120b. The oxide layer 120a is preferably made of silicon oxide, and the nitride layer 120b is preferably made of silicon nitride. Lightly doped regions 130 and 140 are formed in the substrate 100 at the bottom of the sidewall 120. The dopant is preferably phosphorus (P) or arsenic (As). Heavily doped regions 150 and 160 are formed in the substrate 100 on the side of the sidewall 120 away from the gate structure 110. The dopant is preferably phosphorus (P) or arsenic (As). The heavily doped region 150 is adjacent to the lightly doped region 130, and the heavily doped region 160 is adjacent to the lightly doped region 140.

[0055] Specifically, a gate dielectric layer 110a and a polysilicon gate 110b are sequentially formed on the substrate 100 to form a gate structure 110. Using the gate structure 110 as a mask, a first ion implantation is performed on the substrate 100 to form temporary doped regions, which are located within the substrate 100 on both sides of the gate structure 110. Next, an oxide layer 120a and a nitride layer 120b are sequentially formed on the sidewalls of the gate structure 110 to form sidewalls 120, which are located on both sides of the gate structure 110. Then, using the gate structure 110 and the sidewalls 120 as masks, a second ion implantation is performed on the substrate 100. The dose of the second ion implantation is greater than that of the first ion implantation, forming heavily doped regions 150 and 160 within the temporary doped regions. The areas within the temporary doped regions where the heavily doped regions 150 and 160 are not formed are designated as lightly doped regions 130 and 140. The doping depth of the heavily doped regions 150 and 160 is greater than that of the lightly doped regions 130 and 140. The lightly doped regions 130 and 140 serve as lightly doped LDD regions, and the heavily doped regions 150 and 160 serve as source or drain doped regions, respectively.

[0056] In step S02, please refer to Figure 7 As shown, a self-aligned metal silicide barrier layer 170 is formed, which covers the substrate 100, the gate structure 110 and the sidewall 120.

[0057] In this embodiment, the self-aligned metal silicide barrier layer 170 is a superposition layer of silicon oxide and silicon nitride or a silicon-rich oxide layer, and the self-aligned metal silicide barrier layer 170 can be formed by chemical vapor deposition.

[0058] In step S03, please refer to Figure 8 As shown, the self-aligned metal silicide barrier layer 170 in the self-aligned metal silicide formation region is etched, and the remaining portion of the self-aligned metal silicide barrier layer at the corner formed by the sidewall 120 and the substrate 100 forms an isolation structure 180. The isolation structure 180 is located at the bottom of the sidewall of the sidewall, and the longitudinal section of the isolation structure 180 is triangular.

[0059] The substrate 100 includes a non-self-aligned metal silicide formation region and a self-aligned metal silicide formation region. The non-self-aligned metal silicide formation region does not require the formation of self-aligned metal silicides and therefore needs to be covered by the self-aligned metal silicide barrier layer 170. However, the self-aligned metal silicide formation region requires the formation of self-aligned metal silicides, therefore a portion of the self-aligned metal silicide barrier layer 170 within the self-aligned metal silicide formation region needs to be removed. Figures 6 to 9Only the self-aligned metal silicide formation region is shown in the image.

[0060] Specifically, a photoresist layer (not shown) is formed on the substrate 100, the photoresist layer covers the self-aligned metal silicide barrier layer 170, and a photolithography process (i.e., exposure and development process) is performed on the photoresist layer to form a photoresist pattern (not shown). The photoresist pattern covers the non-self-aligned metal silicide formation region and exposes the self-aligned metal silicide formation region. Then, the self-aligned metal silicide barrier layer 170 can be etched using the photoresist pattern as a mask.

[0061] Preferably, the self-aligned metal silicide barrier layer 170 is dry etched. The remaining portion of the self-aligned metal silicide barrier layer 170 at the corner formed by the sidewall 120 and the substrate 100 forms an isolation structure 180. The isolation structure 180 is located at the bottom of the sidewall of the sidewall 120, and the longitudinal section of the isolation structure 180 is triangular (the longitudinal section refers to a plane perpendicular to the substrate 100), with one side of the triangle adjacent to the sidewall of the sidewall 120 and the other adjacent side adjacent to the substrate 100.

[0062] In this embodiment, the dry etching mainly includes three stages. The first stage (Step 1) requires etching away most of the self-aligned metal silicide barrier layer 170. The etching gas mainly includes CH3F (fluoromethane), CH4 (methane), and Ar (argon), but is not limited to these. The gas pressure is between 50 mtorr and 200 mtorr, the power is between 700 W and 900 W, and the etching time is between 1 min and 2 min. The second stage (Step 2) uses an endpoint measurement method for etching. The etching conditions are similar to those in Step 1. The etching gases mainly consist of CH3F (fluoromethane), CH4 (methane), and Ar (argon), with a pressure between 50 mtorr and 200 mtorr and a power between 400 W and 600 W. In the third stage (Step 3), the power is between 200 W and 400 W, the pressure is between 30 mtorr and 100 mtorr, and the etching gases mainly use CH2F3 (trifluoromethane) or CH3F (fluoromethane) with high selectivity and a suitable F / C ratio to prevent excessive substrate loss. The etching time is between 5 s and 15 s. Of course, the dry etching conditions are not limited to these, and this invention does not limit them. The size of the isolation structure 180 can be adjusted by adjusting the thickness of the self-aligned metal silicide barrier layer 170 or the etching conditions.

[0063] This embodiment only requires dry etching to remove part of the self-aligned metal silicide barrier layer 170. Compared with the prior art, it saves the wet etching step, simplifies the process, and reduces production costs.

[0064] After forming the isolation structure 180, the process further includes removing the photoresist pattern. Specifically, an ashing process can be used to remove the photoresist pattern.

[0065] In step S04, as Figure 9 As shown, a metal layer 190 is formed, which covers the substrate 100, the gate structure 110, the sidewall 120 and the isolation structure 180.

[0066] The metal layer 190 can be made of one of the following materials: titanium, cobalt, nickel, nickel-platinum alloy, nickel-cobalt alloy, or nickel-cobalt-platinum alloy, and can be formed by physical vapor deposition.

[0067] In step S05, as Figure 10 As shown, the substrate 100 is heat-treated to cause the metal layer 190 to react with the substrate 100 to form a self-aligned metal silicide layer 200. The isolation structure 180 provides a gap between the self-aligned metal silicide layer 200 on the substrate and the lightly doped regions 130 and 140.

[0068] The substrate 100 is heat-treated to cause the metal layer 190 to react with the exposed substrate 100 to form a self-aligned metal silicide layer 200. The reaction is a metal silicide reaction, where the metal elements of the metal layer 190 diffuse and react with silicon within the substrate 100 to form a self-aligned metal silicide layer 200 on the surface of the heavily doped regions 150 and 160. Simultaneously, the metal elements in the metal layer 190 also react with silicon on top of the polysilicon gate 110b within the gate structure 110 to form a self-aligned metal silicide layer 200 on top of the gate structure 110. At the same time, any portions of the metal layer 190 that do not form the self-aligned metal silicide layer 200 are removed.

[0069] Please refer to Figure 10As shown, during the heat treatment of the metal layer 190, the metal elements in the metal layer 190 diffuse and react with the silicon in the substrate 100. The metal elements not only diffuse longitudinally into the surface of the substrate 100, but also diffuse laterally within the substrate 100, towards the lightly doped regions 130 and 140. Due to the isolation structure 180, the lateral diffusion path of the metal elements is extended, so that the metal elements can only diffuse to the bottom of the isolation structure 180 and cannot further diffuse to the bottom of the sidewall 120. This creates a gap between the self-aligned metal silicide layer 200 and the lightly doped regions 130 and 140, thereby reducing the on-resistance, improving device efficiency, and enhancing device reliability.

[0070] The spacing between the final self-aligned metal silicide layer 200 and the lightly doped regions 130 and 140 can be changed by altering the size of the isolation structure 180. Increasing the size of the isolation structure 180, primarily by increasing the size of the side of the isolation structure 180 adjacent to the substrate 100, will increase the spacing between the self-aligned metal silicide layer 200 and the lightly doped regions 130 and 140. The size of the isolation structure 180 can be determined based on specific circumstances.

[0071] In the semiconductor structure and its formation method provided by the present invention, the self-aligned metal silicide barrier layer 170 in the self-aligned metal silicide formation region is etched. The remaining portion of the self-aligned metal silicide barrier layer 170 at the corner formed by the sidewall 120 and the substrate 100 forms an isolation structure 180. When the metal layer 190 is subsequently formed and heat-treated, the metal elements in the metal layer 190 will also undergo lateral diffusion during longitudinal diffusion. However, the presence of the isolation structure 180 prolongs the lateral diffusion path, and the metal elements can only diffuse to the bottom of the isolation structure 180 and cannot further diffuse to the bottom of the sidewall 120. This results in a gap between the self-aligned metal silicide layer 200 and the lightly doped regions 130 and 140, thereby reducing the on-resistance, improving device efficiency, and improving device reliability.

[0072] In addition, the self-aligned metal silicide barrier layer 170 is etched only by dry etching, which saves the wet etching step compared with the prior art, simplifies the process, and reduces production costs.

[0073] Accordingly, the present invention also provides a semiconductor structure formed using the semiconductor structure formation method described above.

[0074] Please refer to Figure 10 As shown, the semiconductor structure includes:

[0075] A substrate 100, a gate structure 110 located on the substrate 100 and a sidewall 120 covering the sidewall of the gate structure 110, and lightly doped regions 130 and 140 formed in the substrate 100 at the bottom of the sidewall 120;

[0076] An isolation structure 180 is located at the corner formed by the side wall 120 and the base 100. The isolation structure 180 is located at the bottom of the side wall of the side wall 120, and the longitudinal section of the isolation structure 180 is triangular.

[0077] A self-aligned metal silicide layer 200 is located within the surface of the substrate 100, and there is a gap between the self-aligned metal silicide layer 200 and the lightly doped regions 130 and 140.

[0078] The semiconductor structure further includes heavily doped regions 150 and 160, which are located within the substrate 100 on the side of the sidewall 120 away from the gate structure 110. The heavily doped region 150 is adjacent to the lightly doped region 130, and the heavily doped region 160 is adjacent to the lightly doped region 140. The doping depth of the heavily doped regions 150 and 160 is greater than the doping depth of the lightly doped regions 130 and 140. The lightly doped regions 130 and 140 serve as lightly doped LDD regions, and the heavily doped regions 150 and 160 serve as source or drain doped regions, respectively.

[0079] The gate structure 110 includes a gate dielectric layer 110a and a polysilicon gate 110b stacked sequentially. The gate dielectric layer 110a is preferably made of silicon oxide, and the polysilicon gate 110b is made of polysilicon. The sidewall 120 includes an oxide layer 120a and a nitride layer 120b. The oxide layer 120a is preferably made of silicon oxide, and the nitride layer 120b is preferably made of silicon nitride.

[0080] The self-aligned metal silicide layer 200 located within the substrate 100 has a gap between it and the lightly doped regions 130 and 140. The self-aligned metal silicide layer 200 forms an ohmic contact with the heavily doped regions 150 and 160, thereby reducing the on-resistance, improving device efficiency, and enhancing device reliability.

[0081] In summary, in the semiconductor structure and its formation method provided by this invention, the self-aligned metal silicide barrier layer within the self-aligned metal silicide formation region is etched, and the remaining portion of the self-aligned metal silicide barrier layer at the corner formed by the sidewall and the substrate forms an isolation structure. During subsequent metal layer formation and heat treatment, the metal elements in the metal layer undergo lateral diffusion during longitudinal diffusion. However, the presence of the isolation structure prolongs the lateral diffusion path, and the metal elements can only diffuse to the bottom of the isolation structure and cannot further diffuse to the bottom of the sidewall. This results in a gap between the self-aligned metal silicide layer and the lightly doped region, thereby reducing the on-resistance, improving device efficiency, and enhancing device reliability.

[0082] In addition, dry etching of the self-aligned metal silicide barrier layer saves the wet etching step compared with the prior art, simplifies the process, and reduces production costs.

[0083] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, Includes the following steps: A substrate is provided on which a gate structure and a sidewall covering the sidewall of the gate structure are formed, and a lightly doped region is formed in the substrate at the bottom of the sidewall. The substrate includes a non-self-aligned metal silicide formation region and a self-aligned metal silicide formation region. A self-aligned metal silicide barrier layer is formed, the self-aligned metal silicide barrier layer covering the substrate, the gate structure and the sidewall; The self-aligned metal silicide barrier layer within the self-aligned metal silicide formation region is etched, and the remaining portion of the self-aligned metal silicide barrier layer at the corner formed by the sidewall and the substrate forms an isolation structure. The isolation structure is located at the bottom of the sidewall of the sidewall, and the longitudinal section of the isolation structure is triangular. At the same time, the self-aligned metal silicide barrier layer within the non-self-aligned metal silicide formation region is retained. A metal layer is formed, the metal layer covering the substrate, the gate structure, the sidewalls, and the isolation structure; as well as, The substrate is heat-treated to cause the metal elements in the metal layer to diffuse and react with the substrate to form a self-aligned metal silicide layer. The isolation structure extends the lateral diffusion path of the metal elements, so that the metal elements diffuse to the bottom of the isolation structure and cannot diffuse to the bottom of the sidewall, thus creating a gap between the self-aligned metal silicide layer on the substrate and the lightly doped region.

2. The forming method as described in claim 1, characterized in that, The self-aligned metal silicide barrier layer is a superposition layer of silicon oxide and silicon nitride or a silicon-rich oxide layer.

3. The forming method as described in claim 1, characterized in that, The self-aligned metal silicide barrier layer within the self-aligned metal silicide formation region is dry-etched to form the isolation structure.

4. The forming method as described in claim 3, characterized in that, The dry etching process comprises three stages. In the first stage, the etching gas consists of CH3F, CH4, and Ar, with a pressure between 50 mtorr and 200 mtorr, a power between 700 W and 900 W, and an etching time between 1 min and 2 min. In the second stage, etching is performed using an endpoint measurement method, with the etching gas consisting of CH3F, CH4, and Ar, a pressure between 50 mtorr and 200 mtorr, and a power between 400 W and 600 W. In the third stage, the etching gas consists of CH2F3 or CH3F, with a pressure between 30 mtorr and 100 mtorr, a power between 200 W and 400 W, and an etching time between 5 s and 15 s.

5. The forming method as described in claim 1, characterized in that, The photoresist pattern formed by photolithography defines the self-aligned metal silicide formation region, and the photoresist pattern covers the non-self-aligned metal silicide formation region and exposes the self-aligned metal silicide formation region.

6. The forming method as described in claim 5, characterized in that, After forming the isolation structure and before forming the metal layer, the method further includes: removing the photoresist pattern.

7. The forming method as described in claim 1, characterized in that, A heavily doped region is also formed in the substrate on the side of the sidewall away from the gate structure, the heavily doped region being adjacent to the lightly doped region.

8. The forming method as described in claim 7, characterized in that, The step of forming the gate structure, the sidewalls, the lightly doped region, and the heavily doped region on the substrate includes: A gate structure is formed on the substrate; Using the gate structure as a mask, the substrate is subjected to a first ion implantation to form a temporary doped region; A sidewall is formed on the side of the gate structure; Using the gate structure and the sidewall as a mask, a second ion implantation is performed on the substrate to form a heavily doped region within the temporary doped region. The area within the temporary doped region where the heavily doped region is not formed is designated as the lightly doped region.

9. The forming method as described in claim 8, characterized in that, The doping depth of the heavily doped region is greater than that of the lightly doped region, and the self-aligned metal silicide layer is located within the surface of the heavily doped region and is spaced apart from the lightly doped region.

10. A semiconductor structure, characterized in that, The semiconductor structure is formed using the method for forming a semiconductor structure as described in any one of claims 1 to 9, the semiconductor structure comprising: A substrate, a gate structure located on the substrate and a sidewall covering the sidewall of the gate structure, a lightly doped region formed in the substrate at the bottom of the sidewall, the substrate including a non-self-aligned metal silicide formation region and a self-aligned metal silicide formation region; An isolation structure is located at the corner formed by the sidewall and the substrate of the self-aligned metal silicide formation region. The isolation structure is located at the bottom of the sidewall of the sidewall, and the longitudinal section of the isolation structure is triangular. A self-aligned metal silicide layer is located within the substrate surface of the self-aligned metal silicide formation region, and there is a gap between the self-aligned metal silicide layer and the lightly doped region.

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