Semiconductor package including stacked semiconductor chips

Abstract

The present application relates to a semiconductor package including stacked semiconductor chips. A semiconductor package includes: a first semiconductor chip stack including a plurality of first semiconductor chips stacked in a vertical direction; a bridge wafer stack arranged to be spaced apart from the first semiconductor chip stack in a horizontal direction and including a plurality of bridge wafers stacked in a vertical direction, wherein the bridge wafers each include a through-electrode, and the through-electrodes aligned in the vertical direction are connected to each other via connecting electrodes between the bridge wafers; a redistribution layer arranged above the first semiconductor chip stack and the bridge wafer stack; a second semiconductor chip arranged above the redistribution layer and configured to receive a voltage via the vertically aligned through-electrodes, the connecting electrodes, and the redistribution layer; and a voltage regulator configured to regulate the voltage.

Description

Technical Field

[0001] This patent document relates to a semiconductor package, and more particularly, to a semiconductor package in which a plurality of semiconductor chips are stacked in a vertical direction. Background Art

[0002] As electronic products become increasingly smaller in size, they require multiple functions and require large amounts of data processing. Consequently, there is a growing need to increase the integration level of semiconductor devices used in such electronic products.

[0003] However, due to limitations in semiconductor integration technology, it is difficult to satisfy required functions with only a single semiconductor chip, and therefore, semiconductor packages having a plurality of semiconductor chips embedded therein have been manufactured. Summary of the Invention

[0004] In one embodiment, a semiconductor package may include: a first semiconductor chip stack, the first semiconductor chip stack including a plurality of first semiconductor chips stacked in a vertical direction; a bridge chip stack, the bridge chip stack being arranged to be spaced apart from the first semiconductor chip stack in a horizontal direction and including a plurality of bridge chips stacked in a vertical direction, wherein the bridge chips respectively include through electrodes, and the through electrodes aligned in the vertical direction are connected to each other through connecting electrodes between the bridge chips; a redistribution layer, the redistribution layer being arranged above the first semiconductor chip stack and the bridge chip stack; a second semiconductor chip being arranged above the redistribution layer and being configured to receive a voltage through the through electrodes, the connecting electrodes and the redistribution layer aligned in the vertical direction; and a voltage regulator, the voltage regulator being configured to regulate a voltage.

[0005] In another embodiment, a semiconductor package may include: a first semiconductor chip stack, the first semiconductor chip stack including a plurality of first semiconductor chips stacked in a vertical direction; a bridge chip stack, the bridge chip stack being arranged to be spaced apart from the first semiconductor chip stack in a horizontal direction and including a plurality of bridge chips stacked in a vertical direction; a redistribution layer, the redistribution layer being arranged above the first semiconductor chip stack and the bridge chip stack; a second semiconductor chip being arranged above the redistribution layer and being configured to receive a voltage through the bridge chip stack and the redistribution layer; and a voltage regulator configured to regulate a voltage and including: a switch, a diode, and a capacitor included in at least one of the bridge chips; an inductor included in the redistribution layer; and a controller included in the second semiconductor chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1is a diagram schematically illustrating an example of a data processing system including a memory system according to one embodiment of the present disclosure.

[0007] Figure 2 is a cross-sectional view illustrating a semiconductor package according to one embodiment of the present disclosure.

[0008] Figure 3A is a diagram illustrating a voltage regulator according to one embodiment of the present disclosure.

[0009] Figure 3B and Figure 3C It shows Figure 3A Diagram of the operation of the voltage regulator.

[0010] Figure 3D Graph showing the current flowing through the inductor when the switch is on / off.

[0011] Figure 4 is a schematic block diagram of a semiconductor package according to another embodiment of the present disclosure.

[0012] Figure 5 is a diagram illustrating a semiconductor package according to another embodiment of the present disclosure.

[0013] Figure 6 It shows Figure 5 A perspective view of an example of an inductor.

[0014] Figure 7 It shows Figure 5 A cross-sectional view of an example of a capacitor.

[0015] Figure 8 A block diagram illustrating an electronic system employing a memory card including a semiconductor package according to one embodiment is presented.

[0016] Figure 9 A block diagram illustrating another electronic system including a semiconductor package according to one embodiment is presented. DETAILED DESCRIPTION

[0017] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0018] The drawings are not necessarily drawn to scale. In some cases, the proportions of at least some structures in the drawings may have been exaggerated in order to clearly illustrate the specific features of the described embodiments. When a specific example with two or more layers is presented in a multilayer structure in the drawings or description, the relative positioning relationship of these layers or the order in which these layers are arranged as shown reflects the specific embodiment of the described or illustrated example, and different relative positioning relationships or the order in which these layers are arranged are possible. In addition, the described or illustrated examples of multilayer structures may not reflect all the layers present in the specific multilayer structure (for example, one or more additional layers may exist between the two illustrated layers). As a specific example, when the first layer in the described or illustrated multilayer structure is referred to as being "on" or "above" the second layer or "on" or "above" the substrate, the first layer may be directly formed on the second layer or substrate, but it may also represent a structure in which one or more other intermediate layers may exist between the first layer and the second layer or substrate. It will be understood that although the terms first, second, third, etc. may be used here to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another, and are not used to define only the elements themselves or to imply a specific order.

[0019] Figure 1 is a diagram schematically illustrating an example of a data processing system including a memory system according to an embodiment of the present disclosure.

[0020] Reference Figure 1 , the data processing system 100 may include a host 110 and a memory system 120 .

[0021] The host 110 may include various wired and / or wireless electronic devices such as mobile phones, MP3 players, laptop computers, desktop computers, game consoles, televisions, projectors, etc. In addition, the host 110 may include at least one operating system (OS). The operating system may manage and control the functions and operations of the host 110 as a whole, and may be executed in response to a request from a user using the data processing system 100 or the memory system 120.

[0022] The memory system 120 may perform various operations in response to a request from the host 110. Specifically, the memory system 120 may store data accessed by the host 110. That is, the memory system 120 may be used as a main memory device or a secondary memory device of the host 110.

[0023] The memory system 120 may include a memory device 140 that stores data and a logic device 130 that controls operations of the memory device 140 .

[0024] The memory device 140 can store data accessed by the host 110 and can include a volatile memory such as a dynamic random access memory (DRAM) or a static random access memory (SRAM), a non-volatile memory such as a NAND flash memory, a resistive random access memory (RRAM), a phase change random access memory (PRAM), a magnetoresistive random access memory (MRAM), or a ferroelectric random access memory (FRAM), or a combination thereof.

[0025] The logic device 130 may control the memory device 140 in response to a request from the host 110. As an example, the logic device 130 may provide data read from the memory device 140 to the host 110, or may store data provided from the host 110 in the memory device 140. The logic device 130 may include a central processing unit (CPU), a controller, an application specific integrated circuit (ASIC), an application processor (AP), etc. Although not shown, the logic device 130 may include various units required for its operation, such as an interface unit for interfacing with the host 110 and the memory device 140, a processor for controlling the overall operation of the memory system 120, a power management unit for receiving and managing power required by the logic device 130, etc.

[0026] Furthermore, in order for the logic device 130 to perform operations such as receiving a command from the host 110 or transmitting data to the host 110, a signal transmission path between the logic device 130 and the host 110 may be required. This signal transmission path is indicated by arrow ①.

[0027] In addition, in order for the logic device 130 to access the memory device 140 and perform read / write / erase operations under the control of the processor, a signal transmission path may be required between the logic device 130 and the memory device 140. This signal transmission path is indicated by arrow ②.

[0028] In addition, in order for the logic device 130 to operate, power may be required. This power may include various levels of power supply voltage or ground voltage required by the logic device 130. Therefore, a power supply path may be required between the logic device 130 and an external device (not shown) that supplies power. This power supply path is indicated by arrow ③.

[0029] In addition, in order for the memory device 140 to operate, power may be required. This power may include various levels of power supply voltage or ground voltage required by the memory device 140. Therefore, a power supply path may be required between the memory device 140 and an external device (not shown) that provides power. This power supply path is indicated by arrow ④.

[0030] In the above-described data processing system 100, the memory device 140 may be implemented as one or more memory chips, and the logic device 130 may be implemented as one or more logic chips. In addition, the memory system 120 including the memory device 140 and the logic device 130 may be implemented in one package. That is, the memory system 120 may be implemented as a system-in-package (SIP) in which the memory chip and the logic chip are integrated in one package. This will be referred to later. Figure 2 Describe this.

[0031] Figure 2 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present disclosure.

[0032] Reference Figure 2 The semiconductor package of this embodiment may include a first redistribution layer 210, a first semiconductor chip stack 220, a bridge chip stack 230, a second redistribution layer 240, a molding layer 250, a first external connection electrode 260, a second semiconductor chip 270 and a second external connection electrode 280.

[0033] The first redistribution layer 210 may include one surface 210A for arranging the first semiconductor chip stack 220 and the bridge wafer stack 230, and another surface 210B, positioned opposite the one surface 210A, for arranging the first external connection electrode 260. The first redistribution layer 210 may be used to electrically connect the first semiconductor chip stack 220 and the bridge wafer stack 230 to the first external connection electrode 260, and may have a wiring structure therefor. In this figure, the wiring structure of the first redistribution layer 210 is schematically illustrated by lines.

[0034] In addition, instead of the first redistribution layer 210 of the present embodiment, various structures having a wiring structure for electrically connecting to the first external connection electrode 260 while supporting the first semiconductor chip stack 220 and the bridge chip stack 230, for example, a substrate such as a printed circuit board (PCB) may be used.

[0035] The first semiconductor chip stack 220 may be disposed above one surface 210A of the first redistribution layer 210. The first semiconductor chip stack 220 may include a plurality of first semiconductor chips 220-1, 220-2, 220-3, and 220-4 stacked in a vertical direction, and first connection electrodes 226 connecting the first semiconductor chips 220-1, 220-2, 220-3, and 220-4 therebetween. In the present embodiment, four first semiconductor chips 220-1, 220-2, 220-3, and 220-4 are stacked, but the present disclosure is not limited thereto, and the number of first semiconductor chips stacked in the vertical direction may be variously modified.

[0036] Each of the plurality of first semiconductor chips 220 - 1 , 220 - 2 , 220 - 3 , and 220 - 4 may include a first body portion 222 and a first through electrode 224 .

[0037] The first main body portion 222 may have one surface 222A facing the second redistribution layer 240 and another surface 222B facing the first redistribution layer 210 by being positioned opposite the one surface 222A. In addition, although not shown, the first main body portion 222 may include a semiconductor body such as a silicon body and a wiring portion formed in the semiconductor body and implementing various integrated circuits. The wiring portion may be disposed adjacent to the one surface 222A of the first main body portion 222, or may be disposed adjacent to the other surface 222B of the first main body portion 222. The wiring portion may be implemented differently depending on the type of the first semiconductor chips 220-1, 220-2, 220-3, and 220-4. For example, when the first semiconductor chips 220-1, 220-2, 220-3, and 220-4 are memory chips, the wiring portion may include a memory cell array having a plurality of memory cells. The first semiconductor chips 220-1, 220-2, 220-3, and 220-4 may include a volatile memory such as DRAM (Dynamic Random Access Memory) or SRAM (Static RAM) or a non-volatile memory such as NAND flash memory, RRAM (Resistive RAM), PRAM (Phase Change RAM), MRAM (Magnetoresistive RAM), or FRAM (Ferroelectric RAM). The first semiconductor chip stack 220 may be substantially the same as the above-mentioned Figure 1 Corresponding to the memory device 140.

[0038] The first through-electrode 224 may extend in the vertical direction to pass through the first main body portion 222 and may have a columnar shape. The first through-electrode 224 may be electrically connected to the wiring portion of the first main body portion 222. In each of the plurality of first semiconductor chips 220-1, 220-2, 220-3, and 220-4, a plurality of first through-electrodes 224 may be arranged in the horizontal direction. When the first main body portion 222 includes a silicon main body, the first through-electrode 224 may include a TSV (Through Silicon Via). The first through-electrode 224 may include a metal such as copper (Cu), tin (Sn), silver (Ag), tungsten (W), nickel (Ni), ruthenium (Ru), or cobalt (Co), or a compound of the metal.

[0039] First connection electrodes 226 may be interposed between the plurality of first semiconductor chips 220-1, 220-2, 220-3, and 220-4 to electrically connect the vertically aligned first through-electrodes 224 to one another. In this figure, in the vertical direction, one end of the first through-electrode 224 may be exposed and located at substantially the same height as one surface 222A of the first body portion 222, and the other end of the first through-electrode 224 may be exposed and located at substantially the same height as the other surface 222B of the first body portion 222. Consequently, one of the first connection electrodes 226 may directly contact one end of the first through-electrode 224 located below it, and may directly contact the other end of the first through-electrode 224 located above it. However, the present disclosure is not limited thereto, and the first connection electrodes 226 may be electrically connected to the first through-electrodes 224 via a wiring portion formed adjacent to one surface 222A or the other surface 222B of the first body portion 222. In the horizontal direction, the arrangement of the first connection electrodes 226 may be substantially the same as that of the first through-electrodes 224. In this embodiment, the first connection electrode 226 is shown as having a column shape, but the present disclosure is not limited thereto, and the first connection electrode 226 may have various shapes such as a column shape, a spherical shape, or a combination thereof. In addition, the first connection electrode 226 may include various metal materials, solder materials, or a combination thereof.

[0040] The first connection electrode 226 as described above may be further formed between the first redistribution layer 210 and the lowermost first semiconductor chip 220 - 1 , and / or between the second redistribution layer 240 and the uppermost first semiconductor chip 220 - 4 .

[0041] Therefore, through the first through electrodes 224 and the first connection electrodes 226, electrical connections can be made between the plurality of first semiconductor chips 220-1, 220-2, 220-3 and 220-4, between the first redistribution layer 210 and the first semiconductor chip stack 220, and between the first semiconductor chip stack 220 and the second redistribution layer 240.

[0042] The bridge wafer stack 230 may be provided on one surface 210A of the first redistribution layer 210 so as to be spaced apart in the horizontal direction from the first semiconductor chip stack 220. In the present embodiment, three bridge wafer stacks 230 and two first semiconductor chip stacks 220 are alternately arranged to be spaced apart from each other in the horizontal direction, but the present disclosure is not limited thereto, and various modifications may be made to the number and arrangement of the bridge wafer stacks 230 and the first semiconductor chip stacks 220 included in the semiconductor package of the present embodiment.

[0043] The bridge wafer stack 230 may include a plurality of bridge wafers 230-1, 230-2, and 230-3 stacked in a vertical direction, and a second connection electrode 236 connecting the bridge wafers to each other. In this embodiment, a case where three bridge wafers 230-1, 230-2, and 230-3 are stacked is shown, but the present disclosure is not limited thereto, and the number of bridge wafers stacked in the vertical direction may be variously modified. Furthermore, the number of bridge wafers included in the bridge wafer stack 230 may be independent of the number of first semiconductor chips included in the first semiconductor chip stack 220. As in this embodiment, when the thickness of one of the bridge wafers 230-1, 230-2, and 230-3 is greater than the thickness of one of the first semiconductor chips 220-1, 220-2, 220-3, and 220-4, the number of bridge wafers may be less than the number of first semiconductor chips. However, the thickness of the bridge wafer stack 230 in the vertical direction may be substantially the same as the thickness of the first semiconductor chip stack 220 (see thickness T1 ).

[0044] Each of the plurality of bridge wafers 230 - 1 , 230 - 2 , and 230 - 3 may include a second body portion 232 and a second through electrode 234 .

[0045] The second main body portion 232 may have one surface 232A facing the second redistribution layer 240 and another surface 232B facing the first redistribution layer 210 while being positioned opposite the one surface 232A. Furthermore, although not shown, the second main body portion 232 may include a semiconductor body, such as a silicon body, and a wiring portion formed within the semiconductor body to implement various integrated circuits. The wiring portion may be disposed adjacent to one surface 232A of the second main body portion 232, or adjacent to another surface 232B of the second main body portion 232. As will be described later, the plurality of bridge wafers 230-1, 230-2, and 230-3 may include some of the components of a voltage regulator. For example, the bridge wafers 230-1, 230-2, and 230-3 may include switches, diodes, capacitors, and the like necessary to implement the voltage regulator. This will be described later.

[0046] The second through-electrode 234 may extend in the vertical direction to pass through the second main body portion 232 and may have a columnar shape. The second through-electrode 234 may be electrically connected to the wiring portion in the second main body portion 232. In each of the plurality of bridge wafers 230-1, 230-2, and 230-3, a plurality of second through-electrodes 234 may be arranged in the horizontal direction. When the second main body portion 232 includes a silicon main body, the second through-electrode 234 may include a TSV. The second through-electrode 234 may include a metal such as copper (Cu), tin (Sn), silver (Ag), tungsten (W), nickel (Ni), ruthenium (Ru), cobalt (Co), or the like, or a compound of the metal.

[0047] Second connection electrodes 236 may be interposed between the plurality of bridge wafers 230-1, 230-2, and 230-3 to electrically connect the second through-electrodes 234 aligned in the vertical direction. In this embodiment, one end of each second through-electrode 234 may be exposed and located at substantially the same height as one surface 232A of the second body portion 232, and the other end of each second through-electrode 234 may be exposed and located at substantially the same height as the other surface 232B of the second body portion 232. Consequently, one of the second connection electrodes 236 may directly contact one end of the second through-electrode 234 located below it and may directly contact the other end of the second through-electrode 234 located above it. However, the present disclosure is not limited thereto, and the second connection electrodes 236 may be electrically connected to the second through-electrodes 234 via a wiring portion formed adjacent to one surface 232A or the other surface 232B of the second body portion 232. Horizontally, the arrangement of the second connection electrodes 236 may be substantially the same as that of the second through-electrodes 234. In this embodiment, the second connection electrode 236 is shown as having a column shape, but the present disclosure is not limited thereto, and the second connection electrode 236 may have various shapes such as a column shape, a spherical shape, or a combination thereof. In addition, the second connection electrode 236 may include various metal materials, solder materials, or a combination thereof.

[0048] The second connection electrode 236 as described above may be further formed between the first redistribution layer 210 and the lowermost bridge wafer 230 - 1 , and / or between the second redistribution layer 240 and the uppermost bridge wafer 230 - 3 .

[0049] Therefore, the second through-electrodes 234 and the second connection electrodes 236 enable electrical connections between the plurality of bridge chips 230 - 1 , 230 - 2 and 230 - 3 , between the first redistribution layer 210 and the bridge chip stack 230 , and between the bridge chip stack 230 and the second redistribution layer 240 .

[0050] The second redistribution layer 240 can be disposed above the first semiconductor chip stack 220 and the bridge wafer stack 230. The second redistribution layer 240 may include one surface 240A for arranging the second external connection electrode 280 connected to the second semiconductor chip 270, and another surface 240B facing the first semiconductor chip stack 220 and the bridge wafer stack 230 by being positioned relative to the one surface 240A. The second redistribution layer 240 can be used to electrically connect the first semiconductor chip stack 220 and the bridge wafer stack 230 to the second external connection electrode 280, and may have a wiring structure for the second redistribution layer 240. In this figure, the wiring structure of the second redistribution layer 240 is schematically shown by lines. In addition, the second redistribution layer 240 may include other components for implementing a voltage regulator, such as an inductor. This will be described later.

[0051] A molding layer 250 may be formed between the first redistribution layer 210 and the second redistribution layer 240 to surround the side surfaces of the first semiconductor chip stack 220 and the bridge wafer stack 230 to mold them. The molding layer 250 may include a molding material such as EMC (epoxy molding compound). In this embodiment, the molding layer 250 may fill the spaces between the plurality of first semiconductor chips 220-1, 220-2, 220-3, and 220-4, between the bottommost first semiconductor chip 220-1 and the first redistribution layer 210, between the topmost first semiconductor chip 220-4 and the second redistribution layer 240, between the plurality of bridge wafers 230-1, 230-2, and 230-3, between the bottommost bridge wafer 230-1 and the first redistribution layer 210, and between the topmost bridge wafer 230-3 and the second redistribution layer 240. Therefore, the mold layer 250 may be formed to surround side surfaces of the first and second connection electrodes 226 and 236 located in the spaces. However, the present disclosure is not limited thereto, and the spaces may be filled with other filling materials (not shown) different from the mold layer 250 .

[0052] The first external connection electrode 260 can be electrically connected to the first redistribution layer 210 and can be used to electrically connect the semiconductor package of this embodiment to an external component (see the dotted rectangle). In this embodiment, the first external connection electrode 260 is shown as having a spherical shape, but the present disclosure is not limited thereto, and the first external connection electrode 260 can have various shapes such as a column shape, a spherical shape, or a combination thereof.

[0053] The second semiconductor chip 270 may be disposed above one surface 240A of the second redistribution layer 240. The second semiconductor chip 270 may be disposed so that one surface 270A thereof faces one surface 240A of the second redistribution layer 240. When the first semiconductor chips 220-1, 220-2, 220-3, and 220-4 are memory chips, the second semiconductor chip 270 may include a logic circuit for controlling the memory chips. That is, the second semiconductor chip 270 may be substantially the same as the above-described Figure 1 The second semiconductor chip 270 may also include other components for implementing a voltage regulator, such as a controller for controlling the on / off switching of the voltage regulator. The components of the plurality of bridge wafers 230-1, 230-2, and 230-3, the second redistribution layer 240, and the second semiconductor chip 270 may form a voltage regulator. This will be described later.

[0054] The second external connection electrode 280 may be interposed between the second semiconductor chip 270 and the second redistribution layer 240 to electrically connect them. In this embodiment, the second external connection electrode 280 is shown as having a spherical shape, but the present disclosure is not limited thereto, and the second external connection electrode 280 may have various shapes such as a columnar shape, a spherical shape, or a combination thereof. In addition, the second external connection electrode 280 may include various metal materials, solder materials, or a combination thereof.

[0055] The space between the second semiconductor chip 270 and the second redistribution layer 240 may be filled with a filling material 285 such as an underfill. The filling material 285 may surround side surfaces of the second external connection electrode 280.

[0056] Therefore, it is possible to implement a SIP in which the first semiconductor chip stack 220 serving as a memory device and the second semiconductor chip 270 serving as a logic device are integrated into one package.

[0057] Next, a signal transmission path and a power supply path in the semiconductor package of the present embodiment will be described.

[0058] First, as indicated by the dotted line ①', transmission of external signals between the second semiconductor chip 270 and the external components of the semiconductor package (refer to the dotted rectangle) can be performed through the first external connection electrode 260 for transmitting external signals, the first redistribution layer 210, the stacked structure of the second connection electrodes 236 and the second through electrodes 234 alternately arranged in the vertical direction, the second redistribution layer 240 and the second external connection electrode 280. Figure 1 When corresponding to the logic device 130, the signal transmission path indicated by the dotted line ①' can be Figure 1 Corresponding to the signal transmission path ①.

[0059] Next, as indicated by the dotted line ②', transmission of internal signals between the second semiconductor chip 270 and the first semiconductor chip stack 220 can be performed through the stacked structure of the first through-electrodes 224 and the first connection electrodes 226 for transmitting internal signals, the second redistribution layer 240, and the second external connection electrodes 280, which are alternately arranged in the vertical direction. Figure 1 When the logic device 130 and the memory device 140 correspond to each other, the signal transmission path indicated by the dotted line ②' can be Figure 1 Corresponding to the signal transmission path ②.

[0060] Next, as indicated by the dotted line ③', power supply from the external components (refer to the dotted rectangle) to the second semiconductor chip 270 can be performed through the first external connection electrode 260 for providing power required by the second semiconductor chip 270, the first redistribution layer 210, the stacked structure of the second connection electrodes 236 and the second through electrodes 234 alternately arranged in the vertical direction, the second redistribution layer 240, and the second external connection electrode 280. Figure 1 When the logic device 130 corresponds to the power supply path shown by the dotted line ③', the power supply path can be Figure 1 This corresponds to the power supply path ③.

[0061] Next, as indicated by the dotted line ④', power supply from the external component (refer to the dotted line) to the first semiconductor chip stack 220 can be performed through the first external connection electrode 260 for providing power required by the first semiconductor chip stack 220, the first redistribution layer 210, the stacked structure of the first connection electrodes 226 and the first through electrodes 224 alternately arranged in the vertical direction, the second redistribution layer 240, and the second external connection electrode 280. Figure 1 When the memory device 140 corresponds to the power supply path indicated by the dotted line ④ ', the power supply path can be Figure 1 Corresponding to the power supply path ④.

[0062] According to the above-described semiconductor package, the following effects can be achieved.

[0063] When the second semiconductor chip 270 is a logic chip, it includes a logic circuit that consumes a large amount of power, and therefore, it can have high heat generation characteristics. However, when the second semiconductor chip 270 is arranged at the uppermost portion of the semiconductor package as in the present embodiment, the heat generated can be easily dissipated upward. Therefore, this heat generation problem can be solved. When the logic device 130 is a logic chip, it includes a logic circuit that consumes a large amount of power, and therefore, it can have high heat generation characteristics. However, when the logic device 130 is arranged at the uppermost portion of the semiconductor package, for example, when the second semiconductor chip 270 is the logic device 130, the heat generated can be easily dissipated upward. Therefore, this heat generation problem can be solved.

[0064] However, when the second semiconductor chip 270 is disposed at the uppermost portion of the semiconductor package, a power supply path (refer to FIG. Figure 2 ③' in the figure may increase in length, resulting in a problem in which power supply becomes difficult. In order to solve this problem, the amplitude of the voltage input from the external component can be increased, but when the amplitude of the voltage required by the second semiconductor chip 270 (for example, a logic chip) is less than the input voltage, a voltage regulator that reduces the input voltage may be required. In this embodiment, by implementing a voltage regulator using a bridge chip stack 230 and a second redistribution layer 240, power supply to the second semiconductor chip 270 can be smoothly performed while maintaining the area of the semiconductor package or not significantly increasing the area of the semiconductor package. This will be described later. When the logic device 130 is, for example, the second semiconductor chip 270 and is disposed at the uppermost portion of the semiconductor package, the power supply path from the external component to the second semiconductor chip 270 (refer to Figure 2 The length of ③') in may increase, resulting in a problem in which power supply becomes difficult. To solve this problem, the amplitude of the voltage input from the external component can be increased, but when the amplitude of the voltage required by the logic device 130 (e.g., a logic chip) is less than the input voltage, a voltage regulator that reduces the input voltage may be required. In this embodiment, by implementing a voltage regulator using a bridge chip stack 230 and a second redistribution layer 240, power supply to the second semiconductor chip 270 (e.g., logic device 130) can be smoothly performed while maintaining the area of the semiconductor package or without significantly increasing the area of the semiconductor package. This will be described later.

[0065] Furthermore, in this embodiment, by relatively increasing the width W2 of the second through-electrode 234 of the bridge wafer laminate 230, the resistance of the power supply path to the second semiconductor chip 270 can be reduced, and the phenomenon of fusion, which causes the power supply path to be cut off due to the flow of high current, can be prevented. In other words, power can be supplied to the second semiconductor chip 270 more smoothly. As an example, the width W2 of the second through-electrode 234 can be greater than the width W1 of the first through-electrode 224.

[0066] In the above-described semiconductor package, the second semiconductor chip 270 is a logic chip or, for example, the logic device 130, and the first semiconductor chips 220-1, 220-2, 220-3, and 220-4 are memory chips. However, the present disclosure is not limited thereto. This embodiment may be applied when the second semiconductor chip 270 has a larger area in a plan view than the first semiconductor chips 220-1, 220-2, 220-3, and 220-4 and consumes more power and / or generates more heat during operation.

[0067] In addition, the following will refer to Figures 3A to 3D The configuration and operation of the voltage regulator are described below with reference to Figures 4 to 7 How to implement the voltage regulator in the semiconductor package of this embodiment is described.

[0068] Figure 3A is a diagram illustrating a voltage regulator according to one embodiment of the present disclosure. Figure 3B and Figure 3C It shows Figure 3A FIGURE 1 shows the operation of the voltage regulator. Specifically, Figure 3B Shows when Figure 3A The current flow path when the switch is turned on (refer to Figure 3B thick arrows), and Figure 3C Shows when Figure 3A The current flow path when the switch is open (refer to Figure 3C thick arrows). Figure 3D Graph showing the current flowing through the inductor when the switch is on / off.

[0069] Reference Figure 3A The voltage regulator of this embodiment may include a switch, a controller, a diode D, an inductor L and a capacitor C.

[0070] A controller may be connected to a control terminal of the switch to control the on / off switching of the switch. The switch may be a three-terminal device having an input terminal connected to an input voltage Vin, an output terminal connected to an inductor L, and a control terminal. For example, the switch may include a transistor. The inductor L may have an input terminal connected to the switch and an output terminal connected to an output voltage Vout. The diode D may have an output terminal connected between the switch and the inductor L and an input terminal connected between ground GND and the output voltage Vout. The capacitor C may have two terminals connected between the inductor L and the output voltage Vout and between ground GND and the output voltage Vout, respectively.

[0071] Reference Figure 3B , when the switch is turned on, the input voltage Vin can be connected to the inductor L. At this time, because the reverse current is applied to the diode D, the diode D can be in a cut-off state. Therefore, due to the difference between the input voltage Vin and the output voltage Vout, the current flowing through the inductor L can increase. This is shown in Figure 3D In the connected Ton section.

[0072] In a state where the switch is turned on, the current flowing through the inductor L may flow to both the capacitor C and the load, and thus, the capacitor C may be charged.

[0073] Reference Figure 3C , when the switch is turned off, the input voltage Vin applied to the inductor L can be removed. Even so, the current of the inductor L may not change immediately. This is because in the state where the switch is turned off, a forward current is applied to the diode D to turn on the diode D, so the current flowing through the load and the diode D flows back to the inductor L. In addition, in the state where the switch is turned off, the capacitor C can be discharged to the load, thereby increasing the total amount of current flowing through the load. As a result, the current flowing through the inductor L can gradually decrease. This is also well shown in Figure 3D In the disconnection Toff section.

[0074] In such a voltage regulator, the amplitude of the output voltage Vout can be appropriately adjusted by appropriately adjusting the on / off time and / or on / off period of the switch to minimize the difference between the peak value of the current flowing through the inductor L in the on-state Ton section and the peak value of the current flowing through the inductor L in the off-state Toff section. Specifically, an output voltage Vout that is reduced by a predetermined degree compared to the input voltage Vin can be obtained. As used herein, the term "predetermined" with respect to a parameter (such as a predetermined degree, predetermined depth, predetermined angle, predetermined voltage, etc.) means that the value of the parameter is determined before the parameter is used in a process or algorithm. For certain embodiments, the value of the parameter is determined before the process or algorithm begins. In other embodiments, the value of the parameter is determined during the process or algorithm but before the parameter is used in the process or algorithm.

[0075] Figure 4 is a schematic block diagram of a semiconductor package according to another embodiment of the present disclosure. Figure 4 Schematically shows the Figure 2 In the semiconductor package, specifically, Figure 2 How to realize the bridge wafer stack, the second redistribution layer and the second semiconductor chip Figure 3A For ease of description, Figure 4 Only the Figure 2 A portion of the semiconductor package corresponding to the bridge wafer stack, the second redistribution layer, and the second semiconductor chip.

[0076] Reference Figure 4 The semiconductor package of this embodiment may include a bridge wafer stack 430, a second redistribution layer 440, and a second semiconductor chip 470 stacked in sequence in a vertical direction. In this case, the bridge wafer stack 430 may include a plurality of bridge wafers 430-1, 430-2, and 430-3 stacked in the vertical direction. In this embodiment, a case where three bridge wafers 430-1, 430-2, and 430-3 are stacked is shown, but the present disclosure is not limited thereto, and various modifications may be made to the number of bridge wafers stacked in the vertical direction.

[0077] In this case, the voltage regulator may include a switch 432 , a diode 434 , and a capacitor 436 formed in the bridge wafer stack 430 , an inductor 442 formed in the second redistribution layer 440 , and a controller 472 formed in the second semiconductor chip 470 .

[0078] The controller 472 can be electrically connected to the control terminal of the switch 432 to control the on / off state of the switch 432. The shorter the electrical connection path between the controller 472 and the switch 432, the faster the controller 472 controls the switch 432. To this end, the switch 432 can be formed in the uppermost bridge wafer 430-3 of the bridge wafer stack 430, which is closest to the second semiconductor chip 470. However, the present disclosure is not limited thereto, and the switch 432 can be formed in one of the plurality of bridge wafers 430-1, 430-2, and 430-3.

[0079] The electrical path between the controller 472 and the control terminal of the switch 432 is indicated by arrows Although not shown, the electrical path This can be achieved through connecting electrodes between the second semiconductor chip 470 and the second redistribution layer 440, a wiring structure in the second redistribution layer 440, connecting electrodes between the uppermost bridge wafer 430-3 and the second redistribution layer 440, and a wiring structure in the uppermost bridge wafer 430-3.

[0080] The input terminal of the switch 432 can be connected to an external component (not shown) to receive power, ie, the input voltage Vin. The electrical path between the input terminal of the switch 432 and the external component is indicated by arrows Although not shown, the electrical path This can be achieved by a stacked structure of connection electrodes and through electrodes connecting the plurality of bridge wafers 430 - 1 , 430 - 2 , and 430 - 3 .

[0081] The output terminal of the switch 432 can be connected to the inductor 442 to transmit the voltage provided to the switch 432. The electrical path between the output terminal of the switch 432 and the inductor 442 is indicated by the arrow Although not shown, the electrical path This can be achieved through the wiring structure in the uppermost bridge wafer 430 - 3 , the connection electrodes between the second redistribution layer 440 and the uppermost bridge wafer 430 - 3 , and the wiring structure in the second redistribution layer 440 .

[0082] Diode 434 can be formed together with switch 432 in the same bridge wafer as switch 432. For example, diode 434 can be formed in the uppermost bridge wafer 430-3. This is because the area occupied by switch 432 and diode 434 is small, which facilitates forming switch 432 and diode 434 in one bridge wafer and shortens the electrical path between switch 432 and diode 434.

[0083] The output terminal of the diode 434 can be connected to the electrical path That is, the output terminal of the diode 434 can be connected between the output terminal of the switch 432 and the input terminal of the inductor 442. The electrical path connected to the output terminal of the diode 434 is indicated by the arrow Although not shown, the electrical path This can be achieved by a wiring structure in the uppermost bridge wafer 430 - 3 . The input terminal of the diode 434 can be electrically connected to ground.

[0084] The inductor 442 may be formed in the second redistribution layer 440. This is because the area occupied by the inductor 442 is relatively large compared to the switch 432, the diode 434, the capacitor 436, etc. As described above, the input terminal of the inductor 442 may be connected to the second redistribution layer 440 through the electrical path The output terminal of the inductor 442 is connected to the output terminal of the switch 432. The output terminal of the inductor 442 can be connected to the second semiconductor chip 470, and thus the power regulated by the voltage regulator (ie, the output voltage Vout) can be provided to the second semiconductor chip 470. The electrical path between the output terminal of the inductor 442 and the second semiconductor chip 470 is indicated by arrows. Although not shown, the electrical path This can be achieved through a wiring structure in the second redistribution layer 440 and a connection electrode between the second redistribution layer 440 and the second semiconductor chip 470 .

[0085] Capacitor 436 may be formed in the remaining bridge wafers 430-1 and 430-2 of the bridge wafer stack 430, except for the topmost bridge wafer 430-3. Capacitor 436 may not be formed in the topmost bridge wafer 430-3 to increase the capacitance of capacitor 436 by ensuring sufficient area for forming capacitor 436. If capacitor 436 were formed in the topmost bridge wafer 430-3, in which switch 432 and diode 434 are formed, the area for forming capacitor 436 may be insufficient. Alternatively, capacitor 436 may be formed in all bridge wafers of the remaining bridge wafers 430-1 and 430-2, except for the topmost bridge wafer 430-3, to further increase the capacitance of capacitor 436. However, the present disclosure is not limited thereto. In another embodiment, capacitor 436 may be formed in the topmost bridge wafer 430-3. Alternatively, capacitor 436 may be formed in one of the remaining bridge wafers 430-1 and 430-2.

[0086] One end of the capacitor 436 may be connected to the second semiconductor chip 470 (ie, the output voltage Vout). The electrical path connected to one end of the capacitor 436 is indicated by arrow Although not shown, this electrical path This can be achieved by a stacked structure of connection electrodes and through-electrodes connecting the plurality of bridge wafers 430-1, 430-2, and 430-3, a connection electrode between the uppermost bridge wafer 430-3 and the second redistribution layer 440, a wiring structure of the second redistribution layer 440, and a connection electrode between the second redistribution layer 440 and the second semiconductor chip 470. The other end of the capacitor 436 can be electrically connected to ground.

[0087] Therefore, the semiconductor package of this embodiment can be realized Figure 3A The voltage regulator described in .

[0088] Figure 5 is a more detailed diagram showing a semiconductor package according to another embodiment of the present disclosure. Figure 4 In FIG, the components of the voltage regulator and the electrical connections therebetween are briefly shown with boxes and lines. Figure 5 , an example of components for implementing a voltage regulator and electrical connections therebetween is shown.

[0089] Reference Figure 5 The semiconductor package of this embodiment may include a bridge wafer stack 530, a second redistribution layer 540, and a second semiconductor chip 570 sequentially stacked in a vertical direction. The bridge wafer stack 530, the second redistribution layer 540, and the second semiconductor chip 570 may be substantially the same as Figure 4 The bridge wafer stack 430 , the second redistribution layer 440 and the second semiconductor chip 470 correspond to each other.

[0090] The bridge wafer stack 530 may include a plurality of bridge wafers 530 - 1 , 530 - 2 , and 530 - 3 stacked in a vertical direction and a second connection electrode 536 connecting them to each other. Each of the plurality of bridge wafers 530 - 1 , 530 - 2 , and 530 - 3 may include a second body portion 532 and a second through electrode 534 .

[0091] The second body portion 532 may have one surface 532A and another surface 532B. The second body portion 532 may include a semiconductor body 532S and a wiring portion 532W disposed above the semiconductor body 532S. The wiring portion 532W may be disposed adjacent to the one surface 532A of the second body portion 532. In addition to the transistor TR, the diode D, and the capacitor C to be described later, the wiring structure in the wiring portion 532W is schematically shown by lines.

[0092] The second through electrode 534 may be formed to penetrate the semiconductor body 532S. One end of the second through electrode 534 may be connected to the wiring portion 532W, and may be electrically connected to the second connection electrode 536 located above the second through electrode 534 through the wiring portion 532W. On the other hand, the other end of the second through electrode 534 may directly contact the second connection electrode 536 located below the second through electrode 534.

[0093] The second through electrodes 534 and the second connection electrodes 536, which are electrically connected to each other while being aligned in the vertical direction, can perform the same function. In this embodiment, the stacked structure of the second through electrodes 534 and the second connection electrodes 536 located on the leftmost side can be connected to the input voltage Vin, the stacked structure of the second through electrodes 534 and the second connection electrodes 536 located on the rightmost side can be connected to the ground GND, and the stacked structure of the second through electrodes 534 and the second connection electrodes 536 therebetween can be connected to the output voltage Vout.

[0094] The second redistribution layer 540 may be disposed above the bridge wafer stack 530 and may be electrically connected to the bridge wafer stack 530 through a second connection electrode 536 disposed between the uppermost bridge wafer 530-3 and the second redistribution layer 540. A wiring structure in the second redistribution layer 540 is schematically illustrated by lines, except for an inductor L to be described later.

[0095] The second semiconductor chip 570 may be disposed over the second redistribution layer 540 and may be electrically connected to the second redistribution layer 540 through a second external connection electrode 580 disposed between the second redistribution layer 540 and the second semiconductor chip 570. A detailed configuration of the second semiconductor chip 570 is omitted except for a controller 572 to be described later.

[0096] Here, the transistor TR corresponding to the switch of the voltage regulator can be formed in one of the multiple bridge wafers 530-1, 530-2, and 530-3. For example, the transistor TR can be formed in the uppermost bridge wafer 530-3. More specifically, the transistor TR can include a gate G formed above the semiconductor body 532S and junction regions J formed in the semiconductor body 532S at both sides of the gate G. The gate G can correspond to the control terminal of the switch, and the two junction regions J can correspond to the input terminal and output terminal of the switch, respectively.

[0097] The gate G may be part of the wiring structure of the wiring portion 532W. The gate G may be connected to the controller 572 through the wiring structure of the wiring portion 532W, the second connection electrode 536, the wiring structure of the second redistribution layer 540, and the second external connection electrode 580. Therefore, the controller 572 may control the on / off state of the transistor TR by applying a predetermined voltage to the gate G.

[0098] Among the two junction regions J, the junction region J corresponding to the input terminal of the transistor TR (for example, the junction region J on the left) can be connected to the stacked structure of the second through electrode 534 and the second connection electrode 536 connected to the input voltage Vin through the wiring structure of the wiring part 532W connected thereto.

[0099] Among the two junction regions J, the junction region J corresponding to the output terminal of the transistor TR (for example, the junction region J on the right side) can be connected to the input terminal of the inductor L through the wiring structure of the wiring portion 532W connected thereto, the second connection electrode 536, and the wiring structure of the second redistribution layer 540.

[0100] The diode D may be implemented by two junction regions having different conductivity types formed in the semiconductor body 532S. One of the two junction regions (e.g., the N-type junction region) may correspond to the output terminal of the diode D and may be connected to the wiring structure between the junction region J corresponding to the output terminal of the transistor TR and the second connection electrode 536 via the wiring structure of the wiring portion 532W connected thereto. The other of the two junction regions (e.g., the P-type junction region) may correspond to the input terminal of the diode D and may be connected to the stacked structure of the second through electrode 534 and the second connection electrode 536 connected to the ground GND via the wiring structure of the wiring portion 532W connected thereto.

[0101] The inductor L may be formed in the second redistribution layer 540. As described above, the input terminal of the inductor L may be connected to the junction region J corresponding to the output terminal of the transistor TR, for example, the junction region J on the right side, through the wiring structure connected thereto, the second connection electrode 536, and the wiring structure of the wiring portion 532W of the uppermost bridge chip 530-3. The output terminal of the inductor L may be connected to the second semiconductor chip 570 through the wiring structure connected thereto and the second external connection electrode 580 to provide the output voltage Vout to the second semiconductor chip 570. In addition, the output terminal of the inductor L may be connected to a stacked structure of a second through electrode 534 and a second connection electrode 536. That is, there may be a stacked structure of a second through electrode 534 and a second connection electrode 536 connected to the output voltage Vout. For example, in Figure 6 The specific shape of the inductor L is shown in FIG. , but the shape of the inductor L is not limited to Figure 6 The shape shown in .

[0102] Figure 6 It shows Figure 5 A perspective view of an example of an inductor.

[0103] Reference Figure 6 , the inductor L may include a conductive line 610 and a conductive via 620. The conductive line 610 may include a first conductive line 610-1 and a second conductive line 610-2 located at different layers in a vertical direction.

[0104] The plurality of first conductive lines 610-1 may be arranged parallel to one another, and the plurality of second conductive lines 610-2 may cross the plurality of first conductive lines 610-1 at a predetermined angle while being arranged parallel to one another. One end of one of the plurality of first conductive lines 610-1 may overlap with one end of the corresponding second conductive line 610-2 and may be connected thereto via a conductive via 620. The other end of one of the plurality of first conductive lines 610-1 may overlap with one end of another second conductive line 610-2 adjacent to the corresponding second conductive line 610-2 and may be connected thereto via a conductive via 620. Thus, the plurality of first conductive lines 610-1 and the plurality of second conductive lines 610-2 may be connected to one another in a chain shape.

[0105] The two ends E1 and E2 of the inductor L may be positioned to extend from the first conductive line 610-1 and / or the second conductive line 610-2. The two ends E1 and E2 of the inductor L may be connected to the above Figure 5 The wiring structure of the second redistribution layer 540 is shown in FIG.

[0106] Although not shown, the conductive line 610 and the conductive via 620 forming the inductor L may be molded with an insulating material. In addition, a material having a high magnetic permeability compared to the insulating material may be interposed between the first conductive line 610-1 and the second conductive line 610-2.

[0107] Return to reference Figure 5 , the capacitor C may be formed in each of the remaining bridge chips 530-1 and 530-2 except the uppermost bridge chip 530-3 of the bridge chip stack 530. One end of the capacitor C may be connected to the stacked structure of the second through electrode 534 and the second connection electrode 536 connected to the output voltage Vout through the wiring structure of the wiring portion 532W connected thereto. The other end of the capacitor C may be connected to the stacked structure of the second through electrode 534 and the second connection electrode 536 connected to the ground GND through the wiring structure of the wiring portion 532W connected thereto. For example, in Figure 7 The specific shape of the capacitor C is shown in FIG. 1 , but the shape of the capacitor C is not limited to Figure 7 The shape shown in .

[0108] Figure 7 It shows Figure 5 A cross-sectional view of an example of a capacitor.

[0109] Reference Figure 7 , the capacitor C may include a first electrode 710, a second electrode 730, and a dielectric layer 720 interposed between the first electrode 710 and the second electrode 730. Specifically, the capacitor C may correspond to a trench capacitor in which the first electrode 710, the second electrode 730, and the dielectric layer 720 are formed along a trench 701 formed in the semiconductor body 532S.

[0110] More specifically, the wiring portion 532W disposed above the semiconductor body 532S may include a first insulating layer I1, a second insulating layer I2, and a third insulating layer I3. A trench 701 may be formed to a predetermined depth in the first insulating layer I1 and the semiconductor body 532S. The trench 701 may be located horizontally between the second through-electrode 534 connected to the output voltage Vout and the second through-electrode 534 connected to the ground GND. One or more trenches 701 may be formed.

[0111] The first electrode 710 may have a thin thickness that does not completely fill the trench 701 and may be conformally formed along a surface of the trench 701 and an upper surface of the first insulating layer 11. The first electrode 710 may be connected to one end of the second through electrode 534 connected to the ground GND.

[0112] The dielectric layer 720 may have a thin thickness that does not completely fill the trench 701 in which the first electrode 710 is formed, and may be formed over the first electrode 710 to be located inside each of the plurality of trenches 701 .

[0113] The second electrode 730 may be formed to penetrate the second insulating layer 12 and extend onto the upper surface of the second insulating layer 12 while completely filling the remaining space of the trench 701 in which the first electrode 710 and the dielectric layer 720 are formed. The second electrode 730 may be connected to one end of the second through electrode 534 connected to the output voltage Vout.

[0114] In this embodiment, a trench type capacitor is shown, but the present disclosure is not limited thereto, and capacitors of various shapes in which a dielectric layer is interposed between two electrodes may be implemented.

[0115] Return to reference Figure 5 As a result, a voltage regulator including the transistor TR, the diode D, the capacitor C, the inductor L, and the controller 572 can be implemented in the semiconductor package of the present embodiment.

[0116] According to the above-described semiconductor package, a voltage regulator can be implemented without increasing the area of the bridge wafers 530 - 1 , 530 - 2 , and 530 - 3 or the area of the second redistribution layer 540 . As a result, power can be smoothly supplied to the second semiconductor chip 570 .

[0117] According to the above embodiments of the present disclosure, it is possible to provide a semiconductor package capable of improving heat dissipation characteristics and supplying a stable voltage while satisfying high performance / high capacity requirements.

[0118] Figure 8 A block diagram illustrating an electronic system including a memory card 7800 employing at least one of the semiconductor packages according to the embodiments is presented. Memory card 7800 includes a memory 7810, such as a nonvolatile memory device, and a memory controller 7820. Memory 7810 and memory controller 7820 can store data or read stored data. At least one of memory 7810 and memory controller 7820 can include at least one of the semiconductor packages according to the described embodiments.

[0119] The memory 7810 may include a nonvolatile memory device to which the technology of the embodiments of the present disclosure is applied. The memory controller 7820 may control the memory 7810 so as to read out stored data or store data in response to a read / write request from the host 7830.

[0120] Figure 9 A block diagram illustrating an electronic system 8710 including at least one of the semiconductor packages according to the described embodiments is presented. The electronic system 8710 may include a controller 8711, an input / output device 8712, and a memory 8713. The controller 8711, the input / output device 8712, and the memory 8713 may be coupled to each other via a bus 8715 that provides a path through which data may be moved.

[0121] In one embodiment, the controller 8711 may include one or more microprocessors, digital signal processors, microcontrollers, and / or logic devices capable of performing the same functions as these components. The controller 8711 or the memory 8713 may include one or more semiconductor packages according to embodiments of the present disclosure. The input / output device 8712 may include at least one selected from a keypad, a keyboard, a display device, a touch screen, and the like. The memory 8713 is a device for storing data. The memory 8713 may store data and / or commands to be executed by the controller 8711, etc.

[0122] The memory 8713 may include a volatile memory device such as DRAM and / or a non-volatile memory device such as flash memory. For example, the flash memory may be installed in an information processing system such as a mobile terminal or a desktop computer. The flash memory may constitute a solid-state disk (SSD). In this case, the electronic system 8710 may stably store a large amount of data in the flash memory system.

[0123] The electronic system 8710 may further include an interface 8714 configured to send data to and receive data from a communication network. The interface 8714 may be a wired type or a wireless type. For example, the interface 8714 may include an antenna or a wired or wireless transceiver.

[0124] The electronic system 8710 may be implemented as a mobile system, a personal computer, an industrial computer, or a logic system that performs various functions. For example, the mobile system may be any one of a personal digital assistant (PDA), a portable computer, a tablet computer, a mobile phone, a smart phone, a wireless phone, a laptop computer, a memory card, a digital music system, and an information transmission / reception system.

[0125] If the electronic system 8710 represents a device capable of performing wireless communications, the electronic system 8710 can be used in a communication system using technology such as CDMA (Code Division Multiple Access), GSM (Global System for Mobile Communications), NADC (North American Digital Cellular), E-TDMA (Enhanced Time Division Multiple Access), WCDMA (Wideband Code Division Multiple Access), CDMA2000, LTE (Long Term Evolution), or Wibro (Wireless Broadband Internet).

[0126] Although various embodiments have been described for purposes of illustration, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the present teachings as defined by the following claims.

[0127] CROSS-REFERENCE TO RELATED APPLICATIONS

[0128] This application claims priority from Korean Patent Application No. 10-2021-0017839, filed on February 8, 2021, which is hereby incorporated by reference in its entirety.

Claims

1. A semiconductor package, comprising: a first semiconductor chip stack including a plurality of first semiconductor chips stacked in a vertical direction; a bridge wafer stack disposed to be spaced apart from the first semiconductor chip stack in a horizontal direction and including a plurality of bridge wafers stacked in the vertical direction, wherein the plurality of bridge wafers respectively include through electrodes, and the through electrodes aligned in the vertical direction are connected to each other via connection electrodes between the plurality of bridge wafers; a redistribution layer disposed over the first semiconductor chip stack and the bridge wafer stack; a second semiconductor chip disposed over the redistribution layer and receiving a voltage through the through-electrodes, the connection electrodes, and the redistribution layer aligned in the vertical direction; and a voltage regulator, wherein the voltage regulator regulates the voltage, wherein the voltage regulator comprises: a switch included in an uppermost bridge wafer of the plurality of bridge wafers that is closest to the second semiconductor chip; a diode included in the uppermost bridge wafer of the plurality of bridge wafers; a capacitor included in the remaining bridge wafers of the plurality of bridge wafers except the uppermost bridge wafer; an inductor included in the redistribution layer; and A controller is included in the second semiconductor chip.

2. The semiconductor package according to claim 1, wherein Each of the plurality of bridge wafers includes a semiconductor body and a wiring portion disposed above the semiconductor body, and The through-electrode passes through the semiconductor body and is electrically connected to the wiring portion.

3. The semiconductor package according to claim 2, wherein The switch includes a transistor including a gate formed over the semiconductor body and junction regions formed in the semiconductor body at both sides of the gate.

4. The semiconductor package according to claim 3, wherein The gate is connected to the controller through the wiring portion and the redistribution layer, wherein a junction region at one of both sides of the gate is connected to one end of the through electrode through a wiring portion, the through electrode being provided in the bridge wafer in which the switch is formed and connected to an input voltage, and The junction region at the other of the two sides of the gate is connected to the inductor through the wiring portion and the redistribution layer.

5. The semiconductor package according to claim 3, wherein The diode includes a junction region formed in the semiconductor body of the bridge wafer in which the switch is formed, and the junction region has different conductivity types. The semiconductor package according to claim 5 , wherein: One of the junction regions of the diode is connected between the junction region at the other of both sides of the gate and the inductor through the wiring portion, and The other of the junction regions of the diode is connected to one end of the through-electrode, which is provided in the bridge wafer in which the switch is formed and is connected to the ground, through the wiring portion.

7. The semiconductor package according to claim 2, wherein The capacitor includes a first electrode, a second electrode, and a dielectric layer between the first electrode and the second electrode, wherein the first electrode is connected to the through electrode provided in the bridge wafer in which the capacitor is formed and connected to an output voltage, and wherein the second electrode is connected to the through electrode provided in the bridge wafer in which the capacitor is formed and connected to the ground.

8. The semiconductor package according to claim 7, wherein The first electrode, the second electrode, and the dielectric layer are formed along a trench formed in the semiconductor body.

9. The semiconductor package according to claim 1, wherein The inductor comprises: a plurality of first conductive lines, wherein the plurality of first conductive lines are parallel to each other; a plurality of second conductive lines disposed above the first conductive lines and crossing the first conductive lines while being arranged in parallel with each other; and a conductive via connecting the first conductive line and the second conductive line in an overlapping region between the first conductive line and the second conductive line, and The two ends of the first conductive line respectively overlap with one end of a second conductive line and the other end of another second conductive line adjacent to the second conductive line.

10. The semiconductor package according to claim 1, wherein The through-electrodes include a first through-electrode connected to an input voltage, a second through-electrode connected to an output voltage, and a third through-electrode connected to a ground, and Wherein, in the horizontal direction, the second through-electrode is arranged between the first through-electrode and the third through-electrode.

11. The semiconductor package according to claim 1, wherein The remaining bridge wafers include two or more bridge wafers, and wherein the capacitor is formed in each of the two or more bridge wafers.

12. The semiconductor package according to claim 1, wherein The first semiconductor chip includes a memory chip, and The second semiconductor chip includes a logic chip.

13. A semiconductor package, comprising: a first semiconductor chip stack including a plurality of first semiconductor chips stacked in a vertical direction; a bridge wafer stack disposed to be spaced apart from the first semiconductor chip stack in a horizontal direction and including a plurality of bridge wafers stacked in the vertical direction; a redistribution layer disposed over the first semiconductor chip stack and the bridge wafer stack; a second semiconductor chip disposed over the redistribution layer and receiving a voltage through the bridge wafer stack and the redistribution layer; as well as a voltage regulator, wherein the voltage regulator regulates the voltage, wherein the voltage regulator comprises: a switch included in an uppermost bridge wafer of the plurality of bridge wafers that is closest to the second semiconductor chip; a diode included in the uppermost bridge wafer of the plurality of bridge wafers; a capacitor included in the remaining bridge wafers of the plurality of bridge wafers except the uppermost bridge wafer; an inductor included in the redistribution layer; and A controller is formed in the second semiconductor chip.

14. The semiconductor package according to claim 13, wherein The control terminal, input terminal and output terminal of the switch are connected to the controller, input voltage and input terminal of the inductor respectively, wherein the output terminal of the inductor is connected to the second semiconductor chip, wherein an input terminal of the diode is connected to ground, and an output terminal of the diode is connected between the output terminal of the switch and the input terminal of the inductor, and One end and the other end of the capacitor are connected to the second semiconductor chip and the ground respectively.

15. The semiconductor package according to claim 13, wherein The remaining bridge wafers include two or more bridge wafers, and wherein the capacitor is formed in each of the two or more bridge wafers.

16. The semiconductor package according to claim 13, wherein The first semiconductor chip includes a memory chip, and The second semiconductor chip includes a logic chip.

Images