Semiconductor memory device

Abstract

Embodiments herein relate to a semiconductor memory device and a method of forming the same. A semiconductor memory device is provided. The semiconductor memory device includes a memory cell having a first electrode, a second electrode, a switching layer, and a via structure. The second electrode is adjacent to a side of the first electrode, and the switching layer covers uppermost surfaces of the first electrode and the second electrode. The via structure is located above an uppermost surface of the second electrode.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor devices, and more specifically to semiconductor memory devices and methods of forming the same. Background Technology

[0002] Semiconductor memory devices are generally classified into volatile memory devices and non-volatile memory (NVM) devices. Resistive random access memory (RRAM) devices are a type of NVM device used in advanced computing systems, such as in-memory processing (PIM) applications and machine learning (ML) applications that utilize techniques based on binary neural networks (BNNs). RRAM devices are suitable for such applications because they can provide a high-density architecture with high parallel programming speed and low power consumption.

[0003] Typical RRAM devices use a switching layer inserted between two electrodes. The switching layer is typically insulating. However, when a sufficiently large potential difference is applied between the electrodes, conductive filaments can form within the switching layer, making it conductive. However, these conductive filaments are often randomly formed across many locations within the switching layer, resulting in undesirable inter-device and periodic variability in the RRAM device.

[0004] Therefore, there is a need to provide semiconductor memory devices with improved device performance and methods for forming them to overcome or at least mitigate the above-mentioned disadvantages. Summary of the Invention

[0005] To achieve the above and other aspects of this disclosure, a semiconductor memory device and a method of forming the same are provided.

[0006] According to one aspect of this disclosure, a memory device is provided. The memory device includes a memory cell having a first electrode, a second electrode, a switching layer, and a via structure. The second electrode is adjacent to one side of the first electrode, and the switching layer covers the uppermost surfaces of both the first and second electrodes. The via structure is located above the uppermost surface of the second electrode.

[0007] According to another aspect of this disclosure, a semiconductor memory device is provided. The semiconductor memory device includes a first electrode, a second electrode, a third electrode, a first insulating element, a second insulating element, and a switching layer. The second electrode and the third electrode are adjacent to and located on opposite lateral sides of the first electrode. The first insulating element is located between the first electrode and the second electrode, and the second insulating element is located between the first electrode and the third electrode. The switching layer covers the uppermost surfaces of the first electrode, the second electrode, the third electrode, the first insulating element, and the second insulating element.

[0008] According to another aspect of this disclosure, a method for forming a semiconductor memory device is provided. The method includes forming a first electrode and a second electrode adjacent to the first electrode; forming an insulating element located between the first electrode and the second electrode; and forming a switching layer covering the uppermost surfaces of the first electrode and the second electrode. The switching layer, the first electrode, and the second electrode form a memory cell of the memory device. Attached Figure Description

[0009] The embodiments of this disclosure will be better understood by reading the following detailed description taken in conjunction with the accompanying drawings:

[0010] Figure 1 This is a cross-sectional view of a semiconductor memory device according to an embodiment of the present disclosure.

[0011] Figures 2A to 2D It is formed according to the embodiments shown in this disclosure. Figure 1 A cross-sectional view of a method for developing semiconductor memory devices.

[0012] Figure 3 This is a cross-sectional view of a semiconductor memory device according to another embodiment of the present disclosure.

[0013] Figures 4A to 4F It is formed according to the embodiments shown in this disclosure. Figure 3 A cross-sectional view of a method for developing semiconductor memory devices.

[0014] Figure 5 An embodiment according to this disclosure is shown. Figure 1 Simulated electric field in semiconductor memory devices.

[0015] For the sake of simplicity and clarity, the accompanying drawings illustrate a general construction method, and specific descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the discussion of embodiments of the device.

[0016] Additionally, the elements in the accompanying drawings are not necessarily drawn to scale. For example, the dimensions of some elements in the drawings may be enlarged relative to other elements to aid in understanding an embodiment of the device. The same reference numerals in different drawings denote the same elements, while similar reference numerals may, but do not necessarily, denote similar elements. Detailed Implementation

[0017] This disclosure generally relates to semiconductor devices, and more specifically to semiconductor memory devices with improved device performance and methods of forming the same.

[0018] A resistive random access memory (RRAM) cell typically includes a pair of electrodes and a switching layer inserted between the electrodes. The switching layer of an RRAM cell is usually insulated.

[0019] RRAM primitives operate by switching between states based on the resistance of a switching layer. For example, when a sufficiently large potential difference is applied between a pair of electrodes, a dielectric breakdown event may occur, and the switching layer becomes conductive as one or more conductive wires are formed within it. By applying a sufficiently small potential difference between the pair of electrodes to disconnect the one or more conductive wires, the switching layer can return to an insulating state.

[0020] When the switching layer is insulating, it has a relatively high resistance, and the RRAM cell can be referred to as being in a high-resistance state (HRS). When the switching layer is conductive, it has a relatively low resistance, and the RRAM cell can be referred to as being in a low-resistance state (LRS). To program an RRAM cell, the RRAM cell is switched from HRS to LRS. To erase an RRAM cell, the RRAM cell is switched from LRS to HRS.

[0021] Various embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that identical and corresponding elements are indicated by the same reference numerals. The embodiments disclosed herein are exemplary and are not intended to be exhaustive or limited to this disclosure.

[0022] Figure 1 This is a cross-sectional view of a memory device 100 according to an embodiment of the present disclosure. The memory device 100 may be arranged in a memory cell region of a semiconductor device, and the memory device 100 may be part of a plurality of memory devices arranged in an array configuration of rows and columns in the memory cell region. For clarity, only one memory device is shown.

[0023] Memory device 100 may include a plurality of memory cells, including a first memory cell 102 and a second memory cell 104. Each memory cell 102, 104 may be a one-bit memory cell. Therefore, memory device 100 may be a two-bit memory device. Memory device 100 may be disposed over a substrate insulating layer (not shown), wherein the substrate insulating layer may be an interlayer dielectric layer (ILD). In one embodiment of this disclosure, memory device 100 is an RRAM device.

[0024] like Figure 1 As shown, the memory device 100 may include a first electrode 106. The first electrode 106 may be a common electrode shared between the first and second memory cells 102, 104. The first electrode 106 may be referred to as an inert electrode. In one embodiment of this disclosure, the first electrode 106 may include an inert conductive material, such as, but not limited to, ruthenium, platinum, titanium nitride, tantalum nitride, combinations thereof, or other inert conductive materials known to those skilled in the art. In another embodiment of this disclosure, the first electrode 106 may have a thickness in the range of about 5 to about 10 nm.

[0025] Each memory cell 102, 104 may further include second electrodes 108a, 108b and insulating elements 110a, 110b, respectively. The second electrodes 108a, 108b may be referred to as active electrodes. The insulating elements 110a, 110b may be referred to as hard mask elements.

[0026] Referring to the first memory cell 102, the second electrode 108a may be arranged adjacent to the first side surface of the first electrode 106. In one embodiment of this disclosure, the second electrode 108a may have an upper surface substantially coplanar with the upper surface of the first electrode 106. In another embodiment of this disclosure, the second electrode 108a may include a conductive material, such as, but not limited to, tantalum, hafnium, titanium, copper, silver, cobalt, tungsten, combinations thereof, or other conductive materials known to those skilled in the art. In yet another embodiment of this disclosure, the second electrode 108 may have a thickness in the range of about 5 to about 30 nm.

[0027] An insulating element 110a of the first memory cell 102 may be disposed between the first electrode 106 and the second electrode 108a. The insulating element 110a may directly contact the first side surface of the first electrode 106 and the first side surface of the second electrode 108a. The insulating element 110a may have an uppermost surface substantially coplanar with the upper surfaces of the first and second electrodes 106 and 108a. In one embodiment of this disclosure, the insulating element 110a may also be located below the second electrode 108a and have an "L-shaped" profile. The insulating element 110a may have a side surface substantially coplanar with the second side surface of the second electrode 108a; the second side surface of the second electrode 108a is laterally opposite to the first side surface. In another embodiment of this disclosure, the insulating element 110a may include an electrically insulating material, such as, but not limited to, various metal nitrides, such as silicon nitride, or other electrically insulating materials known to those skilled in the art. In yet another embodiment of this disclosure, the insulating element 110a may have a thickness of up to about 10 nm.

[0028] The second memory cell 104 of the memory device 100 may be a mirror image of the first memory cell 102; the second memory cell 104 has mirror symmetry about an axis M passing through the center of the first electrode 106. Similar to the first memory cell 102, the second memory cell 104 may include a second electrode 108b and an insulating element 110b.

[0029] The memory device 100 may further include a switching layer 112. The switching layer 112 may cover and directly contact the upper surfaces of the first and second electrodes 106, 108a, 108b of the first and second memory cells 102, 104, and the uppermost surfaces of the insulating elements 110a, 110b. Figure 1 As shown, the switching layer 112 may extend entirely above the upper surface of the first electrode 106. The switching layer 112 may comprise a dielectric material having a dielectric breakdown voltage lower than that of the electrically insulating materials of the insulating elements 110a, 110b. In one embodiment of this disclosure, the switching layer 112 may comprise various metal oxides, such as magnesium oxide, tantalum oxide, hafnium oxide, titanium oxide, aluminum oxide, silicon oxide, combinations thereof, or other dielectric materials known to those skilled in the art.

[0030] The switching layer 112 may be configured with a certain thickness such that when a predetermined potential difference is applied between the first and second electrodes 106, 108a, 108b, the state of the switching layer 112 can switch between HRS and LRS. The voltage required for operation of the first memory cell 102 may further vary depending on the technology node and the type of memory cell manufactured. In one embodiment of this disclosure, the switching layer 112 may have a thickness in the range of about 2 to about 10 nm.

[0031] Each memory cell 102, 104 may be provided with wire structures 114a, 114b electrically coupled to the second electrodes 108a, 108b, respectively. It should be understood that when an element is referred to as "connected" or "coupled" to another element, that element may be directly connected or coupled to the other element, or there may be intermediate elements. Conversely, when an element is referred to as "directly connected" or "directly coupled" to another element, there are no intermediate elements.

[0032] Each line structure 114a, 114b can be used as a bit line for the first and second memory cells 102, 104, respectively. In one embodiment of this disclosure, conductive via structures 116a, 116b can be arranged between the line structures 114a, 114b and the second electrodes 108a, 108b. The line structures 114a, 114b can be electrically coupled to the second electrodes 108a, 108b through the via structures 116a, 116b, respectively. The via structures 116a, 116b can extend through the switching layer 112 to be electrically coupled to the second electrodes 108a, 108b. The line structures 114a, 114b and the via structures 116a, 116b can include conductive materials, such as, but not limited to, aluminum, copper, tungsten, alloys thereof, combinations thereof, or other conductive materials known to those skilled in the art.

[0033] As described above, the memory device 100 can be a two-bit memory device. The first bit of the memory device 100 can correspond to the state of the first memory cell 102, and the second bit of the memory device 100 can correspond to the state of the second memory cell 104. To program the first memory cell 102, a sufficiently large potential difference can be applied between the first and second electrodes 106, 108a of the first memory cell 102 to form one or more conductive wires 118a between the first and second electrodes 106, 108a. The one or more conductive wires 118a can be formed laterally between the first and second electrodes 106, 108a. Similarly, to program the second memory cell 104, a sufficiently large potential difference can be applied between the first and second electrodes 106, 108b of the second memory cell 104 to form one or more conductive wires 118b between the first and second electrodes 106, 108b. The one or more conductive wires 118b can be formed laterally between the first and second electrodes 106, 108b.

[0034] Because the electric field generated at the corner regions of the conductive structure is relatively stronger than that in the non-corner regions, these relatively higher electric fields can easily facilitate the formation of one or more conductive wires within the first and second memory cells 102, 104. Furthermore, since the switching layer 112 has a lower dielectric breakdown voltage than the insulating elements 110a, 110b, it is anticipated that one or more conductive wires 118a, 118b can be formed between the upper corners of the first and second electrodes 106, 108a of the first memory cell 102 and between the upper corners of the first and second electrodes 106, 108b of the second memory cell 104. When a sufficiently large potential difference is applied to cause dielectric breakdown of the switching layer 112, one or more conductive wires 118a can be formed laterally between the upper corners of the first and second electrodes 106, 108a of the first memory cell 102 and laterally between the upper corners of the first and second electrodes 106, 108b of the second memory cell 104.

[0035] The formation of one or more conductive filaments 118a, 118b can be substantially confined at the interface between the switching layer 112 and the insulating elements 110a, 110b. Confining the conductive filaments 118a, 118b at the interface helps minimize the variability in the location where the conductive filaments 118a, 118b can be formed. This filament confinement reduces the randomness of the conductive filaments 118a, 118b, thereby reducing the resistance variability of the switching layer 112. The controlled distribution of the conductive filaments 118 can lead to desired process stability, such as low inter-device variability and cycle-time variability.

[0036] Please note that, although in Figure 1 It is not obvious, but one or more conductive wires 118a, 118b can be formed at any location along the insulating element 110a, 110b between the first and second electrodes 106, 108a, 108b located in the respective memory cell.

[0037] The first and second memory cells 102 and 104 can be independently read or programmed via their respective line structures 114a and 114b, thereby providing a two-bit-line read / write mechanism for the memory device 100. For the two-bit-line read mechanism, for example, when the first and second memory cells 102 and 104 are programmed, the line structures 114a and 114b of the respective memory cells 102 and 104 will read a relatively high current level. In another example, when the first memory cell 102 is the only memory cell being programmed, the line structure 114a of the first memory cell 102 will read a relatively high current level, while the line structure 114b of the second memory cell 104 will read a relatively low current level.

[0038] To write to or program the memory device 100, a sufficiently large potential difference can be applied between the first and second electrodes 106, 108a of the first memory cell 102 and / or the first and second electrodes 106, 108b of the second memory cell 104. For example, the memory device 100 may be in state (11) when both memory cells 102 and 104 are programmed. In another example, the memory device 100 may be in state (10) when only the first memory cell 102 is programmed and the second memory cell 104 is erased. Similarly, the memory device 100 may be in state (01) when only the second memory cell 104 is programmed and the first memory cell 102 is erased.

[0039] Figures 2A to 2D It is formed according to the embodiments shown in this disclosure. Figure 1 A cross-sectional view of a method for a memory device 100. Certain structures can be conventionally manufactured using known processes and techniques, and various aspects of this disclosure can be implemented using the specifically disclosed processes and methods.

[0040] As used herein, “deposition technique” refers to the process of applying one material onto another material (or substrate). Exemplary techniques for deposition include, but are not limited to, spin coating, sputtering, chemical vapor deposition (CVD), physical vapor deposition (PVD), molecular beam deposition (MBD), pulsed laser deposition (PLD), liquid source atomized chemical deposition (LSMCD), or atomic layer deposition (ALD).

[0041] Furthermore, "patterning techniques" include depositing material or photoresist as needed when forming the described pattern, structure, or opening, and patterning, exposing, developing, etching, cleaning, and / or removing the material or photoresist. Exemplary examples of techniques for patterning include, but are not limited to, wet etching lithography processes, dry etching lithography processes, or direct patterning processes. These techniques may use mask sets and mask layers with dopants having the desired conductivity type.

[0042] Figure 2A A first electrode 106 of a memory device 100 according to an embodiment of the present disclosure is shown. The memory device 100 may be formed over a substrate insulating layer (not shown). The memory device 100 may be a two-bit memory device and may include a first region for forming a first memory cell 102 and a second region for forming a second memory cell 104. The first memory cell 102 and the second memory cell 104 may be formed on opposite laterally sides of the first electrode 106 and may respectively form bit cells of the memory device 100.

[0043] The first electrode 106 can be formed by depositing an inert conductive material layer (not shown) over a substrate insulating layer using a deposition technique and patterning the inert conductive material layer using a patterning technique. The first electrode 106 can be a common electrode shared between the first and second memory cells 102 and 104.

[0044] An insulating material layer 110 can be deposited over the first electrode 106 using deposition techniques. The insulating material layer 110 can be deposited over the substrate insulating layer and the first electrode 106. In one embodiment of this disclosure, the insulating material layer 110 can be deposited using a conformal deposition process (e.g., conformal CVD or ALD).

[0045] Figure 2B A memory device 100 is shown after the formation of second electrodes 108a, 108 for each memory cell 102, 104 and insulating elements 110a, 110b, respectively, according to an embodiment of the present disclosure. A conductive material can be deposited over the insulating material layer 110 using deposition techniques. Planarization techniques, such as chemical mechanical planarization (CMP) processes, can be performed to remove portions of the conductive and insulating material 110 to form the second electrodes 108a, 108 and insulating elements 110a, 110b for the first and second memory cells 102, 104, respectively.

[0046] The planarization technique exposes the upper surface of the first electrode 106. The planarization technique advantageously forms a substantially planar topography above the memory device 100, i.e., the upper surfaces of the first and second electrodes 106, 108a, 108b are substantially coplanar with the uppermost surfaces of the insulating elements 110a, 110b.

[0047] Although Figure 2B Not shown, but patterning techniques can be performed to define and electrically isolate multiple memory devices, including memory device 100. Patterning techniques may include using a photoresist mask or stencil to form multiple memory devices arranged in an array configuration of rows and columns.

[0048] Figure 2CA memory device 100 after the formation of switching layer 112 is shown according to an embodiment of the present disclosure. A dielectric material layer can be deposited over the memory device 100 using a deposition technique to form switching layer 112. It is contemplated that switching layer 112 will have a planar morphology substantially similar to that formed by the upper surfaces of the first and second electrodes 106, 180a, 108b and the uppermost surfaces of the insulating elements 110a, 110b. Due to the substantially planar morphology, the deposition technique used to form switching layer 112 can be effectively controlled and is not affected by other process limitations such as photolithography. Therefore, a thin switching layer of substantially uniform thickness can be formed. A substantially uniform thin switching layer may be necessary because it provides stable filamentary path formation and reduced switching voltage during operation of the memory device.

[0049] Figure 2D A memory device 100 is shown after the formation of line structures 114a, 114b and via structures 116a, 116b of the respective memory cells 102, 104, according to an embodiment of the present disclosure. A dielectric layer 120 may be deposited over a switching layer 112 using deposition techniques. The dielectric layer 120 may be referred to as an ILD layer. Openings and / or trenches may be formed in the dielectric layer 120, and conductive material may be deposited in the openings and / or trenches to form the line structures 114a, 114b and / or via structures 116a, 116b. It should be understood that the via structures 116a, 116b and the line structures 114a, 114b may be formed individually or simultaneously in a single deposition process. In one embodiment of the present disclosure, the line structures 114a, 114b may serve as bit lines for the respective first and second memory cells 102, 104.

[0050] Figure 3 This is a cross-sectional view of a memory device 300 according to an embodiment of the present disclosure. The memory device 300 may be arranged in a memory cell region of a semiconductor device, and the memory device 300 may be part of a plurality of memory devices arranged in an array configuration of rows and columns in the memory cell region. For clarity, only one memory device is shown.

[0051] Similar to Figure 1 The memory device 100 and memory device 300 may include a plurality of memory cells, including a first memory cell 302 and a second memory cell 304. Each memory cell 302, 304 may be a one-bit memory cell. Therefore, memory device 300 may be a two-bit memory device. Memory device 300 may be disposed above a substrate insulating layer (not shown), wherein the substrate insulating layer may be an interlayer dielectric layer (ILD). In one embodiment of this disclosure, memory device 300 is an RRAM device.

[0052] like Figure 3 As shown, each memory cell 302, 304 may include first electrodes 306a, 306b, respectively. The first electrodes 306a, 306b may be referred to as inert electrodes. The first electrodes 306a, 306b may have an "L-shaped" profile, and a dielectric layer 322 may be disposed above the first electrodes 306a, 306b. The dielectric layer 322 may be referred to as an ILD layer. In one embodiment of this disclosure, the uppermost surface of the first electrodes 306a, 306b may be substantially coplanar with the upper surface of the dielectric layer 322. In another embodiment of this disclosure, the first electrodes 306a, 306b may include an inert conductive material, such as, but not limited to, ruthenium, platinum, titanium nitride, tantalum nitride, combinations thereof, or other inert conductive materials known to those skilled in the art. In yet another embodiment of this disclosure, the first electrodes 306a, 306b may have a thickness in the range of about 5 to about 10 nm.

[0053] The memory device 300 may include a second electrode 308 disposed between first electrodes 306a and 306b. The second electrode 308 may be a common electrode shared between the first and second memory cells 302 and 304. The second electrode 308 may be referred to as an active electrode. In one embodiment of this disclosure, the second electrode 308 may have an upper surface substantially coplanar with the uppermost surface of the first electrode 306. In another embodiment of this disclosure, the second electrode 308 may include a conductive material, such as, but not limited to, tantalum, hafnium, titanium, copper, silver, cobalt, tungsten, combinations thereof, or other conductive materials known to those skilled in the art. In yet another embodiment of this disclosure, the second electrode 308 may have a thickness in the range of about 5 to about 30 nm.

[0054] The memory device 300 may further include an insulating element 310. The insulating element 310 may be referred to as a hard mask element. The insulating element 310 may be disposed between the first electrodes 306a, 306b and the second electrode 308. The insulating element 310 may directly contact the side surface of the second electrode 308. Alternatively, the insulating element 310 may be located below the second electrode 308 and have a “U-shaped” profile, separating the second electrode 308 from the substrate insulating layer. In one embodiment of this disclosure, the insulating element 310 may have a superior surface substantially coplanar with the upper surface of the second electrode 308. In another embodiment of this disclosure, the insulating element 310 comprises an electrically insulating material, such as, but not limited to, various metal nitrides, such as silicon nitride, or other electrically insulating materials known to those skilled in the art. In yet another embodiment of this disclosure, the insulating element 310 may have a thickness of up to about 10 nm.

[0055] The memory device 300 may further include a switching layer 312. The switching layer 312 may cover and directly contact the dielectric layer 322, the first electrodes 306a and 306b, the insulating element 310, and the second electrode 308. For example... Figure 3 As shown, the switching layer 112 may extend entirely above the uppermost surfaces of the first electrodes 306a and 306b. The switching layer 312 may comprise a dielectric material having a lower dielectric breakdown voltage than the electrically insulating material of the insulating element 310. In one embodiment of this disclosure, the switching layer 312 may comprise various metal oxides, such as magnesium oxide, tantalum oxide, hafnium oxide, titanium oxide, aluminum oxide, silicon oxide, combinations thereof, or other dielectric materials known to those skilled in the art. In another embodiment of this disclosure, the switching layer 312 may have a thickness in the range of about 2 to about 10 nm.

[0056] The memory device 300 may be provided with a wire structure 314. The wire structure 314 may serve as a bit line of the memory device 300. In one embodiment of this disclosure, a conductive via structure 316 may be provided to electrically couple the wire structure 314 to the second electrode 308. The via structure 316 may extend through the switching layer 312 to electrically couple to the second electrode 308. The wire structure 314 and the via structure 316 may include conductive materials, such as, but not limited to, aluminum, copper, tungsten, alloys thereof, combinations thereof, or other conductive materials known to those skilled in the art.

[0057] As described above, memory device 300 can be a two-bit memory device. Similar to memory device 100, the first memory cell 302 of memory device 300 can be programmed by applying a sufficiently large potential difference between the first and second electrodes 306a, 308 of the first memory cell 302 to form one or more conductive wires 318a between the first and second electrodes 306a, 308. Similarly, the second memory cell 304 of memory device 300 can be programmed by applying a sufficiently large potential difference between the first and second electrodes 306b, 308 of the second memory cell 304 to form one or more conductive wires 318b between the first and second electrodes 306b, 308.

[0058] Since the dielectric breakdown voltage of the switching layer 312 is lower than that of the insulating element 310, it is anticipated that when a sufficiently large potential difference is applied to cause dielectric breakdown of the switching layer 312, one or more conductive wires 318a, 318b can be formed between the upper corners of the first and second electrodes 306a, 308 of the first memory cell 302 and between the upper corners of the first and second electrodes 306b, 308 of the second memory cell 304. The formation of one or more conductive wires 318a, 318b is substantially limited to the interface between the switching layer 312 and the insulating element 310; one or more conductive wires 318a, 318b can be laterally formed between the upper corners of the first and second electrodes 306a, 308 of the first memory cell 302 and between the upper corners of the first and second electrodes 306b, 308 of the second memory cell 304.

[0059] The state of the first and second memory cells 302 and 304 can be read via the line structure 314. For example, when the first and second memory cells 302 and 304 are programmed, the line structure 314 will read a first current level. In another example, when the first and second memory cells 302 and 304 are erased, the line structure 314 will read a second current level, which is lower than the first current level. In another example, when the first memory cell 302 is the only programmed memory cell, the line structure 314 will read a third current level, which is lower than the first current level but higher than the second current level. In one embodiment of this disclosure, the third current level is approximately half the current level of the first current level.

[0060] To write to or program the memory device 300, a sufficiently large potential difference can be applied to the first memory cell 302 and / or the second memory cell 304. For example, when both memory cells 302 and 304 are programmed, the memory device 300 may be in state (11). In another example, when only the first memory cell 302 is programmed and the second memory cell 304 is erased, the memory device 300 may be in state (10). In yet another example, when only the second memory cell 304 is programmed and the first memory cell 302 is erased, the memory device 300 may be in state (01).

[0061] Figures 4A to 4F It is formed according to the embodiments shown in this disclosure. Figure 3 A cross-sectional view of a method for a memory device 300. Certain structures can be conventionally manufactured using known processes and techniques, and various aspects of this disclosure can be implemented using the specifically disclosed processes and methods.

[0062] Figure 4AA first portion 310' of an insulating element and a second electrode 308 of a memory device 300 according to an embodiment of the present disclosure are shown. The first portion 310' of the insulating element and the second electrode 308 may be formed over a substrate insulating layer (not shown). The memory device 300 may be a two-bit memory device and may include a first region for forming a first memory cell 302 and a second region for forming a second memory cell 304. The first and second memory cells 302, 304 may be formed on opposite laterally sides of the second electrode 308 and may respectively form bit cells of the memory device 300.

[0063] Various deposition techniques can be used to deposit a first insulating material layer over a substrate insulating layer, and a conductive material layer can be deposited over the first insulating material layer. Patterning techniques can be used to pattern the first insulating material layer and the conductive material layer to form the first portion 310' of the insulating element and the second electrode 308, respectively. The patterning technique can be a one-step or multi-step process. The second electrode 308 can be a common electrode shared between the first and second memory cells 302, 304.

[0064] Figure 4B A memory device 300 is shown after the formation of the second portion 310' of the insulating element, according to an embodiment of the present disclosure. A second insulating material layer may be deposited over the second electrode 308 using a deposition technique. The second insulating material layer may cover the upper surface and sidewalls of the second electrode 308 and the sidewalls of the first portion 310' of the insulating element. Furthermore, the second insulating material may cover the substrate insulating layer. In one embodiment of the present disclosure, the insulating material layer may be deposited using a conformal deposition process (e.g., conformal CVD or ALD).

[0065] Patterning techniques can be used to pattern the second insulating material to retain a portion of the second insulating material on the sidewall of the second electrode 308 and the first portion 310' of the insulating element, forming the second portion 310' of the insulating element. The first and second portions 310', 310' of the insulating element form the insulating element 310 of the memory device 300; the interface between the first and second portions 310', 310' of the insulating element is defined by dashed lines. The insulating element 310 allows the second electrode 308 to be embedded therein. The insulating element 110 can be referred to as a hard mask element. After the patterning technique, the upper surface of the second electrode 308 can be exposed.

[0066] It will be understood that the first and second portions 310', 310" of the insulating element may comprise the same insulating material for ease of manufacture. However, it should be understood that the first and second portions 310', 310" of the insulating element do not necessarily have to be formed of the same insulating material, even if Figure 4BThey are shown as being formed of the same insulating material. It will also be understood that the first and second portions 310', 310" of the insulating element can have different thicknesses, although... Figure 4B They are shown as having similar thicknesses. For example, the thickness of the first portion 310' of the insulating element may be greater than the thickness of the second portion 310"". In one embodiment of this disclosure, the second portion 310" of the insulating element may have a thickness of up to about 10 nm.

[0067] Figure 4C A memory device 300 is illustrated after the deposition of an inert conductive material layer 306 and a dielectric material layer 322, according to an embodiment of the present disclosure. The inert conductive material layer 306 can be deposited over an insulating element 310 and a second electrode 308 using deposition techniques. In one embodiment of the present disclosure, the inert conductive material 306 can be deposited using a conformal deposition process (e.g., conformal CVD or ALD). The inert conductive material layer can cover a substrate insulating layer.

[0068] Patterning techniques can be performed to define and electrically isolate multiple memory devices, including memory device 300, by removing portions of an inert conductive material layer 306 covering a substrate insulating material. The patterning technique may include the use of a photoresist mask or photomask. A dielectric material layer 322 may be deposited over the inert conductive material 306 using a deposition technique after the patterning technique to electrically isolate the multiple memory devices that may be arranged in an array of rows and columns.

[0069] Figure 4D A memory device 300 according to an embodiment of the present disclosure is shown after the formation of the first electrodes 306a, 306b of their respective first and second memory cells 302, 304. Planarization techniques, such as chemical mechanical planarization (CMP) processes, can be performed to remove a portion of the dielectric material 322 and a portion of the inert conductive material layer 306 located above the upper surface of the second electrode 308 to form the first electrodes 306a, 306b of the respective first and second memory cells 302, 304. After the planarization technique, the upper surface of the second electrode 308 and the uppermost surface of the insulating element 310 can be exposed. It will be understood that in order to obtain a substantially planar morphology above the memory device 300, a portion of the second electrode 308 and the insulating element 310 can be removed during the planarization technique.

[0070] Figure 4E A memory device 300 after the formation of a switching layer 312 is shown according to an embodiment of the present disclosure. The switching layer 312 can be connected to... Figure 1The switching layer 312 is synonymous with the switching layer 112 in the text. A dielectric material layer can be deposited over the memory device 300 using deposition techniques to form the switching layer 312. It is expected that the switching layer 312 will have a substantially similar planar morphology. Due to the substantially planar morphology, the deposition technique for forming the switching layer 312 can be effectively controlled to form a switching layer 312 with a substantially uniform thickness.

[0071] Figure 4F A memory device 300 after forming a line structure 314 and a via structure 316, according to an embodiment of the present disclosure, is shown. The line structure 314 and the via structure 316 can be coupled with... Figure 1 In this context, line structures 114a / 114b and via structures 116a / 116b are synonymous. A dielectric layer 320 can be deposited over the switching layer 312 using deposition techniques. Openings and / or trenches can be formed in the dielectric layer 320, and conductive material can be deposited in the openings and / or trenches to form via structures 316 and / or line structures 314 over the second electrode 308. The via structures 316 and line structures 314 can be formed individually or simultaneously in a single deposition process. In one embodiment of this disclosure, the line structure 314 can be used as a bit line of the memory device 300.

[0072] Figure 5 The illustration shows an embodiment of the present disclosure where a sufficiently large potential difference is applied between the first and second electrodes 106, 108a, 108b of the first and second memory cells 102, 104. Figure 1 The simulated electric field of the semiconductor memory device 100 is shown. The electric field strength along the upper and lower corners of the second electrodes 108a and 108b can be higher than the electric field strength in the non-corner regions. These higher electric field strengths can readily facilitate the formation of one or more conductive wires 118a and 118b between the first and second electrodes 106 and 108. Because the dielectric breakdown voltage of the switching layer 112 is lower than the dielectric breakdown voltage of the insulating elements 110a and 110b, it is expected that one or more conductive wires 118a and 118b can be formed between the upper corners of the first and second electrodes 106 and 108a of the first memory cell 102 and between the upper corners of the first and second electrodes 106 and 108b of the second memory cell 104. Therefore, the formation of conductive wires 118a and 118b can be substantially limited to the interface between the switching layer 112 and the insulating elements 110a and 110b.

[0073] As presented in the above disclosure, a semiconductor memory device with improved device performance and a method for forming the same are provided. The memory device may be an RRAM device having two one-bit memory cells. The memory device may include a pair of electrodes, an insulating element, and a switching layer.

[0074] The electrodes and insulating elements form a substantially planar topography, on which a switching layer is formed. The substantially planar topography advantageously allows for the formation of a effectively controlled switching layer, thereby enabling the formation of a thin switching layer with a substantially uniform thickness. During operation of the memory device, the thin switching layer advantageously provides stable filament path formation and reduced switching voltage.

[0075] The switching layer can have a lower dielectric breakdown voltage than the insulating element. When a sufficiently large potential difference is applied between the electrodes, one or more conductive wires can be formed laterally between the electrodes. Since the electric field generated at the corner regions of the electrodes is generally stronger than in the non-corner regions, one or more conductive wires can be substantially confined at the interface between the switching layer and the insulating element. Furthermore, this interface provides the shortest conductive path between the electrodes. Accordingly, it is understood that the thickness of the insulating element between the electrodes should be as thin as possible to form a relatively short conductive path between the electrodes. For example, in Figure 4B In this process, the second portion 310” of the insulating element 310 can be formed to have a thinner thickness than the first portion 310' to facilitate the formation of a short conductive path between the first and second electrodes 306a / 306b, 308. The short conductive path advantageously reduces the switching voltage during operation of the memory device. The substantially confined region of the conductive filament further advantageously reduces the variability of the switching layer in the HRS state and provides improved inter-device control and cycle control.

[0076] Furthermore, the memory devices disclosed herein are compatible with complementary metal-oxide-semiconductor (CMOS) processes using CMOS-compatible materials. It will be understood that, although... Figure 1 and Figure 3 The memory devices shown in the diagram have two memory cells per memory device, but memory devices may alternatively include fewer (e.g., one memory cell) or more memory cells, and thus memory devices may have different bit widths.

[0077] Furthermore, memory devices can be configured in memory arrays with cross-configuration, three-dimensional (3D) configuration, combinations thereof, or any other configuration known to those skilled in the art, thereby achieving a high-density architecture with high parallel programming speed and low power consumption. For example, a 3D configuration can be achieved by repeating the memory arrays separately. Figure 1 and Figure 3 The memory devices 100 and 300, or a combination thereof, are used to implement 3D configuration.

[0078] The terms “top,” “bottom,” “above,” “below,” etc. (if any) used in the specification and claims are for descriptive purposes and are not necessarily used to describe permanent relative positions. It should be understood that the terms thus used are interchangeable where appropriate so that embodiments of the devices described herein can, for example, operate in orientations different from those shown or otherwise described herein.

[0079] Furthermore, the following description of forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features may not be in direct contact.

[0080] Similarly, if a method is described herein as comprising a series of steps, the order of such steps presented herein is not necessarily the only possible order in which these steps can be performed, and specific steps may be omitted and / or other specific steps not described herein may be added to the method. Furthermore, the terms “comprising,” “including,” “having,” and any variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device that comprises a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or not inherent to those processes, methods, articles, or devices. The appearance of the phrase “in an embodiment” herein does not necessarily indicate the same embodiment.

[0081] Furthermore, unless otherwise stated, all figures used in the specification and claims that indicate the quantity, ratio, and numerical properties of materials, reaction conditions, etc., shall be understood to be modified by the term "about" in all cases.

[0082] Furthermore, the approximate language used throughout the specification and claims can be used to modify any quantitative expression that may vary without altering the underlying functionality. Therefore, values ​​modified by one or more terms such as "approximately," "about," or "basically" are not limited to the specified exact values. In some cases, approximate language may correspond to the precision of the instrument used to measure the value. In other cases, approximate language may correspond to the normal tolerance range of the semiconductor industry. For example, "basically coplanar" means substantially in the same plane within the normal tolerance range of the semiconductor industry, and "basically perpendicular" means an angle of ninety degrees plus or minus the normal tolerance range of the semiconductor industry.

[0083] Although several exemplary embodiments have been given in the above detailed description of the device, it should be understood that many variations exist. It should also be understood that the embodiments are merely examples and are not intended to limit the scope, applicability, size, or configuration of the device in any way. Rather, the above detailed description will provide a convenient guide for those skilled in the art to implement exemplary embodiments of the device, and it will be understood that various changes can be made to the function and arrangement of the elements described in the exemplary embodiments and the methods of manufacture without departing from the scope of this disclosure set forth in the appended claims.

Claims

1. A memory device, comprising: a first electrode; a second electrode adjacent to the first electrode; a first insulating element between the first electrode and the second electrode; a switching layer covering an uppermost surface of the first electrode and the second electrode, wherein the switching layer, the first electrode, and the second electrode form a memory cell of the memory device; and a via structure over the uppermost surface of the second electrode, wherein, when formed by applying a potential difference between the first electrode and the second electrode, one or more conductive filaments are confined at an interface between the switching layer and the first insulating element. the switching layer extends over an uppermost surface of the first insulating element.

2. The memory device of claim 1, wherein, 3. The memory device of claim 2, wherein the uppermost surfaces of the first electrode, the second electrode, and the first insulating element are substantially coplanar.

4. The memory device of claim 1, wherein the switching layer comprises a dielectric material having a substantially planar topography.

5. The memory device of claim 4, wherein the switching layer extends entirely over the uppermost surface of the first electrode.

6. The memory device of claim 1, further comprising a line structure over the second electrode, the line structure being electrically coupled to the second electrode through the via structure, wherein the via structure extends through the switching layer, and wherein the line structure forms a bit line of the memory device.

7. The memory device of claim 1, wherein the memory cell is a first memory cell, the memory device further comprising a second memory cell, wherein the first electrode is a common electrode between the first memory cell and the second memory cell.

8. The memory device of claim 7, wherein the second memory cell comprises: a third electrode adjacent to a side of the first electrode laterally opposite the second electrode; a second insulating element between the first electrode and the third electrode; and the switching layer covering an uppermost surface of the third electrode and the second insulating element.

9. The memory device of claim 8, further comprising a line structure over the third electrode, the line structure being electrically coupled to the third electrode, wherein the line structure forms a bit line of the memory device.

10. The memory device of claim 1, wherein the memory cell is a first memory cell, the memory device further comprising a second memory cell, wherein the second electrode is a common electrode between the first memory cell and the second memory cell.

11. The memory device of claim 10, wherein the second memory cell comprises: a third electrode laterally opposite the first electrode from the second electrode; and the switching layer covering an uppermost surface of the third electrode.

12. The memory device of claim 11, wherein, ​ ​ ​ The first insulating element is a first portion of an insulating element into which the second electrode is embedded, a second portion of the insulating element is between the second electrode and the third electrode, and a third portion of the insulating element is below the second electrode; and The switching layer covers uppermost surfaces of the first and second portions of the insulating element, wherein the uppermost surfaces of the first and second portions of the insulating element are substantially coplanar with the uppermost surfaces of the first, second, and third electrodes.

13. The memory device of claim 1, wherein the memory cell is a resistive random access memory cell.

14. A memory device, comprising: a first electrode; a second electrode and a third electrode adjacent and on laterally opposite sides of the first electrode; a first insulating element between the first electrode and the second electrode; a second insulating element between the first electrode and the third electrode; and a switching layer covering uppermost surfaces of the first electrode, the second electrode, the third electrode, the first insulating element, and the second insulating element, wherein, when formed by applying a potential difference between the first electrode and the second electrode, one or more conductive filaments are confined at an interface between the switching layer and the first insulating element, and wherein, when formed by applying a potential difference between the first electrode and the third electrode, one or more conductive filaments are confined at an interface between the switching layer and the second insulating element.

15. The memory device of claim 14, wherein the first electrode is an inert electrode.

16. The memory device of claim 14, wherein the second electrode and the third electrode are active electrodes.

17. The memory device of claim 14, wherein the switching layer has a substantially uniform thickness above the uppermost surfaces of the first electrode, the second electrode, the third electrode, the first insulating element, and the second insulating element.

18. A method of forming a memory device, comprising: forming a first electrode; forming a second electrode adjacent the first electrode; forming an insulating element between the first electrode and the second electrode; forming a switching layer covering uppermost surfaces of the first electrode and the second electrode, wherein the switching layer, the first electrode, and the second electrode form a memory cell of the memory device; and forming a via structure above the uppermost surfaces of the second electrode, wherein, when formed by applying a potential difference between the first electrode and the second electrode, one or more conductive filaments are confined at an interface between the switching layer and the insulating element.

19. The method of claim 18, further comprising performing a planarization technique above the first electrode, the second electrode, and the insulating element prior to forming the switching layer.

20. The method of claim 18, wherein forming the switching layer comprises depositing a metal oxide dielectric material having a substantially planar topography.

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