A frequency locking method based on integrated phase-locked loop

Abstract

The present invention relates to a frequency locking method based on an integrated phase-locked loop. It belongs to the technical field of frequency hopping communication. The frequency locking method based on the integrated phase-locked loop is implemented based on a locked frequency source circuit. The method is specifically as follows: when the integrated phase-locked loop is configured, the first analog switch and the second analog switch are first switched to the normally open end, the reverse end of the operational amplifier is interconnected with the same-direction end through the first analog switch, the voltages of the two endpoints are the same, the output of the operational amplifier is in a suspended state, and since the input voltage remains unchanged, the output of the operational amplifier maintains the previous state at this time, and the second analog switch directly connects the VT pin of the integrated phase-locked loop to an externally specified tuning voltage, thereby ensuring that the VT pin is controlled during the configuration of the integrated phase-locked loop; when the integrated phase-locked loop is configured, the first analog switch and the second analog switch are switched to the normally closed end, and the loop works normally. The present invention can effectively solve the problem of a long locking time of the integrated PLL when frequency hopping across VCO slices.

Description

Technical Field

[0001] The invention relates to a frequency locking method based on an integrated phase-locked loop, belonging to the technical field of frequency hopping communication. Background Art

[0002] Frequency hopping communication is a new type of military communication method that changes frequency quickly and automatically. Tactical frequency hopping radio can implement communication in the process of irregular, high-speed and continuous frequency changes, making it difficult for the enemy to detect, analyze, identify and interfere with radio communication signals, greatly improving the anti-interference ability of tactical radio communication.

[0003] The use of frequency hopping technology enables radio equipment to work in a noisy electromagnetic environment, reducing the impact of the surrounding environment to a very low point, ensuring that the communication link is safe and reliable. Compared with fixed-frequency communication, frequency hopping communication is safer and more reliable, especially when the hopping speed is higher, its anti-interference ability is stronger.

[0004] As the core component of frequency hopping communication equipment, the frequency hopping source has always been the focus of research, and has been developing in the direction of high hopping speed, fine step, high spurious, and wide range.

[0005] Currently, frequency source technology is relatively mature, and the frequency of the integrated phase-locked loop can reach more than 30 GHz, which can meet most frequency hopping rates and spurious usage requirements.

[0006] Integrated PLL integrates the PLL and VCO in the above-mentioned separate PLL solution into one chip, and only a loop filter needs to be built externally to achieve frequency synthesis. This frequency source is small in size, and because the VCO adopts a sub-band solution design, fast frequency hopping can be achieved even in manual calibration mode.

[0007] Attached Figure 1 This is the application schematic diagram of the integrated PLL. Both the PLL and the VCO are integrated inside the integrated PLL. The VCO adopts a sub-band design, and the control interface is generally SPI. Usually, a sub-band corresponds to a locking frequency with a smaller bandwidth. The tuning voltage of the integrated PLL usually fluctuates within a smaller range. Therefore, with the manual calibration mode of the integrated PLL, it can usually achieve a faster locking speed.

[0008] The integrated PLL solution has the most advantages in terms of cost and volume. At the same time, due to the special design of its VCO, the frequency hopping time can also be made shorter. However, the VCO in most existing integrated PLLs adopts a partition design. When hopping between different partitions, the loop voltage will drop sharply, which greatly prolongs the frequency hopping time. Summary of the invention

[0009] The technical problem to be solved by the present invention is to provide a frequency locking method based on an integrated phase-locked loop. Based on the existing advantages of the integrated PLL, the present invention focuses on solving the problem of long frequency hopping time across partitions, thereby making the integrated PLL applicable to more applications.

[0010] The present invention provides a frequency locking method based on an integrated phase-locked loop. The method is implemented based on a frequency locking source circuit. The frequency locking source circuit includes an RC circuit, an operational amplifier, a first analog switch, and a second analog switch. The reverse end of the operational amplifier, the common end of the first analog switch, and the common end of the second analog switch are connected to each other. One end of the first analog switch is connected to the same direction end of the operational amplifier, and two ends of the second analog switch are respectively connected to the output end of the operational amplifier and the VT pin of the integrated phase-locked loop.

[0011] The method is specifically as follows:

[0012] When the integrated phase-locked loop is configured, the first analog switch and the second analog switch are first switched to the normally open end, the reverse end of the operational amplifier is interconnected with the same end through the first analog switch, the voltages of the two ends are the same, the output of the operational amplifier is in a floating state, and since the input voltage remains unchanged, the output of the operational amplifier maintains the previous state at this time, and the second analog switch directly connects the VT pin of the integrated phase-locked loop to the external specified tuning voltage, thereby ensuring that the VT pin is controlled during the integrated phase-locked loop configuration process;

[0013] When the integrated phase-locked loop is configured, the first analog switch and the second analog switch are switched to the normally closed end, and the loop works normally.

[0014] Further preferably, in the locked frequency source circuit, the endpoint at which the first analog switch is connected to the same-direction end of the operational amplifier is a normally open end.

[0015] Further preferably, in the locked frequency source circuit, the endpoint where the second analog switch is connected to the same-direction end of the operational amplifier is a normally closed end, and the endpoint where the second analog switch is connected to the VT pin of the integrated phase-locked loop is a normally closed end.

[0016] Further preferably, in the locked frequency source circuit, the RC circuit comprises a first capacitor, and the first capacitor is arranged between a common end of the first analog switch and a common end of the second analog switch.

[0017] Further preferably, in the locked frequency source circuit, the RC circuit includes a second capacitor, and the second capacitor is arranged between the inverting end of the operational amplifier and the common end of the second analog switch.

[0018] Further preferably, in the locked frequency source circuit, the RC circuit comprises a first resistor, and the first resistor is arranged between the inverting end of the operational amplifier and the common end of the first analog switch.

[0019] The present invention is a method for locking frequency based on an integrated phase-locked loop. Based on the existing frequency hopping rate that can be achieved by the integrated phase-locked loop, an improved design is made to overcome some defects existing in the frequency hopping of the integrated phase-locked loop, greatly shorten the frequency hopping time, and obtain better spurious performance. Compared with the prior art, it has the following advantages:

[0020] Low cost: On the basis of the integrated PLL, adding an analog dual-way switch and an operational amplifier can effectively solve the problem.

[0021] Small size: Compared with other solutions, this solution occupies a smaller size and can meet high integration requirements.

[0022] Short locking time: It effectively solves the problem of long locking time across VCO areas in the old solution, reducing the locking time to 20us, which basically meets the needs of most current application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 This is the application schematic diagram of the integrated PLL.

[0024] Figure 2 The figure is a working principle diagram of the frequency locking method based on the integrated phase-locked loop of the present invention. DETAILED DESCRIPTION

[0025] In order to better explain the present invention and facilitate understanding, the present invention is described in detail below through specific implementation modes in conjunction with the accompanying drawings.

[0026] Figure 2 It is a working principle diagram of the frequency locking method based on an integrated phase-locked loop of the present invention. Figure 2 In the circuit, Q1, SW1, SW2 and RC circuit together form a new loop filter.

[0027] In the RC circuit, R2 is connected between the reverse end of Q1 and the common end of SW1, C2 is connected between the reverse end of Q1 and the common end of SW2, and C3 is connected between the common end of SW1 and the common end of SW2. The RC circuit also includes components such as R, R1, R3, C1, and C4, which play the role of current limiting and protection respectively. The specific settings can be based on actual conditions and are not limited to Figure 2 plan.

[0028] When working stably, SW1 and SW2 are both connected to the normally closed terminal ( Figure 2 The loop works in the normal filter state.

[0029] When the PLL performs frequency hopping, the working status of each device is as follows:

[0030] When performing PLL configuration, both SW1 and SW2 are switched to the normally open end first. The inverting end of Q1 is interconnected with the non-inverting end through SW1, and the voltages of the two ends are the same. The output of Q1 is in a floating state, and since the input voltage remains unchanged, the output of Q1 maintains the previous state. SW2 directly connects the VT pin of the integrated phase-locked loop to the external specified tuning voltage, thereby ensuring that VT is controlled during the PLL configuration process.

[0031] When the PLL configuration is complete, SW1 and SW2 are switched to the normally closed position and the loop operates normally.

[0032] The working principle of the circuit is as follows: Since the PLL is in the configuration process, VT is in an uncontrolled state. During this process, the VT voltage will continue to drop, which will make the subsequent locking time longer. By switching the states of SW1 and SW2, VT is controlled to ensure that VT is maintained at the required level. When the PLL configuration is completed and the loop is switched to the normal state, the VT voltage has reached the tuning voltage required for the next frequency point to lock, thereby shortening the subsequent locking time.

[0033] The embodiments described above are merely descriptions of preferred implementation modes of the present invention and are not intended to limit the scope of the present invention. Without departing from the design spirit of the present invention, various modifications and improvements made to the technical solutions of the present invention by ordinary technicians in this field should all fall within the protection scope determined by the claims of the present invention.

Claims

1. A frequency locking method based on an integrated phase-locked loop, characterized in that: The method is implemented based on a locked frequency source circuit, which includes an RC circuit, an operational amplifier, a first analog switch, and a second analog switch. The reverse end of the operational amplifier, the common end of the first analog switch, and the common end of the second analog switch are connected to each other, one end of the first analog switch is connected to the same direction end of the operational amplifier, and two ends of the second analog switch are respectively connected to the output end of the operational amplifier and an external specified tuning voltage; The method is specifically as follows: When the integrated phase-locked loop is configured, the first analog switch and the second analog switch are first switched to the normally open end, the reverse end of the operational amplifier is interconnected with the same end through the first analog switch, the voltages of the two ends are the same, the output of the operational amplifier is in a floating state, and since the input voltage remains unchanged, the output of the operational amplifier maintains the previous state at this time, and the second analog switch directly connects the VT pin of the integrated phase-locked loop to the external specified tuning voltage, thereby ensuring that the VT pin is controlled during the integrated phase-locked loop configuration process; When the integrated phase-locked loop is configured, the first analog switch and the second analog switch are switched to the normally closed end, and the loop works normally; In the locked frequency source circuit, the endpoint where the first analog switch is connected to the same-direction end of the operational amplifier is a normally open end; In the locked frequency source circuit, the endpoint where the second analog switch is connected to the output end of the operational amplifier is a normally closed end, and the endpoint where the second analog switch is connected to the external specified tuning voltage of the integrated phase-locked loop is a normally open end; In the locked frequency source circuit, the RC circuit includes a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a first resistor, a second resistor, and a third resistor; Specifically, the integrated phase-locked loop CP pin is connected to the first capacitor and one end of the first resistor, the other end of the first capacitor is grounded, the other end of the first resistor is connected to the reverse input terminal of the operational amplifier, the second capacitor and one end of the second resistor, one end of the second capacitor is connected to the reverse input terminal of the operational amplifier, the other end of the second capacitor is connected to the common end of the second analog switch, the third capacitor and one end of the third resistor, one end of the second resistor is connected to the reverse input terminal of the operational amplifier, the other end of the second resistor is connected to the other end of the third capacitor and the common end of the first analog switch, one end of the third capacitor is connected to the common end of the second analog switch and one end of the third resistor, the other end of the third capacitor is connected to the common end of the first analog switch, the other end of the third resistor is connected to the integrated phase-locked loop VT pin and one end of the fourth capacitor, one end of the fourth capacitor is connected to the integrated phase-locked loop VT pin, the other end of the fourth capacitor is grounded, and the same-direction input terminal of the operational amplifier is connected to the normally open end of the first analog switch.

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