A detection system for ADC offset values

Abstract

This invention discloses a system for detecting ADC offset values, comprising: an analog input signal AINX transmitting module, consisting of at least n resistors connected in series, with two first switches between each pair of resistors, and an analog input signal AINX output terminal between each pair of first switches, the analog input signal AINX output terminal being used to provide an analog input signal AINX to the ADC under test, where n represents an even number greater than or equal to 8; and an ADC offset detection module, used to acquire the output code value DX of the ADC under test with the analog input signal AINX, and generate the ADC offset value of the ADC under test based on the ADC's own offset value VOS_adc, wherein the output code value DX represents the output signal generated by the ADC under test after receiving the analog input signal AINX; the ADC offset testing algorithm provided by this invention combines resistor voltage division and cyclic testing to eliminate the offset of the resistors themselves to obtain the accurate offset value of the ADC.

Description

Technical Field

[0001] This invention relates to the field of ADC offset detection, and more particularly to a system for detecting ADC offset. Background Technology

[0002] An ADC, or analog-to-digital converter, is an electronic component that converts analog signals into digital signals. A typical ADC converts an input voltage signal into an output digital signal. Since digital signals themselves do not have inherent meaning, representing only a relative magnitude, any ADC needs a reference analog signal as a standard for conversion. A common reference standard is the magnitude of the largest convertible signal. The output digital signal then represents the magnitude of the input signal relative to the reference signal.

[0003] In the existing technology, the method for testing the internal ADC offset value is usually to divide the reference voltage with a series of resistors, then transmit the divided voltage signal to the ADC for conversion, and finally obtain the ADC offset value.

[0004] The drawback of this method is that the resistors themselves are offset, resulting in inaccurate ADC offset values. CMOS process resistor matching can only achieve a maximum accuracy of 6 bits. In 10-bit and 12-bit ADCs, using a simple resistor divider to measure ADC offset values ​​will result in significant errors. Summary of the Invention

[0005] To address the problems existing in the prior art, the present invention provides a system for detecting ADC offset values, comprising:

[0006] The analog input signal AINX transmitting module consists of at least n resistors connected in series. Between each pair of resistors are two first switches, and between the two first switches is an analog input signal AINX output terminal. The analog input signal AINX output terminal is used to provide the analog input signal AINX to the ADC under test, where n represents an even number greater than or equal to 8.

[0007] The ADC offset detection module is used to acquire the output code value DX of the ADC under test with an analog input signal AINX, and generate the ADC offset value of the ADC under test based on the ADC under test's own offset value VOS_adc. The output code value DX represents the output signal generated by the ADC under test after receiving the analog input signal AINX.

[0008] Preferably, the resistance value of each resistor in the analog input signal AINX transmitting module is the same.

[0009] Preferably, a second switch for controlling the voltage source input is also included between each resistor and the first switch.

[0010] Preferably, the two first switches between every two resistors are simultaneously opened, and the other first switches are simultaneously closed, forming two parallel circuits, each circuit consisting of the same number of resistors.

[0011] Preferably, the first switches of the analog input signal AINX transmitting module cannot be closed simultaneously, wherein the analog input signal AINX transmitting module includes two first switches that are simultaneously open.

[0012] Preferably, the first switch is open, the second switch positioned between it and the resistor is closed, and the other second switches are open.

[0013] Preferably, the analog input signal AINX is generated by the analog input signal output terminal of the two circuits that are electrically connected.

[0014] Preferably, the analog input signal AINX transmitting module consists of eight resistors connected in series.

[0015] The two first switches between each pair of resistors are simultaneously opened, and the other first switches are simultaneously closed, forming two parallel circuits. Each circuit consists of four resistors connected in series. The first switch that is open is closed with the second switch between the resistors, and the other second switches are open.

[0016] The analog input signal AINX is generated by the output terminals of the two electrically connected circuits.

[0017] Preferably, the process by which the ADC offset detection module acquires the ADC offset value includes the following steps:

[0018] The two first switches between the two resistors are simultaneously opened and the other first switches are simultaneously closed.

[0019] Simultaneously close the second switch corresponding to the first open switch, and open the other second switches;

[0020] Collect at least 8 sets of analog input signals AINX sequentially, and obtain the first average value of the analog input signals AINX;

[0021] Collect the output code values ​​DX corresponding to the analog input signal AINX in sequence, and obtain the second average value of the output code values ​​DX.

[0022] The ADC offset value is obtained based on the first average value, the second average value, and the offset value VOS_adc.

[0023] Preferably, the ADC offset detection module sequentially collects eight sets of analog input signals AINX and obtains the first average value;

[0024] The expression for the first average is:

[0025]

[0026] in,

[0027]

[0028]

[0029]

[0030]

[0031]

[0032]

[0033]

[0034]

[0035] ΔR1+ΔR2+ΔR3+ΔR4+ΔR5+ΔR6+ΔR7+ΔR8=0

[0036] VS represents the voltage source input value.

[0037] The present invention discloses the following technical effects:

[0038] The ADC offset test algorithm provided by this invention combines resistor voltage division and cyclic testing to eliminate the offset of the resistor itself and obtain the accurate offset value of the ADC. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 This is a system structure diagram of the present invention;

[0041] Figure 2 This is a diagram showing the series connection method of the voltage divider resistors described in this invention;

[0042] Figure 3 This is a diagram showing the input-output conversion result of the ADC described in this invention. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0044] like Figure 1-3 As shown, the present invention provides a system for detecting ADC offset values, comprising:

[0045] The analog input signal AINX transmitting module consists of at least n resistors connected in series. Between each pair of resistors are two first switches, and between the two first switches is an analog input signal AINX output terminal. The analog input signal AINX output terminal is used to provide the analog input signal AINX to the ADC under test, where n represents an even number greater than or equal to 8.

[0046] The ADC offset detection module is used to acquire the output code value DX of the ADC under test with an analog input signal AINX, and generate the ADC offset value of the ADC under test based on the ADC under test's own offset value VOS_adc. The output code value DX represents the output signal generated by the ADC under test after receiving the analog input signal AINX.

[0047] More preferably, the resistance value of each resistor in the analog input signal AINX transmitting module is the same.

[0048] More preferably, a second switch for controlling the voltage source input is also included between each resistor and the first switch.

[0049] More preferably, the two first switches between every two resistors are simultaneously opened, and the other first switches are simultaneously closed, forming two parallel circuits, each circuit consisting of the same number of resistors.

[0050] Preferably, the first switches of the analog input signal AINX transmitting module cannot be closed simultaneously, wherein the analog input signal AINX transmitting module includes two first switches that are simultaneously open.

[0051] More preferably, the first switch is open, the second switch positioned between it and the resistor is closed, and the other second switches are open.

[0052] More preferably, the analog input signal AINX is generated by the analog input signal output terminal of the two circuits being electrically connected.

[0053] More preferably, the analog input signal AINX transmitting module consists of eight resistors connected in series;

[0054] The two first switches between each pair of resistors are simultaneously opened, and the other first switches are simultaneously closed, forming two parallel circuits. Each circuit consists of four resistors connected in series. The first switch that is open is closed with the second switch between the resistors, and the other second switches are open.

[0055] The analog input signal AINX is generated by the output terminals of the two electrically connected circuits.

[0056] More preferably, the process by which the ADC offset detection module acquires the ADC offset value includes the following steps:

[0057] The two first switches between the two resistors are simultaneously opened and the other first switches are simultaneously closed.

[0058] Simultaneously close the second switch corresponding to the first open switch, and open the other second switches;

[0059] Collect at least 8 sets of analog input signals AINX sequentially, and obtain the first average value of the analog input signals AINX;

[0060] Collect the output code values ​​DX corresponding to the analog input signal AINX in sequence, and obtain the second average value of the output code values ​​DX.

[0061] The ADC offset value is obtained based on the first average value, the second average value, and the offset value VOS_adc.

[0062] More preferably, the ADC offset detection module sequentially collects eight sets of analog input signals AINX and obtains a first average value;

[0063] The expression for the first average is:

[0064]

[0065] in,

[0066] ΔR1+ΔR2+ΔR3+ΔR4+ΔR5+ΔR6+ΔR7+ΔR8=0,

[0067] VS represents the voltage source input value.

[0068] The novel ADC offset testing algorithm mentioned in this invention combines resistor voltage division and cyclic testing to eliminate the offset of the resistor itself and obtain the accurate offset value of the ADC. Its implementation principle is as follows.

[0069] like Figure 2 The voltage divider resistor series connection shown operates as follows: In the first round, when switches S1P and S1N are closed, both S1C switches are open. S2P...S8PS2N...S8N are all open, and S2C...S8C are all closed. The voltage divider signal of AIN1 is output to the ADC to obtain the code value D1. In the second round, when switches S2P and S2N are closed, both S2C switches are open. S1P...S8PS1N...S8N are all open, and S1C...S8C are all closed. The voltage divider signal of AIN2 is output to the ADC to obtain the code value D2. This process continues until AIN8 obtains the code value D8 through the ADC.

[0070] In this resistor string, we first choose R1 = R2 = R3 = R4 = R5 = R6 = R7 = R8.

[0071] Its average value:

[0072]

[0073]

[0074]

[0075]

[0076]

[0077]

[0078]

[0079]

[0080] ΔR1+ΔR2+ΔR3+ΔR4+ΔR5+ΔR6+ΔR7+ΔR8=0.

[0081] first:

[0082]

[0083] Second time:

[0084]

[0085] The third time:

[0086]

[0087] Fourth time:

[0088]

[0089] Fifth time:

[0090]

[0091] Sixth time:

[0092]

[0093] Seventh time:

[0094]

[0095] Eighth time:

[0096]

[0097] Eight average input values:

[0098]

[0099] During the eight-cycle conversion process, the ADC's inherent offset is determined, so the ADC outputs a code value each time.

[0100] have Figure 3 It can be seen that the ADC output code value DX includes the analog input signal AINX and the ADC's own offset value VOS_adc. After eight cyclic conversions, the code values ​​are summed and averaged to obtain the result.

[0101]

[0102] It consists of two parts: ideal VS / 2 + VOS_adc.

[0103] The technical solution proposed in this invention also designed detection scenarios with 4, 6, 8, 10, 12, 14, 16, and 24 resistors connected in series. It was found that the results for 4 and 6 resistors connected in series differed significantly from those for 8 or more resistors, while the differences between the latter groups were smaller. After removing the first two groups, and cyclically testing each of the remaining groups starting from different endpoints, it was found that the detection system formed by 8 resistors connected in series was more stable, with minimal difference in output results. This indicates that the detection system formed by 8 resistors connected in series is most suitable for detecting ADC offset values. Therefore, this invention selected a system composed of 8 resistors connected in series for technical design, realizing the detection of ADC offset values. Furthermore, in circuit designs with more than 8 resistors, it was also found that the above-described approach can be achieved by forming two parallel circuits consisting of 4 resistors each.

[0104] A reasonable explanation is that as the input value of the voltage source VC increases, the resistance composition forming the parallel circuit can be increased. Therefore, as long as the output signal of this invention is achieved, the technical process of this invention can also be realized. Thus, the number of series resistors is entirely determined by the analog input signal AINX. Theoretically, by adjusting the resistance composition according to the input requirements of this signal, it is possible to detect the ADC offset values ​​of different ADCs. However, considering circuit limitations, there will be certain data errors during the signal acquisition and data acquisition process. The detection method designed in this invention collects a corresponding number of detection data points based on the number of series resistors, and after averaging, the result is closer to the actual offset value. This avoids data differences caused by circuit problems and defects in the detection equipment itself, and also avoids errors between data points.

[0105] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

[0106] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0107] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

Claims

1. A system for detecting ADC offset values, characterized in that, include: The analog input signal AINX transmitting module consists of at least n resistors connected in series. Between every two resistors, there are two first switches. Between the two first switches, there is an analog input signal AINX output terminal. The analog input signal AINX output terminal is used to provide an analog input signal AINX to the ADC under test, where n represents an even number greater than or equal to 8. The ADC offset detection module is used to acquire the output code value DX of the ADC under test with the analog input signal AINX, and generate the ADC offset value of the ADC under test according to the offset value VOS_adc of the ADC under test. The output code value DX is used to represent the output signal generated by the ADC under test after receiving the analog input signal AINX. A second switch for controlling the voltage source input is also included between each of the resistors and the first switch; The two first switches between the two resistors are simultaneously opened and the other first switches are simultaneously closed, forming two parallel circuits. Simultaneously close the second switch corresponding to the disconnected first switch, and disconnect the other second switches; The analog input signal AINX is generated by the output terminal of the two electrically connected circuits. Collect all the analog input signals AINX sequentially, and obtain the first average value of the analog input signals AINX; The output code value DX corresponding to the analog input signal AINX is collected sequentially, and the second average value of the output code value DX is obtained. The ADC offset value is obtained based on the first average value, the second average value, and the inherent offset value VOS_adc.

2. The system for detecting ADC offset value according to claim 1, characterized in that: Each resistor in the analog input signal AINX transmitting module has the same resistance value.

3. The system for detecting ADC offset value according to claim 2, characterized in that: Each circuit consists of the same number of the resistors.

4. The system for detecting ADC offset value according to claim 3, characterized in that: The analog input signal AINX transmitting module consists of 8 resistors connected in series. The two first switches between every two resistors are simultaneously opened, and the other first switches are simultaneously closed, forming two parallel circuits. Each circuit consists of four resistors connected in series. The first switch that is opened is closed with the second switch that is connected between the resistor and the other second switches are open. The analog input signal AINX is generated by the two circuits that are electrically connected to the output terminal of the analog input signal AINX.

5. The system for detecting ADC offset value according to claim 4, characterized in that: The ADC offset detection module sequentially collects eight sets of analog input signals AINX and obtains the first average value; The expression for the first average value is: VS represents the voltage source input value.

Images