Feed-forward mismatch error shaping successive approximation analog-to-digital converter and mismatch error shaping method thereof

Abstract

The invention relates to a feed-forward mismatch error shaping successive approximation analog-to-digital converter and a mismatch error shaping method thereof. The analog-to-digital converter comprises a first CDACP module, a first CDACN module, a second CDACP module, a second CDACN module, a four-input dynamic comparator module and a digital logic module. The input ends of the first CDACP module, the first CDACN module, the second CDACP module and the second CDACN module are connected with input voltage, the output ends of the first CDACP module, the first CDACN module, the second CDACP module and the second CDACN module are connected with the input end of the four-input dynamic comparator module, and the output end of the four-input dynamic comparator module is connected with the digital logic module. According to the invention, feed-forward capacitor mismatch error shaping is provided on the basis of traditional feedback capacitor mismatch error shaping, and the method is suitable for a high-precision environment of lower-level board sampling.

Description

Technical Field

[0001] This invention relates to the field of mixed-signal integrated circuit technology, and in particular to a feedforward mismatch error shaping successive approximation analog-to-digital converter and its mismatch error shaping method. Background Technology

[0002] With the rapid development of fields such as the Internet of Things, medical electronics, and industrial automation, the performance requirements for data converters are constantly increasing. Research on high-precision analog-to-digital converters (ADCs) has gradually become a hot topic in both academia and industry. Successive Approximation Register (SAR) ADCs, as a classic ADC architecture, are widely used in medium-precision applications due to their advantages such as simple structure, low power consumption, and small area. Compared with other high-precision ADC architectures (such as Pipeline ADCs and ΔΣ ADCs), SAR ADCs have a significant advantage in energy efficiency.

[0003] Due to limitations such as comparator accuracy and capacitor mismatch, SAR ADCs struggle to achieve 12-bit accuracy without additional calibration. DAC capacitor mismatch is one of the main bottlenecks limiting high accuracy in SAR ADCs. Typical SAR ADCs use a capacitor DAC array to perform digital-to-analog conversion. Ideally, the capacitors in the DAC array should exhibit precise binary weighting. However, in actual manufacturing, factors such as process variations, uneven etching, and oxide layer thickness variations lead to random mismatches between individual capacitors. Traditional methods of increasing capacitor size or using complex calibration schemes are insufficient to meet the energy efficiency and integration requirements of modern electronic systems, driving the development of innovative technologies such as mismatch error shaping.

[0004] Both MES (Mismatch Error Shaping) and DEM (Dynamic Component Matching) technologies are key technologies developed to solve the DAC component mismatch problem in high-precision analog-to-digital converters (ADCs). Their technological background stems from the limitations of traditional calibration methods. DEM technology was proposed earlier. It converts the mismatch error between components into white noise by randomly or sequentially rotating the unit components in the DAC, thereby suppressing harmonic distortion. However, its circuit complexity and size increase exponentially with resolution, making it difficult to apply to high-precision converters.

[0005] Compared to DEM technology, MES technology is more efficient. It borrows the noise shaping concept from Δ-Σ modulators, feeding back the mismatch error from the previous cycle to the current conversion cycle, making the mismatch error exhibit high-pass characteristics in the frequency domain and thus pushing it out of band. Furthermore, since this mismatch error is represented by the digital code extracted from the LSB of the capacitor array in the previous cycle, it can be implemented with simple switching circuits, making it more suitable for high-bit, high-precision applications. However, it introduces new problems such as input range loss. Also, because traditional feedback MES technology is designed based on upper-level sampled SAR ADCs, it cannot be applied to lower-level sampled SAR ADCs with higher precision. In recent years, some scholars have proposed MES application schemes suitable for lower-level sampled SAR ADCs, but these have certain limitations due to the exponential increase in input reference noise. Summary of the Invention

[0006] The purpose of this invention is to provide a feedforward mismatch error shaping successive approximation analog-to-digital converter and its mismatch error shaping method. Based on the traditional feedback capacitor mismatch error shaping, a feedforward capacitor mismatch error shaping method is proposed, which is suitable for high-precision sampling environments of lower-level boards.

[0007] To achieve the above objectives, the present invention provides the following solution:

[0008] A feedforward mismatch error shaping successive approximation analog-to-digital converter includes: a first CDACP module, a first CDACN module, a second CDACP module, a second CDACN module, a four-input dynamic comparator module, and a digital logic module, wherein the first CDACP module, the first CDACN module, the second CDACP module, and the second CDACN module are all composed of a high-order capacitor MSBCAP and a low-order capacitor LSBCAP;

[0009] The input terminals of the first CDACP module, the first CDACN module, the second CDACP module, and the second CDACN module are connected to the input voltage, and the output terminals are connected to the input terminals of the four-input dynamic comparator module. The output terminal of the four-input dynamic comparator module is connected to the digital logic module.

[0010] Optionally, the MSBCAP input terminal of the first CDACP module is connected to the first input voltage through a sampling switch and connected to the output terminal of the digital logic module through a pre-comparison switch; the LSBCAP input terminal of the first CDACP module is connected to the first input voltage through a sampling switch and connected to the output terminal of the digital logic module through a mismatch error shaping MES switch; and the output terminal of the first CDACP module is connected to the first input terminal of the four-input dynamic comparator module.

[0011] Optionally, the MSBCAP input terminal of the first CDACN module is connected to the second input voltage through a sampling switch and connected to the output terminal of the digital logic module through a pre-comparison switch; the LSBCAP input terminal of the first CDACN module is connected to the first input voltage through a sampling switch and connected to the output terminal of the digital logic module through a MES switch; and the output terminal of the first CDACN module is connected to the third input terminal of the four-input dynamic comparator module.

[0012] Optionally, the MSBCAP input terminal of the second CDACP module is connected to the first input voltage via a sampling switch and connected to the output terminal of the digital logic module via a pre-comparison switch; the LSBCAP input terminal of the second CDACP module is connected to the first input voltage via a sampling switch and connected to the output terminal of the digital logic module via a MES switch; and the output terminal of the second CDACP module is connected to the second input terminal of the four-input dynamic comparator module.

[0013] Optionally, the MSBCAP input terminal of the second CDACN module is connected to the second input voltage through a sampling switch and connected to the output terminal of the digital logic module through a pre-compare switch; the LSBCAP input terminal of the second CDACN module is connected to the first input voltage through a sampling switch and connected to the output terminal of the digital logic module through a MES switch; and the output terminal of the second CDACN module is connected to the fourth input terminal of the four-input dynamic comparator module.

[0014] The present invention also provides a mismatch error shaping method for a feedforward mismatch error shaping successive approximation analog-to-digital converter, comprising:

[0015] Based on the chip select signals Φc1 and Φc2, the first CDACP module, the first CDACN module, the second CDACP module, and the second CDACN module are controlled to work alternately in a cyclic manner, alternately acting as an input signal sampling analog-to-digital converter (DAC) and a mismatch error sampling and dynamic range compensation analog-to-digital converter (DAC), and outputting the final ADC conversion result through the digital logic module.

[0016] Optionally, implementing cyclical alternation of operations includes:

[0017] When chip select signal Φc1 is high and chip select signal Φc2 is low, the first CDACP module and the first CDACN module act as the main DAC to sample the input signal, and the second CDACP module and the second CDACN module act as the MES DAC to perform mismatch error sampling and dynamic range compensation. When chip select signal Φc2 is high and chip select signal Φc1 is low, the second CDACP module and the second CDACN module act as the main DAC to sample the input signal, and the first CDACP module and the first CDACN module act as the MES DAC to perform mismatch error sampling and dynamic range compensation.

[0018] Optional, the final conversion result of the ADC for:

[0019] ;

[0020] in, For the input signal value, This is the amount of mismatch error. Let be a complex variable in the Z-transform domain.

[0021] The beneficial effects of this invention are as follows: In this invention, the quantization result of the least significant bit (LSB) of the previous cycle and the capacitor mismatch error are directly fed forward to the second input of the comparator through mismatch error shaping (CDAC). Furthermore, combined with DEM technology, the first CDACN, first CDACP, and second CDACN, second CDACP are used as dynamic elements. This overcomes the shortcoming of traditional mismatch error shaping techniques that cannot shape the highest-order capacitor mismatch. Compared to traditional mismatch error shaping techniques, its advantages include applicability to downstream board sampling without increasing input reference noise, better shaping effect when combined with DEM technology, and the elimination of stability concerns due to the feedforward structure. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a schematic diagram of the structure of a feedforward mismatch error shaping successive approximation analog-to-digital converter according to an embodiment of the present invention;

[0024] Figure 2 This is a timing diagram illustrating the operation of an embodiment of the present invention;

[0025] Figure 3 This is a model of mismatch error shaping behavior in an embodiment of the present invention;

[0026] Figure 4 The figure shows the simulation results of an embodiment of the present invention. Detailed Implementation

[0027] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0028] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0029] like Figure 1 As shown, this embodiment proposes a feedforward mismatch error shaping successive approximation analog-to-digital converter, including: a first CDACP module, a first CDACN module, a second CDACP module, a second CDACN module, a four-input dynamic comparator module, and a digital logic module. The first CDACP module, the first CDACN module, the second CDACP module, and the second CDACN module are all composed of a high-order capacitor MSBCAP and a low-order capacitor LSBCAP.

[0030] The input terminals of the first CDACP module, the first CDACN module, the second CDACP module, and the second CDACN module are connected to the input voltage, and the output terminals are connected to the input terminals of the four-input dynamic comparator module. The output terminals of the four-input dynamic comparator module are connected to the digital logic module.

[0031] Furthermore, the MSBCAP input terminal of the first CDACP module is connected to the first input voltage through a sampling switch and connected to the output terminal of the digital logic module through a pre-comparison switch. The LSBCAP input terminal of the first CDACP module is connected to the first input voltage through a sampling switch and connected to the output terminal of the digital logic module through a mismatch error shaping MES switch. The output terminal of the first CDACP module is connected to the first input terminal of the four-input dynamic comparator module.

[0032] Specifically, the MSBCAP input terminal of the first CDACP module is connected to the first input voltage VIP through a sampling switch φS1, and the MSBCAP input terminal of the first CDACP module is connected to the output terminal D of the digital logic module through a pre-compare switch φPRE1. PRE The LSBCAP input terminal of the first CDACP module is connected to the first input voltage VIP through a sampling switch φS1, and is connected to the output terminal D of the digital logic module through a MES switch φMES1. LSB (N-1) The output of the first CDACP module is connected to the first input of the four-input dynamic comparator module and is connected to the voltage VCM through the reset switch φS3.

[0033] Furthermore, the MSBCAP input terminal of the first CDACN module is connected to the second input voltage through a sampling switch and connected to the output terminal of the digital logic module through a pre-compare switch. The LSBCAP input terminal of the first CDACN module is connected to the first input voltage through a sampling switch and connected to the output terminal of the digital logic module through a MES switch. The output terminal of the first CDACN module is connected to the third input terminal of the four-input dynamic comparator module.

[0034] Specifically, the MSBCAP input terminal of the first CDACN module is connected to the second input voltage VIN through a sampling switch φS1, and the MSBCAP input terminal of the first CDACN module is connected to the output terminal D of the digital logic module through a pre-compare switch φPRE1. PRE The LSBCAP input terminal of the first CDACN module is connected to the first input voltage VIN via a sampling switch φS1, and is connected to the output terminal D of the digital logic module via a MES switch φMES1. LSB '(N-1), the output of the first CDACN module is connected to the third input of the four-input dynamic comparator module, and is connected to the voltage VCM through the reset switch φS3.

[0035] Furthermore, the MSBCAP input terminal of the second CDACP module is connected to the first input voltage through a sampling switch and connected to the output terminal of the digital logic module through a pre-comparison switch. The LSBCAP input terminal of the second CDACP module is connected to the first input voltage through a sampling switch and connected to the output terminal of the digital logic module through a MES switch. The output terminal of the second CDACP module is connected to the second input terminal of the four-input dynamic comparator module.

[0036] Specifically, the MSBCAP input terminal of the second CDACP module is connected to the first input voltage VIP through a sampling switch φS2, and the MSBCAP input terminal of the second CDACP module is connected to the output terminal D of the digital logic module through a pre-compare switch φPRE2. PRE The LSBCAP input terminal of the second CDACP module is connected to the first input voltage VIP through a sampling switch φS2, and is connected to the output terminal D of the digital logic module through a MES switch φMES2. LSB (N-1) The output of the second CDACP module is connected to the second input of the four-input dynamic comparator module and is connected to the voltage VCM through the reset switch φS3.

[0037] Furthermore, the MSBCAP input terminal of the second CDACN module is connected to the second input voltage through a sampling switch and connected to the output terminal of the digital logic module through a pre-compare switch. The LSBCAP input terminal of the second CDACN module is connected to the first input voltage through a sampling switch and connected to the output terminal of the digital logic module through a MES switch. The output terminal of the second CDACN module is connected to the fourth input terminal of the four-input dynamic comparator module.

[0038] Specifically, the MSBCAP input terminal of the second CDACN module is connected to the second input voltage VIN through a sampling switch φS2, and the MSBCAP input terminal of the second CDACN module is connected to the output terminal D of the digital logic module through a pre-compare switch φPRE2. PRE The LSBCAP input terminal of the second CDACN module is connected to the first input voltage VIN via sampling switch φS2, and connected to the output terminal D of the digital logic module via MES switch φMES2. LSB '(N-1), The output of the second CDACN module is connected to the fourth input of the four-input dynamic comparator module, and is connected to the voltage VCM through the reset switch φS3.

[0039] The comparison result output from the four-input dynamic comparator is connected to the digital logic module, which stores the comparison structure for each bit. The pre-comparator inputs are VIP and VIN signals, and the output is stored in the digital logic module and connected to the D... PRE '、D PRE The digital logic module output ports D<11:0> are responsible for outputting the comparison result of the ADC in this cycle. LSB (N-1) and D LSB (N-1) is responsible for outputting the LSB digital code of the capacitor array stored in the previous cycle to the CDAC, via output port D. PRE '、D PRE The pre-comparison result is output to the CDAC. The final ADC conversion result is output from the DOUT port of the digital logic module.

[0040] This embodiment also provides a mismatch error shaping method for a feedforward mismatch error shaping successive approximation analog-to-digital converter, including:

[0041] Based on the chip select signals Φc1 and Φc2, the first CDACP module, the first CDACN module, the second CDACP module, and the second CDACN module are controlled to work alternately in a cyclic manner, alternately acting as an input signal sampling analog-to-digital converter (DAC) and a mismatch error sampling and dynamic range compensation analog-to-digital converter (DAC), and outputting the final ADC conversion result through the digital logic module.

[0042] Furthermore, achieving cyclical alternation of work includes:

[0043] When chip select signal Φc1 is high and chip select signal Φc2 is low, the first CDACP module and the first CDACN module act as the main DAC to sample the input signal, and the second CDACP module and the second CDACN module act as the MES DAC to perform mismatch error sampling and dynamic range compensation. When chip select signal Φc2 is high and chip select signal Φc1 is low, the second CDACP module and the second CDACN module act as the main DAC to sample the input signal, and the first CDACP module and the first CDACN module act as the MES DAC to perform mismatch error sampling and dynamic range compensation.

[0044] In this embodiment, φS1 is the sampling clock for the first CDACN and the first CDACP, φS2 is the sampling clock for the second CDACN and the second CDACP, φS3 is the reset clock for the upper-level board of the capacitor array, φCOMP is the comparator clock, φPRE is the pre-comparator clock, φPRE1 and φPRE2 are the dynamic range compensation clocks, φMES1 and φMES2 are the mismatch error sampling clocks, and Φc1 and Φc2 are the chip select signals.

[0045] Work sequence diagram as follows Figure 2 As shown, the specific mismatch error shaping process is as follows: During a certain cycle of the ADC operation, Φc1 is high, Φc2 is low, and φS1 and φS3 are high. The first CDACN and the first CDACP, as input signal sampling DACs, begin sampling the input signals VIN and VIP. Simultaneously, φPRE and φMES2 are high. The pre-comparator compares the magnitudes of the inputs VIP and VIN, stores the comparison results through the digital logic module, and transmits them through the D... PRE '、D PRE The port output samples DPRE' and DPRE. Here, the second CDACN and second CDACP are used for mismatch error sampling and dynamic range compensation. Subsequently, φS1, φS3, φPRE, φMES2, and φPRE2 go low, and when they go high, the sampling operation for the input signal and capacitor mismatch error ends. φCOMP goes high, and the comparator module begins sequential comparisons. The entire ADC is in the quantization phase, and the digital logic module controls the first CDACN and first CDACP to participate in the conversion based on the comparator comparison result via the chip select signal Φc1. After the last comparison is completed, φCOMP goes low. At this time, the ADC conversion result is subtracted from the previous cycle's LSB digital code D through the operation of the digital logic module. LSB The final conversion result for this period can be obtained by combining (N-1) with the dynamic range compensation value for this period.

[0046] The next cycle then begins. To handle the MSBCAP mismatch, the second CADCN and second CDACP are used as input signal sampling DACs in the next cycle, while the first CDACN and first CDACP are used for mismatch error sampling and dynamic range compensation. At this time, Φc2 is high and Φc1 is low. Subsequent operations are similar to the previous cycle: φS2 and φS3 are high, and the second CDACN and second CDACP, as input signal sampling DACs, begin sampling the input signals VIN and VIP. Simultaneously, φPRE and φMES1 are high, and the pre-comparator compares the magnitudes of the input VIP and VIN. The comparison result is stored in the digital logic module and transmitted through a digital circuit. PRE '、D PRE The port output, DLSB(N-1), of the digital logic module output terminal outputs the low-order conversion result of the previous cycle to the LSBCAP of the first CDACN and the first CDACP. Subsequently, φPRE1 goes high, and the MSBCAP of the first CDACN and the first CDACP respectively outputs the low-order conversion result of the previous cycle to the LSBCAP of the first CDACN and the first CDACP. PRE '、D PRE Sampling is then performed. Subsequently, φS2, φS3, φPRE, φMES1, and φPRE1 go low, ending the sampling operation of the input signal and capacitor mismatch error. φCOMP goes high, and the comparator module begins sequential comparisons. The entire ADC is in the quantization stage, and the digital logic module controls the second CDACN and the second CDACP to participate in the conversion through the chip select signal Φc2 based on the comparator comparison results. After the final comparison is completed, φCOMP goes low. As an embodiment of the present invention, the above operation is repeated cyclically to achieve a combination of feedforward capacitor mismatch error shaping and dynamic element averaging techniques. The error caused by the low-order capacitor mismatch of the previous cycle is summed with the signal of the current cycle through a multi-input comparator and participates in the conversion together. The purpose is to use the error caused by the low-order capacitor mismatch of the previous cycle to represent the low-order capacitor mismatch error of the current cycle. In the circuit implementation, the CDAC used for sampling the input signal can be called the main DAC, and the CDAC used for mismatch error sampling and dynamic range compensation can be called the MES DAC.

[0047] During circuit operation, the main DAC and MES DAC are continuously implemented by two sets of differential capacitor array DACs alternating cyclically. This operation is equivalent to treating the two sets of differential capacitor array DACs as two pairs of components and performing dynamic component matching. On the one hand, this reduces the impact of mismatch errors between the two sets of differential capacitor array DACs. On the other hand, it also processes the mismatch error of the high-order capacitor MSBCAP, which cannot be shaped by traditional MES technology, thus reducing the impact of high-order capacitor mismatch errors. The digital code on the LSB bits of the main CDAC capacitor array that participated in the conversion in the previous cycle is stored through the digital logic module. In the ADC sampling stage of the next cycle, the digital code is input to the MES ADC. The purpose is to restore the voltage represented by the ideal digital code to an analog quantity containing mismatch errors, and feed it forward to the multi-input comparator for summation. It is important to note that the MES DAC in this cycle is the main DAC in the previous cycle, so the mismatch voltage in the restored analog voltage value is the mismatch error generated during the conversion process of the main DAC in the previous cycle.

[0048] The mismatch error essentially arises from the error generated when the capacitor array DAC converts digital code into analog quantity during the ADC conversion process, such as... Figure 3 The behavioral model of the mismatch error shaping ADC describes the signal processing flow from the analog domain to the digital domain of a feedforward mismatch error shaping successive approximation analog-to-digital converter, where V LSB (n-1) represents the voltage value on the LSB of the previous period capacitor array, which includes the mismatch error E(n-1) of the lower bits of the previous period capacitor array and the ideal voltage D corresponding to the lower bits of the digital code of the previous period capacitor array. LSB (n-1), by subtracting D from the number field LSB (n-1) can be used to obtain the final output of the ADC in this cycle.

[0049] The output can be represented as:

[0050] ;

[0051] in, For the input signal value, This is the amount of mismatch error. Let be a complex variable in the Z-transform domain. It can be seen that the mismatch error is filtered by a first-order filter.

[0052] Since mismatch error shaping involves summing the voltage value of the LSB bits of the capacitor array from the previous cycle with the input voltage of the current cycle, it results in a loss of input range. Therefore, an input dynamic range compensation module needs to be added to the circuit. In the embodiment of this invention, the low-order capacitor LSBCAP of the added MES DAC is responsible for sampling the mismatch error of the previous cycle and performing feedforward capacitor mismatch error shaping, while the high-order capacitor MSBCAP does not need to process the mismatch error of the previous cycle. Based on the pre-comparison result of the input signals VIP and VIN, the bottom plate of the high-order capacitor MSBCAP can be connected to VDD or GND. The purpose is to perform level shifting on the input signal to prevent the input signal from mismatching with VDD. LSB The sum of (n-1) exceeds the quantization range of the ADC, thus compensating for the dynamic range loss caused by the MES technology.

[0053] This invention addresses the shortcomings of traditional mismatch error shaping methods, such as their inability to be applied to lower-level board sampling ADCs and their inability to shape high-level capacitors. It borrows from the method of using feedforward noise-shaping SAR ADCs to handle residual voltage, proposing a feedforward mismatch error shaping SAR ADC. Unlike traditional feedback mismatch error shaping, this invention does not add the input signal to the mismatch error during the sampling stage. Instead, it uses feedforward noise shaping to store the mismatch error through capacitors and then adds it to the input signal using a multi-input comparator, making it more suitable for lower-level board sampling ADCs. Furthermore, regarding the mismatch of high-level capacitors, since the two pairs of CDACN and CDAC alternately act as the main DAC and MES DAC, it can be considered as two sets of components performing dynamic component averaging, reducing the impact of high-level capacitor mismatch. With an added 5% capacitor mismatch, the feedforward mismatch error shaping of this invention achieves a successive approximation analog-to-digital converter SNDR of 78.47dB and an SFDR of 84.3dB. Figure 4 The SNDR and SFDR of a feedforward mismatch error shaping successive approximation analog-to-digital converter are presented in the case of capacitor mismatch.

[0054] The embodiments described above are merely preferred embodiments of the present invention and are not intended to limit the scope of the present invention. Various modifications and improvements made to the technical solutions of the present invention by those skilled in the art without departing from the spirit of the present invention should fall within the protection scope defined by the claims of the present invention.

Claims

1. A feedforward mismatch error shaping successive approximation analog-to-digital converter, characterized in that, include: The module comprises a first CDACP module, a first CDACN module, a second CDACP module, a second CDACN module, a four-input dynamic comparator module, and a digital logic module, wherein the first CDACP module, the first CDACN module, the second CDACP module, and the second CDACN module are each composed of a high-order capacitor MSBCAP and a low-order capacitor LSBCAP. The input terminals of the first CDACP module, the first CDACN module, the second CDACP module, and the second CDACN module are connected to the input voltage, and the output terminals are connected to the input terminals of the four-input dynamic comparator module. The output terminal of the four-input dynamic comparator module is connected to the digital logic module.

2. The feedforward mismatch error shaping successive approximation analog-to-digital converter according to claim 1, characterized in that, The MSBCAP input terminal of the first CDACP module is connected to the first input voltage through a sampling switch and connected to the output terminal of the digital logic module through a pre-comparison switch. The LSBCAP input terminal of the first CDACP module is connected to the first input voltage through a sampling switch and connected to the output terminal of the digital logic module through a mismatch error shaping MES switch. The output terminal of the first CDACP module is connected to the first input terminal of the four-input dynamic comparator module.

3. The feedforward mismatch error shaping successive approximation analog-to-digital converter according to claim 1, characterized in that, The MSBCAP input terminal of the first CDACN module is connected to the second input voltage through a sampling switch and connected to the output terminal of the digital logic module through a pre-comparison switch. The LSBCAP input terminal of the first CDACN module is connected to the first input voltage through a sampling switch and connected to the output terminal of the digital logic module through a MES switch. The output terminal of the first CDACN module is connected to the third input terminal of the four-input dynamic comparator module.

4. The feedforward mismatch error shaping successive approximation analog-to-digital converter according to claim 1, characterized in that, The MSBCAP input terminal of the second CDACP module is connected to the first input voltage through a sampling switch and connected to the output terminal of the digital logic module through a pre-comparison switch. The LSBCAP input terminal of the second CDACP module is connected to the first input voltage through a sampling switch and connected to the output terminal of the digital logic module through a MES switch. The output terminal of the second CDACP module is connected to the second input terminal of the four-input dynamic comparator module.

5. The feedforward mismatch error shaping successive approximation analog-to-digital converter according to claim 1, characterized in that, The MSBCAP input terminal of the second CDACN module is connected to the second input voltage through a sampling switch and connected to the output terminal of the digital logic module through a pre-comparison switch. The LSBCAP input terminal of the second CDACN module is connected to the first input voltage through a sampling switch and connected to the output terminal of the digital logic module through a MES switch. The output terminal of the second CDACN module is connected to the fourth input terminal of the four-input dynamic comparator module.

6. A mismatch error shaping method using a feedforward mismatch error shaping successive approximation analog-to-digital converter as described in any one of claims 1-5, characterized in that, include: Based on the chip select signals Φc1 and Φc2, the first CDACP module, the first CDACN module, the second CDACP module, and the second CDACN module are controlled to work alternately in a cyclic manner, alternately acting as an input signal sampling analog-to-digital converter (DAC) and a mismatch error sampling and dynamic range compensation analog-to-digital converter (DAC), and outputting the final ADC conversion result through the digital logic module.

7. The mismatch error shaping method according to claim 6, characterized in that, Achieving cyclical alternation of work includes: When chip select signal Φc1 is high and chip select signal Φc2 is low, the first CDACP module and the first CDACN module act as the main DAC to sample the input signal, and the second CDACP module and the second CDACN module act as the MES DAC to perform mismatch error sampling and dynamic range compensation. When chip select signal Φc2 is high and chip select signal Φc1 is low, the second CDACP module and the second CDACN module act as the main DAC to sample the input signal, and the first CDACP module and the first CDACN module act as the MES DAC to perform mismatch error sampling and dynamic range compensation.

8. The mismatch error shaping method according to claim 6, characterized in that, ADC final conversion result for: ； in, For the input signal value, This is the amount of mismatch error. Let be a complex variable in the Z-transform domain.

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