A signal automatic notch filter circuit and device thereof

Abstract

The present invention discloses a signal automatic trap circuit, which generates a periodic clock signal through a time base circuit; then, a pulse counting circuit is used to count the pulses of the periodic clock signal of the time base circuit, and when the count reaches a preset number of pulses, a high level is output, otherwise a low level is output; then, two counting circuits are used to perform output level inversion processing according to the high level output by the pulse counting circuit, and output two counting signals of periodic high and low level switching; finally, the trap circuit performs signal trap processing according to the periodic clock signal of the time base circuit and the two counting signals of periodic high and low level switching of the two counting circuits. The present invention does not need to adopt a DSP processor, and only realizes anti-howling through a simple circuit structure combined with the function of a mainstream technology notch filter. The circuit debugging is simple, modular and low-cost, and can be widely used in the field of anti-howling technology.

Description

Technical Field

[0001] The invention relates to the technical field of anti-howling, in particular to a signal automatic trap circuit and equipment thereof. Background Art

[0002] In the power amplifier sound amplification system, when the microphone is pointed at the speaker, the sound waves emitted by the speaker will be received by the microphone through sound reflection. This will form positive feedback in the entire sound amplification system. This will form a self-excitation phenomenon, which is the microphone howling. Since the signal is a feedback superposition process, the howling frequency gradually changes from low frequency to high frequency, and the sound intensity also gradually increases. Howling is destructive to the sound amplification system. Therefore, microphone anti-howling technology was developed. Existing anti-howling technologies mainly include:

[0003] 1. Use DSP technology to realize the function of digital notch filter through software. Calculate the howling frequency and use the algorithm to suppress the howling frequency signal to achieve the purpose of preventing microphone howling. It is also the existing mainstream technology. The disadvantage is that the cost is high and AD sampling (analog to digital), DA digital to analog) chips and DSP processors are required. The cost cannot be reduced and can only be used for high-end product applications.

[0004] 2. The frequency shifting technology is used to shift the frequency of the signal received by the microphone to produce a phase difference, so that the feedback signal cannot overlap with the original signal and cannot form self-excitation. The purpose of preventing microphone howling is achieved. Disadvantage 1 is that when there are multiple frequency points of howling and the feedback signal is strong, the signal will still overlap to form self-excitation, and the anti-howling will lose its meaning. 2. The serious problem is that the human voice drifts a little due to the frequency shifting, which is not real. 3. The analog frequency shifting circuit is used, which is difficult in debugging or production. It has been eliminated by the market at present.

[0005] 3. Chip technology: that is, there is no DSP processor in the chip, and the sampling software algorithm is fixed. Save the price of DSP processor. The mainstream technology is to invert the signal and suppress it. That is, the signal received by the microphone is inverted to produce a 180-degree phase difference and then the signal is limited, destroying the feedback signal overlap (self-excitation) process to achieve the purpose of preventing microphone howling. Disadvantages: The chip price is high, and a single-chip microcomputer must be added to control the parameters. The chip cost is also more than 40 yuan, and the cost of the single-chip microcomputer is not low. The most used solution on low-end products. It is also a helpless choice.

[0006] 4. At present, the mainstream technology for preventing microphone howling is the notch filter. That is, the howling frequency is limited and suppressed. It is a targeted processing method that does not affect other frequencies. It has high market recognition, the best on-site effect, and a realistic listening experience. Since the circuit cost of preventing microphone howling is relatively high, low-end products do not have the function of preventing microphone howling. Users can only purchase it separately. Summary of the invention

[0007] In view of this, the present invention provides a signal automatic notch filter circuit and device thereof, which realizes anti-howling through a notch filter circuit parameter adjustment circuit combined with a simple circuit design of a notch filter circuit with a notch filter, with low cost and simple circuit.

[0008] In a first aspect, an embodiment of the present invention provides a signal automatic trap circuit, including a trap circuit and a trap circuit parameter adjustment circuit; the trap circuit parameter adjustment circuit includes a time base circuit, a pulse counting circuit and a second counting circuit;

[0009] The time base circuit is used to generate a periodic clock signal;

[0010] The pulse counting circuit is used to count the pulses of the periodic clock signal of the time base circuit, and output a high level when the count reaches a preset number of pulses, otherwise it outputs a low level;

[0011] The two counting circuits are used to perform output level inversion processing according to the high level output by the pulse counting circuit, and output two counting signals with periodic high and low level switching;

[0012] The trap circuit is used for performing signal trap processing according to the periodic clock signal of the time base circuit and the two counting signals of the two counting circuits which are periodically switched between high and low levels.

[0013] Optionally, the time base circuit includes a resistor R1, a resistor R5, a resistor R6, a capacitor C1, a capacitor C2, a capacitor C4 and a timing chip U2; one end of the resistor R1 is electrically connected to pin 7 of the timing chip U2, and the other end is electrically connected to pin 4 and pin 8 of the timing chip U2; one end of the resistor R5 is electrically connected to pin 7 of the timing chip U2, and the other end is electrically connected to pin 2 and pin 6 of the timing chip U2; one end of the resistor R6 is electrically connected to pin 3 of the timing chip U2, and the other end is electrically connected to the pulse The impulse counting circuit is electrically connected to the trap circuit; one end of the capacitor C1 is electrically connected to pins 4 and 8 of the timing chip U2, and the other end is electrically connected to the GND end; one end of the capacitor C2 is electrically connected to pins 2 and 6 of the timing chip U2, and the other end is electrically connected to the GND end; one end of the capacitor C4 is electrically connected to pin 5 of the timing chip U2, and the other end is electrically connected to the GND end; pin 1 of the timing chip U2 is electrically connected to the GND end, and pin 8 of the timing chip U2 is electrically connected to the power supply.

[0014] Optionally, the pulse counting circuit includes a digital pulse counting chip U5, which is used to count a preset number of 100 pulses of the periodic clock signal of the timing circuit, and output a high level when the count reaches 100, otherwise it outputs a low level; the pulse counting chip U5 includes a first counting module U5A for counting 10 and a second counting module U5B for counting 10.

[0015] Optionally, pin 1 of the first counting module U5A is electrically connected to the timing circuit; pin 3 of the first counting module U5A is electrically connected to pin 4; pin 2, pin 8 and pin 16 of the first counting module U5A are electrically connected to pin 14 of the second counting module U5B, and a capacitor C3 is connected between pin 16 of the first counting module U5A and pin 14 of the second counting module U5B; pin 7 of the first counting module U5A is electrically connected to pin 15 of the second counting module U5B; pin 12 of the second counting module U5B is electrically connected to pin 13; and pin 9 of the second counting module is electrically connected to the two counting circuits.

[0016] Optionally, the two counting circuits include a resistor R2, a resistor R3, a resistor R7, a transistor Q1 and a binary counter U3; the resistor R3, the collector of the transistor Q1, the emitter of the transistor Q1 and the GND terminal are electrically connected in sequence; pin 1 of the binary counter U3 is electrically connected to the collector of the transistor Q1; pin 13 of the binary counter U3, the resistor R7 and the base of the transistor Q1 are electrically connected in sequence; pin 16, pin 7, pin 9 and pin 10 of the binary counter U3 are electrically connected in sequence, and resistor R2 is connected between pin 6 and pin 7 of the binary counter U3; pin 8 of the binary counter U3 is electrically connected to the GND terminal; pin 14 of the binary counter U3 is connected to the trap circuit, for outputting two counting signals with periodic high and low level switching to the trap circuit.

[0017] Optionally, when the pulse counting circuit outputs a low level, the binary counter counts the low level input from the pin 2 as 0 and outputs a low level at the pin 14;

[0018] When the pulse counting circuit outputs a high level, the binary counter counts the high level input from pin 2 as 1 and outputs a high level at pin 14;

[0019] When the pulse counting circuit outputs a high level again, the binary counter counts to 2 according to the high level input from pin 2, and outputs a high level at pin 13. According to the transistor Q1 whose emitter is electrically connected to the GND terminal, a low level is input to pin 1 of the binary counter electrically connected to the collector of the transistor Q1, and a zeroing process is performed. The binary counter counts to 0, and the signal automatic notch filter circuit returns to the state of when the pulse counting circuit outputs a low level, the binary counter counts to 0 according to the low level input from pin 2, and outputs a low level at pin 14.

[0020] Optionally, the trap circuit includes a first digital potentiometer U4, a second digital potentiometer U6 and a third digital potentiometer U7; the timing circuit is electrically connected to pin 1 of the first digital potentiometer U4, pin 1 of the second digital potentiometer U6 and pin 1 of the third digital potentiometer U7, and is used to input the periodic clock signal to the trap circuit; the two counting circuits are electrically connected to pin 2 of the first digital potentiometer U4, pin 2 of the second digital potentiometer U6 and pin 2 of the third digital potentiometer U7, and are used to input the two counting signals of periodic high and low level switching to the trap circuit.

[0021] Optionally, the resistance values ​​of the first digital potentiometer U4, the second digital potentiometer U6 and the third digital potentiometer U7 of the trap circuit are divided into 100 stages, and the resistance values ​​are determined according to the periodic clock signal input by the pin 1 and the two counting signals of the periodic high and low level switching input by the pin 2;

[0022] When the pin 2 inputs a high level, the pin 1 inputs a clock, and the resistance value increases by 1; when 100 clocks are input, the resistance value is the largest;

[0023] When the pin 2 inputs a low level, the pin 1 inputs a clock, and the resistance value decreases by 1; when 100 clocks are input, the resistance value is the smallest.

[0024] Optionally, the circuit further includes a signal buffer, and the signal buffer is used to isolate the input audio signal front and back; the signal buffer is electrically connected to the trap circuit.

[0025] In a second aspect, an embodiment of the present invention provides a device with an automatic signal trap circuit, comprising the automatic signal trap circuit as described in the first aspect of the embodiment of the present invention.

[0026] The beneficial effects of the present invention are: the parameters of the trap filter circuit are adjusted through the trap filter circuit parameter adjustment circuit; specifically, a periodic clock signal is generated through the time base circuit; then, a pulse counting circuit is used to count the pulses of the periodic clock signal of the time base circuit, and when the count reaches a preset number of pulses, a high level is output, otherwise a low level is output; then, two counting circuits are used to perform output level inversion processing according to the high level output by the pulse counting circuit, and output two counting signals of periodic high and low level switching; finally, the trap filter circuit performs signal trap processing according to the periodic clock signal of the time base circuit and the two counting signals of periodic high and low level switching of the two counting circuits. The present invention does not need to use a DSP processor, and only uses a simple circuit structure combined with the function of the mainstream technology trap filter to achieve anti-howling. The circuit debugging is simple, modular and low-cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 A schematic diagram of the overall architecture principle of a signal automatic trap circuit provided by an embodiment of the present invention;

[0028] Figure 2 An overall circuit diagram of a signal automatic trap circuit provided by an embodiment of the present invention;

[0029] Figure 3 A schematic diagram of the structure of a digital potentiometer provided in an embodiment of the present invention;

[0030] Figure 4 This is the pin function diagram of the X9C104 digital potentiometer;

[0031] Figure 5 A schematic diagram of the parameter adjustment principle of a digital potentiometer provided in an embodiment of the present invention;

[0032] Figure 6 A schematic diagram of the counting principle of a pulse counter provided in an embodiment of the present invention;

[0033] Figure 7 A schematic diagram of the counting principle of a binary counter provided in an embodiment of the present invention;

[0034] Figure 8 A schematic diagram of the structure of a second counting circuit provided by an embodiment of the present invention;

[0035] Fig. 9 A schematic diagram of the corresponding relationship between the time base clock, pulse count and second count provided in an embodiment of the present invention;

[0036] Fig.10 It is a circuit structure diagram of a double-T passive notch filter;

[0037] Fig.11It is a circuit structure diagram of a double-T active trap;

[0038] Fig.12 A schematic diagram of the structure of a double-T trap circuit provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0039] The concept, specific structure and technical effects of the present invention will be clearly and completely described below in combination with the embodiments and drawings to fully understand the purpose, characteristics and effects of the present invention.

[0040] Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, other embodiments obtained by those skilled in the art without creative work all fall within the protection scope of the present invention.

[0041] In addition, all the connection relationships mentioned in the text do not only refer to direct connection of components, but refer to the fact that a better connection structure can be formed by adding or reducing connection accessories according to the specific implementation situation. The various technical features in the present invention can be combined interchangeably without conflicting with each other.

[0042] The embodiment of the present invention provides a signal automatic trap circuit, comprising a trap circuit and a trap circuit parameter adjustment circuit; the trap circuit parameter adjustment circuit comprises a time base circuit, a pulse counting circuit and a second counting circuit;

[0043] The time base circuit is used to generate a periodic clock signal;

[0044] The pulse counting circuit is used to count the pulses of the periodic clock signal of the time base circuit, and output a high level when the count reaches a preset number of pulses, otherwise it outputs a low level;

[0045] The two counting circuits are used to perform output level inversion processing according to the high level output by the pulse counting circuit, and output two counting signals with periodic high and low level switching;

[0046] The trap circuit is used for performing signal trap processing according to the periodic clock signal of the time base circuit and the two counting signals of the two counting circuits which are periodically switched between high and low levels.

[0047] In some embodiments, the timing circuit includes a resistor R1, a resistor R5, a resistor R6, a capacitor C1, a capacitor C2, a capacitor C4 and a timing chip U2; one end of the resistor R1 is electrically connected to pin 7 of the timing chip U2, and the other end is electrically connected to pin 4 and pin 8 of the timing chip U2; one end of the resistor R5 is electrically connected to pin 7 of the timing chip U2, and the other end is electrically connected to pin 2 and pin 6 of the timing chip U2; one end of the resistor R6 is electrically connected to pin 3 of the timing chip U2, and the other end is electrically connected to the The pulse counting circuit is electrically connected to the trap circuit; one end of the capacitor C1 is electrically connected to pins 4 and 8 of the timing chip U2, and the other end is electrically connected to the GND end; one end of the capacitor C2 is electrically connected to pins 2 and 6 of the timing chip U2, and the other end is electrically connected to the GND end; one end of the capacitor C4 is electrically connected to pin 5 of the timing chip U2, and the other end is electrically connected to the GND end; pin 1 of the timing chip U2 is electrically connected to the GND end, and pin 8 of the timing chip U2 is electrically connected to the power supply.

[0048] In some embodiments, the pulse counting circuit includes a digital pulse counting chip U5, which is used to count a preset number of 100 pulses of the periodic clock signal of the timing circuit, and output a high level when the count reaches 100, otherwise it outputs a low level; the pulse counting chip U5 includes a first counting module U5A for counting 10 and a second counting module U5B for counting 10.

[0049] In some embodiments, pin 1 of the first counting module U5A is electrically connected to the timing circuit; pin 3 of the first counting module U5A is electrically connected to pin 4; pin 2, pin 8 and pin 16 of the first counting module U5A are electrically connected to pin 14 of the second counting module U5B, and a capacitor C3 is connected between pin 16 of the first counting module U5A and pin 14 of the second counting module U5B; pin 7 of the first counting module U5A is electrically connected to pin 15 of the second counting module U5B; pin 12 of the second counting module U5B is electrically connected to pin 13; and pin 9 of the second counting module is electrically connected to the two counting circuits.

[0050] In some embodiments, the two counting circuits include a resistor R2, a resistor R3, a resistor R7, a transistor Q1 and a binary counter U3; the resistor R3, the collector of the transistor Q1, the emitter of the transistor Q1 and the GND terminal are electrically connected in sequence; the pin 1 of the binary counter U3 is electrically connected to the collector of the transistor Q1; the pin 13 of the binary counter U3, the resistor R7 and the base of the transistor Q1 are electrically connected in sequence; the pin 16, the pin 7, the pin 9 and the pin 10 of the binary counter U3 are electrically connected in sequence, and the resistor R2 is connected between the pin 6 and the pin 7 of the binary counter U3; the pin 8 of the binary counter U3 is electrically connected to the GND terminal; the pin 14 of the binary counter U3 is connected to the trap circuit, for outputting two counting signals with periodic high and low level switching to the trap circuit.

[0051] In some embodiments, when the pulse counting circuit outputs a low level, the binary counter counts to 0 according to the low level input from the pin 2, and outputs a low level at the pin 14;

[0052] When the pulse counting circuit outputs a high level, the binary counter counts the high level input from pin 2 as 1 and outputs a high level at pin 14;

[0053] When the pulse counting circuit outputs a high level again, the binary counter counts to 2 according to the high level input from pin 2, and outputs a high level at pin 13. According to the transistor Q1 whose emitter is electrically connected to the GND terminal, a low level is input to pin 1 of the binary counter electrically connected to the collector of the transistor Q1, and a zeroing process is performed. The binary counter counts to 0, and the signal automatic notch filter circuit returns to the state of when the pulse counting circuit outputs a low level, the binary counter counts to 0 according to the low level input from pin 2, and outputs a low level at pin 14.

[0054] In some embodiments, the trap circuit includes a first digital potentiometer U4, a second digital potentiometer U6 and a third digital potentiometer U7; the timing circuit is electrically connected to pin 1 of the first digital potentiometer U4, pin 1 of the second digital potentiometer U6 and pin 1 of the third digital potentiometer U7, and is used to input the periodic clock signal to the trap circuit; the two counting circuits are electrically connected to pin 2 of the first digital potentiometer U4, pin 2 of the second digital potentiometer U6 and pin 2 of the third digital potentiometer U7, and are used to input the two counting signals of periodic high and low level switching to the trap circuit.

[0055] In some embodiments, the resistance values ​​of the first digital potentiometer U4, the second digital potentiometer U6 and the third digital potentiometer U7 of the trap circuit are divided into 100 stages, and the resistance values ​​are determined according to the periodic clock signal input by the pin 1 and the two counting signals of the periodic high and low level switching input by the pin 2;

[0056] When the pin 2 inputs a high level, the pin 1 inputs a clock, and the resistance value increases by 1; when 100 clocks are input, the resistance value is the largest;

[0057] When the pin 2 inputs a low level, the pin 1 inputs a clock, and the resistance value decreases by 1; when 100 clocks are input, the resistance value is the smallest.

[0058] In some embodiments, the circuit further includes a signal buffer, and the signal buffer is used to isolate the input audio signal front and back; the signal buffer is electrically connected to the trap circuit.

[0059] In a second aspect, an embodiment of the present invention provides a device with an automatic signal trap circuit, comprising the automatic signal trap circuit as described in the first aspect of the embodiment of the present invention.

[0060] The following takes a specific signal automatic trap circuit as an example, and further describes the present invention in detail in conjunction with the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain the present invention, and are not used to limit the present invention:

[0061] Reference Figure 1 and Figure 2 A signal automatic trap circuit includes a trap circuit and a trap circuit parameter adjustment circuit; the trap circuit parameter adjustment circuit includes a time base circuit, a pulse counting circuit and a second counting circuit. Specifically, the adjustment principle of the trap circuit parameter adjustment circuit is:

[0062] 1. U4, U7, and U6 in the circuit are X9C104 chips (digital potentiometer chips). Figure 3 As shown, the chip is divided into A / B for easy understanding of the circuit. The left side is the chip pin, part A is the control line, and part B is the variable resistor.

[0063] The principle of digital resistor X9C104 chip adjustment: U4, U6, U7 are digital adjustable resistor X9C104 chips, which are 100-stage adjustable resistors. The resistance value is divided into 100 stages internally. The adjustable resistance is determined by pin 1 (INC) and pin 2 (U / D). The pin functions of the chip are as follows: Figure 4 As shown, the principle of adjustable internal resistance value is as follows Figure 5 shown.

[0064] A: When pin 2 (U / D) is high, pin 1 (INC) is one clock, and the internal resistance value increases by 1. The resistance value of the resistor with 100 clocks is the largest.

[0065] B: When pin 2 (U / D) is at a low level, pin 1 (INC) is one clock, and the internal resistance value decreases by 1. The resistance value of the resistor with 100 clocks is the smallest.

[0066] C: Connect the timing signal to the chip pin 1 (INC) and the second counting signal to the chip pin 2 (U / D) to complete the adjustable parameters of the digital resistor X9C104 chip.

[0067] D: Time base clock

[0068] The circuit formed by U2 (EN555 chip) in the overall circuit diagram is a precise multivibrator circuit. It can generate a stable clock signal. It is used as a time base clock signal. It is directly connected to the digital resistor X9C104 chip pin 1 (INC).

[0069] E: Two counting signals

[0070] In the overall circuit diagram, the (U5) 74HC390 chip is used as a pulse counter and the (U3) SN74LS161 binary counter is used. The two counters U5A and U5B inside the 74HC390 chip (U5) form a 100 counter. Figure 6 , count the U2 (EN555 chip) time base clock, when counting to 100 pulses, pin QD outputs a high level. And enters (U3) SN74LS161 binary counter. The count true value of the 74HC390 (U5) digital pulse counting chip is shown in Table 1:

[0071] Table 1

[0072]

[0073]

[0074] Reference Figure 7 SN74LS161 (U3) binary counter counts the pulses after 100 counts of 74HC390 chip (U5). The main purpose is to reverse the output level of SN74LS161 pin Q0. To achieve the purpose of (pulses after the first 100 counts) Q0 outputs low level; (pulses after the second 100 counts) Q0 outputs high level. In this way, the Q0 output level inversion continues. And connect to X9C104 chip pin 2 (UD). Among them, the 74LS161 truth table is shown in Table 2:

[0075] Table 2

[0076]

[0077] SN74LS161 (U3) pin Q0 output level inversion implementation principle: refer to Figure 8 , circuit (U3) pin 2 is the input counting signal, pin 1 is the reset clearing function; pin Q0 is the second counting signal output;

[0078] Condition 1: When the SN74LS161 true straight meter counts to 0 (the pulse output is low before counting to 100), pin Q0 outputs a low level.

[0079] Condition 2: When the SN74LS161 true straight meter counts to 1 (the first pulse after 100 counts outputs a high level), pin Q0 outputs a high level.

[0080] Condition 3: When the SN74LS161 true straight meter counts to 2 (the pulse after the second 100 counts outputs a high level), pin Q1 outputs a high level. Connected to Q1 transistor NPN type, the transistor conducts to control (U3) pin 1 to pull down to ground. (U3) pin 1 is low level. Reset chip count clearing function; pin Q0 outputs a low level when the SN74LS161 true straight meter counts to 0. Return to condition 1. Repeat this process.

[0081] The corresponding relationship between the time base clock U2 (EN555 chip) and the (U5) 74HC390 chip 100 count and the (U3) SN74LS161 binary count is as follows Fig. 9 As shown. Through counting operation, it is connected to the digital resistor X9C104 chip to achieve the purpose of automatically adjusting the internal resistance value of the digital resistor.

[0082] It should also be noted that the trap circuit adopts a double-T trap circuit, and the principle is:

[0083] 1. Notch filter, also known as band-stop filter, is used to suppress or attenuate signals in a certain frequency band, while allowing all signals outside the frequency band to pass. A typical RC double-T network is composed of an RC low-pass filter and an RC high-pass filter in parallel. In principle, a low-pass filter with a cutoff frequency of f1 and a high-pass filter with a cutoff frequency of f2 are connected in parallel. When the condition f1<f2 is met, a band-stop filter is formed. When the input signal passes through the circuit, all signals with f<f1 can pass through the low-pass filter, and all signals with f>f2 can pass through the high-pass filter. Only signals with a frequency range of f1<f<f2 are blocked.

[0084] 2. The values ​​of the components in the double-T network satisfy the relationship: C1=C2=C, C3=2C, that is, C3=2C1=2C2; R1=R2=R, R3=1 / 2R, that is, R1=R2=2R3.

[0085] 3. Fig.10 The circuit satisfies the following circuit equation:

[0086] (V1-V2)sC1=2V2 / R3+(V2-V4)sC2

[0087] (V1-V2) / R1=(V3-V4) / R2+V3sC3

[0088] (V3-V4) / R2+(V2-V4)sC2=0

[0089] 4. Through the above four formulas, we can get:

[0090]

[0091] 5. It can be seen that the above formula satisfies the typical second-order system characteristics, so we can get:

[0092]

[0093]

[0094]

[0095] Wherein, ω0 represents the center angular frequency, 2β represents the stop bandwidth, and Q represents the quality factor of the notch characteristic.

[0096] 6. Calculation of notch center frequency: Center frequency The center notch frequency can be changed by simply changing the value of the resistor. Fig.11 Since the passive twin-T network has a small input impedance and a large output impedance, it is easily affected by the circuit stages before and after, has poor characteristics, and has a low Q value, so it is not suitable for direct use. Usually, an operational amplifier plus appropriate feedback is used on the basis of the twin-T network to form a practical active twin-T trap.

[0097] The digital resistor X9C104 is automatically adjustable through the adjustment principle of the above-mentioned notch filter circuit parameter adjustment circuit, and then used to change the notch filter parameters. Calculation of notch center frequency: Center frequency The center notch frequency can be changed by simply changing the value of the resistor.

[0098] Reference Fig.12, U6B, U4B, U7B, C8, C9, C10, U1B form a double T notch filter. U6B, U4B, U7B (X9C104 chip) are 100-stage variable resistors. Changing the resistance value changes the notch frequency, which is used to adjust the notch parameters. Limiting the howling frequency of the microphone. It is also the core of the circuit. U1B is an operational amplifier. The analog signal reaches the U1A operational amplifier through the C7 capacitor to form a signal buffer, isolating the signal from front to back. After entering the notch filter for limiting suppression, it is output from the C6 capacitor.

[0099] By changing the resistance value, the notch filter parameters can be changed. The signal notch capability is achieved, and the overlapping self-excitation condition of the microphone feedback signal is destroyed. The microphone is prevented from squeaking. The circuit repeats the notch process from low frequency to high frequency and from high frequency to low frequency. Therefore, the signal notch filter function can be realized without a DSP processor.

[0100] In summary, the embodiments of the present invention disclose a signal automatic notch filter circuit and device thereof. The present invention combines a notch filter circuit parameter adjustment circuit with a simple circuit design of a notch filter circuit with a notch filter, does not require a DSP processor, and only uses a simple circuit structure combined with the function of a notch filter of mainstream technology to achieve anti-howling. The circuit has simple circuit debugging, modularization and low cost.

[0101] The above is a specific description of the preferred implementation of the present invention, but the present invention is not limited to the described implementation mode. Those skilled in the art may make various equivalent modifications or substitutions without violating the spirit of the present invention. These equivalent modifications or substitutions are all included in the scope defined by the claims of this application.

Claims

1. A signal automatic trap circuit, characterized in that: It includes a notch filter circuit and a notch filter circuit parameter adjustment circuit; the notch filter circuit parameter adjustment circuit includes a time base circuit, a pulse counting circuit and a second counting circuit; The time base circuit is used to generate a periodic clock signal; The pulse counting circuit is used to count the pulses of the periodic clock signal of the time base circuit, and output a high level when the count reaches a preset number of pulses, otherwise it outputs a low level; The two counting circuits are used to perform output level inversion processing according to the high level output by the pulse counting circuit, and output two counting signals with periodic high and low level switching; The trap circuit is used for performing signal trap processing according to the periodic clock signal of the time base circuit and the two counting signals of the periodic high and low level switching of the two counting circuits; Wherein, the trap circuit includes a first digital potentiometer U4, a second digital potentiometer U6 and a third digital potentiometer U7; the timing circuit is electrically connected to pin 1 of the first digital potentiometer U4, pin 1 of the second digital potentiometer U6 and pin 1 of the third digital potentiometer U7, and is used to input the periodic clock signal to the trap circuit; the two counting circuits are electrically connected to pin 2 of the first digital potentiometer U4, pin 2 of the second digital potentiometer U6 and pin 2 of the third digital potentiometer U7, and are used to input the two counting signals of periodic high and low level switching to the trap circuit; The resistance values ​​of the first digital potentiometer U4, the second digital potentiometer U6 and the third digital potentiometer U7 of the trap circuit are divided into 100 stages, and the resistance values ​​are determined according to the periodic clock signal input from the pin 1 and the two counting signals of the periodic high and low level switching input from the pin 2; When the pin 2 inputs a high level, the pin 1 inputs a clock, and the resistance value increases by 1; when 100 clocks are input, the resistance value is the largest; When the pin 2 inputs a low level, the pin 1 inputs a clock, and the resistance value decreases by 1; when 100 clocks are input, the resistance value is the smallest.

2. The automatic signal trap circuit according to claim 1, characterized in that: The time base circuit includes a resistor R1, a resistor R5, a resistor R6, a capacitor C1, a capacitor C2, a capacitor C4 and a timing chip U2; one end of the resistor R1 is electrically connected to pin 7 of the timing chip U2, and the other end is electrically connected to pins 4 and 8 of the timing chip U2; one end of the resistor R5 is electrically connected to pin 7 of the timing chip U2, and the other end is electrically connected to pins 2 and 6 of the timing chip U2; one end of the resistor R6 is electrically connected to pin 3 of the timing chip U2, and the other end is electrically connected to the pulse timing chip U2. The digital circuit is electrically connected to the trap circuit; one end of the capacitor C1 is electrically connected to pins 4 and 8 of the timing chip U2, and the other end is electrically connected to the GND end; one end of the capacitor C2 is electrically connected to pins 2 and 6 of the timing chip U2, and the other end is electrically connected to the GND end; one end of the capacitor C4 is electrically connected to pin 5 of the timing chip U2, and the other end is electrically connected to the GND end; pin 1 of the timing chip U2 is electrically connected to the GND end, and pin 8 of the timing chip U2 is electrically connected to the power supply.

3. The signal automatic trap circuit according to claim 1, characterized in that: The pulse counting circuit includes a digital pulse counting chip U5, which is used to count a preset number of 100 pulses of the periodic clock signal of the timing circuit. When the count reaches 100, a high level is output, otherwise a low level is output; the pulse counting chip U5 includes a first counting module U5A for 10 counting and a second counting module U5B for 10 counting.

4. The automatic signal trap circuit according to claim 3, characterized in that: Pin 1 of the first counting module U5A is electrically connected to the timing circuit; Pin 3 of the first counting module U5A is electrically connected to Pin 4; Pin 2, Pin 8 and Pin 16 of the first counting module U5A are electrically connected to Pin 14 of the second counting module U5B, and a capacitor C3 is connected between Pin 16 of the first counting module U5A and Pin 14 of the second counting module U5B; Pin 7 of the first counting module U5A is electrically connected to Pin 15 of the second counting module U5B; Pin 12 of the second counting module U5B is electrically connected to Pin 13; Pin 9 of the second counting module is electrically connected to the two counting circuits.

5. The signal automatic trap circuit according to claim 1, characterized in that: The two counting circuits include a resistor R2, a resistor R3, a resistor R7, a transistor Q1 and a binary counter U3; the resistor R3, the collector of the transistor Q1, the emitter of the transistor Q1 and the GND terminal are electrically connected in sequence; the pin 1 of the binary counter U3 is electrically connected to the collector of the transistor Q1; the pin 13 of the binary counter U3, the resistor R7 and the base of the transistor Q1 are electrically connected in sequence; the pin 16, the pin 7, the pin 9 and the pin 10 of the binary counter U3 are electrically connected in sequence, and the resistor R2 is connected between the pin 6 and the pin 7 of the binary counter U3; the pin 8 of the binary counter U3 is electrically connected to the GND terminal; the pin 14 of the binary counter U3 is connected to the trap circuit, and is used to output two counting signals with periodic high and low level switching to the trap circuit.

6. The signal automatic trap circuit according to claim 5, characterized in that: When the pulse counting circuit outputs a low level, the binary counter counts the low level inputted at its pin 2 to 0, and outputs a low level at pin 14; When the pulse counting circuit outputs a high level, the binary counter counts the high level input from pin 2 as 1 and outputs a high level at pin 14; When the pulse counting circuit outputs a high level again, the binary counter counts to 2 according to the high level input from pin 2, and outputs a high level at pin 13. According to the transistor Q1 whose emitter is electrically connected to the GND terminal, a low level is input to pin 1 of the binary counter electrically connected to the collector of the transistor Q1, and a zeroing process is performed. The binary counter counts to 0, and the signal automatic notch filter circuit returns to the state of when the pulse counting circuit outputs a low level, the binary counter counts to 0 according to the low level input from pin 2, and outputs a low level at pin 14.

7. The signal automatic trap circuit according to claim 1, characterized in that: It also includes a signal buffer, which is used to isolate the input audio signal from the front and back; the signal buffer is electrically connected to the trap circuit.

8. A device with a signal automatic trap circuit, characterized in that: The invention comprises the signal automatic trap circuit as claimed in any one of claims 1 to 7.

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