A test method and device based on high-speed signal test

Abstract

The application provides a test method and device based on high-speed signal test, which comprises high-speed signal test and direct current information test. The high-speed signal test is as follows: an instruction about high-speed signal test is sent to a preset first test module and / or a preset second test module; a channel instruction is generated based on the instruction and sent to a first switching control unit to transmit control resources; in a resource unit, the control resources are transmitted to a to-be-tested module by a switching channel to perform high-speed signal test. The scheme can simultaneously perform high-speed signal test and direct current information test, has low test cost, high resource effective reuse rate, high test efficiency, and can meet the high-speed signal test requirements of low-end, terminal and high-end products. On the basis of high-speed signal test, the direct current information test is expanded by using existing hardware basis, high-speed signal test and direct current information test are simultaneously realized, and the resources of the test machine are fully utilized.

Description

Technical Field

[0001] This invention relates to the field of semiconductor testing, and in particular to a testing method and apparatus based on high-speed signal testing. Background Technology

[0002] The complete chip manufacturing process includes several stages such as chip design, wafer fabrication, packaging, and testing, among which wafer fabrication is particularly complex.

[0003] A wafer is a silicon wafer used to fabricate silicon semiconductor circuits; its raw material is silicon. High-purity polycrystalline silicon is dissolved, doped with silicon crystal seeds, and then slowly pulled out to form a cylindrical single-crystal silicon ingot. After grinding, polishing, and slicing, the silicon ingot forms a silicon wafer. The semiconductor industry has extremely high requirements for wafer surface defect detection, demanding high efficiency and accuracy to capture effective defects and achieve real-time detection.

[0004] Each chip has an extremely large number of dies, and organizing a single pin test pattern is a very complex process. This requires that during production, models with the same chip specifications be manufactured in large quantities.

[0005] ATE (Automatic Test Equipment) is a collection of test instruments controlled by a high-performance computer. It's a test system composed of test instruments and a computer, with the computer controlling the test hardware by executing instructions from the test program. Semiconductor chip ATEs are used to test the functionality and performance integrity of integrated circuits. They are crucial equipment in the integrated circuit manufacturing process, ensuring integrated circuit quality. Testing integrated circuits typically involves four processes: test program design, program compilation, vector loading, and test execution.

[0006] High-speed signal testing is a crucial testing procedure for chips, wafers, and dies. Conventional test equipment has limited resources and cannot meet the needs of some high-speed signal testing. On the other hand, test equipment that supports high-end signal testing is extremely expensive, has very low resource utilization, is difficult to use for large-scale testing, and is not suitable for testing in specialized industries. Summary of the Invention

[0007] In view of this, the present invention proposes a testing method and apparatus based on high-speed signal testing, the specific scheme of which is as follows:

[0008] A test method based on high-speed signal testing includes high-speed signal testing, wherein the high-speed signal testing is as follows:

[0009] The preset server sends a first test command for high-speed signal testing to the preset first test module and / or the preset second test module;

[0010] The first test module generates a first channel instruction carrying the first control resource and the first channel information based on the first test instruction, and sends the first channel instruction to the preset first switching control unit;

[0011] The first switching control unit switches the corresponding channel according to the first channel information, so as to transmit the first control resource to the preset resource unit through the channel. The resource unit is preset with a high-speed signal channel related to the high-speed signal test.

[0012] In the resource unit, the first control resource is transferred to the module under test by switching to the high-speed signal channel to perform the first high-speed signal test;

[0013] The second test module generates a second channel instruction carrying the second control resource and the second channel information based on the first test instruction, and sends the second channel instruction to the preset second switching control unit;

[0014] The second switching control unit switches the corresponding channel according to the second channel information, so as to transmit the second control resource to the module under test through the channel for the second high-speed signal test.

[0015] In one specific embodiment, a DC information test is also included, which is as follows:

[0016] The server sends a second test command regarding DC information testing to a preset industrial control computer;

[0017] The industrial control computer distributes the second test command to one or more ATE devices;

[0018] The ATE device parses the second test command to obtain DC test resources, and controls the preset resource switching control unit to transfer the DC test resources to the resource unit. The resource unit has a preset DC information channel for the DC information test.

[0019] In the resource unit, the DC information channel is switched to transfer the DC test resources to the module under test for DC information testing.

[0020] In one specific embodiment, the test result of the module under test in the DC information test is detected to obtain DC information test data;

[0021] The DC information test data is uploaded to the ATE device, and the ATE device uploads the DC information test data to the server through the industrial control computer;

[0022] The test results of the module under test in the first high-speed signal test and the second high-speed test are detected to obtain the first high-speed signal test data and the second high-speed signal test data, respectively.

[0023] The first high-speed signal test data and the second high-speed signal test data are uploaded to the server through the first test module;

[0024] The server integrates the first high-speed signal test data, the second high-speed signal test data, and the DC information test results to determine whether the module under test has a fault and the cause of the fault.

[0025] In one specific embodiment, the first test module is smaller than the second test module in terms of the high-speed signal testing rate;

[0026] The first test module supports remote deployment of high-speed signals;

[0027] The second test module supports near-end placement of high-speed signals.

[0028] In one specific embodiment, the rate of the first test module for high-speed signal testing is no higher than 1.5Gbps, so as to realize the testing of low-to-mid-range high-speed signals at remote locations;

[0029] The second test module has a high-speed signal testing rate of over 1.5Gbps to enable near-end mid-to-high-end high-speed signal testing.

[0030] In one specific embodiment, the module under test includes at least one chip, at least one wafer, or at least one die;

[0031] The high-speed signal testing can achieve parallel testing of multiple chips, multiple wafers, or multiple dies;

[0032] The DC information test can realize parallel testing of multiple chips, multiple wafers or multiple dies.

[0033] In one specific embodiment, the first test module, the first switching control unit, the resource unit, and the resource switching control unit are integrated into an onboard resource module, which is connected to the service board in the ATE device.

[0034] The second test module and the second switching control unit are integrated into the high-speed signal processing module;

[0035] The onboard resource module is the same as the high-speed signal processing module in terms of the number of chips, wafers, and dies used in parallel testing.

[0036] A testing device based on high-speed signal testing includes the following:

[0037] The server is used to send the first test command for high-speed signal testing to the preset first test module and / or the preset second test module.

[0038] The first test module is used to receive the first test instruction, generate a first channel instruction carrying the first control resource and the first channel information based on the first test instruction, and send the first channel instruction.

[0039] The first switching control unit is used to switch the corresponding channel according to the first channel information so as to transmit the first control resource to the preset resource unit through the channel;

[0040] The resource unit is pre-configured with a high-speed signal channel for the high-speed signal test, which is used to switch to the high-speed signal channel to transfer the first control resource to the module under test for the first high-speed signal test.

[0041] The second test module is used to generate a second channel instruction carrying second control resources and second channel information based on the first test instruction, and to issue the second channel instruction.

[0042] The second switching control unit is used to switch the corresponding channel according to the second channel information, so as to transmit the second control resource to the module under test through the channel for the second high-speed signal test.

[0043] In one specific embodiment, the server is also used to issue a second test command regarding DC information testing;

[0044] The testing apparatus also includes:

[0045] An industrial control computer is used to receive the second test command and distribute the second test command to one or more ATE devices;

[0046] ATE equipment is used to parse the second test command to obtain DC test resources and control the transmission of the DC test resources;

[0047] A resource switching control unit, connected to the ATE equipment, is used to transmit the DC test resources to the resource unit under the control of the ATE equipment.

[0048] The resource unit is pre-configured with a DC information channel for the DC information test, which is used to switch to the DC information channel to transfer the DC test resources to the module under test for DC information testing.

[0049] In one specific embodiment, the resource switching control unit, the resource unit, the first test module, and the first switching control unit are integrated into a preset onboard resource module, and the onboard resource module is connected to the service board in the ATE device;

[0050] The second test module and the second switching control unit are integrated into the high-speed signal processing module;

[0051] The testing device can perform parallel testing on multiple chips, multiple wafers, or multiple dies.

[0052] The onboard resource module is the same as the high-speed signal processing module in terms of the number of chips, wafers, and dies used in parallel testing.

[0053] Beneficial Effects: This invention proposes a testing method and apparatus based on high-speed signal testing, capable of simultaneously performing high-speed signal testing and DC information testing on multiple wafers, dies, or chips. It offers low testing cost, high resource utilization, and high testing efficiency. By incorporating a dedicated high-speed processing module into the testing machine, high-speed signal testing at different rates can be achieved, meeting the high-speed signal testing needs of low-end, mid-range, and high-end devices. Building upon high-speed signal testing, DC information testing is extended using existing hardware, simultaneously realizing both high-speed signal testing and DC information testing, fully utilizing the testing machine's resources. Attached Figure Description

[0054] Figure 1 This is a schematic flowchart of a high-speed signal testing method according to an embodiment of the present invention;

[0055] Figure 2 This is a schematic flowchart of a DC information testing method according to an embodiment of the present invention;

[0056] Figure 3 This is a schematic diagram of the test result feedback process according to an embodiment of the present invention;

[0057] Figure 4 This is a schematic diagram of the test device module according to an embodiment of the present invention.

[0058] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0059] Reference numerals: 1-Server; 2-Onboard resource module; 3-High-speed signal processing module; 4-Industrial control computer; 5-ATE device; 6-Module under test; 21-First test module; 22-First switching control unit; 23-Resource unit; 24-Resource switching control unit; 31-First test module; 32-Second switching control unit. Detailed Implementation

[0060] In the following, various embodiments of the invention will be described more fully. The invention may have various embodiments, and adjustments and changes may be made therein. However, it should be understood that there is no intention to limit the various embodiments of the invention to the specific embodiments disclosed herein, but rather the invention should be understood to cover all adjustments, equivalents, and / or alternatives falling within the spirit and scope of the various embodiments disclosed herein.

[0061] It should be noted that, regarding parallel testing of wafers, existing technologies are basically unable to perform parallel testing of multiple wafers due to limitations in testing equipment. However, the solution proposed in this application can theoretically achieve parallel high-speed signal testing and parallel DC signal testing of multiple wafers.

[0062] The terminology used in the various embodiments disclosed herein is for the purpose of describing particular embodiments only and is not intended to limit the various embodiments disclosed herein. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which the various embodiments disclosed herein pertain. The terms (such as those defined in commonly used dictionaries) are to be interpreted as having the same meaning as in the context of the relevant technical field and are not to be interpreted as having an idealized or overly formal meaning, unless clearly defined in the various embodiments disclosed herein.

[0063] Example 1

[0064] Embodiment 1 of this invention discloses a testing method based on high-speed signal testing, which can perform high-speed signal testing on chips, wafers, and dies, with high resource utilization and low cost. A flowchart of the testing method is attached to the specification. Figure 1 As shown, the specific solution is as follows:

[0065] A testing method based on high-speed signal testing includes high-speed signal testing and DC information testing. This embodiment of the testing method can achieve parallel high-speed signal testing and DC information testing for chips, wafers, and dies. Due to the differences in their structures, the purposes and items of testing differ for wafers, chips, and dies.

[0066] Take high-speed signal testing of chips and wafers as an example.

[0067] High-speed signal testing of the chip primarily verifies whether the chip under test conforms to preset production specifications. This includes verifying whether the timing meets the predetermined design, whether the image or signal quality meets the predetermined design, and also includes power supply testing, waveform testing, impedance testing, etc. In this embodiment, power supply testing is performed in the resource unit.

[0068] There are many types of defects on the wafer surface, some generated during manufacturing and others due to inherent material defects. Different defect detection methods can lead to different categorizations of defects. In this embodiment, high-speed signal testing is performed on the wafer to ensure that every die in the entire wafer meets the basic characteristics of the device, typically including voltage, current, timing, and functional verification. This can be used to assess the manufacturer's manufacturing process level.

[0069] DC information testing of chips, wafers, and dies involves testing parameters related to current and voltage. DC information testing includes short-circuit testing, open-circuit testing, leakage current testing, maximum current testing, output drive current testing, and threshold voltage testing. The corresponding test results can be obtained according to the actual testing requirements.

[0070] In this embodiment, the high-speed signal test includes high-speed signal testing by a first test module and high-speed signal testing by a second test module. The first and second test modules can perform high-speed signal testing simultaneously or separately.

[0071] The high-speed signal test of the first test module is as per the attached instruction manual. Figure 1 As shown, the details are as follows:

[0072] 101. The preset server sends the first test command for high-speed signal testing to the preset first test module;

[0073] 102. The first test module generates a first channel instruction carrying the first control resource and the first channel information based on the first test instruction, and sends the first channel instruction to the preset first switching control unit;

[0074] 103. The first switching control unit switches the corresponding channel according to the first channel information, so as to transmit the first control resource to the preset resource unit through the channel. The resource unit has a preset high-speed signal channel for high-speed signal testing.

[0075] 104. In the resource unit, switch to the high-speed signal channel to transfer the first control resource to the module under test and perform the first high-speed signal test.

[0076] The high-speed signal test for the second test module is as per the attached instruction manual. Figure 1 As shown, the details are as follows:

[0077] 111. The preset server sends the first test command for high-speed signal testing to the preset second test module;

[0078] 112. The second test module generates a second channel instruction carrying the second control resource and the second channel information based on the first test instruction, and sends the second channel instruction to the preset second switching control unit;

[0079] 113. The second switching control unit switches the corresponding channel according to the second channel information, so as to transmit the second control resources to the module under test through the channel for the second high-speed signal test.

[0080] The first and second test modules can perform different high-speed signal tests respectively. For example, different items of high-speed signal testing can be performed using the two test modules. Preferably, the first and second test modules can perform high-speed signal testing at different rates.

[0081] The first test module, the first switching control unit, the resource unit, and the resource switching control unit are integrated into an onboard resource module, which connects to the service board in the ATE equipment. The onboard resource module is attached to the ATE equipment. The second test module and the second switching control unit are integrated into a high-speed signal processing module. Because the first test module is integrated into the onboard resource module, the position of the onboard resource module is essentially fixed, thus limiting the mobility of the first test module. Furthermore, the path between the first test module and the module under test (DUT) is relatively long, requiring a long cable for communication. The cable length affects the signal arrival time at the DUT, making precise control of signal timing difficult and hindering accurate measurement of the DUT's impedance characteristics, ultimately impacting the test results of the high-speed signal test.

[0082] The second test module is located on top of the high-speed signal processing module. The high-speed signal processing module is independent of other modules and its position can be arbitrarily set, giving the second test module strong positional flexibility. It can be positioned near-end or far-end according to the requirements of high-speed signal testing to meet the testing needs of mid-to-high-end high-speed signals. Preferably, the first test module supports far-end placement of high-speed signals; the second test module supports near-end placement, eliminating the need for long cables, reducing signal timing delays caused by cables, and enabling high-precision high-speed signal testing. The chip or wafer under test is assigned a product number, and the server can select either the first or second test module for high-speed signal testing based on the product number.

[0083] Based on the different rate requirements of high-speed signal testing, it can be divided into three levels: low-end, mid-range, and high-end. Among them, high-end high-speed signal testing has the highest rate requirements. The first test module, combined with the second test module, can meet the testing needs of low-end, mid-range, and high-end high-speed signals. Preferably, the first test module has a lower rate than the second test module in terms of high-speed signal testing speed. That is, the first test module is used for far-end low-to-mid-range high-speed signal testing, and the second test module is used for near-end mid-to-high-range high-speed signal testing.

[0084] Given the relatively long path between the first test module and the module under test, it is suitable for remote deployment of high-speed signals. Therefore, the first test module is used to meet the requirement of remote testing of low-to-mid-range high-speed signals. Based on the mobility of the second test module, it can be deployed near the high-range signal location to meet the requirement of near-end testing of mid-to-high-range high-speed signals.

[0085] Among them, near-end high-speed signal testing refers to placing the high-speed signal test module (second test module) relatively close to the module under test, testing higher-speed applications. Far-end low-speed signal testing refers to placing the high-speed signal test module (i.e., first test module) relatively far from the module under test, testing relatively low-to-medium speed applications.

[0086] More preferably, the first test module has a high-speed signal testing rate of no more than 1.5Gbps to achieve low-to-mid-range high-speed signal testing at distant locations; the second test module has a high-speed signal testing rate of 1.5Gbps or higher to achieve high-end high-speed signal testing at near locations. The first and second test modules are combined to achieve high-speed signal testing at low, mid, and high end levels.

[0087] In this embodiment, the ATE device is a test machine, and existing technologies commonly use test machines for high-speed signal testing. However, test machines capable of high-speed signal testing of chips or wafers, especially those capable of high-end high-speed signal testing, are extremely expensive, have very low resource reuse rates, and are inefficient, making them unsuitable for testing large quantities of chips or wafers. Conventional test machines also have limited resource precision, making it difficult to meet the most basic testing requirements for high-speed signals. The method in this embodiment only requires adding a dedicated high-speed processing module to the test machine to achieve high-speed signal testing at different rates. The testing cost is far lower than existing test machines capable of high-end high-speed signal testing, and it can meet the high-speed signal testing needs of low-end, mid-range, and high-end devices.

[0088] The test method in this embodiment also supports DC information testing, as described in the attached manual. Figure 2 As shown, the details are as follows:

[0089] 121. The server sends a second test command regarding DC information testing to the preset industrial control computer;

[0090] 122. The industrial control computer distributes the second test command to one or more ATE devices; the industrial control computer can establish a communication connection with one or more ATE devices, and each ATE device can perform the test of the module under test.

[0091] 123. The ATE equipment parses the second test command to obtain DC test resources, and controls the preset resource switching control unit to transfer the DC test resources to the resource unit. The resource unit has a preset DC information channel for DC information testing.

[0092] 124. In the resource unit, switch to the DC information channel to transfer the DC test resources to the module under test and perform DC information testing.

[0093] After completing the DC information test and high-speed signal test, the test results need to be fed back to the server, as shown in the instruction manual. Figure 3 As shown, the details are as follows:

[0094] 131. Detect the test results of the module under test in DC information testing to obtain DC information test data;

[0095] 132. Upload the DC information test data to the ATE equipment, and the ATE equipment uploads the DC information test data to the server through the industrial control computer;

[0096] 133. Detect the test results of the module under test in the first high-speed signal test and the second high-speed test, and obtain the first high-speed signal test data and the second high-speed signal test data respectively;

[0097] 134. Upload the first high-speed signal test data and the second high-speed signal test data to the server through the first test module;

[0098] 135. The server integrates the first high-speed signal test data, the second high-speed signal test data, and the DC information test results to determine whether the module under test has a fault and the cause of the fault. Preferably, after information integration, the module under test is classified, including categories such as OS abnormality, voltage abnormality, and current abnormality. After classification, the abnormal chips or wafers under each category can be obtained.

[0099] As per the instruction manual Figure 4 As shown, DC information testing requires sequentially passing through a server, industrial control computer, ATE equipment, resource switching control unit, resource unit, and the module under test. This embodiment's testing method, based on high-speed signal testing, utilizes existing hardware to extend DC information testing, simultaneously achieving both high-speed signal testing and DC information testing, thus fully utilizing the testing machine's resources.

[0100] In this embodiment, the module under test includes at least one chip, at least one wafer, or at least one die; high-speed signal testing can realize parallel testing of multiple chips, multiple wafers, or multiple dies; DC information testing can realize parallel testing of multiple chips, multiple wafers, or multiple dies. Parallel testing of multiple chips, multiple wafers, or multiple dies is suitable for batch testing and has a high effective resource reuse rate, further reducing the overall testing cost. Assuming that an onboard resource module can control a maximum of N chips for parallel testing, the maximum number of parallel tests supported by the resource switching control unit, resource unit, first test module, and first switching control unit is also N. Preferably, this is to match the number of chips or wafers tested by the first test module. That is, the onboard resource module and the high-speed signal processing module are the same in terms of the number of chips, wafers, and dies tested in parallel. Since the high-speed signal processing module can control a maximum of N chips for parallel testing, the maximum number of parallel tests supported by the second test module and the second switching control unit is also N.

[0101] Preferably, the DC information test and the high-speed signal test of the first test module cannot be performed simultaneously, but the DC information test and the high-speed signal test of the second test module can be performed simultaneously. (See attached specification) Figure 4 As shown, the first test module requires the use of resource units on the onboard resource module when performing high-speed signal testing, and DC information testing also requires the use of resource units. The resource units have preset channels for high-speed signal testing and channels for DC information testing, and these two channels cannot be activated simultaneously. When high-speed signal testing is required, the resource unit switches to the channel transmission control resources for high-speed signal testing, at which point DC information testing cannot be performed. Similarly, when DC information testing is performed, the resource unit switches to the channel transmission control resources for DC information testing, at which point high-speed signal testing of the first test module cannot be performed, but high-speed signal testing of the second test module can be performed. Therefore, the solution in this embodiment can ensure that DC information testing and high-speed signal testing can be performed simultaneously, greatly improving testing efficiency.

[0102] In one specific embodiment, since the high-speed signal processing module is independent of the test machine, multiple high-speed signal processing modules can be added to expand the test station. Each high-speed signal processing module can be used to implement different test items.

[0103] Preferably, the resource switching control unit can control the connection of resources to resource units. Resources include DPS (Device Power Supply Unit), BPMU (Board Precision Measurement Unit), CBIT (Control Bit), etc. High-speed signal testing and DC information testing can only be performed with the assistance of resources.

[0104] This embodiment provides a testing method based on high-speed signal testing, capable of simultaneously performing high-speed signal testing and DC information testing. It boasts low testing cost, high resource utilization, and high testing efficiency. By incorporating a dedicated high-speed processing module into the testing machine, high-speed signal testing at different rates can be achieved, meeting the high-speed signal testing needs of low-end, mid-range, and high-end devices. Building upon high-speed signal testing, DC information testing is extended using existing hardware, enabling simultaneous high-speed signal testing and DC information testing, thus fully utilizing the testing machine's resources.

[0105] Example 2

[0106] Embodiment 2 of the present invention discloses a testing device based on high-speed signal testing, used to implement the testing method based on high-speed signal testing in Embodiment 1. The specific structure of the testing device is shown in the appendix to the specification. Figure 4 As shown, the specific solution is as follows:

[0107] A test apparatus based on high-speed signal testing, comprising:

[0108] Server 1 is used to issue a first test command for high-speed signal testing to a preset first test module 21 and / or a preset second test module 31, and to issue a second test command for DC information testing to an industrial control computer 4; it receives feedback DC information test data and high-speed information test data, integrates the first high-speed signal test data, the second high-speed signal test data, and the DC information test results, and analyzes to determine whether the module under test 6 has a fault and the cause of the fault. Preferably, after information integration, the module under test 6 is classified, and the classification categories include OS abnormality, voltage abnormality, current abnormality, etc. After classification, the abnormal chips or wafers under each category can be obtained.

[0109] The first test module 21 has pre-stored control resources for high-speed signal testing. It is used to receive the first test command, generate a first channel command carrying the first control resources and the first channel information based on the first test command, and issue the first channel command.

[0110] The first switching control unit 22 is used to switch the corresponding channel according to the first channel information so as to transmit the first control resource to the preset resource unit 23 through the channel; in addition, there will be other communication data transmission between the first test module 21, the server 1, and the first switching control unit 22.

[0111] Resource unit 23 is pre-configured with a high-speed signal channel for high-speed signal testing, used to switch to the high-speed signal channel to transfer the first control resource to the module under test 6 for high-speed signal testing of the first test module 21;

[0112] The second test module 31 has pre-stored control resources for high-speed signal testing, which is used to generate a second channel instruction carrying the second control resources and the second channel information based on the first test instruction, and to issue the second channel instruction.

[0113] The second switching control unit 32 is used to switch the corresponding channel according to the second channel information, so as to transmit the second control resources to the module under test 6 through the channel to perform high-speed signal testing on the second test module 31.

[0114] The industrial control computer 4 is used to receive the second test command and distribute it to one or more ATE devices 5. After acquiring the DC information test data of the module under test 6, it is also responsible for uploading the DC information test data to the server 1. The industrial control computer 4 can realize communication between the server 1 and one or more ATE devices 5.

[0115] ATE device 5 is used to parse the second test command to obtain DC test resources and control the transmission of DC test resources; it is also responsible for acquiring the DC information test data of the module under test 6 (the test result of the module under test 6 after the DC information test) and reporting it to the industrial control computer 4.

[0116] Resource switching control unit 24 is connected to ATE device 5 and is used to transmit DC test resources to resource unit 23 under the control of ATE device 5.

[0117] Resource unit 23 is pre-configured with a DC information channel for DC information testing, which is used to switch to the DC information channel to transfer DC test resources to the module under test 6 for DC information testing.

[0118] Among them, the resource switching control unit 24, resource unit 23, first test module 21 and first switching control unit 22 are integrated into the preset onboard resource module 2, and the onboard resource module 2 is connected to the service board in the ATE equipment 5; the second test module 31 and the second switching control unit 32 are integrated into the high-speed signal processing module 3; the test device can perform parallel tests on multiple chips, multiple wafers or multiple dies; the onboard resource module 2 and the high-speed signal processing module 3 are the same in terms of the number of chips, wafers and dies tested in parallel.

[0119] This embodiment discloses a test device based on high-speed signal testing, which systematizes the test method of Embodiment 1 and makes it more practical.

[0120] This invention proposes a testing method and apparatus based on high-speed signal testing, capable of simultaneously performing high-speed signal testing and DC information testing. It boasts low testing cost, high resource utilization efficiency, and high testing efficiency. By incorporating a dedicated high-speed processing module into the testing machine, high-speed signal testing at different rates can be achieved, meeting the high-speed signal testing needs of low-end, mid-range, and high-end devices. Building upon high-speed signal testing, DC information testing is extended using existing hardware, enabling simultaneous high-speed signal testing and DC information testing, thus fully utilizing the testing machine's resources.

[0121] Those skilled in the art will understand that the accompanying drawings are merely schematic diagrams of a preferred embodiment, and the modules or processes shown in the drawings are not necessarily essential for implementing the present invention. Those skilled in the art will understand that the modules in the apparatus of the embodiment can be distributed within the apparatus of the embodiment as described, or can be located in one or more apparatuses different from this embodiment, with corresponding changes. The modules of the above-described embodiment can be combined into one module, or further divided into multiple sub-modules. The above-described serial numbers are for descriptive purposes only and do not represent the superiority or inferiority of the embodiment. The above disclosures are only a few specific embodiments of the present invention; however, the present invention is not limited thereto, and any variations conceived by those skilled in the art should fall within the protection scope of the present invention.

Claims

1. A test method based on high-speed signal testing, characterized in that, This includes high-speed signal testing, which is as follows: The preset server sends a first test command for high-speed signal testing to the preset first test module and / or the preset second test module; The first test module generates a first channel instruction carrying the first control resource and the first channel information based on the first test instruction, and sends the first channel instruction to the preset first switching control unit; The first switching control unit switches the corresponding channel according to the first channel information, so as to transmit the first control resource to the preset resource unit through the channel. The resource unit is preset with a high-speed signal channel related to the high-speed signal test. In the resource unit, the first control resource is transferred to the module under test by switching to the high-speed signal channel to perform the first high-speed signal test; The second test module generates a second channel instruction carrying the second control resource and the second channel information based on the first test instruction, and sends the second channel instruction to the preset second switching control unit; The second switching control unit switches the corresponding channel according to the second channel information, so as to transmit the second control resource to the module under test through the channel for the second high-speed signal test; It also includes DC information testing, which is as follows: The server sends a second test command regarding DC information testing to a preset industrial control computer; The industrial control computer distributes the second test command to one or more ATE devices; The ATE device parses the second test command to obtain DC test resources, and controls the preset resource switching control unit to transfer the DC test resources to the resource unit. The resource unit has a preset DC information channel for the DC information test. In the resource unit, the DC information channel is switched to transfer the DC test resources to the module under test for DC information testing.

2. The test method according to claim 1, characterized in that, The test results of the module under test in the DC information test are detected to obtain DC information test data; The DC information test data is uploaded to the ATE device, and the ATE device uploads the DC information test data to the server through the industrial control computer; The test results of the module under test in the first high-speed signal test and the second high-speed test are detected to obtain the first high-speed signal test data and the second high-speed signal test data, respectively. The first high-speed signal test data and the second high-speed signal test data are uploaded to the server through the first test module; The server integrates the first high-speed signal test data, the second high-speed signal test data, and the DC information test data to determine whether the module under test has a fault and the cause of the fault.

3. The test method according to claim 1, characterized in that, In terms of high-speed signal testing rate, the first test module is smaller than the second test module; The first test module supports remote deployment of high-speed signals; The second test module supports near-end placement of high-speed signals.

4. The test method according to claim 3, characterized in that, The first test module has a high-speed signal testing rate of no more than 1.5Gbps to enable remote low-to-mid-range high-speed signal testing. The second test module has a high-speed signal testing rate of over 1.5Gbps to enable near-end mid-to-high-end high-speed signal testing.

5. The test method according to claim 1, characterized in that, The module under test includes at least one chip, at least one wafer, or at least one die; The high-speed signal testing can achieve parallel testing of multiple chips, multiple wafers, or multiple dies; The DC information test can realize parallel testing of multiple chips, multiple wafers or multiple dies.

6. The test method according to claim 1, characterized in that, The first test module, the first switching control unit, the resource unit, and the resource switching control unit are integrated into an onboard resource module, which is connected to the service board in the ATE equipment. The second test module and the second switching control unit are integrated into the high-speed signal processing module; The onboard resource module is the same as the high-speed signal processing module in terms of the number of chips, wafers, and dies used in parallel testing.

7. A testing device based on high-speed signal testing, characterized in that, Including the following: The server is used to send the first test command for high-speed signal testing to the preset first test module and / or the preset second test module. The first test module is used to receive the first test instruction, generate a first channel instruction carrying the first control resource and the first channel information based on the first test instruction, and send the first channel instruction. The first switching control unit is used to switch the corresponding channel according to the first channel information so as to transmit the first control resource to the preset resource unit through the channel; The resource unit is pre-configured with a high-speed signal channel for the high-speed signal test, which is used to switch to the high-speed signal channel to transfer the first control resource to the module under test for the first high-speed signal test. The second test module is used to generate a second channel instruction carrying second control resources and second channel information based on the first test instruction, and to issue the second channel instruction. The second switching control unit is used to switch the corresponding channel according to the second channel information, so as to transmit the second control resource to the module under test through the channel for the second high-speed signal test; The server is also used to issue a second test command regarding DC information testing; The testing apparatus also includes: An industrial control computer is used to receive the second test command and distribute the second test command to one or more ATE devices; ATE equipment is used to parse the second test command to obtain DC test resources and control the transmission of the DC test resources; A resource switching control unit, connected to the ATE equipment, is used to transmit the DC test resources to the resource unit under the control of the ATE equipment. The resource unit is pre-configured with a DC information channel for the DC information test, which is used to switch to the DC information channel to transfer the DC test resources to the module under test for DC information testing.

8. The testing apparatus according to claim 7, characterized in that, The resource switching control unit, the resource unit, the first test module, and the first switching control unit are integrated into a preset onboard resource module, and the onboard resource module is connected to the service board in the ATE equipment. The second test module and the second switching control unit are integrated into the high-speed signal processing module; The testing device can perform parallel testing on multiple chips, multiple wafers, or multiple dies. The onboard resource module is the same as the high-speed signal processing module in terms of the number of chips, wafers, and dies used in parallel testing.

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