Address conversion method, electronic device and electronic equipment

Abstract

An address translation method, an electronic device, and an electronic equipment. The address translation method includes: obtaining a target address to be translated; generating a page table reading request using the target address and sending the page table reading request through a first interconnection; enabling a page table query unit to receive the page table reading request sent through the first interconnection, and querying at least one-level page table from a storage device step by step according to the page table reading request to obtain a first address corresponding to the target address; enabling the page table query unit to return the queried first address through the first interconnection. In this address translation method, the page table query unit reads the page table from the storage device without passing through a bus or an on-chip interconnection, or reads the page table from the storage device through fewer buses or on-chip interconnections, thereby reducing the latency of the bus or on-chip interconnection for reading the page table from the storage device and improving the efficiency of address translation.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to an address conversion method, an electronic device, and an electronic equipment. Background Art

[0002] In the field of computer technology, programmers can write programs using any virtual address (VA) within the range specified by the system instead of the physical address. The address used by the central processing unit (CPU) when executing an application program is a virtual address. Usually, different processes running in the system are assigned different virtual address spaces, and the virtual address space of each process covers a relatively large range. For example, when allocating memory to a process or the process accessing memory, it is necessary to map the virtual address to the physical address (PA), and the physical address is the real physical memory access address. Distinguishing between virtual addresses and physical addresses for use has become the mainstream trend in the industry. Summary of the Invention

[0003] At least one embodiment of the present disclosure provides an address conversion method, including: obtaining a target address to be converted; generating a page table reading request using the target address and sending the page table reading request through a first interconnection; enabling a page table query unit to receive the page table reading request sent through the first interconnection, and querying at least one-level page table from a storage device step by step according to the page table reading request to obtain a first address corresponding to the target address; enabling the page table query unit to return the queried first address through the first interconnection.

[0004] For example, in the address conversion method provided by at least one embodiment of the present disclosure, generating the page table reading request using the target address is performed when the first address corresponding to the target address is not cached in the storage management unit that performs address conversion.

[0005] For example, in the address conversion method provided by at least one embodiment of the present disclosure, the first interconnection includes a first interconnection unit, sending the page table reading request through the first interconnection unit, and receiving the page table reading request sent through the first interconnection unit.

[0006] For example, in the address conversion method provided by at least one embodiment of the present disclosure, the first interconnection unit includes a bus or an on-chip interconnection.

[0007] For example, in the address conversion method provided in at least one embodiment of the present disclosure, the first interconnection also includes a second interconnection unit and a third interconnection unit, and the first interconnection unit communicates with the third interconnection unit via the second interconnection unit; the read page table request is issued via the first interconnection unit, the second interconnection unit and the third interconnection unit in sequence.

[0008] For example, in the address conversion method provided by at least one embodiment of the present disclosure, the page table read request is received sequentially issued by the third interconnection unit, the second interconnection unit, and the first interconnection unit.

[0009] For example, in the address conversion method provided in at least one embodiment of the present disclosure, the second interconnect unit includes an inter-chip connection, and the third interconnect unit includes a bus or an on-chip interconnect.

[0010] For example, in the address conversion method provided in at least one embodiment of the present disclosure, the step-by-step query of at least one level of page table to obtain the first address corresponding to the target address and the use of the target address to generate the read page table request are performed in different chips respectively.

[0011] For example, in the address conversion method provided in at least one embodiment of the present disclosure, the target address is a virtual address and the first address is a physical address; or, the target address is a virtual address and the first address is an intermediate physical address; or, the target address is an intermediate physical address and the first address is a physical address.

[0012] At least one embodiment of the present disclosure also provides an electronic device, comprising: a first interconnect; a storage management unit, coupled to the first interconnect, and configured to: obtain a target address, generate a read page table request using the target address, and issue the read page table request via the first interconnect; a page table query unit, coupled to the first interconnect, and configured to: receive the read page table request issued via the first interconnect, query at least one level of page table from a storage device level by level according to the read page table request to obtain a first address corresponding to the target address, and return the queried first address to the storage management unit via the first interconnect.

[0013] For example, in the electronic device provided by at least one embodiment of the present disclosure, the storage management unit is a system storage management unit.

[0014] For example, in the electronic device provided by at least one embodiment of the present disclosure, the page table query unit corresponds to a plurality of different storage management units.

[0015] For example, in the electronic device provided by at least one embodiment of the present disclosure, the storage management unit and the page table query unit are respectively located in different wafers, and the first interconnect includes an inter-wafer connection.

[0016] At least one embodiment of the present disclosure further provides an electronic device, which includes the electronic device provided by any embodiment of the present disclosure, and the electronic device further includes the storage device, wherein the storage device is configured to store a multi-level page table.

[0017] For example, in the electronic device provided by at least one embodiment of the present disclosure, the page table query unit is further configured to directly access the storage device or be coupled to the storage device through another interconnect, wherein the another interconnect is different from the first interconnect.

[0018] For example, in the electronic device provided by at least one embodiment of the present disclosure, for the case where the page table query unit directly accesses the storage device, the storage device includes a storage controller, the storage controller includes the page table query unit, or the storage device includes a cache, and the cache includes the page table query unit.

[0019] For example, in the electronic device provided by at least one embodiment of the present disclosure, the storage device is a double data rate synchronous dynamic random access memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure and do not limit the present disclosure.

[0021] Figure 1 It is a working principle diagram of a system storage management unit;

[0022] Figure 2 It is a schematic flowchart of an address conversion method provided by at least one embodiment of the present disclosure;

[0023] Figure 3 It is for Figure 2 a schematic diagram of an example of steps S10 to S30 in

[0024] Figure 4 It is for Figure 2 a schematic diagram of an example of step S40 in

[0025] Figure 5 It is for Figure 2 a schematic diagram of an example of steps S10 to S40 in

[0026] Figure 6 It is for Figure 2Schematic diagram of another example of steps S10 to S40;

[0027] Figure 7 Schematic block diagram of an electronic device provided by at least one embodiment of the present disclosure;

[0028] Figure 8 Schematic block diagram of an electronic device provided by at least one embodiment of the present disclosure;

[0029] Figure 9 Schematic block diagram of another electronic device provided by at least one embodiment of the present disclosure; and

[0030] Figure 10 Schematic block diagram of yet another electronic device provided by at least one embodiment of the present disclosure. Detailed implementation manners

[0031] To make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are some but not all of the embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present disclosure without creative efforts shall fall within the scope of protection of the present disclosure.

[0032] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure shall have the ordinary meanings understood by those of ordinary skill in the art to which the present disclosure pertains. The "first", "second" and similar terms used in the present disclosure do not denote any order, quantity or importance, but are only used to distinguish different components. Similarly, the terms such as "a", "an" or "the" do not denote a quantity limitation, but mean that there is at least one. The terms such as "including" or "comprising" mean that the elements or items appearing before this term cover the elements or items listed after this term and their equivalents, without excluding other elements or items. The terms such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms such as "upper", "lower", "left" and "right" are only used to represent relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0033] The present disclosure will be described below through several specific embodiments. To keep the following description of the embodiments of the present disclosure clear and concise, the detailed descriptions of known functions and known components may be omitted. When any component of the embodiments of the present disclosure appears in more than one drawing, the component is denoted by the same or similar reference numeral in each drawing.

[0034] The Memory Management Unit (MMU) is located between the execution unit (such as the CPU or the processor core of the CPU) and the memory in a computer system, providing the conversion from virtual addresses to physical addresses. The process from virtual addresses to physical addresses is called address translation (or mapping). For example, the data / instruction addresses behind the execution of a user program are all virtual addresses. The virtual addresses are issued by the execution unit, intercepted by the MMU, and converted into physical addresses. The MMU may also have other functions such as memory attribute conversion and permission checking.

[0035] The System Memory Management Unit (SMMU) is widely used in various System on Chip (SoC). It is located between I / O peripherals and, for example, a bus. As a memory management unit, it is also mainly used for the conversion from virtual addresses to physical addresses for peripherals, that is, converting virtual addresses into corresponding physical addresses.

[0036] The conversion rules (mapping rules) from virtual addresses to physical addresses are stored in the page table, and the page table is stored in the storage device of the system. The MMU (such as the SMMU) includes a Page Walker Unit (PWU) and a Translation Lookaside Buffer (TLB). To achieve the conversion from a virtual address to a physical address, first the MMU checks the TLB to see if the corresponding physical address is already cached. If there is a hit in the TLB, the conversion work is directly completed. If there is a miss in the TLB, then the MMU needs to use the virtual address through the PWU to query the page table for conversion in the system's storage device (such as Double Data Rate Synchronous Dynamic Random Access Memory (DDR)) once or multiple times, and finally obtain the physical address corresponding to the virtual address, thereby enabling the access operation to the physical address.

[0037] Figure 1 It is a schematic diagram of the working principle of a system memory management unit. As Figure 1 shown, a pre-designed circuit function module applied to an Application Specific Integrated Circuit (ASIC) or a Field Programmable Gate Array (FPGA) is called an Intellectual Property Core (IP core), or also simply called IP. The IP can be any logic module or function module used in an ASIC or an FPGA, such as a filter, a memory controller, an interface program, etc. In this disclosure, the IP core is used to refer to the circuit function module, and the specific functions, structures, etc. of the circuit function module are not limited in the embodiments of this disclosure.

[0038] For example, as Figure 1 shown, taking the SMMU as an example, when the IP needs to perform read / write access, for example, it first issues the virtual address VA to be accessed. After receiving the virtual address VA, the SMMU needs to perform a conversion from the virtual address to the physical address. To perform this conversion, the SMMU needs to use the high-order field (usually called the index part) corresponding to the page table in the virtual address VA to read the page table in the DDR. After reading back the content of the page table, the SMMU combines the content of the page table with the low-order field (usually called the offset part) corresponding to the offset address in the virtual address VA, converts the virtual address VA to the physical address PA and outputs it, and then continues the subsequent access operation based on this physical address.

[0039] The behavior of the SMMU to read the page table in the DDR is simply referred to as PTW (Page Table Walking). To achieve a single conversion from the virtual address VA to the physical address PA, in the case where the operating system uses a multi-level page table, the SMMU needs to perform multiple PTW operations. For example, Figure 1 taking the common address width as 48 bits (bit), the page granularity as 4KB, and there are 4 levels of page tables (from the 0th level page table to the 3rd level page table) as an example for illustration. In this example, the high 36 bits in the virtual address are the index part, and the low 12 bits are the offset part. The index part consists of 4 fields composed of 9 bits, corresponding to the 0th level to the 3rd level page tables in order from high to low. After receiving the virtual address VA sent by the IP, the SMMU obtains the index part in the virtual address VA. Based on the fields corresponding to the 0th level to the 3rd level page tables, the SMMU needs to perform 4 PTW operations in sequence (for example, named PTW0, PTW1, PTW2, and PTW3 respectively). For example, when the SMMU performs PTW, it sends the page table read request and the corresponding address fields to the Network-on-chip (NoC, as an example of on-chip interconnection). The NoC then sends the page table read request to the DDR, and then accesses the corresponding page table (one of the 0th level to the 3rd level page tables) in the DDR according to the page table read request, and retrieves the page table content read from the page table from the DDR.

[0040] For example, as Figure 1As shown, PTW0 accesses the level-0 page table using the corresponding level-0 field according to the starting physical address of the multi-level page table recorded in, for example, the page table base address register. The page table content retrieved from the level-0 page table is the storage address Addr0 of the level-1 page table that PTW1 is to access in the DDR; PTW1 accesses the level-1 page table using the corresponding level-1 field, and the page table content retrieved from the level-1 page table is the storage address Addr1 of the level-2 page table that PTW2 is to access in the DDR; PTW2 accesses the level-2 page table using the corresponding level-2 field, and the page table content retrieved from the level-2 page table is the storage address Addr2 of the level-3 page table that PTW3 is to access in the DDR; PTW3 accesses the level-3 page table using the corresponding level-3 field, and the page table content retrieved from the level-3 page table is the storage address (e.g., physical address) of the target page. The physical address PA corresponding to the virtual address VA can be obtained by adding the offset part in the virtual address VA to the storage address of the target page.

[0041] Therefore, in order to perform address translation to obtain the physical address PA from the virtual address VA, it is necessary to first perform and complete PTW0, PTW1, PTW2, and PTW3 according to the index part in the virtual address VA. Each time the SMMU performs a PTW, it has to go through the NoC and access the DDR, so it needs to experience the delay on the NoC and the delay in accessing the DDR. For example, the delay on the NoC is represented by "noc_delay", and the delay in accessing the DDR is represented by "ddr_delay". For the Figure 1 scheme shown, if the SMMU completes one conversion from the virtual address VA to the physical address PA and requires 4 PTWs, the total delay Delay0 required can be calculated at least as follows:

[0042] Delay0 = 4 * noc_delay + 4 * ddr_delay Formula (1)

[0043] Since in a computer system, most of the communication processes between various functional circuit modules have to go through the bus or on-chip interconnect (such as the NoC), the bus or on-chip interconnect is very busy and there are a large number of resource competition situations. Therefore, the delay generated by the SMMU each time it performs a PTW on the bus or on-chip interconnect is relatively large. It can be seen from this that each time the SMMU reads the page table from the storage device, it takes a lot of time, resulting in a long time for the conversion from the virtual address to the physical address, thus reducing the efficiency and performance of the SoC.

[0044] At least one embodiment of the present disclosure provides an address translation method, which includes: obtaining a target address to be translated; generating a page table read request using the target address and sending the page table read request through a first interconnect; enabling a page table query unit to receive the page table read request sent through the first interconnect, and querying at least one-level page table from a storage device step by step according to the page table read request to obtain a first address corresponding to the target address; enabling the page table query unit to return the queried first address through the first interconnect.

[0045] At least one embodiment of the present disclosure further provides an electronic device corresponding to executing the above address translation method.

[0046] At least one embodiment of the present disclosure further provides an electronic equipment corresponding to the above electronic device.

[0047] The address translation method, electronic device, and electronic equipment provided by at least one embodiment of the present disclosure, during the process of address translation, enable the page table query unit to read the page table from the storage device without passing through the bus or on-chip interconnect, or read the page table from the storage device through fewer buses or on-chip interconnects, thereby reducing the latency of the bus or on-chip interconnect for reading the page table from the storage device, improving the efficiency of address translation, and improving the efficiency and performance of, for example, a SoC.

[0048] Hereinafter, at least one embodiment of the present disclosure will be described in detail with reference to the accompanying drawings. It should be noted that the same reference numerals in different drawings will be used to refer to the same elements that have been described.

[0049] Figure 2 It is a schematic flowchart of an address translation method provided by at least one embodiment of the present disclosure.

[0050] For example, as Figure 2 shown, at least one embodiment of the present disclosure provides an address translation method for performing address translation in a computer system, for example, converting a virtual address into a physical address, whereby the obtained physical address can be used to access the target address, and the target address can point to, for example, a storage address in a storage device, and can point to a certain functional circuit module within the computer system, such as a direct memory access (DMA) unit, a PCIE device, etc. For example, the computer system includes at least one memory management unit (MMU) (such as an SMMU) and a page table access unit (PWU) independently arranged from the MMU. For example, the page table access unit is coupled and communicates with the memory management unit through an interconnect, rather than being a part of the MMU or directly coupled and communicating with the MMU, so the page table access unit is not arranged inside the memory management unit. The above address translation method can be executed by the memory management unit and the page table access unit. As Figure 2 shown, the address translation method includes the following steps S10 to S40.

[0051] Step S10: Obtain a target address to be converted;

[0052] Step S20: Generate a page table read request using the target address and send the page table read request via a first interconnect;

[0053] Step S30: Enable a page table query unit to receive the page table read request sent via the first interconnect and query at least one level of page tables from a storage device step by step according to the page table read request to obtain a first address corresponding to the target address;

[0054] Step S40: Enable the page table query unit to return the obtained first address via the first interconnect.

[0055] For example, a storage management unit is generally used in a system to perform the conversion from the target address to the first address in the above steps S10 to S40, and further uses a PWU to perform this conversion operation in this process. For example, the storage management unit may be an SMMU, and this storage management unit may further include a TLB, for example; in other embodiments, the storage management unit may also be other electronic components capable of implementing an address conversion function, and the embodiments of the present disclosure do not limit this.

[0056] For example, the target address is a virtual address to be converted, and the first address is a physical address; or, the target address is a virtual address to be converted, and the first address is an intermediate physical address (IPA); or, the target address is an intermediate physical address to be converted, and the first address is a physical address.

[0057] For example, the intermediate physical address PA is a concept introduced after computer virtualization. For a computer system that supports virtualization, each virtual machine system (guest OS) cannot directly map a virtual address VA to the physical address PA of the entire system, but maps it to a restricted physical address space. Therefore, in a computer system that supports virtualization, the virtual machine system (guest OS) is responsible for mapping the virtual address VA to the intermediate physical address PA, while the virtual machine monitor (Hypervisor) is responsible for mapping the intermediate physical address PA to a specific physical address PA. The address conversion operations are involved in both the conversion from the virtual address VA to the intermediate physical address PA and the conversion from the intermediate physical address PA to the physical address PA, and both can be performed by the address conversion method of at least one embodiment of the present disclosure.

[0058] For example, the generation of a read page table request using the target address is performed when the first address corresponding to the target address is not cached in the TLB of the memory management unit that performs address translation. For example, when the memory management unit performs the conversion of the target address to the first address, if the first address corresponding to the target address is cached in the TLB of the memory management unit, the memory management unit does not generate a read page table request, but directly completes the conversion of the target address to the first address inside the TLB of the memory management unit; if the first address corresponding to the target address is not cached in the TLB of the memory management unit, the memory management unit generates a read page table request and performs the address conversion in steps S10 to S40, for example.

[0059] For example, in at least one embodiment, the computer system may include multiple memory management units and at least one page table query unit independent of these memory management units. For example, each page table query unit may be used for a corresponding one of the memory management units or for a corresponding multiple different memory management units, that is, multiple memory management units may share, for example, one page table query unit.

[0060] For example, in at least one embodiment, the memory management unit and the page table query unit may be located in the same die, and the two are coupled and communicate with each other through on-chip interconnection; in at least one embodiment, the memory management unit and the page table query unit may also be located in different dies respectively, and the first interconnection for coupling and communicating between the memory management unit and the page table query unit includes die-to-die connection (D2D).

[0061] Figure 3 For Figure 2 a schematic diagram of an example of steps S10 to S30 in Figure 4 For Figure 2 a schematic diagram of an example of step S40 in

[0062] For example, as Figure 3As shown, in step S10, the storage management unit 110 obtains an access request for the target address 101 issued by the IP or processor (IP / CPU) 300, thereby generating an address translation request for the target address. In step S20, the storage management unit 110 generates a read page table request 102 using the target address 101. Taking the system using an n-level page table as an example, that is, taking the storage management unit 110 needing to perform n read page table operations in the storage device 200 as an example, the read page table request 102 includes PTW0, PTW1,..., PTWn-1; the storage management unit 110 sends the read page table request 102 to the remote page table query unit 130 via the first interconnect 120. In step S30, the page table query unit 130 receives the read page table request 102 from the storage management unit 110 via the first interconnect 120, and queries at least one level of page table (i.e., n is greater than or equal to 1, for example, n equals 3 or 4) from the storage device 200 step by step according to the read page table request 102 to obtain the first address corresponding to the target address 101. For example, in the case where the target address is a virtual address, the first address may be a physical address or an intermediate physical address.

[0063] For example, as Figure 3 shown, the process by which the page table query unit 130 queries at least one level of page table from the storage device 200 step by step to obtain the first address corresponding to the target address 101 is as follows: PTW0 uses the corresponding 0th-level field to access the 0th-level page table according to the starting physical address of the multi-level page table recorded in, for example, the page table base address register, and the page table content retrieved from the 0th-level page table is the storage address Addr0 of the 1st-level page table that PTW1 is to access in the DDR; PTW1 uses the corresponding 1st-level field to access the 1st-level page table, and the page table content retrieved from the 1st-level page table is the storage address Addr1 of the 2nd-level page table that PTW2 is to access in the DDR; PTW2 uses the corresponding 2nd-level field to access the 2nd-level page table, and the page table content retrieved from the 2nd-level page table is the storage address Addr2 of the 3rd-level page table that PTW3 is to access in the DDR;...; PTWn-1 uses the corresponding (n-1)th-level field to access the (n-1)th-level page table, and the page table content retrieved from the (n-1)th-level page table is the storage address of the target page table, and adding the offset part in the virtual address VA to the storage address of the target page table can obtain the first address corresponding to the target address.

[0064] For example, as Figure 4 shown, in step S40, the page table query unit 130 returns the result (here it is the first address) of the queried multi-level page table 103 (Addr0 / Addr1 / ... / Addr n-2 / first address) to the storage management unit 110 at one time via the first interconnect 120; the storage management unit 110 outputs the obtained first address 1031 for subsequent operations (such as accessing the storage device or peripherals), thus completingFigure 3 Conversion of the target address 101 to the first address 1031 in

[0065] For example, the target address 101 is a virtual address VA, and the first address 1031 is a physical address PA; or, the target address 101 is a virtual address VA, and the first address 1031 is an intermediate physical address IPA; or, the target address 101 is an intermediate physical address IPA, and the first address 1031 is a physical address PA.

[0066] For example, the storage management unit 110 generates a read page table request 102 (PTW0, PTW1,..., PTWn-1) using the target address 101 when the first address 1031 corresponding to the target address 101 is not cached in the storage management unit 110 (e.g., in the TLB) that performs the address conversion. For example, when the storage management unit 110 performs the conversion of the target address 101 to the first address 1031, if the first address 1031 corresponding to the target address 101 is already cached in the storage management unit 110 (e.g., in the TLB), the storage management unit 110 does not generate a read page table request 102, but directly completes the conversion of the target address 101 to the first address 1031 inside the storage management unit 110; if the first address 1031 corresponding to the target address 101 is not cached in the storage management unit 110, the storage management unit 110 generates a read page table request 102 and performs the address conversion in, for example, steps S10 to S40.

[0067] For example, as Figure 3 and Figure 4 shown, in the address conversion method provided in at least one embodiment of the present disclosure, as long as the storage management unit 110 issues a read page table request 102 once, it can directly query the multi-level page table 103 from the storage device 200 through the page table query unit 130, so as to obtain the first address 1031. For example, the delay on the first interconnect 120 is represented by "noc_delay", and the delay for accessing the storage device 200 is represented by "ddr_delay". If the storage management unit 110 needs n PTWs to complete the conversion of the target address 101 to the first address 1031, the total delay Delay1 required can be expressed as:

[0068] Delay1 = 1 * noc_delay + n * ddr_delay Formula (2)

[0069] Comparing Formula (2) with Formula (1), taking n = 4 as an example, compared with the Figure 1 scheme in, Delay1 is reduced by 3 times the delay (3 * noc_delay) for the first interconnect 120 to read the page table from the storage device 200 compared to Delay0.

[0070] It can be seen therefrom that the page table query unit 130 can directly read the page table from the storage device 200 without passing through the first interconnect 120, for example, to obtain the first address 1031, thereby reducing the latency of the first interconnect 120 reading the page table from the storage device 200, improving the conversion efficiency from the target address 101 to the first address 1031, and enhancing the efficiency and performance of, for example, the SoC.

[0071] In another example of the above embodiment, the storage management unit itself may include, for example, a level 0 page table and the storage management unit itself also has (at least partially) a page table query function. Then, for the initial read page table request generated based on the target address, the storage management unit can directly execute PTW0 locally (i.e., within the storage management unit), and then use the storage address Addr0 of the level 1 page table obtained by querying the level 0 page table, the target address (or the remaining address part of the target address except the field corresponding to the level 0 page table), etc. to obtain a further read page table request. The further read page table request is sent to the page table query unit independent of the storage management unit for subsequent page table query operations to obtain the first address corresponding to the target address, and the first address is returned to the storage management unit. This example can also reduce the latency caused by the first interconnect operation during the page table query process, thereby improving the efficiency and performance of, for example, the SoC.

[0072] Figure 5 For Figure 2 a schematic diagram of an example of steps S10 to S40; Figure 6 For Figure 2 a schematic diagram of another example of steps S10 to S40.

[0073] For example, the operation of "generating a read page table request using the target address" in step S20 and the operation of "querying at least one level of page table step by step to obtain the first address corresponding to the target address" in step S30 can be executed in one die, or separately in different dies. For example, Figure 5 shows the case where the above two operations are executed in one die. At this time, the storage management unit 110 and the page table query unit 130 are located in the same die, and the two are coupled and communicate with each other through the first interconnect; for example, Figure 6 shows the case where the above two operations are executed separately in different dies. At this time, the storage management unit 110 and the page table query unit 130 are located in different dies respectively, and the two are coupled and communicate with each other through the first interconnect and other interconnects.

[0074] For example, as Figure 5As shown, the first interconnect 120 includes a first interconnect unit 121 . The storage management unit 110 issues a page table read request 102 via the first interconnect unit 121 , and the page table query unit 130 receives the page table read request 102 issued via the first interconnect unit 121 .

[0075] For example, Figure 5 As shown, in step S10, the storage management unit 110 obtains the target address 101 issued by the IP / CPU 300. In step S20, the storage management unit 110 generates a read page table request 102 (PTW0, PTW1, ..., PTWn-1) using the target address 101; the storage management unit 110 issues the read page table request 102 via the first interconnect unit 121. In step S30, the page table query unit 130 receives the read page table request 102 issued via the first interconnect unit 121, and queries at least one level of page table from the storage device 200 level by level according to the read page table request 102 to obtain a first address corresponding to the target address 101. In step S40, the page table query unit 130 returns the multi-level page table 103 (Addr0 / Addr1 / … / Addrn-2 / first address) obtained by the query to the storage management unit 110 at one time through the first interconnection unit 121; the storage management unit 110 outputs the obtained first address 1031, thereby completing the conversion from the target address 101 to the first address 1031.

[0076] For example, the first interconnection unit 121 can be a bus or an on-chip interconnection, or it can also be other electronic components that can realize the address transmission function. For example, the on-chip interconnection can be an on-chip network (NoC), and the on-chip network can be a switch network, a ring network, a tree network, a mesh network, a torus network, etc. The embodiments of the present disclosure are not limited to this.

[0077] For example, Figure 6 As shown, the first interconnect 120 further includes a second interconnect unit 122 and a third interconnect unit 123. The first interconnect unit 121 communicates with the third interconnect unit 123 via the second interconnect unit 122. For example, the storage management unit 110 sends a read page table request 102 via the first interconnect unit 121, the second interconnect unit 122, and the third interconnect unit 123 in sequence, and the page table query unit 130 receives the read page table request 102 sent via the third interconnect unit 123, the second interconnect unit 122, and the first interconnect unit 121 in sequence.

[0078] For example, Figure 6As shown, in step S10, the storage management unit 110 obtains the target address 101 sent by the IP / CPU 300. In step S20, the storage management unit 110 generates a read page table request 102 (PTW0, PTW1, ……, PTWn-1) using the target address 101; the storage management unit 110 sequentially sends the read page table request 102 through the first interconnect unit 121, the second interconnect unit 122, and the third interconnect unit 123. In step S30, the page table query unit 130 receives the read page table request 102 sequentially sent through the third interconnect unit 123, the second interconnect unit 122, and the first interconnect unit 121, and queries at least one-level page table from the storage device 200 according to the read page table request 102 to obtain the first address corresponding to the target address 101. In step S40, the page table query unit 130 returns the obtained multi-level page table 103 (Addr0 / Addr1 / …… / Addrn-2 / first address) to the storage management unit 110 at one time through the third interconnect unit 123, the second interconnect unit 122, and the first interconnect unit 121; the storage management unit 110 outputs the obtained first address 1031, thus completing the conversion of the target address 101 to the first address 1031.

[0079] For example, the third interconnect unit 123 and the first interconnect unit 121 can be a bus or an on-chip interconnect, or can also be other electronic components capable of implementing the address transmission function. For example, the on-chip interconnect can be a network-on-chip (NoC), and the network-on-chip can be a cross (Switch) network, a ring network, a tree network, a mesh network, a torus network, etc. The embodiments of the present disclosure do not limit this; the second interconnect unit 122 includes die-to-die connection (D2D), or can also be other electronic components capable of implementing the connection function between different dies. The embodiments of the present disclosure do not limit this.

[0080] Figure 7 It is a schematic block diagram of an electronic device provided by at least one embodiment of the present disclosure.

[0081] For example, as Figure 7As shown, the electronic device 100 includes a first interconnect 120, a storage management unit 110, and a page table query unit 130, and can execute an address conversion method according to any embodiment of the present disclosure. The storage management unit 110 is coupled to the first interconnect 120 and is configured to: obtain a target address 101; generate a page table read request 102 using the target address 101; and issue the page table read request 102 via the first interconnect 120. The page table query unit 130 is coupled to the first interconnect 120 and is configured to: receive the page table read request 102 issued via the first interconnect 120, query at least one level of page tables from the storage device according to the page table read request 102 to obtain a first address 1031 corresponding to the target address 102, and return the obtained multi-level page tables 103 to the storage management unit 110 via the first interconnect 120; the storage management unit 110 outputs the obtained first address 1031, thereby completing the conversion of the target address 101 to the first address 1031.

[0082] Similarly, in this embodiment, for example, the storage management unit 110 may be an SMMU, or may be other electronic components capable of implementing the address conversion function, and the embodiments of the present disclosure do not limit this. For example, the storage management unit 110 and the page table query unit 130 may be located in the same die; they may also be located in different dies respectively, and the first interconnect includes a die-to-die connection (D2D). For example, the page table query unit 130 may be used for the same storage management unit 110, or may be used for multiple different storage management units 110.

[0083] Figure 8 It is a schematic block diagram of an electronic device provided by at least one embodiment of the present disclosure.

[0084] For example, as Figure 8 shown, the electronic device 10 includes, for example, Figure 7 the electronic device 100 and a storage device 200 as shown. The storage device 200 is configured to store multi-level page tables, including the multi-level page tables 103 (Addr0 / Addr1 / …… / Addr n-2 / first address) queried by the page table query unit 130 in Figures 3 to 6 .

[0085] For example, as Figure 8 shown, the electronic device 100 obtains a target address 101, generates a page table read request 102 using the target address 101, and queries the multi-level page tables 103 from the storage device 200 according to the page table read request 102 to obtain a first address 1031 corresponding to the target address 102. The electronic device 100 outputs the obtained first address 1031, thereby completing the conversion of the target address 101 to the first address 1031.

[0086] For example, the storage device 200 may include DDR, or may be other storage devices capable of storing multi-level page tables, and the embodiments of the present disclosure do not limit this.

[0087] For example, in the electronic device 10 as Figure 8 shown, the page table query unit 130 of the electronic device 100 is further configured to directly access the storage device 200 or be coupled to the storage device 200 through another interconnect (not shown in the figure), and this another interconnect is different from the first interconnect 120.

[0088] For example, for the case where the page table query unit 130 is coupled to the storage device 200 through another interconnect, this another interconnect is different from the first interconnect 120. In this case, the process of the page table query unit 130 accessing the storage device 200 does not pass through the first interconnect 120. Therefore, the delay of the first interconnect 120 in reading the page table from the storage device 200 is reduced, and further the conversion efficiency from the target address 101 to the first address 1031 is improved.

[0089] Figure 9 Schematic block diagram of another electronic device provided by at least one embodiment of the present disclosure.

[0090] For example, as Figure 9 shown, for the case where the page table query unit 130 directly accesses the storage device 200, the page table query unit 130 may be integrated in the storage device 200. Therefore, it is possible to directly access the storage device 200 without passing through other buses or on-chip interconnections. At this time, the process of the page table query unit 130 accessing the storage device 200 also does not pass through the first interconnect 120. Therefore, the delay of the first interconnect 120 in reading the page table from the storage device 200 is reduced, and further the conversion efficiency from the target address 101 to the first address 1031 is improved.

[0091] For this case, the storage device 200 may include, for example, a memory controller (MC), and this memory controller includes the page table query unit 130, that is, the page table query unit 130 is integrated in the memory controller. The memory controller is used to manage read and write operations of the storage device, etc.; or, the storage device 200 may include, for example, a cache, and this cache includes the page table query unit 130; or, it may also be that the page table query unit 130 is integrated in other components of the storage device 200, and the embodiments of the present disclosure do not limit this.

[0092] Figure 10 Schematic block diagram of yet another electronic device provided by at least one embodiment of the present disclosure.

[0093] For example, as Figure 10As shown, the electronic device 400 is, for example, suitable for implementing the address conversion method provided by the embodiments of the present disclosure. The electronic device 400 may be a terminal device or a server, etc. It should be noted that Figure 10 The illustrated electronic device 400 is only an example, and it will not impose any limitations on the functions and usage scope of the embodiments of the present disclosure.

[0094] For example, as Figure 10 shown, the electronic device 400 may include a processing device (such as a central processing unit, a graphics processing unit, etc.) 41, which may perform various appropriate actions and processes according to the program stored in the read-only memory (ROM) 42 or the program loaded from the storage device 48 into the random access memory (RAM) 43. In the RAM 43, various programs and data required for the operation of the electronic device 400 are also stored. The processing device 41, the ROM 42, and the RAM 43 are connected to each other through a bus 44. The input / output (I / O) interface 45 is also connected to the bus 44. Generally, the following devices may be connected to the I / O interface 45: an input device 46 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 37 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 48 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 49. The communication device 49 may allow the electronic device 400 to communicate with other electronic devices wirelessly or wiredly to exchange data. Although Figure 10 the illustrated electronic device 400 has various devices, it should be understood that it is not required to implement or include all the illustrated devices, and the electronic device 400 may alternatively implement or include more or fewer devices.

[0095] For the detailed description and technical effects of the electronic device 10 / 400, reference may be made to the description of the electronic device in the foregoing text, and details are not described herein again.

[0096] Regarding the present disclosure, the following points need to be explained:

[0097] (1) In the drawings of the embodiments of the present disclosure, only the structures related to the embodiments of the present disclosure are involved, and other structures may refer to the general design.

[0098] (2) Without conflict, the features in the same embodiment and different embodiments of the present disclosure may be combined with each other.

[0099] The above are only the specific implementation manners of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of changes or substitutions, which should be covered by the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. An address translation method, comprising: causing a storage management unit to obtain a target address to be translated; causing the storage management unit to generate a page table read request using the target address and issue the page table read request via a first interconnect; causing a page table query unit to receive the page table read request issued via the first interconnect and, according to the page table read request, query at least one level of page tables in a storage device level by level to obtain a first address corresponding to the target address, wherein the page table query unit is independent of the storage management unit and is no longer part of the storage management unit, and the page table query unit communicates with the storage management unit via the first interconnect; causing the page table query unit to return the queried first address via the first interconnect; wherein the page table read request includes n sub-requests, the at least one level of page tables includes n levels of page tables, and n is an integer greater than 1; the querying at least one level of page tables in a storage device level by level according to the page table read request to obtain a first address corresponding to the target address includes: retrieving, according to the n sub-requests, n storage addresses corresponding to the n levels of page tables from the storage device, wherein the n storage addresses include the first address; wherein the address translation method further includes: causing the page table query unit to return the n storage addresses via the first interconnect at one time.

2. The method according to claim 1, wherein, Generating the page table read request using the target address is performed when the first address corresponding to the target address is not cached in the storage management unit that performs the address translation.

3. The method according to claim 1, wherein, The first interconnect includes a first interconnect unit; issuing the page table read request via the first interconnect unit and receiving the page table read request issued via the first interconnect unit.

4. The method according to claim 3, wherein The first interconnect unit is a bus or an on-chip interconnect.

5. The method according to claim 3, wherein, The first interconnect further includes a second interconnect unit and a third interconnect unit, and the first interconnect unit communicates with the third interconnect unit via the second interconnect unit; issuing the page table read request sequentially via the first interconnect unit, the second interconnect unit, and the third interconnect unit.

6. The method according to claim 5, wherein receiving the page table read request issued sequentially via the third interconnect unit, the second interconnect unit, and the first interconnect unit.

7. The method according to claim 5, wherein The second interconnect unit includes an inter-die connection, and the third interconnect unit includes a bus or an on-chip interconnect.

8. According to the method according to any one of claims 5-7, wherein, Generating the page table read request using the target address and querying at least one level of page tables in a storage device level by level to obtain a first address corresponding to the target address are respectively performed on different dies.

9. The method according to claim 1, wherein, The target address is a virtual address, and the first address is a physical address; or, The target address is a virtual address, and the first address is an intermediate physical address; or, The target address is an intermediate physical address, and the first address is a physical address.

10. An electronic device, comprising: a first interconnect; a storage management unit, coupled to the first interconnect and configured to: obtain a target address, generate a page table read request using the target address, and issue the page table read request via the first interconnect; A page table query unit, coupled to the first interconnect, and configured to: receive the page table read request issued via the first interconnect, query at least one level of page tables from a storage device step by step according to the page table read request to obtain a first address corresponding to the target address, and return the queried first address to the storage management unit via the first interconnect. Wherein, the page table query unit is independent of the storage management unit and is no longer part of the storage management unit. The page table query unit communicates with the storage management unit via the first interconnect. Wherein, the page table read request includes n sub-requests, and the at least one level of page tables includes n levels of page tables, where n is an integer greater than 1. The page table query unit is further configured to: Retrieve n storage addresses corresponding to the n levels of page tables from the storage device according to the n sub-requests, where the n storage addresses include the first address; Return the n storage addresses to the storage management unit via the first interconnect at one time.

11. The electronic device according to claim 10, wherein, The storage management unit is a system storage management unit.

12. The electronic device according to claim 10, wherein, The page table query unit corresponds to multiple different storage management units.

13. The electronic device according to claim 11, wherein, The storage management unit and the page table query unit are respectively located on different chips, and the first interconnect includes an inter-chip connection.

14. An electronic device, comprising the electronic device according to any one of claims 10-13, the electronic device further comprising the storage device, wherein, The storage device is configured to store multi-level page tables.

15. The electronic device according to claim 14, wherein, The page table query unit is configured to directly access the storage device or be coupled to the storage device via another interconnect, where the another interconnect is different from the first interconnect.

16. The electronic device according to claim 15, wherein, For the case where the page table query unit directly accesses the storage device, the storage device includes a storage controller, and the storage controller includes the page table query unit, or The storage device includes a cache, and the cache includes the page table query unit.

17. The electronic device according to claim 14, wherein, The storage device is a double data rate synchronous dynamic random access memory.

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